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Subsequent patch to synthesize a vPASID will make use of this helper. No functional change intended. Cc: Michael S. Tsirkin Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Reviewed-by: Michael S. Tsirkin Tested-by: Eric Auger Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum Reviewed-by: Yi Liu Message-id: 20260126104342.253965-36-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/pci/pcie.c | 19 ++++++++++++------- include/hw/pci/pcie.h | 2 ++ 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index aa9024e532..c481c16c0f 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -1284,18 +1284,13 @@ void pcie_acs_reset(PCIDevice *dev) } } =20 -/* PASID */ -void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, - bool exec_perm, bool priv_mod) +void pcie_pasid_common_init(PCIDevice *dev, uint16_t offset, + uint8_t pasid_width, bool exec_perm, bool priv= _mod) { static const uint16_t control_reg_rw_mask =3D 0x07; uint16_t capability_reg; =20 assert(pasid_width <=3D PCI_EXT_CAP_PASID_MAX_WIDTH); - - pcie_add_capability(dev, PCI_EXT_CAP_ID_PASID, PCI_PASID_VER, offset, - PCI_EXT_CAP_PASID_SIZEOF); - capability_reg =3D ((uint16_t)pasid_width) << PCI_PASID_CAP_WIDTH_SHIF= T; capability_reg |=3D exec_perm ? PCI_PASID_CAP_EXEC : 0; capability_reg |=3D priv_mod ? PCI_PASID_CAP_PRIV : 0; @@ -1307,6 +1302,16 @@ void pcie_pasid_init(PCIDevice *dev, uint16_t offset= , uint8_t pasid_width, pci_set_word(dev->wmask + offset + PCI_PASID_CTRL, control_reg_rw_mask= ); =20 dev->exp.pasid_cap =3D offset; + +} + +/* PASID */ +void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, + bool exec_perm, bool priv_mod) +{ + pcie_add_capability(dev, PCI_EXT_CAP_ID_PASID, PCI_PASID_VER, offset, + PCI_EXT_CAP_PASID_SIZEOF); + pcie_pasid_common_init(dev, offset, pasid_width, exec_perm, priv_mod); } =20 /* PRI */ diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index d68bfa6257..fc02aeb169 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -155,6 +155,8 @@ void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_de= v, DeviceState *dev, void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp); =20 +void pcie_pasid_common_init(PCIDevice *dev, uint16_t offset, + uint8_t pasid_width, bool exec_perm, bool priv= _mod); void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, bool exec_perm, bool priv_mod); void pcie_pri_init(PCIDevice *dev, uint16_t offset, uint32_t outstanding_p= r_cap, --=20 2.43.0