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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702987; x=1770307787; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=P1FHnLGv0F1KpDJLLP83IUidm8bElFCZsHk7cWMFi/Q=; b=gFbqZsPnlaG1pcG5Vrn6euayd/GMXxvyOg6f25ynz3s8xq3z+FrGk2wMjOYbbWg7ya xqmfRH3Zi18qyyFneZsOdlrwL3LdkFOYSBOUJadFD/staWutcJWkHRXhCFqGQVMvUg0O NgzNmKEfM3QdSHdsBuf7eYai6XKgJF29y7WQDpm4CEfaB2phgLG4WEIYtNQg3bt+8NDs 9o+ZCnhIUXzO/thdCxu9YY9hmVnIg5LhxnCrMgykdxj65gYI2gQlT0fSs7nnnPbwWksg r+rG1k6f0l8GqAh9Qu3a8LHAjAxHJhrlzxZ/XN/DwyTBWu3EHyDj8BrGPxvESGoDkDdr Fe1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702987; x=1770307787; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=P1FHnLGv0F1KpDJLLP83IUidm8bElFCZsHk7cWMFi/Q=; b=aLYB0504wdFryBzg7c5dCWL14OPRw16gtmLfRjbuNmUoficT15TNgTVuUnTLbQ/rpi fOGTVK1o7TMvI5ynTH7QmlRlfgdveg33hSVZQdO7jJn85xa6BgUdOEei3veuoZWDLuow dFB7AYTpcNm5vpZCn0EoTjr/rGouEKJnE38F7mfyij8KWtcVKcLU+M20BZ45Ekiyp+06 zDO1yf/GnCAxR6gMZUqlBZokzT8PKLt8i+VAjTGeOHZKMJvhxsxa4pzGLGdA9RJPT6Uc EF/u2Ar1LWERsgYp+BN7gUcDNZZnTU1WKq+PamlMrIRM7svwENAWIfDIZTZIMLzSIdYM g1OQ== X-Gm-Message-State: AOJu0YxGLnPK0ygtN0d9VhhATN6z0NiV9Evx5/5lQiTUO1lMBIk0mFhJ 1BQsy2N8lZ6Yo9jRqLH7pzov1yeoqmkzKvGStOznxw3EnCApuHDTGZSx+hNM38jIss2T4ObYgor WhU3j6JU= X-Gm-Gg: AZuq6aIbz4r5UA42FrwPdOW26aRJjUX6mO8ia+1da52fmiIDLbn79o0onJeAQeo6BzQ 9mMTk4TYuc+MTTSV09zGANK7hBlZN9vQ692YI8M7slAoL3A7+KrK2hnPAggnRRNy1q3W9rhOMn8 A9wqghDeOdT0lF2Qu83yv5yyF0M5eRuYMVsItR8zOODhHhoZvRCvGoVW+Znc+Cjr3TDi9SNcy8n D7jdSJyLrfFwm7lgN3XlY44Scy6kPgOGnZVhUzjhxQIgVmv2mSRqhU5fGfIW6VrhKa0VYfjTnmt QzaRHN817U83vOVUem0n+i6FIitNnl5wS08Owaz3hUPew3ji/5lxMjn/eHHPAIE4zEMlEeM9jUP +ycYirg0ca+e81DhxNdcFmchkoOQQQ2/MrYBC2bfboQ2tBm5E8vRfSa8jQbY/AOo1L5baqzhalh T4gi9sl8QVOUyTll8zlLAHtJhcLVJ6nw== X-Received: by 2002:a5d:5f94:0:b0:432:e00b:8687 with SMTP id ffacd0b85a97d-435f3aa7957mr159981f8f.31.1769702987178; Thu, 29 Jan 2026 08:09:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/43] hw/arm/virt: Set PCI preserve_config for accel SMMUv3 Date: Thu, 29 Jan 2026 16:08:57 +0000 Message-ID: <20260129160917.1415092-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703247962158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Introduce a new pci_preserve_config field in virt machine state which allows the generation of DSM #5. This field is only set if accel SMMU is instantiated. In a subsequent patch, SMMUv3 accel mode will make use of IORT RMR nodes to enable nested translation of MSI doorbell addresses. IORT RMR requires _DSM #5 to be set for the PCI host bridge so that the Guest kernel preserves the PCI boot configuration. Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao Reviewed-by: Eric Auger Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-24-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 8 ++++++++ hw/arm/virt.c | 1 + include/hw/arm/virt.h | 1 + 3 files changed, 10 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 03b4342574..9032a5df1c 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -164,6 +164,14 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMap= Entry *memmap, .pci_native_hotplug =3D !acpi_pcihp, }; =20 + /* + * Accel SMMU requires RMRs for MSI 1-1 mapping, which require _DSM + * function 5 (_DSM for Preserving PCI Boot Configurations). + */ + if (vms->pci_preserve_config) { + cfg.preserve_config =3D true; + } + if (vms->highmem_mmio) { cfg.mmio64 =3D memmap[VIRT_HIGH_PCIE_MMIO]; } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 91fec582ed..899b02e1f7 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3080,6 +3080,7 @@ static void virt_machine_device_pre_plug_cb(HotplugHa= ndler *hotplug_dev, } object_property_set_uint(OBJECT(dev), "msi-gpa", db_start, &error_abort); + vms->pci_preserve_config =3D true; } } } diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 5907d41dbb..3b382bdf49 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -182,6 +182,7 @@ struct VirtMachineState { bool legacy_smmuv3_present; MemoryRegion *sysmem; MemoryRegion *secure_sysmem; + bool pci_preserve_config; }; =20 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) --=20 2.43.0