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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702984; x=1770307784; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8J4eY9wxv1cYUuMQ9c6DeC3OQdL9/UJSVtl7VAJyfKI=; b=Az96hfw43lFu6Ug1d+QxrcQZEUdRvx1fYUbronjAIuzO9kc7kvwr6SnPwU/ovNbg10 tc8i7NimXSdCKu1TSF2hjUcPxYkGUHkexPu6/xE1SqvqohRcrPaBvgO9zaWpdhpLwY2x UOBiKqpI742or8cj0RPEVNOFRuN05BJw4KQaqfWpzpanHFplb7EBX5hXBl1P3uBOUApx BZBjclJjvtxW77BNkFfS8efuDQPo90CJCgS5x5OFzUfaNakG+nqZ11b8o0eTzy3T0ZcE 7Tdi9g6s1SNQ9/lHOw/Xg9xmflFWxtcFYi16LBGE9ZXPUUpDsgd5nSlnF59oipDmWJZ/ SQNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702984; x=1770307784; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=8J4eY9wxv1cYUuMQ9c6DeC3OQdL9/UJSVtl7VAJyfKI=; b=pgqXrmCVa4kD0hSflWMN5/1oavX1t0gOxVBfirkvZ0rp/ToAS3X3PggRChZ4l5CNwh TaWikHtQyu7b6A+KzvrZGIVchvX42kCf3Z9pSh1h6aaPp74gAm4GMFi2V49EVg57Rd+0 ZU+dwb80AluZB8eh2hToBP7M6rhu95TlpZgQz5U2T/5ctvcEV1ieDQuPtF8JRX06XEyw lPJ3MLg9G8R6zLFJ+kZlPB2GnWxz7ROccdX9p2HxJeHC9+PAQP5MnsnTx/sZCTHocKLA ykimz/xVUqAxVvS5ELKpeKZZyOsrIrVLNaIFUOxmComSgeHv72TG+nP+JPkkL9sNcIAi hyNw== X-Gm-Message-State: AOJu0YyMulYFoHKhlccG9jyFodEIbCV5WeXevPsnH3WSC7aEOM4tC+Jz U3xlq1DdcagExVHhLTdPAqg8NLzAhB/Hg5DPa+udyq60nM6F7BsHbFTk3enoURvboK0Lnzx3PfB GvLIxa/I= X-Gm-Gg: AZuq6aJPeSbcSfmV+4w+yELP478CJtrpSoZdqszXWu+GtboSvxNNkg4qiL+cy2Zbn5d NwhFdxbdNdy7ZCMNo2ip21XFbwact3oz8IfIMPxC5JDqLIBhzMS7L/3yUlznepldap9Vvh3VGjl +kqiV0YLl8RGBW0KS4oF94+ymXMJhiFjQvDUFhnj5p3rwUap55LDfYLXnyqeUWV3MkN/PWna4Ls 0aCgzYJrsSBJCFWnG311Ma8qhsktXDQ7nOAvHROmyuUvO4CneJcOCDOnk881Co20LwYhTp9aeSd vkLkoX1ByZ2C5O2xiAhG1HJQfTmVkw7yuUr30Sj5ML8JuPWYBwQc872ZuCqDlCffxjTENQSZ+/v x80hB7LhCYm7ZBWlGV21KFUx5hC7SJT7DdyKdcOQd1/P+iJDGEI7uTcbhPaKVSDq0PxW/CbVFst j6pRABlNcUUiEOmwnwhcBHxqQqWeAVsA== X-Received: by 2002:a5d:5d06:0:b0:435:e450:f05e with SMTP id ffacd0b85a97d-435f3abb7d7mr126369f8f.63.1769702983580; Thu, 29 Jan 2026 08:09:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/43] hw/arm/smmuv3: Initialize ID registers early during realize() Date: Thu, 29 Jan 2026 16:08:54 +0000 Message-ID: <20260129160917.1415092-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703050810158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Factor out ID register init into smmuv3_init_id_regs() and call it from realize(). This ensures ID registers are initialized early for use in the accelerated SMMUv3 path and will be utilized in subsequent patch. Other registers remain initialized in smmuv3_reset(). Reviewed-by: Nicolin Chen Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-21-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 4efef73373..e301bb467d 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -258,7 +258,12 @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo= *info) info->recorded =3D true; } =20 -static void smmuv3_init_regs(SMMUv3State *s) +/* + * Called during realize(), as the ID registers will be accessed early in = the + * SMMUv3 accel path for feature compatibility checks. The remaining regis= ters + * are initialized later in smmuv3_reset(). + */ +static void smmuv3_init_id_regs(SMMUv3State *s) { /* Based on sys property, the stages supported in smmu will be adverti= sed.*/ if (s->stage && !strcmp("2", s->stage)) { @@ -298,7 +303,11 @@ static void smmuv3_init_regs(SMMUv3State *s) s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1); s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1); s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1); + s->aidr =3D 0x1; +} =20 +static void smmuv3_reset(SMMUv3State *s) +{ s->cmdq.base =3D deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS); s->cmdq.prod =3D 0; s->cmdq.cons =3D 0; @@ -310,7 +319,6 @@ static void smmuv3_init_regs(SMMUv3State *s) =20 s->features =3D 0; s->sid_split =3D 0; - s->aidr =3D 0x1; s->cr[0] =3D 0; s->cr0ack =3D 0; s->irq_ctrl =3D 0; @@ -1903,7 +1911,7 @@ static void smmu_reset_exit(Object *obj, ResetType ty= pe) c->parent_phases.exit(obj, type); } =20 - smmuv3_init_regs(s); + smmuv3_reset(s); smmuv3_accel_reset(s); } =20 @@ -1935,6 +1943,7 @@ static void smmu_realize(DeviceState *d, Error **errp) sysbus_init_mmio(dev, &sys->iomem); =20 smmu_init_irq(s, dev); + smmuv3_init_id_regs(s); } =20 static const VMStateDescription vmstate_smmuv3_queue =3D { --=20 2.43.0