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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702974; x=1770307774; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bcuFNIgtAmUa4zoyaYJellTHjqr2qi6wGu1/tr6ixAc=; b=yPEkW9MmDeE1aao4H5e0okz2Zk8HbrAXlGyia1VElcwuAe1D4/A8f7EA8c1dZFfcLZ o4IBnX6CVU7zNzqzDBvOKfY8971Sxck0T1RgbeFVkGVMpM77aoO4Fix1z51JP4sND6gM ALgEM9b+pYwr3fE34E+d3QCUxtdJ73U/RTBLS5jcUPw69z5BuDqHoX4gPL4Nekff3/mq FrTmYHHjb6IKZncwQkwcA9WM5R1L2Sycor4rAoc1u9k2SPg69h6/907ua3DohDEHZk3m qqRsQzxg3aq9izOcr0HND+DKSxL/Gwq2Vqot3VyLIHVCxNsI5Slpv7dQOt/JSbT83EOx X8Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702974; x=1770307774; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=bcuFNIgtAmUa4zoyaYJellTHjqr2qi6wGu1/tr6ixAc=; b=mPMmgKKofyEgBNfdhmgtSWY7DZL4gzIRsmR2g0cK6FFy+tdDH3EnjHZvMXNmBuk78E XOab+UTAsNj28rSb6c56G1qD8s0SksMfeaY6rrDgx253Yt0ch+PK4KQy3kRbMKQVMqP+ /m4p+HBHjfFju32AtuChwIqnWFKI85liO34st5tJeY1ByA1VwkQh8L9OuAmDxFLkLdq0 kzbmnfgliytoTGhQ3rDtOHEQ/iGldx1i8zyMOegtiyzesCNjvKekXyc0dJXXGEzZ5Df5 WO6BTE4RbXL6HgImMyCczA8fMFup2bTaewMG+d6aBg/EgqRIDi1AH+LBOw/9UaTYoCsc GRyA== X-Gm-Message-State: AOJu0YzLOZ5fq+tTnGSiWRqxON7Av+eDoJitWMLQOME7/fPY5Od1Sjsq 4gVeYoKviK7GVmUNOsEv7SAZ4QfdexHiJINo/H77CYSqAilmXEMf6ofRHnYi5HXFHQTuifqg4yC SCFxqFLA= X-Gm-Gg: AZuq6aL5h6GFd4PtBo93Kw7UEAOc3Xtob6/a/2Hq/HW2RVtzEHfyKDq2dw+3Uu58rj7 Bk8ZUgAUatRuGP5L9O58YWGDnd9IMBeMYO6Vlvl8cWmNJWvQlwu2xxO3g3c7ml1SuEHzfwMqUKS d/RycZDMz1pi99Kf6fPFi5kcyiOKmjWDE95eOX62HHm7T0lWxopk8jFaU3CITZ3vtgh3bCepyaj WwZ7J7YloCKE4zvJyjCR4OId75Msl4IoEAnPRGCwQUo2G4/DFdniPkV9Zebf3EQtHI9vyEAqN7L 3MnHjfVZ0a3qnf3wBO/7bUFxj5rgGoyEth1C+PDVjSH90IDEUrSAYMSjJtfB3jwo94u7Evkq5gI nte5aXy+iUiMFU3FSdwr1sIjPg3oN2GN6ZzaqlikuxAP2Rkqj2KpzQEe0ldCiIAP4gfStQiF3oU Qii0pnex5voT8bol707cJyqKy5aczlUA== X-Received: by 2002:a05:6000:4205:b0:433:1d30:44c with SMTP id ffacd0b85a97d-435f3aac3cdmr129466f8f.43.1769702974141; Thu, 29 Jan 2026 08:09:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/43] hw/arm/smmuv3-accel: Add set/unset_iommu_device callback Date: Thu, 29 Jan 2026 16:08:46 +0000 Message-ID: <20260129160917.1415092-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703209790158500 From: Nicolin Chen Implement the VFIO/PCI callbacks to attach and detach a HostIOMMUDevice to a vSMMUv3 when accel=3Don, - set_iommu_device(): attach a HostIOMMUDevice to a vIOMMU - unset_iommu_device(): detach and release associated resources In SMMUv3 accel=3Don mode, the guest SMMUv3 is backed by the host SMMUv3 via IOMMUFD. A vIOMMU object (created via IOMMU_VIOMMU_ALLOC) provides a per-VM, security-isolated handle to the physical SMMUv3. Without a vIOMMU, the vSMMUv3 cannot relay guest operations to the host hardware nor maintain isolation across VMs or devices. Therefore, set_iommu_device() allocates a vIOMMU object if one does not already exist. There are two main points to consider in this implementation: 1) VFIO core allocates and attaches a S2 HWPT that acts as the nesting parent for nested HWPTs(IOMMU_DOMAIN_NESTED). This parent HWPT will be shared across multiple vSMMU instances within a VM. 2) A device cannot attach directly to a vIOMMU. Instead, it attaches through a proxy nested HWPT (IOMMU_DOMAIN_NESTED). Based on the STE configuration,there are three types of nested HWPTs: bypass, abort, and translate. -The bypass and abort proxy HWPTs are pre-allocated. When SMMUv3 operates in global abort or bypass modes, as controlled by the GBPA register, or issues a vSTE for bypass or abort we attach these pre-allocated nested HWPTs. -The translate HWPT requires a vDEVICE to be allocated first, since invalidations and events depend on a valid vSID. -The vDEVICE allocation and attach operations for vSTE based HWPTs are implemented in subsequent patches. In summary, a device placed behind a vSMMU instance must have a vSID for translate vSTE. The bypass and abort vSTEs are pre-allocated as proxy nested HWPTs and is attached based on GBPA register. The core-managed nesting parent S2 HWPT is used as parent S2 HWPT for all the nested HWPTs and is intended to be shared across vSMMU instances within the same VM. set_iommu_device(): - Reuse an existing vIOMMU for the same physical SMMU if available. If not, allocate a new one using the nesting parent S2 HWPT. - Pre-allocate two proxy nested HWPTs (bypass and abort) under the vIOMMU and install one based on GBPA.ABORT value. - Add the device to the vIOMMU=E2=80=99s device list. unset_iommu_device(): - Re-attach device to the nesting parent S2 HWPT. - Remove the device from the vIOMMU=E2=80=99s device list. - If the list is empty, free the proxy HWPTs (bypass and abort) and release the vIOMMU object. Introduce struct SMMUv3AccelState, representing an accelerated SMMUv3 instance backed by an iommufd vIOMMU object, and storing the bypass and abort proxy HWPT IDs. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Zhangfei Gao Reviewed-by: Eric Auger Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-13-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 156 +++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 18 ++++ hw/arm/trace-events | 4 + include/hw/arm/smmuv3-common.h | 3 + include/hw/arm/smmuv3.h | 1 + 5 files changed, 182 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index be09cf8b73..9c2b917a11 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -8,6 +8,7 @@ =20 #include "qemu/osdep.h" #include "qemu/error-report.h" +#include "trace.h" =20 #include "hw/arm/smmuv3.h" #include "hw/core/iommu.h" @@ -15,6 +16,7 @@ #include "hw/pci-host/gpex.h" #include "hw/vfio/pci.h" =20 +#include "smmuv3-internal.h" #include "smmuv3-accel.h" =20 /* @@ -43,6 +45,157 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUStat= e *bs, SMMUPciBus *sbus, return accel_dev; } =20 +static uint32_t smmuv3_accel_gbpa_hwpt(SMMUv3State *s, SMMUv3AccelState *a= ccel) +{ + return FIELD_EX32(s->gbpa, GBPA, ABORT) ? + accel->abort_hwpt_id : accel->bypass_hwpt_id; +} + +static bool +smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, + Error **errp) +{ + SMMUv3AccelState *accel =3D s->s_accel; + struct iommu_hwpt_arm_smmuv3 bypass_data =3D { + .ste =3D { SMMU_STE_CFG_BYPASS | SMMU_STE_VALID, 0x0ULL }, + }; + struct iommu_hwpt_arm_smmuv3 abort_data =3D { + .ste =3D { SMMU_STE_VALID, 0x0ULL }, + }; + uint32_t s2_hwpt_id =3D idev->hwpt_id; + uint32_t viommu_id, hwpt_id; + IOMMUFDViommu *viommu; + + if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, + IOMMU_VIOMMU_TYPE_ARM_SMMUV3, + s2_hwpt_id, &viommu_id, errp)) { + return false; + } + + viommu =3D g_new0(IOMMUFDViommu, 1); + viommu->viommu_id =3D viommu_id; + viommu->s2_hwpt_id =3D s2_hwpt_id; + viommu->iommufd =3D idev->iommufd; + + /* + * Pre-allocate HWPTs for S1 bypass and abort cases. These will be att= ached + * later for guest STEs or GBPAs that require bypass or abort configur= ation. + */ + if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, viommu_id, + 0, IOMMU_HWPT_DATA_ARM_SMMUV3, + sizeof(abort_data), &abort_data, + &accel->abort_hwpt_id, errp)) { + goto free_viommu; + } + + if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, viommu_id, + 0, IOMMU_HWPT_DATA_ARM_SMMUV3, + sizeof(bypass_data), &bypass_data, + &accel->bypass_hwpt_id, errp)) { + goto free_abort_hwpt; + } + + /* Attach a HWPT based on SMMUv3 GBPA.ABORT value */ + hwpt_id =3D smmuv3_accel_gbpa_hwpt(s, accel); + if (!host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp)) { + goto free_bypass_hwpt; + } + accel->viommu =3D viommu; + return true; + +free_bypass_hwpt: + iommufd_backend_free_id(idev->iommufd, accel->bypass_hwpt_id); +free_abort_hwpt: + iommufd_backend_free_id(idev->iommufd, accel->abort_hwpt_id); +free_viommu: + iommufd_backend_free_id(idev->iommufd, viommu->viommu_id); + g_free(viommu); + return false; +} + +static bool smmuv3_accel_set_iommu_device(PCIBus *bus, void *opaque, int d= evfn, + HostIOMMUDevice *hiod, Error **e= rrp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(hiod); + SMMUState *bs =3D opaque; + SMMUv3State *s =3D ARM_SMMUV3(bs); + SMMUPciBus *sbus =3D smmu_get_sbus(bs, bus); + SMMUv3AccelDevice *accel_dev =3D smmuv3_accel_get_dev(bs, sbus, bus, d= evfn); + + if (!idev) { + return true; + } + + if (accel_dev->idev) { + if (accel_dev->idev !=3D idev) { + error_setg(errp, "Device already has an associated idev 0x%x", + idev->devid); + return false; + } + return true; + } + + if (s->s_accel->viommu) { + goto done; + } + + if (!smmuv3_accel_alloc_viommu(s, idev, errp)) { + error_append_hint(errp, "Unable to alloc vIOMMU: idev devid 0x%x: = ", + idev->devid); + return false; + } + +done: + accel_dev->idev =3D idev; + accel_dev->s_accel =3D s->s_accel; + QLIST_INSERT_HEAD(&s->s_accel->device_list, accel_dev, next); + trace_smmuv3_accel_set_iommu_device(devfn, idev->devid); + return true; +} + +static void smmuv3_accel_unset_iommu_device(PCIBus *bus, void *opaque, + int devfn) +{ + SMMUState *bs =3D opaque; + SMMUPciBus *sbus =3D g_hash_table_lookup(bs->smmu_pcibus_by_busptr, bu= s); + HostIOMMUDeviceIOMMUFD *idev; + SMMUv3AccelDevice *accel_dev; + SMMUv3AccelState *accel; + SMMUDevice *sdev; + + if (!sbus) { + return; + } + + sdev =3D sbus->pbdev[devfn]; + if (!sdev) { + return; + } + + accel_dev =3D container_of(sdev, SMMUv3AccelDevice, sdev); + idev =3D accel_dev->idev; + accel =3D accel_dev->s_accel; + /* Re-attach the default s2 hwpt id */ + if (!host_iommu_device_iommufd_attach_hwpt(idev, idev->hwpt_id, NULL))= { + error_report("Unable to attach the default HW pagetable: idev devi= d " + "0x%x", idev->devid); + } + + accel_dev->idev =3D NULL; + accel_dev->s_accel =3D NULL; + QLIST_REMOVE(accel_dev, next); + trace_smmuv3_accel_unset_iommu_device(devfn, idev->devid); + + if (QLIST_EMPTY(&accel->device_list)) { + iommufd_backend_free_id(accel->viommu->iommufd, accel->bypass_hwpt= _id); + iommufd_backend_free_id(accel->viommu->iommufd, accel->abort_hwpt_= id); + iommufd_backend_free_id(accel->viommu->iommufd, + accel->viommu->viommu_id); + g_free(accel->viommu); + accel->viommu =3D NULL; + } +} + /* * Only allow PCIe bridges, pxb-pcie roots, and GPEX roots so vfio-pci * endpoints can sit downstream. Accelerated SMMUv3 requires a vfio-pci @@ -145,6 +298,8 @@ static const PCIIOMMUOps smmuv3_accel_ops =3D { .supports_address_space =3D smmuv3_accel_supports_as, .get_address_space =3D smmuv3_accel_find_add_as, .get_viommu_flags =3D smmuv3_accel_get_viommu_flags, + .set_iommu_device =3D smmuv3_accel_set_iommu_device, + .unset_iommu_device =3D smmuv3_accel_unset_iommu_device, }; =20 static void smmuv3_accel_as_init(SMMUv3State *s) @@ -168,6 +323,7 @@ void smmuv3_accel_init(SMMUv3State *s) { SMMUState *bs =3D ARM_SMMU(s); =20 + s->s_accel =3D g_new0(SMMUv3AccelState, 1); bs->iommu_ops =3D &smmuv3_accel_ops; smmuv3_accel_as_init(s); } diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 0dc6b00d35..efb631db4f 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -10,10 +10,28 @@ #define HW_ARM_SMMUV3_ACCEL_H =20 #include "hw/arm/smmu-common.h" +#include "system/iommufd.h" +#ifdef CONFIG_LINUX +#include +#endif #include CONFIG_DEVICES =20 +/* + * Represents an accelerated SMMU instance backed by an iommufd vIOMMU obj= ect. + * Holds bypass and abort proxy HWPT IDs used for device attachment. + */ +typedef struct SMMUv3AccelState { + IOMMUFDViommu *viommu; + uint32_t bypass_hwpt_id; + uint32_t abort_hwpt_id; + QLIST_HEAD(, SMMUv3AccelDevice) device_list; +} SMMUv3AccelState; + typedef struct SMMUv3AccelDevice { SMMUDevice sdev; + HostIOMMUDeviceIOMMUFD *idev; + QLIST_ENTRY(SMMUv3AccelDevice) next; + SMMUv3AccelState *s_accel; } SMMUv3AccelDevice; =20 #ifdef CONFIG_ARM_SMMUV3_ACCEL diff --git a/hw/arm/trace-events b/hw/arm/trace-events index f3386bd7ae..2aaa0c40c7 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -66,6 +66,10 @@ smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotif= ier node for iommu mr=3D%s smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t i= ova, uint8_t tg, uint64_t num_pages, int stage) "iommu mr=3D%s asid=3D%d vm= id=3D%d iova=3D0x%"PRIx64" tg=3D%d num_pages=3D0x%"PRIx64" stage=3D%d" smmu_reset_exit(void) "" =20 +#smmuv3-accel.c +smmuv3_accel_set_iommu_device(int devfn, uint32_t devid) "devfn=3D0x%x (id= ev devid=3D0x%x)" +smmuv3_accel_unset_iommu_device(int devfn, uint32_t devid) "devfn=3D0x%x (= idev devid=3D0x%x)" + # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" strongarm_ssp_read_underrun(void) "SSP rx underrun" diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h index f644618f38..153310248d 100644 --- a/include/hw/arm/smmuv3-common.h +++ b/include/hw/arm/smmuv3-common.h @@ -100,6 +100,9 @@ REG32(STE_7, 28) #define STE_CFG_ABORT(config) (!(config & 0x4)) #define STE_CFG_BYPASS(config) (config =3D=3D 0x4) =20 +#define SMMU_STE_VALID (1ULL << 0) +#define SMMU_STE_CFG_BYPASS (1ULL << 3) + /* Update STE fields */ #define STE_SET_VALID(ste, v) = \ ((ste)->word[0] =3D FIELD_DP32((ste)->word[0], STE_0, VALID, (v))) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index bb7076286b..e54ece2d38 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -66,6 +66,7 @@ struct SMMUv3State { =20 /* SMMU has HW accelerator support for nested S1 + s2 */ bool accel; + struct SMMUv3AccelState *s_accel; }; =20 typedef enum { --=20 2.43.0