From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703018; cv=none; d=zohomail.com; s=zohoarc; b=Wk0N679UGBQPs9d9rH7wwVuf+D3f8pXVyUOT3iezdOYw6Mqy+bcrzxvWcgyYMszj5A3wVH8XTEKE2mivd5WUuMj2FHWLUBBRZBGa8mGRqvbv0UmsZ4Dyr3sX6w6gKqBJwNFbd49gHZJvg8g04SCsD6U9IUaOix1QyfWjiJNoylM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703018; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=OFYLZeT7ofyrXtsXvZMxt3gggy8HcN1+3roFl5J8Wow=; b=T1iQzrlE/v5vL8j1Ix5SO0Qmdgb+lAjQEU3WJu0YPOeoDjtFjvfmxgTPY9E4ebZC6b3KKaedKO6zmDn75yBIAs4ZaYu6OnXmmxVGzGr14A3ZfLDH8tpPUW7stFnOO7d910pkJoMj6ZrmLsdrPs4g2Yc7czrLko0NCCQGYeWwD7I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703018406133.31627861850416; Thu, 29 Jan 2026 08:10:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUaH-0008RM-Q3; Thu, 29 Jan 2026 11:09:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaD-0008QH-44 for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:25 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaA-0006Tz-4h for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:24 -0500 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-43591b55727so1042227f8f.3 for ; Thu, 29 Jan 2026 08:09:21 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702960; x=1770307760; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=OFYLZeT7ofyrXtsXvZMxt3gggy8HcN1+3roFl5J8Wow=; b=tu7baT6Dl87A6ThM+/M5EKi+Yi7M7oHF6cwj6tOj6T74FSQgIKzBb+UePfIQAHhFKt cvKrwM7++NmwwyY0dZ1A7XMXGUpt7kMHtmvg32ntGu/pIyLNsNaglGhItFZ7T1esoWOR x0j8DsQ3DaU/68DCRtG5B3a3ueT2JPa3+BJv21aFTRQsVri5h0SNNQHabeBwSCJOvT+Y 04vwEvlzZZ2vuVWcUb4AbCM7GN3jstej40EJOolBTal2bAVyqP33CmHPtm5zsKABjKXw VQaobqTaNydIQDmkTxmxOAdMM54PPgB7bDYEweTZ2RXorKa+ll3+fkc2nOLN39eU/g/5 fMtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702960; x=1770307760; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=OFYLZeT7ofyrXtsXvZMxt3gggy8HcN1+3roFl5J8Wow=; b=tqtuiX6/2AMfmAUT59MIC8WwvP/vVK6F2BcVikcV0t7uWbCBCtEjZcnCfKzjFMYaF1 vbR2BfTDiEdsW9tRfXKE9diJVaxcpWaSKrRzJnJztGI/JoOZaf+AVESGtYIVEXIsVSzd Df+4jMQjPnQQcLy/klTSURszG5lHnylr1R8tFYlRP6bQ4fjMksk/uX1XC2jcED4LjgnJ 003vURjSErP14jDF5F5hPQ8ZNwVi76E2bGypg+m+IvOdpCnOliSRvEZwta4MzighrkPE OM7/BmeJV7s6e69dXfv28TDAceBBEJM/EcYbLgk6aUrgRUu96WuXr7L1Ax2lhMz7f8n0 Rdww== X-Gm-Message-State: AOJu0YwurirbrDK3eZBzl4JUDevYuGROM3hHbp5PX3FndkV4OCKYm0C2 zH7Q1H5ByD7POasyUoFM5Ae5QHWQmHsTtA+oYVl8BACNjfjbYYsGlJWFCSH+GO4Sw0V9Un2NVAt x0AOdIcQ= X-Gm-Gg: AZuq6aK5o1GJXEtKhN/Ur5BfXXWnLEoOz4j2YMbMXSAZBFFndhMnbtxTPu5JYXcqfZB yLVGZJOwzhyYTgwgSg75qN/+nWOmieesPe2xN+1rLHQLH7P2tzFblea9v3fzxdvQd1VIb+LwKBd v5j+Dv6Fv/ROW0gV8tvZeujSYJa4vN5m9p1zwpV1Ilors2yVDBWvRQ4Fx3H8u9ncSmIDNZbJLlW wctIWQK3nhQ62lZ8Bqgpk8ZDz39nPpeoueyU8Qkwk3Qd8zuSiwqlSsR/zVRpFMMkRWotL+SoN1l q7Es9l+AXQZ6Edbw1i7Ji+LGeQ/BPNlXPxDD6XI5SZHUAwixEvcUNKiAEGPNFA5jsVbJqwm/JXn NR8GrIm9HT//1RzNB+ohGizx+hNubC/j9v4ZnHakDhExLcSHkzxQc5yV+L/FnRuMMZYN1Eg+VaM +7D7RfUx1J1tXrFzBpCfb0SVv43MkxQw== X-Received: by 2002:a05:6000:1862:b0:435:96ec:679e with SMTP id ffacd0b85a97d-435f3a7b8d5mr192408f8f.23.1769702960256; Thu, 29 Jan 2026 08:09:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/43] backends/iommufd: Introduce iommufd_backend_alloc_viommu Date: Thu, 29 Jan 2026 16:08:35 +0000 Message-ID: <20260129160917.1415092-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703020659158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Add a helper to allocate a viommu object. Also introduce a struct IOMMUFDViommu that can be used later by vendor IOMMU implementations. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Reviewed-by: Jonathan Cameron Signed-off-by: Shameer Kolothum Tested-by: Zhangfei Gao Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Reviewed-by: Yi Liu Message-id: 20260126104342.253965-2-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- backends/iommufd.c | 26 ++++++++++++++++++++++++++ backends/trace-events | 1 + include/system/iommufd.h | 14 ++++++++++++++ 3 files changed, 41 insertions(+) diff --git a/backends/iommufd.c b/backends/iommufd.c index 086bd67aea..c65dc41d71 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -447,6 +447,32 @@ bool iommufd_backend_invalidate_cache(IOMMUFDBackend *= be, uint32_t id, return !ret; } =20 +bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, + uint32_t viommu_type, uint32_t hwpt_id, + uint32_t *out_viommu_id, Error **errp) +{ + int ret; + struct iommu_viommu_alloc alloc_viommu =3D { + .size =3D sizeof(alloc_viommu), + .type =3D viommu_type, + .dev_id =3D dev_id, + .hwpt_id =3D hwpt_id, + }; + + ret =3D ioctl(be->fd, IOMMU_VIOMMU_ALLOC, &alloc_viommu); + + trace_iommufd_backend_alloc_viommu(be->fd, dev_id, viommu_type, hwpt_i= d, + alloc_viommu.out_viommu_id, ret); + if (ret) { + error_setg_errno(errp, errno, "IOMMU_VIOMMU_ALLOC failed"); + return false; + } + + g_assert(out_viommu_id); + *out_viommu_id =3D alloc_viommu.out_viommu_id; + return true; +} + bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev, uint32_t hwpt_id, Error **errp) { diff --git a/backends/trace-events b/backends/trace-events index e1992ba12f..1ae94c4290 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -21,3 +21,4 @@ iommufd_backend_free_id(int iommufd, uint32_t id, int ret= ) " iommufd=3D%d id=3D%d (% iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int r= et) " iommufd=3D%d hwpt=3D%u enable=3D%d (%d)" iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t i= ova, uint64_t size, uint64_t flags, uint64_t page_size, int ret) " iommufd= =3D%d hwpt=3D%u iova=3D0x%"PRIx64" size=3D0x%"PRIx64" flags=3D0x%"PRIx64" p= age_size=3D0x%"PRIx64" (%d)" iommufd_backend_invalidate_cache(int iommufd, uint32_t id, uint32_t data_t= ype, uint32_t entry_len, uint32_t entry_num, uint32_t done_num, uint64_t da= ta_ptr, int ret) " iommufd=3D%d id=3D%u data_type=3D%u entry_len=3D%u entry= _num=3D%u done_num=3D%u data_ptr=3D0x%"PRIx64" (%d)" +iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint32_t viommu_id, int ret) " iommufd=3D%d type=3D%u dev= _id=3D%u hwpt_id=3D%u viommu_id=3D%u (%d)" diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 1392706b83..bc4acd1e8b 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -38,6 +38,16 @@ struct IOMMUFDBackend { /*< public >*/ }; =20 +/* + * Virtual IOMMU object that represents physical IOMMU's virtualization + * support + */ +typedef struct IOMMUFDViommu { + IOMMUFDBackend *iommufd; + uint32_t s2_hwpt_id; /* ID of stage 2 HWPT */ + uint32_t viommu_id; /* virtual IOMMU ID of allocated object */ +} IOMMUFDViommu; + bool iommufd_backend_connect(IOMMUFDBackend *be, Error **errp); void iommufd_backend_disconnect(IOMMUFDBackend *be); =20 @@ -59,6 +69,10 @@ bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint= 32_t dev_id, uint32_t data_type, uint32_t data_len, void *data_ptr, uint32_t *out_hwpt, Error **errp); +bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, + uint32_t viommu_type, uint32_t hwpt_id, + uint32_t *out_hwpt, Error **errp); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769702997; cv=none; d=zohomail.com; s=zohoarc; b=RQ84oQGwzrWpBTJIj4w7IOAPFqiyPOxE1caq+lmE6hfq6TJnG8X22zMN0XL/r5VODAUE5Fa6QPwT4pGKT4HrCgO6uPy3fYB6aOYsUMwyR5YWb4QTGRutxh7nbn+qWP1UWorEj8TV5tVTH0jsadbg/wmdR26bpeje+T4+bf9qqiE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769702997; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=T0N0B5cWcZZOhJc+vK4KHyIYqbyF+U6ChwUVIRwX2tA=; b=TJDVTiCsNwFNiCDuTRWWa8W5kEo+ERdclmmofVuMP8jMAU4bq0V9j/6XQEv6DYYAt2TczCoDBfqU0oICy8xrtUC3DUUmmoT1kANnknAtqrwyc38fStvA2oQiBm5BR+x8sUA/hO6kDx4+Mn+e8D1UXrX0fTal202jmPxlsT2Cyqg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769702997680430.7280140989063; Thu, 29 Jan 2026 08:09:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUaK-0008Sj-Mu; Thu, 29 Jan 2026 11:09:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaE-0008QY-NY for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:27 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaB-0006UR-SE for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:25 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-480142406b3so8835355e9.1 for ; Thu, 29 Jan 2026 08:09:23 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702962; x=1770307762; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=T0N0B5cWcZZOhJc+vK4KHyIYqbyF+U6ChwUVIRwX2tA=; b=aTPB5D10lIdQ/H9E8ir4KQO26Y4c+K27ieq65BWmaBnsWHoebxUYz+VXEayXoLjO0q JARhnHNtFZtWlP6MjoXOILDOnw2VWshxoybxZCHU6lU4ohKN7mdobZ1NxZ8V5/7NbWjn JwwLQMvgr4v3d9KV92BJgkKSFvOKZGPebIFzqnJOjDORJsybHdC6t0u77mO+H9zLStPv QQQVxogHkvZJIlq4HvqminxM4xuzEay/T19HrrhxZ7tfZ1SrxuKsZJ17SFHoTXVBHimD DcdGSQMrpVRT6YyBWdNWN7EA0aVBIvMNIIixIJcerS8UC29WxMlO/kKn3xLCIsDWB8aT B+vQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702962; x=1770307762; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=T0N0B5cWcZZOhJc+vK4KHyIYqbyF+U6ChwUVIRwX2tA=; b=r8SdvwixmY8U8t99dWLGrAIwL8XYrMdbJVCcv7vFP7MK4qMg/gW7UzM1QmBCjmWBwZ E1+5iTmXMRcEPR68iAILU8h+1x/7/5eYK4hF5U5kL7zAo/OQ5JPFBLjmGxx1Kgrld85M Vc+PdmhzgI7PIVKXRqJn7enGkvW9+APJRcoSwq8RJDpnSy+DfecQZAAsC5V5sz4ALHOm nf67k7IfT0eIE8H/0Eevipo9xC51gp7HyTnS50RC85kwhlJCpCLQ8FowTfcfeve11FmZ cpLH2RSxUIU3obVnsr/8LAVmxEtNh1qgjNauRK1x36wqSEmUT6eHPON8qEFAIyD11Cq+ FtoQ== X-Gm-Message-State: AOJu0Yy6IrRoWVFwS/y4bxh/23iUWx5hNaZuUoEWGAuD67jz0zsr8PRo amk5pj2plGYGPQVH5ByoaMSr070SgSvPlaIfmJ5nNtSwqoSbHjm7Wtv9FYmVCo3k1DgRAnlXnXi NRKPwCoc= X-Gm-Gg: AZuq6aKGf8bGvZxzuy62Q5gNecpDa1g+71nrUczMJK8rJe6nyp3JW7vOSxUg4NehtaJ frZ18QIbWwv2cM+1GpCfkMfkhta7TP1FKjp/U05FHn4JlQcRNBOnpSGfw71n6f3A942PXM1JcPa gGzHOZ+vontOaUTdfE/phxgSVv80gwzWxI8E9vk+FAQOj5ozV5OzYyt7GGM8gooWPDkntjIov+q WvaSuEGqGqRjNFIKm0cXpIMBAFnjbJ564Vs0B/v/1yptWLNUw5ebOhUmV2/N9XbT2dHBer5TQCw 4KaPpdjygYaZN7ihXnBam5eQBGBPiaA53PKdztRUtzaK3UOpLjzch0TDrVJQLHDINYJ+s+yIbVa xM/YdUXDjNQqR0TYbjkAHJaw+t5LiBviqxVmCqMHw+AC215NKRHpGt2cHOFRfFpRxPaM2mefmTA 35wQTuHbp6Vqik6/M3KcX+Q3R3ovJAFVSvUJIZuJop X-Received: by 2002:a05:6000:1a8d:b0:431:1ae:a3be with SMTP id ffacd0b85a97d-435f3a6f7fbmr156796f8f.3.1769702962318; Thu, 29 Jan 2026 08:09:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/43] backends/iommufd: Introduce iommufd_backend_alloc_vdev Date: Thu, 29 Jan 2026 16:08:36 +0000 Message-ID: <20260129160917.1415092-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769702998582158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Add a helper to allocate an iommufd device's virtual device (in the user space) per a viommu instance. While at it, introduce a struct IOMMUFDVdev for later use by vendor IOMMU implementations. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Reviewed-by: Yi Liu Message-id: 20260126104342.253965-3-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- backends/iommufd.c | 27 +++++++++++++++++++++++++++ backends/trace-events | 1 + include/system/iommufd.h | 12 ++++++++++++ 3 files changed, 40 insertions(+) diff --git a/backends/iommufd.c b/backends/iommufd.c index c65dc41d71..e3a3c1480e 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -473,6 +473,33 @@ bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, = uint32_t dev_id, return true; } =20 +bool iommufd_backend_alloc_vdev(IOMMUFDBackend *be, uint32_t dev_id, + uint32_t viommu_id, uint64_t virt_id, + uint32_t *out_vdev_id, Error **errp) +{ + int ret; + struct iommu_vdevice_alloc alloc_vdev =3D { + .size =3D sizeof(alloc_vdev), + .viommu_id =3D viommu_id, + .dev_id =3D dev_id, + .virt_id =3D virt_id, + }; + + ret =3D ioctl(be->fd, IOMMU_VDEVICE_ALLOC, &alloc_vdev); + + trace_iommufd_backend_alloc_vdev(be->fd, dev_id, viommu_id, virt_id, + alloc_vdev.out_vdevice_id, ret); + + if (ret) { + error_setg_errno(errp, errno, "IOMMU_VDEVICE_ALLOC failed"); + return false; + } + + g_assert(out_vdev_id); + *out_vdev_id =3D alloc_vdev.out_vdevice_id; + return true; +} + bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev, uint32_t hwpt_id, Error **errp) { diff --git a/backends/trace-events b/backends/trace-events index 1ae94c4290..14a7ecf5aa 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -22,3 +22,4 @@ iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, = bool start, int ret) " iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t i= ova, uint64_t size, uint64_t flags, uint64_t page_size, int ret) " iommufd= =3D%d hwpt=3D%u iova=3D0x%"PRIx64" size=3D0x%"PRIx64" flags=3D0x%"PRIx64" p= age_size=3D0x%"PRIx64" (%d)" iommufd_backend_invalidate_cache(int iommufd, uint32_t id, uint32_t data_t= ype, uint32_t entry_len, uint32_t entry_num, uint32_t done_num, uint64_t da= ta_ptr, int ret) " iommufd=3D%d id=3D%u data_type=3D%u entry_len=3D%u entry= _num=3D%u done_num=3D%u data_ptr=3D0x%"PRIx64" (%d)" iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint32_t viommu_id, int ret) " iommufd=3D%d type=3D%u dev= _id=3D%u hwpt_id=3D%u viommu_id=3D%u (%d)" +iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" diff --git a/include/system/iommufd.h b/include/system/iommufd.h index bc4acd1e8b..567dfb7b1d 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -48,6 +48,14 @@ typedef struct IOMMUFDViommu { uint32_t viommu_id; /* virtual IOMMU ID of allocated object */ } IOMMUFDViommu; =20 +/* + * Virtual device object for a physical device bind to a vIOMMU. + */ +typedef struct IOMMUFDVdev { + uint32_t vdevice_id; /* object handle for vDevice */ + uint32_t virt_id; /* virtual device ID */ +} IOMMUFDVdev; + bool iommufd_backend_connect(IOMMUFDBackend *be, Error **errp); void iommufd_backend_disconnect(IOMMUFDBackend *be); =20 @@ -73,6 +81,10 @@ bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, ui= nt32_t dev_id, uint32_t viommu_type, uint32_t hwpt_id, uint32_t *out_hwpt, Error **errp); =20 +bool iommufd_backend_alloc_vdev(IOMMUFDBackend *be, uint32_t dev_id, + uint32_t viommu_id, uint64_t virt_id, + uint32_t *out_vdev_id, Error **errp); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703050; cv=none; d=zohomail.com; s=zohoarc; b=BieGmm5F34KQWFwTDcV25feaeAAXCDQnM92b4eYzAHse1ndzj6/+5w2prWW70LjrmReCptYDvln/A+m0WIEHWdNhl7Uix1+igI+d1J/kyN6J0XBNNnl9fxS5puJiMRhSQPIubiyfiysnZQJfVQINwEFQ2oTrxh3mkTnZ3fY2RzY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703050; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=tOHeTTSLqbsAURnZwmNj8yFq/wlmRq5J+W/kAsI1onY=; b=UOiyFYDmPp0selaVNWzxALFZoPNPjm0+wxEEWr1+ltkrhdeQXgSC8VAEilKvbBS1GBsuLrK7mtMVelyp3yjnhXirnipJYNKSsOWarMMHhJaDcNiQCCAkqPiZ3L+6ojlRuB/nrczP8zd7BgTe6/r5dYyw+rykSMhNnk0q3kzPi0U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703050393425.26510716060386; Thu, 29 Jan 2026 08:10:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUaJ-0008SD-7R; Thu, 29 Jan 2026 11:09:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaG-0008Qt-L9 for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:28 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaC-0006Ub-UB for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:27 -0500 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-43591b55727so1042309f8f.3 for ; Thu, 29 Jan 2026 08:09:24 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702963; x=1770307763; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=tOHeTTSLqbsAURnZwmNj8yFq/wlmRq5J+W/kAsI1onY=; b=oriCjVY5uUeASIApWZXNjQHLWEDZQDaS7neR6PP6zj0m/JUzOx9XWC1SdFd6AftqmW eneF+009st2YaxzzPBLqWEB6rQE7tlgi5cEHM55Q4iqkh2tGPaJ3+2w/5+jiNAMs1/rf ls4PuxKuASmDZPO3a3Dh+kvkhelL2haVX4XiIWIZRyITuGvDVvXGgszUxwYGuatBdZPK vu9G2scRYczsX7dyJx7j7yGhIj0l/8q/ibGiWUaQmXXYieLviIE3H1msQbHA3E7f5Pp+ VpWxp9kE63IPeio5XGtmyI/fB3x7dhdSCTNlaTpEBju1OVxFH7EUS2NoYn87L8tyAc1W SmgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702963; x=1770307763; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=tOHeTTSLqbsAURnZwmNj8yFq/wlmRq5J+W/kAsI1onY=; b=SlHSBG6NGEU9C6cpyHFRDGbpddJzAc4/0kFWSuviM0JtN40BI7H/zJbbe05LrydTLu v53DryK1qfprDXzeyaCgkVF/AHYamGdOpJWVVanR4hz4q7CMfNKDwHaiNZedVoFx/eQV Pvli9/8Mo8qOhPDxkAoBFPzyvGKQxkahHTKr4nuNP6/Hpwy6jWjTU9tMC87Vb/keXu7m t6kOaPQ4ekdotvjECPHIisJN4SBjS9OBKb1TXsZXO4C+BQHvohvjJcnhrfyYeB5tIa9b ZKCuI69aeGsfJunYQTlRqW7znQjQIPod6g11Qd11JbqAZaTydS4H9EbhFeID90IXTBEG 1EXg== X-Gm-Message-State: AOJu0YwEftHWTar/IEdeAjqeSZJ6ENwYTj+JjTUTMtfXuVtFiD3Rku8n Arn0P3MFtNa/Z5XEORBH879ph+wmy0EwpIIRHCHf9z1iNi7H+9/RyhzjDbNlZA6hensoVDwCY+Z s2efeY6k= X-Gm-Gg: AZuq6aLN8l6kMEoMkkJqvvqZllnO0sSpVKi5FUCAr6K9w0VG3Du9IJQr3XLDa9R+lTV jeGhwVsX37sc00oVBJr1v4+wZFPIH4oIkgjY/qEN0uJbuCAC0H1O3NiAyl+bWK2A8i0gCnOmroq Z8+bhGacJnLf2n6idTpnEfptjy++zpn+zkJR8XnrB/1UMyy4D+OJ1uR052ypC4ivsq7AYwGN3AX r/QdnInKMLXoaRG7qHznhdboU46wBbKU9RuF8HGeOC12Hh2UUYn+C0cZXCJt/sRWst8nkNVLLNh 1VBD50gHvJqKZis9iUHRrCUNHVkusZUtcPvGls5JuEIXbPD1VQRdYKChPc0QA8H5AFs9147qjp7 fg3DiYI9o/Zpnc0mifDGdvKQKDbPr32A7Bk3Knpk5Iy9dVTNBZq6iyPOJOLnhHV4AL89IYiMwSw 4NDw5xlZCGTtMYxIS9JLzsZwIxFC3rgw== X-Received: by 2002:a05:6000:1ac7:b0:42f:b707:56f0 with SMTP id ffacd0b85a97d-435f3aaa42fmr144381f8f.37.1769702963384; Thu, 29 Jan 2026 08:09:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/43] hw/arm/smmu-common: Factor out common helper functions and export Date: Thu, 29 Jan 2026 16:08:37 +0000 Message-ID: <20260129160917.1415092-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703052269154101 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Factor out common helper functions and export. Subsequent patches for smmuv3 accel support will make use of this. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-4-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmu-common.c | 44 +++++++++++++++++++++--------------- include/hw/arm/smmu-common.h | 6 +++++ 2 files changed, 32 insertions(+), 18 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index cdcfb1343d..1492d7dd95 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -847,12 +847,24 @@ SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8= _t bus_num) return NULL; } =20 -static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) +void smmu_init_sdev(SMMUState *s, SMMUDevice *sdev, PCIBus *bus, int devfn) { - SMMUState *s =3D opaque; - SMMUPciBus *sbus =3D g_hash_table_lookup(s->smmu_pcibus_by_busptr, bus= ); - SMMUDevice *sdev; static unsigned int index; + g_autofree char *name =3D g_strdup_printf("%s-%d-%d", s->mrtypename, d= evfn, + index++); + sdev->smmu =3D s; + sdev->bus =3D bus; + sdev->devfn =3D devfn; + + memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), + s->mrtypename, OBJECT(s), name, UINT64_MAX); + address_space_init(&sdev->as, MEMORY_REGION(&sdev->iommu), name); + trace_smmu_add_mr(name); +} + +SMMUPciBus *smmu_get_sbus(SMMUState *s, PCIBus *bus) +{ + SMMUPciBus *sbus =3D g_hash_table_lookup(s->smmu_pcibus_by_busptr, bus= ); =20 if (!sbus) { sbus =3D g_malloc0(sizeof(SMMUPciBus) + @@ -861,23 +873,19 @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, vo= id *opaque, int devfn) g_hash_table_insert(s->smmu_pcibus_by_busptr, bus, sbus); } =20 + return sbus; +} + +static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) +{ + SMMUState *s =3D opaque; + SMMUPciBus *sbus =3D smmu_get_sbus(s, bus); + SMMUDevice *sdev; + sdev =3D sbus->pbdev[devfn]; if (!sdev) { - char *name =3D g_strdup_printf("%s-%d-%d", s->mrtypename, devfn, i= ndex++); - sdev =3D sbus->pbdev[devfn] =3D g_new0(SMMUDevice, 1); - - sdev->smmu =3D s; - sdev->bus =3D bus; - sdev->devfn =3D devfn; - - memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), - s->mrtypename, - OBJECT(s), name, UINT64_MAX); - address_space_init(&sdev->as, - MEMORY_REGION(&sdev->iommu), name); - trace_smmu_add_mr(name); - g_free(name); + smmu_init_sdev(s, sdev, bus, devfn); } =20 return &sdev->as; diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index b49b2f27fa..f5060cf36f 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -184,6 +184,12 @@ OBJECT_DECLARE_TYPE(SMMUState, SMMUBaseClass, ARM_SMMU) /* Return the SMMUPciBus handle associated to a PCI bus number */ SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num); =20 +/* Return the SMMUPciBus handle associated to a PCI bus */ +SMMUPciBus *smmu_get_sbus(SMMUState *s, PCIBus *bus); + +/* Initialize SMMUDevice handle associated to a SMMUPciBus */ +void smmu_init_sdev(SMMUState *s, SMMUDevice *sdev, PCIBus *bus, int devfn= ); + /* Return the stream ID of an SMMU device */ static inline uint16_t smmu_get_sid(SMMUDevice *sdev) { --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703250; cv=none; d=zohomail.com; s=zohoarc; b=MJfuL35osioSZV7Vd0C9q9FmwauIQNACCDb9jnGeGDD3MZE0hyJCHoJJ+6fk+YjtlEQRBQmZSycCd78XmBIMYHazGOcR5I/NyYg/esLPUPCx8viglZazu1T3BV+Px5VyAhXqyEKoAz3rC0OVYcDOVDf6bnSPtGHDWyRy98AM9Xc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703250; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=L9xXgSAQQ0ho77YnxVcq3hL9FgFenk/Ub66527/ohzQ=; b=jItvnHUQUNnBg62Z8BVGUoYa9xtFuu9lvbk6hzhaOyFqayxexdO/Jhvpg0wJyFp4gVit7D5vjCgORRyi8vRyVyqjg7LjBlePP8RBk9NyOun+3p0YnEu0fzi5IUtJIxbXT8h1vlTCyEwrGb/jq13j9P9DYa0vokvrcqQ8whClO2Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703250142316.49565713827826; Thu, 29 Jan 2026 08:14:10 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUaI-0008Rw-OJ; Thu, 29 Jan 2026 11:09:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaG-0008Qs-KY for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:28 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaE-0006XY-Gn for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:27 -0500 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-42fb4eeb482so894641f8f.0 for ; Thu, 29 Jan 2026 08:09:25 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702965; x=1770307765; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=L9xXgSAQQ0ho77YnxVcq3hL9FgFenk/Ub66527/ohzQ=; b=C2EU9eRwQy+7Q7+UmYE9Ih/TqCfYZvEtdZXDkHLHJKygP3R9wOxlbmSKCEjdBH5byO 71MgqXAojYaYjQdvGtgoFBXpcoYupO7sD7SwiDYl2GRqEBuTdZfWRvS73ypBRZXPiFvM ORuygTXBEeCJZQm4zsc0avE99ZIkgbz6zxMcxSBk5uMBQOu5d13jCknlw2DRVlEdVwdu VX5qpzrNgn0TJI1o7z4Nt9XhIpZX6U1MBZ68umPJLjqoDUAOP22JEncaKCCljh1siU/4 021YFKMsm9U2wSDxgDQIjag/szTakwfZRpvPtn9epV555qhiAPIoDaxb9PD59HClccfc AdwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702965; x=1770307765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=L9xXgSAQQ0ho77YnxVcq3hL9FgFenk/Ub66527/ohzQ=; b=tNFIkmb1YXjpbjSC/BjN5R+QdEgJKpAEJQ9qj+P2QRzvA5+oEwiEywuPtR99OFa9dV nzSjKrxhEzchcOTUU3aZsbtR9NUDki18UytwvDbFw5v2zxEq1eVnTicMdILWZDzN3rt3 +gUdpHC7L9fbYoH9Li0yo0NKjSqJ2KgReHIybDlWVvB408SICM818Nf/LVV4AqNqDsW1 RbdMVcds7MD2QJkKJqhMJc2Y1c1P82v7P+H2E/PY9EuELUX0MQHZC1D4MMlhCPckYWTk 3bzp6V2QLd/4vWSKZBQteUG5jiSM48yuwhg7lB+QcH1nYNI5URaS+rqIJzSpjDLCFuDo W39Q== X-Gm-Message-State: AOJu0YxKE8WLbR3OxBZ7yIaec0aJyyBoP0Cls7pBnUtnJPIWxu1jwHTC tWuE2NglnE3GUJWX8LSkzvgz1dBo6qn5cVHgdZQcm1f1XA2SMMWAzh7EhtDG+LIxDnKwu+ATqHw VjN6gM0Y= X-Gm-Gg: AZuq6aKHgd8GUyEHlxQr9qsQKe6VdA8hqLUWT5qZ76lms3UL4ZHcnP/LxKrLm00sl5z oC59j+COdJ7itH/YgefTPaV86GbPOfAS/lcOsczfuoQC5qMM5QS0eeI4cEj38X0jr3kjdNeSv49 wb1XNcEpJOGd70HZ0XKgV3yHTkfazNrolDVGNmnpzyFWcMRwGNSiq4zNLlpZJ5K2n63Z1iqxTvK lI6atgWDuSGgGdv2BK97lj47he1cZ0oJG69HacK8PObejnTLNLUl5ju2vv/kmxtpU+MC0PuFBtb gca1orl9BYSpnTVMobvoYSKu7JOh2BcQwH/ZqS2oJ4gih08QXZPHAQozzvaDuXdJLew10Ll1lcB j3xCh8EC/qrQtcdB7vVWjXak6I4g8vD56utIX2AgEilGYEUrquQ/RYLGFf4EJ85E7VkT7fHRFZ0 b5kTZ+IYjq1ZHM7bu16hJAlHWfpDZYjw== X-Received: by 2002:a05:6000:26cd:b0:430:f7c9:94c3 with SMTP id ffacd0b85a97d-435f3a864dcmr188130f8f.25.1769702964597; Thu, 29 Jan 2026 08:09:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/43] hw/arm/smmu-common: Make iommu ops part of SMMUState Date: Thu, 29 Jan 2026 16:08:38 +0000 Message-ID: <20260129160917.1415092-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703251382154100 From: Shameer Kolothum Make iommu ops part of SMMUState and set to the current default smmu_ops. No functional change intended. This will allow=C2=A0SMMUv3 accel implementa= tion to set a=C2=A0different=C2=A0iommu ops later. Reviewed-by: Jonathan Cameron Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Zhangfei Gao Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-5-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmu-common.c | 7 +++++-- include/hw/arm/smmu-common.h | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 1492d7dd95..58c4452b1f 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -959,6 +959,9 @@ static void smmu_base_realize(DeviceState *dev, Error *= *errp) "smmu-secure-memory-view"); } =20 + if (!s->iommu_ops) { + s->iommu_ops =3D &smmu_ops; + } /* * We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based e= xtra * root complexes to be associated with SMMU. @@ -978,9 +981,9 @@ static void smmu_base_realize(DeviceState *dev, Error *= *errp) } =20 if (s->smmu_per_bus) { - pci_setup_iommu_per_bus(pci_bus, &smmu_ops, s); + pci_setup_iommu_per_bus(pci_bus, s->iommu_ops, s); } else { - pci_setup_iommu(pci_bus, &smmu_ops, s); + pci_setup_iommu(pci_bus, s->iommu_ops, s); } return; } diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index f5060cf36f..7b975abc25 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -166,6 +166,7 @@ struct SMMUState { AddressSpace memory_as; MemoryRegion *secure_memory; AddressSpace secure_memory_as; + const PCIIOMMUOps *iommu_ops; }; =20 struct SMMUBaseClass { --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769702980; cv=none; d=zohomail.com; s=zohoarc; b=I2ui6jKAqt80F5NqJ4cOcWae1RVXaxAnp12s5clp/5O4BZf6q1mJE91hTSX5B5KEwYDKC28ixmqej7HxZKPo4cpH+ZiCAfuhzB5CEQyPd8B3gJw1ySdyDmYzidZL3YlNUP8PHv4By91cy52Vy/lK2w1S3b2T+vENuf3TdPgcKh0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769702980; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=vSfhDkCekIUYfdNzWRcVdLrx+XPd/qEmA3R+NEN9G0A=; b=bf35DBGjaS9AERLT7Ye0YJ0sZ9QbU0mw+IVVMkR7ylZKplKkeHR3H0R8xhjgLAU+/CcTWZacGvpZ/Nood7Rz7jnDfFoLQi3QIKGAh3SXPFV+IF4jKYo0VNBIWIjeYP/2fYiAIPANyu2O+OMRi+V0naZS2NSpJl33oFsV1zxg9tI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769702980194769.1067889722545; Thu, 29 Jan 2026 08:09:40 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUaL-0008Uk-So; Thu, 29 Jan 2026 11:09:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaI-0008Rs-HN for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:30 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaG-0006Y5-DG for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:30 -0500 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-42fbbc3df8fso931101f8f.2 for ; Thu, 29 Jan 2026 08:09:27 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702966; x=1770307766; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=vSfhDkCekIUYfdNzWRcVdLrx+XPd/qEmA3R+NEN9G0A=; b=GGcqfDpTC+TtaYKKU1oTeU8QCe/xYvbEL9L38JjPINggM88urDhmBs9CfdHY5Z4JYs ph1NOKT1SVZFU4DS8RRQ1EyRX+8/JTDIxwBre+1MTU2kUWjirMhHkDoqfp568QHQcMp6 VkjXP2ZX8fpcF84cz8pVcimYNnBMGcCv8g6WrgRePVJ+mAnjTtgQjuetnVIo/Ge3vWH5 PW12phSYcpE2TIr/A52h+GW175Ej1HTraRMtzFui3tnkEZf2XTElhNCLbU6KCjwWT/Ur cSpjfxoaR+hZsu/gLQ79MUKLnymldzR8sUbJ2+NI9PDBNjWrk5xjxSdPzIa770VYOVbJ TEYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702966; x=1770307766; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=vSfhDkCekIUYfdNzWRcVdLrx+XPd/qEmA3R+NEN9G0A=; b=g//5n27ooPLgXay4akk2jzq4enDqa+v/W2y/8BtMedV070nksCPOoUK7vi558rA1k9 1J1KUfstVU/ZRDyaFLXapNw6HeI90PVj6gz7DGjb8rUxUxCR5QjIf/kB01c3pS3Jh9me Sw8mjKjuVg6fJ6xSb++0snoq2qsMIp60NgPD8aWM/nqTAEdGzA6Bm2/AzLVeyps44cwR ol8MPuOlJ5UqOojGAnFedIm7lN4sDqzv3MmTwPtZeX3CmuO6OI//pzn97xeItQIMLpxc iY04hVv+EGDZOBqbN3oA4RSrqRT+MxhhPGejJgQT6ZqCZzEo+W7VB8ewtnFalwQffyhR /2JQ== X-Gm-Message-State: AOJu0YwKxAtug7s1O8+q4SttGXEHlaVYOxbs6xi2dgNBdF3JmvHWXr26 aE6siyvlT+omjBbIysLysWui7OUZzGwqG4Cc4INeWRSBzJneJxhLB7JAW0h+jpxkkRzglO9+joU H/J5H5PA= X-Gm-Gg: AZuq6aI95/4faJnRKCLVsajgdLhLBbixSX8v0HH6KvGcBaIsx2prhT9RS2wuVwaQUp1 tzOF4F4YDoCl3jxJ3Ft5UWUMx8LSd6g/1jPeVJ7+TsmTQPJ+GwbsTj0Vc2ZQlSBUMHEduOe7bdJ vPZZkUxyPoFiCTo0ynhtse0Yo+dHzr8rwZurafjzwnBrk0KvJgaX32sTl6RwCjngjUO9+WkyOD+ /PEqbwdN4whGNFP9TSruPRikdZrN6JFsCmKmZ9WXjlJuTKiR3BLNhyLbgfVyda83qORQSMPHvsS guhtlojR80c5mFbrNE6hjfxhh+yDwr1rAa2xShqiF1pGpfkV/cg/Zr8ZjTNoxpUsdNLiLenXVxM YHtSuLoSxDh/F9ExC8sjMAyT75kZhwbQWt3z22HCvXwlsYBkYuuBOiexPJs4N9HMwjU9Xj6CXHB Tw+VlfXMaOY0B274Zj3KTDr250I5331g== X-Received: by 2002:a5d:64c7:0:b0:432:5c34:fb22 with SMTP id ffacd0b85a97d-435f3a7bee5mr169962f8f.22.1769702965784; Thu, 29 Jan 2026 08:09:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/43] hw/arm/smmuv3-accel: Introduce smmuv3 accel device Date: Thu, 29 Jan 2026 16:08:39 +0000 Message-ID: <20260129160917.1415092-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769702981610154100 From: Shameer Kolothum Set up dedicated PCIIOMMUOps for the accel SMMUv3, since it will need different callback handling in upcoming patches. This also adds a CONFIG_ARM_SMMUV3_ACCEL build option so the feature can be disabled at compile time. Because we now include CONFIG_DEVICES in the header to check for ARM_SMMUV3_ACCEL, the meson file entry for smmuv3.c needs to be changed to arm_ss.add. The =E2=80=9Caccel=E2=80=9D property isn=E2=80=99t user visible yet and it = will be introduced in a later patch once all the supporting pieces are ready. Signed-off-by: Shameer Kolothum Reviewed-by: Nicolin Chen Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Zhangfei Gao Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-6-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/Kconfig | 5 ++++ hw/arm/meson.build | 3 ++- hw/arm/smmuv3-accel.c | 59 +++++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 27 +++++++++++++++++++ hw/arm/smmuv3.c | 5 ++++ include/hw/arm/smmuv3.h | 3 +++ 6 files changed, 101 insertions(+), 1 deletion(-) create mode 100644 hw/arm/smmuv3-accel.c create mode 100644 hw/arm/smmuv3-accel.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 97d747e206..c66c452737 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -626,8 +626,13 @@ config FSL_IMX8MP_EVK depends on TCG select FSL_IMX8MP =20 +config ARM_SMMUV3_ACCEL + bool + depends on ARM_SMMUV3 + config ARM_SMMUV3 bool + select ARM_SMMUV3_ACCEL if IOMMUFD =20 config FSL_IMX6UL bool diff --git a/hw/arm/meson.build b/hw/arm/meson.build index aeaf654790..c250487e64 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -84,7 +84,8 @@ arm_common_ss.add(when: 'CONFIG_ARMSSE', if_true: files('= armsse.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'm= cimx7d-sabre.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: files('fsl-imx8mp.c'= )) arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-ev= k.c')) -arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) +arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) +arm_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true: files('smmuv3-accel.c= ')) arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c'= , 'mcimx6ul-evk.c')) arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) arm_common_ss.add(when: 'CONFIG_XEN', if_true: files( diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c new file mode 100644 index 0000000000..99ef0db8c4 --- /dev/null +++ b/hw/arm/smmuv3-accel.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd + * Copyright (C) 2025 NVIDIA + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "hw/arm/smmuv3.h" +#include "smmuv3-accel.h" + +static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *= sbus, + PCIBus *bus, int devfn) +{ + SMMUDevice *sdev =3D sbus->pbdev[devfn]; + SMMUv3AccelDevice *accel_dev; + + if (sdev) { + return container_of(sdev, SMMUv3AccelDevice, sdev); + } + + accel_dev =3D g_new0(SMMUv3AccelDevice, 1); + sdev =3D &accel_dev->sdev; + + sbus->pbdev[devfn] =3D sdev; + smmu_init_sdev(bs, sdev, bus, devfn); + return accel_dev; +} + +/* + * Find or add an address space for the given PCI device. + * + * If a device matching @bus and @devfn already exists, return its + * corresponding address space. Otherwise, create a new device entry + * and initialize address space for it. + */ +static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void *opaque, + int devfn) +{ + SMMUState *bs =3D opaque; + SMMUPciBus *sbus =3D smmu_get_sbus(bs, bus); + SMMUv3AccelDevice *accel_dev =3D smmuv3_accel_get_dev(bs, sbus, bus, d= evfn); + SMMUDevice *sdev =3D &accel_dev->sdev; + + return &sdev->as; +} + +static const PCIIOMMUOps smmuv3_accel_ops =3D { + .get_address_space =3D smmuv3_accel_find_add_as, +}; + +void smmuv3_accel_init(SMMUv3State *s) +{ + SMMUState *bs =3D ARM_SMMU(s); + + bs->iommu_ops =3D &smmuv3_accel_ops; +} diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h new file mode 100644 index 0000000000..0dc6b00d35 --- /dev/null +++ b/hw/arm/smmuv3-accel.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd + * Copyright (C) 2025 NVIDIA + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ARM_SMMUV3_ACCEL_H +#define HW_ARM_SMMUV3_ACCEL_H + +#include "hw/arm/smmu-common.h" +#include CONFIG_DEVICES + +typedef struct SMMUv3AccelDevice { + SMMUDevice sdev; +} SMMUv3AccelDevice; + +#ifdef CONFIG_ARM_SMMUV3_ACCEL +void smmuv3_accel_init(SMMUv3State *s); +#else +static inline void smmuv3_accel_init(SMMUv3State *s) +{ +} +#endif + +#endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 985dfb345f..95d44f81ed 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -32,6 +32,7 @@ #include "qapi/error.h" =20 #include "hw/arm/smmuv3.h" +#include "smmuv3-accel.h" #include "smmuv3-internal.h" #include "smmu-internal.h" =20 @@ -1882,6 +1883,10 @@ static void smmu_realize(DeviceState *d, Error **err= p) SysBusDevice *dev =3D SYS_BUS_DEVICE(d); Error *local_err =3D NULL; =20 + if (s->accel) { + smmuv3_accel_init(s); + } + c->parent_realize(d, &local_err); if (local_err) { error_propagate(errp, local_err); diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index d183a62766..bb7076286b 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -63,6 +63,9 @@ struct SMMUv3State { qemu_irq irq[4]; QemuMutex mutex; char *stage; + + /* SMMU has HW accelerator support for nested S1 + s2 */ + bool accel; }; =20 typedef enum { --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769702997; cv=none; d=zohomail.com; s=zohoarc; b=X3K/YbazgOQqcb54DCQg9fB74EcG6gA7k1O0LZPFWOnXEoCQ+KxmMUdm1vtz2dV7+pYuLf34EDsHAc30osL4DMTts5i7MuFTnvYHymq6OU6PLXXwBTUD42IwXT++46OuDKrZgNRqAsdQioGRAb+bp2BtPxLfhUnePjQ/+2cDc9U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769702997; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=8pC6F/zj3QNaYDR/bID0RLslNcwqHXMeuqDP6SLHYeY=; b=DcnPpjqHu829uPJQizSsoi7M4NphmDT5S5LQEMXk2oBIGaNSqbED/9M9cJkfL+6Pnh3wFRJlStuEL8QVYQUXxHORe5vDSF4epqZTFIciMjT40SrizLhF4hW1aBSWB+rNqI8qF/S/JTTs7CgpwEcHNYE11kDFBbHQoL6kAK1rzMQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769702997145848.7783032392365; Thu, 29 Jan 2026 08:09:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUaL-0008Ug-S9; Thu, 29 Jan 2026 11:09:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaJ-0008SR-MP for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:31 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaG-0006YI-HL for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:31 -0500 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-4327555464cso973485f8f.1 for ; Thu, 29 Jan 2026 08:09:28 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702967; x=1770307767; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8pC6F/zj3QNaYDR/bID0RLslNcwqHXMeuqDP6SLHYeY=; b=zhpaf4xYqNleBOSx2gHy58TCVvoGJfsA3mM6MbDV/wWQX9T1VSpf45MaHe1FrAd3Tb M6mnkNGA4ptwCalHa+hcKCbXBvTSBKpJ0FRqOIt0zyYzDI9F+bVJf38cogKUDYF/Cpze OxOvS0oAmhM7M9Q1tXOh7CkHRNf461JZrjSkLxILVuljDPopNywKrueEcWNu01Zk6hjs UsM2VjU7wwunXe++F9WHUNL6sHgf2/wZ4SlZlVUehqoFAd1XVxKpxurRMV3hYqX4u0ID tBPqKLFZcjCmwTFptN6X475wTPj8qIF9UmT9a+1LeCgUtJ7WdYICzGOOi4weL8qct+4M oO+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702967; x=1770307767; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=8pC6F/zj3QNaYDR/bID0RLslNcwqHXMeuqDP6SLHYeY=; b=S2ZjZI73ai1NGtIkuwvRcBhWRYZt6KmJov8C8sf5A3rwcD9YGl2AGWUNvEsNTAURxV +peogkn1sZOZXTDbSiFo271GXyJlhCIxc4wzuLOqZZLpQm4eEMSRxJAXoAvoroug0Sno czMYHet2pUqDbBAapbJPrW6kj/+YR+ShLKfStw/PbdhIzc2xiPrMDSMMt/oXLHXPIBdB Cyi0SUU+ihybv+pSgsjc5F97EOQHee8auV95qIzOgPLFP3bV8DLr6jQiqBJUMKQXsvLo Y9OadzsRmfXuH4hyZuG5C6ZQ+yZcaI1cUiOTx3t1mknh7qOFFmZ+HiBGTjLC3vXJX42u bqaQ== X-Gm-Message-State: AOJu0Yzzyn+Dta5l3+cHmPhmxkGOVdzStga5rT5wjYWqJKYFDjTOspxF JQEZyqM3czsf0V7yynT61j7zvci3LMSMV/Lw9aEzUJNSORJxF0nvQEpEUk85Dc6SHAllfNConNL O/ZPIRps= X-Gm-Gg: AZuq6aLnA3kU3bbjan5xhZ67Oi+0MH+M5auBaqrPebMZaA2ec23Ah0TJNe3h8g1orUk fHJDGT9aXIDtNpImqOabF2mG5mIYwbkGAqK5hipT4NQ5vmtJetep6pIvj29sji6urzN+jaDN9gG bhEUwkBkZtNlqrNLk6e7Hk1f8N8BSdD8v3bQDSKA/4pQbPvbetxmRx47Z7HO3xU+Nj48rCHKqn3 YsWAh6OKQqe8RkzYt9VRhldOMx6ihM40PkcvUTDhfTDaAeYdY+RTut7U31r6j/b3ubS3LHCSLG6 MeffGG8LA5Fnf+WZPnGABD+hLxgHw87AjswBRqrfWFs54vW2NR+BtSjMCIlS2oU7UpdKdshy/P1 Wi6ew+3qAkbZrvSzhTEVUxKgSkv912ZCtKZWhi3HAy+zdK7wMgcB7dh10HpGeoDrub/GPmlfeHn 8+SKVfI1Pb0jHNd6vFhhCbUCYP2O4o1Q== X-Received: by 2002:a5d:5f54:0:b0:431:3a5:d9ae with SMTP id ffacd0b85a97d-435f3a6cc94mr184486f8f.4.1769702967096; Thu, 29 Jan 2026 08:09:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/43] hw/arm/smmuv3-accel: Initialize shared system address space Date: Thu, 29 Jan 2026 16:08:40 +0000 Message-ID: <20260129160917.1415092-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769702999367154100 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum To support accelerated SMMUv3 instances, introduce a shared system-wide AddressSpace (shared_as_sysmem) that aliases the global system memory. This shared AddressSpace will be used in a subsequent patch for all vfio-pci devices behind all accelerated SMMUv3 instances within a VM. Sharing a single system AddressSpace ensures that all devices behind accelerated SMMUv3s use the same system address space pointer. This allows VFIO/iommufd to reuse a single IOAS ID in iommufd_cdev_attach(), enabling the Stage-2 page tables to be shared within the VM rather than duplicated for each SMMUv3 instance. Reviewed-by: Nicolin Chen Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Zhangfei Gao Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-7-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 99ef0db8c4..b2eded743e 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -11,6 +11,14 @@ #include "hw/arm/smmuv3.h" #include "smmuv3-accel.h" =20 +/* + * The root region aliases the global system memory, and shared_as_sysmem + * provides a shared Address Space referencing it. This Address Space is u= sed + * by all vfio-pci devices behind all accelerated SMMUv3 instances within = a VM. + */ +static MemoryRegion root, sysmem; +static AddressSpace *shared_as_sysmem; + static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *= sbus, PCIBus *bus, int devfn) { @@ -51,9 +59,27 @@ static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_address_space =3D smmuv3_accel_find_add_as, }; =20 +static void smmuv3_accel_as_init(SMMUv3State *s) +{ + + if (shared_as_sysmem) { + return; + } + + memory_region_init(&root, OBJECT(s), "root", UINT64_MAX); + memory_region_init_alias(&sysmem, OBJECT(s), "smmuv3-accel-sysmem", + get_system_memory(), 0, + memory_region_size(get_system_memory())); + memory_region_add_subregion(&root, 0, &sysmem); + + shared_as_sysmem =3D g_new0(AddressSpace, 1); + address_space_init(shared_as_sysmem, &root, "smmuv3-accel-as-sysmem"); +} + void smmuv3_accel_init(SMMUv3State *s) { SMMUState *bs =3D ARM_SMMU(s); =20 bs->iommu_ops =3D &smmuv3_accel_ops; + smmuv3_accel_as_init(s); } --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703206; cv=none; d=zohomail.com; s=zohoarc; b=SHoNa+pl4ehn7Ib87t3soXR3FfE8RtBI3P2Bnt1bsgNcbl4Jd/J7JB4Igmq+9GPT/Sz9V8A7Lor424xQf7MqEkn55G2XVNWItdDfdiuzgYxantXImXDIl8I799ZzFffdwOFSFlhWPhwOkKffVWzt2Zt7wkodRWcAhDFBNWMQuKI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703206; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=8uo5dKYAD+vYGvFL/kQyxMD5SHu1nUB/IkGWYYMNAkw=; b=b3nWu6xMlL7E1lxV4cKTM34YGAp4j+yekCzqy5iE9Xcpc/gla0faLI4b82A0xlJea+vp4oPbFte546udHiLwdjL1Ykunr59W0XsKa/rZ/GkCJ+84823tYiwwHbL+OA9T1YZfVIxYv7KEmAZqRi0ncsRTzRz+m5PjCJVOQsS67M8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703206139394.8663647171221; Thu, 29 Jan 2026 08:13:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUaM-0008Vd-LG; Thu, 29 Jan 2026 11:09:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaK-0008Sd-2s for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:32 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaI-0006YW-9L for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:31 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4801bc32725so8868545e9.0 for ; Thu, 29 Jan 2026 08:09:29 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702968; x=1770307768; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8uo5dKYAD+vYGvFL/kQyxMD5SHu1nUB/IkGWYYMNAkw=; b=uPyOzanG1O3grTLdoWeSl4hXa31gKpaAtBm0VfyEM9eDUWS1HmXNvMFrkCJBEA7rg8 /bu89aEGnpK7aYClnkz1cMfdc2/IQ2zmeJgiakDTOKTKx2XltJoME1fsRM/Rbc/okS7t 1f6mHseGpwQdl8Te/tpUm3VdhJNFiLsqzv+M1054Jp0akFjLKAFgrUyAFUy79gsl29gY mgedUbhzFHt+AFvBSjuK5smKocSIKVhHuznxABd8ywNzCqLczI1KglROUNDB/DJ6GtKA QSVrGRuQx36gCxqcQpTWCYQrkVBM7L/VUsou4bUL2VJWZJ+dmQMKTCT/BFGntQz75gx7 e39Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702968; x=1770307768; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=8uo5dKYAD+vYGvFL/kQyxMD5SHu1nUB/IkGWYYMNAkw=; b=roRM1pzyBMEbhfe7ApNwuGXOr4u3to9W5iZRy8zE23sU5BphVpzMgUkQmOEzGIZSmn 1JAq+a6BnRv4pF4aG4jKMceDOdxyj2OeI7vuPqTCfgwL9yWStTO8jr3FFKskdIbFxIve lESEjSh3areOqfFHshDZi8INkCMKEzsJuv+wIK8xD51vhaBn4i7qwWOmM7eYxxXk4Uhg EsrE8zLB3vXZQ+wJhPME+NZMHhWT3SryhRfr9WKJdzZ8V/urm+Revh5ihfL7sAPXlmF8 vyyj3tSQqdgypJdI9ateNrmTR5yfOarl+scnK4MPl+YYh3Ra7Ee/3PTOlyvmWy0bruGC xtzg== X-Gm-Message-State: AOJu0YyfQ6x/ons55iddm7v//KFv2ehkGdCbEUWaQrrSSsHND2SQvCDC tggit14oFcttQ7WhTWSPfZONepjun18bLBySc615yEZvY3UPUmfYD3at3kXEkGEh05O552wZEp7 m541/FIo= X-Gm-Gg: AZuq6aJO7kFBOhfouKyTAUCRuwvf8KZG17xJXQ43iDVUGvMYUdY4NvhKmqs3Dk0RFsy h+Lai8OvaVe/9PBHkrOT3BG20g7BNWn7UEJIj1S3qswuNihwGigHl7TPuGWFiw7Fn0m7HkF5m9K A5VkKveKG/VfMKQMDAAGTGdY0Gi93ztfTNz3GlJOVFTaFIV++0JsZMbRLwOGkGyJJiIPAYA8c9c Fl2wxI719a0OwNDgDzaK+1l6ZR4Z78zYpQgnRI0iJZVgeVoR/N5n4IYSIEMOocyIpB9jFw9iaC1 MwU+J0eOkzgE+D9k5hqmvHBp3Tc6ST/QhVRrDz8G6x+tJ6sIk3pTeyMuw8j8IruPW+k7rMdZi/i AFibi+piSm6VlwfKOs49nZcZ6D4QkQG7Qx/gGst5kYpOxz7/bhckASKG4vCRKsHGNZS2ekb1Sdl Msmwmhaj9NjcJfbklniOovZ3V4u81G7Q== X-Received: by 2002:a05:600c:1994:b0:480:1c2f:b003 with SMTP id 5b1f17b1804b1-48069c788e8mr115791675e9.20.1769702968337; Thu, 29 Jan 2026 08:09:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/43] hw/pci/pci: Move pci_init_bus_master() after adding device to bus Date: Thu, 29 Jan 2026 16:08:41 +0000 Message-ID: <20260129160917.1415092-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703208482154100 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum During PCI hotplug, in do_pci_register_device(), pci_init_bus_master() is called before storing the pci_dev pointer in bus->devices[devfn]. This causes a problem if pci_init_bus_master() (via its get_address_space() callback) attempts to retrieve the device using pci_find_device(), since the PCI device is not yet visible on the bus. Fix this by moving the pci_init_bus_master() call to after the device has been added to bus->devices[devfn]. This prepares for a subsequent patch where the accel SMMUv3 get_address_space() callback retrieves the pci_dev to identify the attached device type. No functional change intended. Cc: Michael S. Tsirkin Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Reviewed-by: Michael S. Tsirkin Tested-by: Eric Auger Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum Reviewed-by: Yi Liu Message-id: 20260126104342.253965-8-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/pci/pci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 8cbf5f5d70..229ea7cfb1 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -1381,9 +1381,6 @@ static PCIDevice *do_pci_register_device(PCIDevice *p= ci_dev, pci_dev->bus_master_as.max_bounce_buffer_size =3D pci_dev->max_bounce_buffer_size; =20 - if (phase_check(PHASE_MACHINE_READY)) { - pci_init_bus_master(pci_dev); - } pci_dev->irq_state =3D 0; pci_config_alloc(pci_dev); =20 @@ -1427,6 +1424,9 @@ static PCIDevice *do_pci_register_device(PCIDevice *p= ci_dev, pci_dev->config_write =3D config_write; bus->devices[devfn] =3D pci_dev; pci_dev->version_id =3D 2; /* Current pci device vmstate version */ + if (phase_check(PHASE_MACHINE_READY)) { + pci_init_bus_master(pci_dev); + } return pci_dev; } =20 --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703047; cv=none; d=zohomail.com; s=zohoarc; b=PCDt9R7A4uBE6AKeUJr13HIdlllL5aRqQfw6lQgkYL/fabBsB4cJogQhui45WvrDicWyOlFSfUEBCuahqRK08gmdSPfTT7XxphEMKzSj3VhUGnBn9qfW9yFbw48E/hI4AALyEjblxfG//KYnFNurph3wdtgBojlHe3AjJM5DC+g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703047; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=0+bTXNZrF8nEHoS/zxRQKgSxIuUNxJKWJE+/JYInqmk=; b=C8ngV49orFh/YQnUCZoInTEh/K7vYqq5DQqP8SMiSMPUySVRflnZ8EeJwhDmo3laWeh8Q5WpwCI+X+WtgzDPtfm6sKYVGlpiMk6VXiwsoKzrmZO9K5SDYy/SK/tM64C5LO9HPgjeUHKNsblIneRUgBJQxSNBXG6pTqEJ0isLBJg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703047725858.9360781134942; Thu, 29 Jan 2026 08:10:47 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUaV-00008f-GM; Thu, 29 Jan 2026 11:09:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaL-0008Ua-EZ for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:33 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaJ-0006Zi-L5 for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:33 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-4807068eacbso9920035e9.2 for ; Thu, 29 Jan 2026 08:09:31 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702970; x=1770307770; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0+bTXNZrF8nEHoS/zxRQKgSxIuUNxJKWJE+/JYInqmk=; b=aSPnj+sphKWcpFW+EoWAioFyWPxVx+LXgf6pF9faibMCHt+5WIIEBb8kOK3QNN2Zsd odKRHjA+MTweTdH2ZhJZdMIencE6ejBQI4DSvCiTCa065e9LzCGTW//SZVag8hTAWM1U wPonPbFCdMFsEB8SjJyfsT0BYsNEcZAd+U+aCfoNVs6X1U94TZpQ/biUlqU7/oiWTcj9 AcVZf9zv60Hc3UvDup4whQvKra6xK8cSkLH7lkQx7g9TJSxR0fPTcDi3XIoHfvqTlJ5u fYr/FNAwH7NszkOCf/xH3kTRV3CsDcqR0e/6a2VOlzzzqD1TqZQGZNUJJdd5yhk34vJW SLHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702970; x=1770307770; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=0+bTXNZrF8nEHoS/zxRQKgSxIuUNxJKWJE+/JYInqmk=; b=rNdMYMYAV0V9r8Hx3SVxL2f85VfVrTMIDvCdjp8e+mGLQ4L/rUAIZHKOcDZiNl7RTY hOK/Td/tUJyYMMqTQHWdZmsxCaXL02AxKV5R2V0H5Eiqq56G9Rhau3qYlk9VEOGy2aKY sFZcfQztOBF/4UD6G9VUTPfqzM1evdkQySlvQ+TKTydh85BEWRAbsmPBvSTgq81IlPEb WCMDHu2paKjDz2Zxftq6Q4glgepZujqRnwRHTcpkTv8U7KBK+43NbAHxX5ec/gapJedC zl12Dw3lP/dUgtDlfJ4VdZpeyqrRgEDobTzzFmLZ3YIIKXmWfjUouMZYNtq9U2J3kYeJ xqog== X-Gm-Message-State: AOJu0YzYzfJElUGXO62YCwPpKjaeGwVPZ7fdO8dBQfRBcLpeVNP9EJQV BiAYL4Ok2dl9XkbN6LJUobBzvXYFXfGw6Kt89ePWB23El59igy25r0uiZTb6fI/3Xdy0pzuHTjP 8PfftFfM= X-Gm-Gg: AZuq6aJWSXSJn+0CgAY0+C9Xbe/rn6nORe8xGrI7pxHYjpe9AF7MgTVOQ3730ThZpff I/IGn+IbRI6mJXBSs2PK+OExa217rN4908E8p+XXF6xVFYPrTgLsYHmjGrMjj9Sw7L+njFem6/s wh5IB60sktu0TESqpEfgKf7u4lDg8lbUMGZGpcehLGEHGgjITgjJtLZoLfIWBmOtt9LzAmX5Xl7 /zLSEbfH2RADdylroBEKvz2XZtZxK7hZhvLI2pL+cGXZk1IQs3+uLcLtWAHzugjGhL5UnwtJlUk NmRaCNe5Ut+qPPfgzMxcBI1nycZNgoQvFNFYxmqNufh1RKx2jsJG5WSi8gk8nZO1HhrCb8w/vYg nB7iYQ4yjO8qgfMEUufjNqp48pbpgTKH+8ZAYnBrWcnu5dj4z3QdypDwTtMHMyQVqpffx4iN3L4 tV07YCNeGzDdJnpz5/eybEymKDtjK7rA== X-Received: by 2002:a05:600c:1990:b0:47b:deb9:15fb with SMTP id 5b1f17b1804b1-48069c8a660mr129120445e9.33.1769702969506; Thu, 29 Jan 2026 08:09:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/43] hw/pci/pci: Add optional supports_address_space() callback Date: Thu, 29 Jan 2026 16:08:42 +0000 Message-ID: <20260129160917.1415092-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703049022158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Introduce an optional supports_address_space() callback in PCIIOMMUOps to allow a vIOMMU implementation to reject devices that should not be attached to it. Currently, get_address_space() is the first and mandatory callback into the vIOMMU layer, which always returns an address space. For certain setups, su= ch as hardware accelerated vIOMMUs (e.g. ARM SMMUv3 with accel=3Don), attaching emulated endpoint devices is undesirable as it may impact the behavior or performance of VFIO passthrough devices, for example, by triggering unnecessary invalidations on the host IOMMU. The new callback allows a vIOMMU to check and reject unsupported devices early during PCI device registration. Cc: Michael S. Tsirkin Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Reviewed-by: Michael S. Tsirkin Tested-by: Eric Auger Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum Reviewed-by: Yi Liu Message-id: 20260126104342.253965-9-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/pci/pci.c | 20 ++++++++++++++++++++ include/hw/pci/pci.h | 19 +++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 229ea7cfb1..101e745bd5 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -135,6 +135,21 @@ static void pci_set_master(PCIDevice *d, bool enable) d->is_master =3D enable; /* cache the status */ } =20 +static bool +pci_device_supports_iommu_address_space(PCIDevice *dev, Error **errp) +{ + PCIBus *bus; + PCIBus *iommu_bus; + int devfn; + + pci_device_get_iommu_bus_devfn(dev, &iommu_bus, &bus, &devfn); + if (iommu_bus && iommu_bus->iommu_ops->supports_address_space) { + return iommu_bus->iommu_ops->supports_address_space(bus, + iommu_bus->iommu_opaque, devfn, errp); + } + return true; +} + static void pci_init_bus_master(PCIDevice *pci_dev) { AddressSpace *dma_as =3D pci_device_iommu_address_space(pci_dev); @@ -1424,6 +1439,11 @@ static PCIDevice *do_pci_register_device(PCIDevice *= pci_dev, pci_dev->config_write =3D config_write; bus->devices[devfn] =3D pci_dev; pci_dev->version_id =3D 2; /* Current pci device vmstate version */ + if (!pci_device_supports_iommu_address_space(pci_dev, errp)) { + do_pci_unregister_device(pci_dev); + bus->devices[devfn] =3D NULL; + return NULL; + } if (phase_check(PHASE_MACHINE_READY)) { pci_init_bus_master(pci_dev); } diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 6fd8984c99..ddb0c98e9f 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -417,6 +417,25 @@ typedef struct IOMMUPRINotifier { * framework for a set of devices on a PCI bus. */ typedef struct PCIIOMMUOps { + /** + * @supports_address_space: Optional pre-check to determine whether a = PCI + * device can be associated with an IOMMU. If this callback returns tr= ue, + * the IOMMU accepts the device association and get_address_space() ca= n be + * called to obtain the address_space to be used. + * + * @bus: the #PCIBus being accessed. + * + * @opaque: the data passed to pci_setup_iommu(). + * + * @devfn: device and function number. + * + * @errp: pass an Error out only when return false + * + * Returns: true if the device can be associated with an IOMMU, false + * otherwise with errp set. + */ + bool (*supports_address_space)(PCIBus *bus, void *opaque, int devfn, + Error **errp); /** * @get_address_space: get the address space for a set of devices * on a PCI bus. --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769702995; cv=none; d=zohomail.com; s=zohoarc; b=X7WVHmIt3EA0TWKy1wc6TPuWFihRR4nchQBt35Zd0fm3UjkTzbHnJfvF5WEea0C/RyDwwwxR4KV9jdR3ZS0Z12PgKUPq6VjVwQvS/uN+Yj6JV35qPeSoGdwqAF+V+kp5gRFS+gDiaLkPRZ5edstNdBY3N6jxMXeC88d4lkZOQfs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769702995; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Z13uXKrf8/Vg9Np7XNzNgTT9vT/RUmS7H/xdYMAPddE=; b=jQp2IFR/uumQMFXzvBAPZ1Zp9ZeAxngQuXqNBgBhkRgXJdeIWe2K8fdlzcCM0/AUm77YvEsb77J8qN2naBAty3JxK6oqQ3Q4PyilxhGsSj0zwutG8YR1TdlB1fv7xpQb1nDGQPy7sFvDQ8j9TXTkPiBAl0X6Q5tMeZI0z95fJ18= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769702995329461.2670738115644; Thu, 29 Jan 2026 08:09:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUab-0000AG-Lk; Thu, 29 Jan 2026 11:09:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaM-0008VX-8Q for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:34 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaK-0006Zn-K1 for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:34 -0500 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-432d256c2e6so1100886f8f.3 for ; Thu, 29 Jan 2026 08:09:31 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702971; x=1770307771; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Z13uXKrf8/Vg9Np7XNzNgTT9vT/RUmS7H/xdYMAPddE=; b=PWl2V6KYHUPKM74wuIOKAD6p53VuZ725qRifmGOICHAV/krcL1ruW+FLUmfDRU6BND /qGNRKfD4/7vsrEIcS5g+u7+C2S5yavCujHUvS1v/KWC2GvfLgxMQtxxyvVbb66xDen1 CjB2FhRuo1hZKlEPisDdGxqJnoQVfFofXjk5+MLlsejhxwHuiPCgvhe7STNiukRuj21Y C7yVl8wzD7h2pVkalFWvqZc8BfT1kphUrTMQWgAkpxvsCGjU1QGI9khxVlgjBN52Lxlt Q8iNFX53YS/0+OTNfl1Nw94v+/IFv9b+OXuTGFiB3Ux4Ylj5FX4KosSua7Ezob+aIhcF t0WQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702971; x=1770307771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Z13uXKrf8/Vg9Np7XNzNgTT9vT/RUmS7H/xdYMAPddE=; b=fzD8lGF1zqlU6bIx/kdOeQZwHk+tgAYrb/DvtE39kAcmAukXao/0W8c/rd6F/KOUKQ PMLWrhMev5PMESRryh33AwwvW+7eMM1ZRODH4WV7gjoW2R31dFZXKdHGyE8PfPXXzc5a eE9EJJ9+rmXS+4v/GVew02MdYjUPs5mN6j7TidbfSVt6Ws31e2chfialHAFtU/3x9Ub5 jXMkFea50CgW7TPVk/5zbL8M9RxLe8wJn2DlA7VASYiQ4VF7cg5P4tYRR0jajo13jq7J oitzjQJT2MKo1gvCRSidA2Asiuia6GaD1Y4VlaOdZpQPMFb3Z4Uu8HhKSAgfURnSj8Ip wc+Q== X-Gm-Message-State: AOJu0YzfU5IXHAwx3bADtRhsXIeFY+pnMtVU65Tv/UkeT9TbYkzJPmJ3 dmFbQjw2eClXtl1DfaAuTOajL56pfOc8FKpFwsAI/kE7PdCKr28p/YGpRPCP2/Y207dsKX5RK63 TSscDUag= X-Gm-Gg: AZuq6aLIHjkMPZO6IhVcayd/b/tSlDZd2DOPO+5e+JdmrgzyX4TEvC2frddMi3ShKg8 BtugszDhY0yUw7bKaM6aQJj9LNfoLW9cVAxunh2Gcpr7nUlhRbMiWKvUrflK2DgZ/5U/RsV+6hT 6VEgvwMnjj+5kch/5aOHL/Uq5CiQU40Zlnj8DkL6IE0Pz4v5We708gNZckpO4+3cnxcKp9EqPD8 AbCvLgsA+7tJP6Fg2EphbQwXxHFVspQGjcPmF5PaKR1tAEFM++Zgr8anFaL6k7PKGL4RIMWCzHT yUtKXj8+Sz9vwSmJ0aXr0QteYDJfA1sqJMaqopep8sjKsoiJWSAjGkUBuAhNYEwfG7y+BBC2RqJ 3evwXzfGvoBGAVPivXYBuzMYZtoqMw6LYdh8daRN9aVPRM673F+BHID0w/P1zYvuTJ5rWy0tzfM YlpKv8OCTfeGv5pX2TcMedYQ5ethhvXw== X-Received: by 2002:a5d:5f84:0:b0:434:24fe:b25f with SMTP id ffacd0b85a97d-435f3ab212bmr142176f8f.37.1769702970622; Thu, 29 Jan 2026 08:09:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/43] hw/pci-bridge/pci_expander_bridge: Move TYPE_PXB_PCIE_DEV to header Date: Thu, 29 Jan 2026 16:08:43 +0000 Message-ID: <20260129160917.1415092-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769702997421154100 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Move the TYPE_PXB_PCIE_DEV definition to header so that it can be referenced by other code in subsequent patch. Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Tested-by: Eric Auger Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum Reviewed-by: Yi Liu Message-id: 20260126104342.253965-10-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/pci-bridge/pci_expander_bridge.c | 1 - include/hw/pci/pci_bridge.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 08d40aa2ea..b6e2eb7969 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -48,7 +48,6 @@ struct PXBBus { char bus_path[8]; }; =20 -#define TYPE_PXB_PCIE_DEV "pxb-pcie" OBJECT_DECLARE_SIMPLE_TYPE(PXBPCIEDev, PXB_PCIE_DEV) =20 static GList *pxb_dev_list; diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index a055fd8d32..b61360b900 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -106,6 +106,7 @@ typedef struct PXBPCIEDev { =20 #define TYPE_PXB_PCIE_BUS "pxb-pcie-bus" #define TYPE_PXB_CXL_BUS "pxb-cxl-bus" +#define TYPE_PXB_PCIE_DEV "pxb-pcie" #define TYPE_PXB_DEV "pxb" OBJECT_DECLARE_SIMPLE_TYPE(PXBDev, PXB_DEV) =20 --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703115; cv=none; d=zohomail.com; s=zohoarc; b=W9MbQ41fnYmh/uZTzoISGvdKFFhiFY2xiy0KLKWjTsQLzm+y5IFWMLXhuY9VTWeqG7PVIyjJVZx7GmehpHXS2lFStEoKg9mpkOz2+fXDhzi/bteCqDbS+XRtiGsrQMEV0Z6ia5K2bonAv0YlLDkgDBi80rL2cd3ouVjMmb88ScQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703115; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=EdqpYAEo9HKKYO0HNXK8z4+e4Jb03at30j4c2u3DrAk=; b=AbXiPQHGx7S2wGjFFxjNO9gm3B31Wut9ljkitsKpJvuRaF8DLH1kbmmEhKaqiRL54mJkueg0GUuw0w/Sh6vWtUlY6UGL9ewRCvEQx+5Ma/bKMrqeN+rM7Lp/ZtF+PVi5ulQB2Rsw89nUvaAqkDpg0NwxUdSIzukZur0NQq9GmEE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176970311538346.29496687894027; Thu, 29 Jan 2026 08:11:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUaR-00005v-LP; Thu, 29 Jan 2026 11:09:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaN-000050-OF for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:35 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaL-0006a8-Cc for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:35 -0500 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-435903c4040so814445f8f.3 for ; Thu, 29 Jan 2026 08:09:32 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702972; x=1770307772; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=EdqpYAEo9HKKYO0HNXK8z4+e4Jb03at30j4c2u3DrAk=; b=sl23plPOUDgwjJumFO4SK5qqk0Tw643zERZDo013fpepZW0Y4V8OQl9SeUezWN1tWp iHOjXva3YWfm98iX5eYa8ixetgWVTyzY5flMpUOgKWQgElsU7wZ7Aycco2UeYjLA5KDy iUkI4fBigV3iLeuKY4P9tjnVTyVsEkFcFvcdZU/7sCRzkKCgsMo2EcChejCES/ir2ulO L9Oyh3AWpn6rDKRDVSUGoMAtlFZ23XR/rQGU2V0K15rAWl9Q4he596O+sq7G2tMLO5ak cAt8xZ8jSY3Qo1YoEW3VDCb4664MRhszx4OxoS7hN5Tq/LgOkj6M0uVbSnkV76lKgyVf vY8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702972; x=1770307772; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=EdqpYAEo9HKKYO0HNXK8z4+e4Jb03at30j4c2u3DrAk=; b=EltdR4zOmOkAw7xO5jKaZ8ASVRtL1gE9Aj0xibBAwAyLBpOTAdB6xqhlhL9PWP+POh W44dQPA68Y7f3eyuu/HzqVPFW+ybQeUSIs02f/8LR077OcJmqdm2dPV72wTQAnVcK0jo Nkxv4R6f47KYpX2Ks04jcz23pYooIiyMvqx/JdGqMmhq71rcvPnjfk8Pjmo/DoTZvudH rZ5449rXRVHCrSWofWx375g3iRiCPppsVc5nJ7xaC2k5x7lCEEknPTZtRV1BLHSceevJ /wd+zAeb605CUzWra/135mzt1VV0575/S0hSw53TEKxIUwqB/bIefdQVNIKuXLzP6age qiww== X-Gm-Message-State: AOJu0Yw+/GGh2m9QEs5ImbQGk98/OF9KuYEJGceGEaKJJ8sqB6tkED+/ 6Hre264tgL1Lo5xrSVRyKpx9YaEGVxHUZFQUkUv/dS5ESGYxaanbL7YxUIItieMDjrw3G45gUfM L3L1jpjU= X-Gm-Gg: AZuq6aI0vu6aeYXa0Vw6e32x8y76tNYZLu8dbe8FS33cyP9YNpp1CIZaAu930sMeh2C YJ0hbVG9x32KaMJQM7cCWjEgYmszt+wYlVFR4yEZ5PMADWZyJE09EAhyGs6xXobVGkAk2rs0/JI X377AXVWqBhBzC5zJgn9q+n982En8nMZBJdw/U6frGOFo+s4KCIl+Sa2FMMvsOMhGWf5NriOgY7 7HzAPL4qUJ9jhSIpvo95QC9chrzAQhl0RYPiu40zH3M56KBT90NFpMoyZZTvN1YEIXUQT3r4GGg ZWVT6BaolDC5Zu44PVrR5mX6DtPVRhsuFewuE00dgr+43Woe7iyaIvX2n0BImbOLee72WavbnS+ A26RMvklQoDCVoApisNhaJ4QF2QMQIAakAUlPhYlJ0mdsCoFeEOw8zeu2ZoAdVh4Sm4qIZaupHu Cr1smFlNCBVL6aGp4eyzbzp+ef8VFLzzH7NjJOqxEN X-Received: by 2002:a5d:5f47:0:b0:432:84f9:8c04 with SMTP id ffacd0b85a97d-435f3a86558mr177509f8f.24.1769702971731; Thu, 29 Jan 2026 08:09:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/43] hw/arm/smmuv3-accel: Restrict accelerated SMMUv3 to vfio-pci endpoints with iommufd Date: Thu, 29 Jan 2026 16:08:44 +0000 Message-ID: <20260129160917.1415092-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703117170158500 From: Shameer Kolothum Accelerated SMMUv3 is only meaningful when a device can leverage the host SMMUv3 in nested mode (S1+S2 translation). To keep the model consistent and correct, this mode is restricted to vfio-pci endpoint devices using the iommufd backend. Non-endpoint emulated devices such as PCIe root ports and bridges are also permitted so that vfio-pci devices can be attached downstream. All other device types are unsupported in accelerated mode. Implement supports_address_space() callback to reject all such unsupported devices. This restriction also avoids complications with IOTLB invalidations. Some TLBI commands (e.g. CMD_TLBI_NH_ASID) lack an associated SID, making it difficult to trace the originating device. Allowing emulated endpoints would require invalidating both QEMU=E2=80=99s software IOTLB and the host= =E2=80=99s hardware IOTLB, which can significantly degrade performance. A key design choice is the address space returned for accelerated vfio-pci endpoints. VFIO core has a container that manages an HWPT. By default, it allocates a stage-1 normal HWPT, unless vIOMMU requests for a nesting parent HWPT for accelerated cases. VFIO core adds a listener for that HWPT and sets up a handler vfio_container_region_add() where it checks the memory region. -If the region is a non-IOMMU translated one (system address space), VFIO treats it as RAM and handles all stage-2 mappings for the core allocated nesting parent HWPT. -If the region is an IOMMU address space, VFIO instead enables IOTLB notifier handling and translation replay, skipping the RAM listener and therefore not installing stage-2 mappings. For accelerated SMMUv3, correct operation requires the S1+S2 nesting model, and therefore VFIO must take the "system address space" path so that stage-2 mappings are properly built. Returning an alias of the system address space ensures this happens. Returning the IOMMU address space would omit stage-2 mapping and break nested translation. Another option considered was forcing a pre-registration path using vfio_prereg_listener() to set up stage-2 mappings, but this requires changes in VFIO core and was not adopted. Returning an alias of the system address space keeps the design aligned with existing VFIO/iommufd nesting flows and avoids the need for cross-subsystem changes. In summary: - vfio-pci devices(with iommufd as backend) return an address space aliased to system address space. - bridges and root ports return the IOMMU address space. Reviewed-by: Jonathan Cameron Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-11-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 77 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 76 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index b2eded743e..2fcd301322 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -7,8 +7,13 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/error-report.h" =20 #include "hw/arm/smmuv3.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci-host/gpex.h" +#include "hw/vfio/pci.h" + #include "smmuv3-accel.h" =20 /* @@ -37,6 +42,48 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState= *bs, SMMUPciBus *sbus, return accel_dev; } =20 +/* + * Only allow PCIe bridges, pxb-pcie roots, and GPEX roots so vfio-pci + * endpoints can sit downstream. Accelerated SMMUv3 requires a vfio-pci + * endpoint using the iommufd backend; all other device types are rejected. + * This avoids supporting emulated endpoints, which would complicate IOTLB + * invalidation and hurt performance. + */ +static bool smmuv3_accel_pdev_allowed(PCIDevice *pdev, bool *vfio_pci) +{ + + if (object_dynamic_cast(OBJECT(pdev), TYPE_PCI_BRIDGE) || + object_dynamic_cast(OBJECT(pdev), TYPE_PXB_PCIE_DEV) || + object_dynamic_cast(OBJECT(pdev), TYPE_GPEX_ROOT_DEVICE)) { + return true; + } else if ((object_dynamic_cast(OBJECT(pdev), TYPE_VFIO_PCI))) { + *vfio_pci =3D true; + if (object_property_get_link(OBJECT(pdev), "iommufd", NULL)) { + return true; + } + } + return false; +} + +static bool smmuv3_accel_supports_as(PCIBus *bus, void *opaque, int devfn, + Error **errp) +{ + PCIDevice *pdev =3D pci_find_device(bus, pci_bus_num(bus), devfn); + bool vfio_pci =3D false; + + if (pdev && !smmuv3_accel_pdev_allowed(pdev, &vfio_pci)) { + if (vfio_pci) { + error_setg(errp, "vfio-pci endpoint devices without an iommufd= " + "backend not allowed when using arm-smmuv3,accel=3D= on"); + + } else { + error_setg(errp, "Emulated endpoint devices are not allowed wh= en " + "using arm-smmuv3,accel=3Don"); + } + return false; + } + return true; +} /* * Find or add an address space for the given PCI device. * @@ -47,15 +94,43 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUStat= e *bs, SMMUPciBus *sbus, static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void *opaque, int devfn) { + PCIDevice *pdev =3D pci_find_device(bus, pci_bus_num(bus), devfn); SMMUState *bs =3D opaque; SMMUPciBus *sbus =3D smmu_get_sbus(bs, bus); SMMUv3AccelDevice *accel_dev =3D smmuv3_accel_get_dev(bs, sbus, bus, d= evfn); SMMUDevice *sdev =3D &accel_dev->sdev; + bool vfio_pci =3D false; =20 - return &sdev->as; + if (pdev && !smmuv3_accel_pdev_allowed(pdev, &vfio_pci)) { + /* Should never be here: supports_address_space() filters these ou= t */ + g_assert_not_reached(); + } + + /* + * In the accelerated mode, a vfio-pci device attached via the iommufd + * backend must remain in the system address space. Such a device is + * always translated by its physical SMMU (using either a stage-2-only + * STE or a nested STE), where the parent stage-2 page table is alloca= ted + * by the VFIO core to back the system address space. + * + * Return the shared_as_sysmem aliased to the global system memory in = this + * case. Sharing address_space_memory also allows devices under differ= ent + * vSMMU instances in the same VM to reuse a single nesting parent HWP= T in + * the VFIO core. + * + * For non-endpoint emulated devices such as PCIe root ports and bridg= es, + * which may use the normal emulated translation path and software IOT= LBs, + * return the SMMU's IOMMU address space. + */ + if (vfio_pci) { + return shared_as_sysmem; + } else { + return &sdev->as; + } } =20 static const PCIIOMMUOps smmuv3_accel_ops =3D { + .supports_address_space =3D smmuv3_accel_supports_as, .get_address_space =3D smmuv3_accel_find_add_as, }; =20 --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703188; cv=none; d=zohomail.com; s=zohoarc; b=Pwsp4zs6z0PS7qL6igCYIEehtVPTvciI2QENrTO5hvL7JC+lAhF/IIlx1zvkqz5OxzJsXUr5a3hZy6Ux0kkllSdDnTREjLSQIKS/US97sNigTy0oMFeSbxO3VAo1ta/Y745TFgx0qji670FnAhWx0VrKDZEcb11k2boWZzPNIps= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703188; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Ckk3q/EmqlkqmYKXWb5LjFCrWrKBLmaPbXOkEvFedwk=; b=Kp9r/BXZUMMM9klKmpSr9OczIP6htitUqQ+MieaQpmxC6semkQi6gZpby2sd5GwqMLCaG5TIZHX0zLFSjlRTEh77WofcskgQEiWmGk4e4FiqW9R+TorP4SUNKONWPPMntIo+1QxUYStFggy7IQgzx903hVQ2ptaPUQZsxHTydOc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703188216631.6595542393082; Thu, 29 Jan 2026 08:13:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUad-0000F9-AL; Thu, 29 Jan 2026 11:09:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaO-00005H-7S for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:36 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaM-0006aL-JW for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:35 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-47d59da3d81so16561245e9.0 for ; Thu, 29 Jan 2026 08:09:34 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702973; x=1770307773; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Ckk3q/EmqlkqmYKXWb5LjFCrWrKBLmaPbXOkEvFedwk=; b=scaWKmitWeIJobXt5s0v26MncHN1pu3+RvJBihYpQ7+CoDk0k4RhPylTlmgQwnNRa4 GU1ZRQ5SSwn0UIZ7l7OPtZV2Qu6VMJQV43lmRePYn2kbc+vTyzNnxgWXtrOjV+E8T44p wOAmN4bFAzJGMKF1C4h1xLQHeHlDt6054ZUvzZ0NgC+QOWCjm9bAcP+ao+AfiQ5ybFvX 8aRRnTI0UMGU8/mM/ipwhQNImdylfQ9RyGhymaGAxnZkAtThij52IytKDdLyYM2L1iZ+ mMmlUx5AnXA9BJ0IFQnM3hZhL5+9tHqYYy23i1zlO3zh2ti5MbWcpWT+7vYuXZ3p4cwc CJ/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702973; x=1770307773; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Ckk3q/EmqlkqmYKXWb5LjFCrWrKBLmaPbXOkEvFedwk=; b=LFwNmFs3bIrF3S+tRoB2K23OXOLCVjL5lnov1RAhB1e0OFYsHlbLfpt+cp60/ZFNgE dBaqCjHMcIygDpnbPCGkQmpDjfU6Ly4x7XAFZm/fxb2CkQDctXJn1HtJgMtKGgzMaGGh byOWS9+TUTL/ZbLDqjtmStoTxyYuL4mPW1iHC/CKTjAoxdehCxAbhqgVYrgqhMyUrlBG 55bBzJL3omxkZGaddhnkW3V6O1zjdhwMCpmecH8IJRdzKeHkz4/J1JolhWKTuONuV2ZU 4bvHJqTiZr8m0F7pMsihkAeniFyUX6ODMJHBEf47WJxEx6aalZtZbRMTCZv+Fpkpn9aa BEEw== X-Gm-Message-State: AOJu0YwruEPEZhj8eYYBRNnr2p7hRmQrzKgmXvDJlr1X1qgzKa5Z/SR8 tNbMsRf3zleCPr7uF54SpLYy5Oq9a9TDLZ66IcohLvl3FgGGyYVCmXZCqehpfzfeKIXzzVLVcdG wtyAyhvo= X-Gm-Gg: AZuq6aKaJLhi88aZCmzh+ib2P9rNJKJxAZpRV9UxpCga3ezhu4ayBETxwanbTbrUgM3 bnyA548EaclUTIf0IXGLh4CqJuYRW5AYgAtYfQFwxwkjUIdi25t9VU82G7t6k782RahD4fQXau6 j42JZqMxV/85gn8hDLaLOIArKaE8gn9qUy4d9FhYHUWQvGKUTgiq/s/rRkCIMprTrHUEMGPOKCU x4D2yDZVW4FR0VDNwvGQLjN3K95f7Ir08fTVaA2ILA1uAu+cw2mx4eL06HZC/S3QFJuYPMxMTR6 QunRoUSGlitUWGhWc8xrVBK70i1tghHVI3C1ua6Rifw6+FIaDIc+349ZZjOr56GPR6ZFQQENyLa Qzmav/jPIMYJTSYea7C0SOf05m29yjXAgs4D+uHco7volyps3BzpN6HTVxJ1rg8XyUb842pAVDI cP5JSaqRyCxg3RoYSU60ATlu8BXH3dxT7mQAQxqqOF X-Received: by 2002:a05:6000:2c07:b0:435:932e:f932 with SMTP id ffacd0b85a97d-435ea09c280mr4879535f8f.7.1769702972869; Thu, 29 Jan 2026 08:09:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/43] hw/arm/smmuv3: Implement get_viommu_cap() callback Date: Thu, 29 Jan 2026 16:08:45 +0000 Message-ID: <20260129160917.1415092-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703190472154100 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum For accelerated SMMUv3, we need nested parent domain creation. Add the callback support so that VFIO can create a nested parent. Reviewed-by: Nicolin Chen Reviewed-by: Jonathan Cameron Signed-off-by: Shameer Kolothum Tested-by: Zhangfei Gao Reviewed-by: Eric Auger Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-12-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 2fcd301322..be09cf8b73 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -10,6 +10,7 @@ #include "qemu/error-report.h" =20 #include "hw/arm/smmuv3.h" +#include "hw/core/iommu.h" #include "hw/pci/pci_bridge.h" #include "hw/pci-host/gpex.h" #include "hw/vfio/pci.h" @@ -129,9 +130,21 @@ static AddressSpace *smmuv3_accel_find_add_as(PCIBus *= bus, void *opaque, } } =20 +static uint64_t smmuv3_accel_get_viommu_flags(void *opaque) +{ + /* + * We return VIOMMU_FLAG_WANT_NESTING_PARENT to inform VFIO core to cr= eate a + * nesting parent which is required for accelerated SMMUv3 support. + * The real HW nested support should be reported from host SMMUv3 and = if + * it doesn't, the nesting parent allocation will fail anyway in VFIO = core. + */ + return VIOMMU_FLAG_WANT_NESTING_PARENT; +} + static const PCIIOMMUOps smmuv3_accel_ops =3D { .supports_address_space =3D smmuv3_accel_supports_as, .get_address_space =3D smmuv3_accel_find_add_as, + .get_viommu_flags =3D smmuv3_accel_get_viommu_flags, }; =20 static void smmuv3_accel_as_init(SMMUv3State *s) --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703208; cv=none; d=zohomail.com; s=zohoarc; b=n2vERA8G/xkpjW47F9jnyqk7m/LpghpZiUNC3eZCwPSAGe6kkIcDL/eYqnt7IODXpcRPl2cox5InzQdRexJYLCCjzWdzx6ue+5uiiYjQKcuETAbY+J1kzCE6v4BSVRuJw6lCuPz/TFG0TOHTuvMEsXJluzpCuwcnmNRBDHPh1mY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703208; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=bcuFNIgtAmUa4zoyaYJellTHjqr2qi6wGu1/tr6ixAc=; b=gi3ECNpdbj+mXMbZFu6fD3wR5QZWzb7lXL1X+wzjNgxWsqEsGqnsb4lByc4OVM3h/sdcVOOncorqHV2uzY3scPLXucrZ7Xb9fzCIETEvzxeGdOJ4FCwUXTViij5AxKCpuw8plb9fG4raOdoboM4R8dfm8RQfkOReVE80KxP66xY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703208785541.8184430882449; Thu, 29 Jan 2026 08:13:28 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUad-0000Fe-Db; Thu, 29 Jan 2026 11:09:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaR-00005k-0R for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:39 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaO-0006bT-Cj for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:38 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-42fb2314eb0so1043827f8f.2 for ; Thu, 29 Jan 2026 08:09:35 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702974; x=1770307774; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bcuFNIgtAmUa4zoyaYJellTHjqr2qi6wGu1/tr6ixAc=; b=yPEkW9MmDeE1aao4H5e0okz2Zk8HbrAXlGyia1VElcwuAe1D4/A8f7EA8c1dZFfcLZ o4IBnX6CVU7zNzqzDBvOKfY8971Sxck0T1RgbeFVkGVMpM77aoO4Fix1z51JP4sND6gM ALgEM9b+pYwr3fE34E+d3QCUxtdJ73U/RTBLS5jcUPw69z5BuDqHoX4gPL4Nekff3/mq FrTmYHHjb6IKZncwQkwcA9WM5R1L2Sycor4rAoc1u9k2SPg69h6/907ua3DohDEHZk3m qqRsQzxg3aq9izOcr0HND+DKSxL/Gwq2Vqot3VyLIHVCxNsI5Slpv7dQOt/JSbT83EOx X8Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702974; x=1770307774; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=bcuFNIgtAmUa4zoyaYJellTHjqr2qi6wGu1/tr6ixAc=; b=mPMmgKKofyEgBNfdhmgtSWY7DZL4gzIRsmR2g0cK6FFy+tdDH3EnjHZvMXNmBuk78E XOab+UTAsNj28rSb6c56G1qD8s0SksMfeaY6rrDgx253Yt0ch+PK4KQy3kRbMKQVMqP+ /m4p+HBHjfFju32AtuChwIqnWFKI85liO34st5tJeY1ByA1VwkQh8L9OuAmDxFLkLdq0 kzbmnfgliytoTGhQ3rDtOHEQ/iGldx1i8zyMOegtiyzesCNjvKekXyc0dJXXGEzZ5Df5 WO6BTE4RbXL6HgImMyCczA8fMFup2bTaewMG+d6aBg/EgqRIDi1AH+LBOw/9UaTYoCsc GRyA== X-Gm-Message-State: AOJu0YzLOZ5fq+tTnGSiWRqxON7Av+eDoJitWMLQOME7/fPY5Od1Sjsq 4gVeYoKviK7GVmUNOsEv7SAZ4QfdexHiJINo/H77CYSqAilmXEMf6ofRHnYi5HXFHQTuifqg4yC SCFxqFLA= X-Gm-Gg: AZuq6aL5h6GFd4PtBo93Kw7UEAOc3Xtob6/a/2Hq/HW2RVtzEHfyKDq2dw+3Uu58rj7 Bk8ZUgAUatRuGP5L9O58YWGDnd9IMBeMYO6Vlvl8cWmNJWvQlwu2xxO3g3c7ml1SuEHzfwMqUKS d/RycZDMz1pi99Kf6fPFi5kcyiOKmjWDE95eOX62HHm7T0lWxopk8jFaU3CITZ3vtgh3bCepyaj WwZ7J7YloCKE4zvJyjCR4OId75Msl4IoEAnPRGCwQUo2G4/DFdniPkV9Zebf3EQtHI9vyEAqN7L 3MnHjfVZ0a3qnf3wBO/7bUFxj5rgGoyEth1C+PDVjSH90IDEUrSAYMSjJtfB3jwo94u7Evkq5gI nte5aXy+iUiMFU3FSdwr1sIjPg3oN2GN6ZzaqlikuxAP2Rkqj2KpzQEe0ldCiIAP4gfStQiF3oU Qii0pnex5voT8bol707cJyqKy5aczlUA== X-Received: by 2002:a05:6000:4205:b0:433:1d30:44c with SMTP id ffacd0b85a97d-435f3aac3cdmr129466f8f.43.1769702974141; Thu, 29 Jan 2026 08:09:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/43] hw/arm/smmuv3-accel: Add set/unset_iommu_device callback Date: Thu, 29 Jan 2026 16:08:46 +0000 Message-ID: <20260129160917.1415092-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703209790158500 From: Nicolin Chen Implement the VFIO/PCI callbacks to attach and detach a HostIOMMUDevice to a vSMMUv3 when accel=3Don, - set_iommu_device(): attach a HostIOMMUDevice to a vIOMMU - unset_iommu_device(): detach and release associated resources In SMMUv3 accel=3Don mode, the guest SMMUv3 is backed by the host SMMUv3 via IOMMUFD. A vIOMMU object (created via IOMMU_VIOMMU_ALLOC) provides a per-VM, security-isolated handle to the physical SMMUv3. Without a vIOMMU, the vSMMUv3 cannot relay guest operations to the host hardware nor maintain isolation across VMs or devices. Therefore, set_iommu_device() allocates a vIOMMU object if one does not already exist. There are two main points to consider in this implementation: 1) VFIO core allocates and attaches a S2 HWPT that acts as the nesting parent for nested HWPTs(IOMMU_DOMAIN_NESTED). This parent HWPT will be shared across multiple vSMMU instances within a VM. 2) A device cannot attach directly to a vIOMMU. Instead, it attaches through a proxy nested HWPT (IOMMU_DOMAIN_NESTED). Based on the STE configuration,there are three types of nested HWPTs: bypass, abort, and translate. -The bypass and abort proxy HWPTs are pre-allocated. When SMMUv3 operates in global abort or bypass modes, as controlled by the GBPA register, or issues a vSTE for bypass or abort we attach these pre-allocated nested HWPTs. -The translate HWPT requires a vDEVICE to be allocated first, since invalidations and events depend on a valid vSID. -The vDEVICE allocation and attach operations for vSTE based HWPTs are implemented in subsequent patches. In summary, a device placed behind a vSMMU instance must have a vSID for translate vSTE. The bypass and abort vSTEs are pre-allocated as proxy nested HWPTs and is attached based on GBPA register. The core-managed nesting parent S2 HWPT is used as parent S2 HWPT for all the nested HWPTs and is intended to be shared across vSMMU instances within the same VM. set_iommu_device(): - Reuse an existing vIOMMU for the same physical SMMU if available. If not, allocate a new one using the nesting parent S2 HWPT. - Pre-allocate two proxy nested HWPTs (bypass and abort) under the vIOMMU and install one based on GBPA.ABORT value. - Add the device to the vIOMMU=E2=80=99s device list. unset_iommu_device(): - Re-attach device to the nesting parent S2 HWPT. - Remove the device from the vIOMMU=E2=80=99s device list. - If the list is empty, free the proxy HWPTs (bypass and abort) and release the vIOMMU object. Introduce struct SMMUv3AccelState, representing an accelerated SMMUv3 instance backed by an iommufd vIOMMU object, and storing the bypass and abort proxy HWPT IDs. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Zhangfei Gao Reviewed-by: Eric Auger Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-13-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 156 +++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 18 ++++ hw/arm/trace-events | 4 + include/hw/arm/smmuv3-common.h | 3 + include/hw/arm/smmuv3.h | 1 + 5 files changed, 182 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index be09cf8b73..9c2b917a11 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -8,6 +8,7 @@ =20 #include "qemu/osdep.h" #include "qemu/error-report.h" +#include "trace.h" =20 #include "hw/arm/smmuv3.h" #include "hw/core/iommu.h" @@ -15,6 +16,7 @@ #include "hw/pci-host/gpex.h" #include "hw/vfio/pci.h" =20 +#include "smmuv3-internal.h" #include "smmuv3-accel.h" =20 /* @@ -43,6 +45,157 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUStat= e *bs, SMMUPciBus *sbus, return accel_dev; } =20 +static uint32_t smmuv3_accel_gbpa_hwpt(SMMUv3State *s, SMMUv3AccelState *a= ccel) +{ + return FIELD_EX32(s->gbpa, GBPA, ABORT) ? + accel->abort_hwpt_id : accel->bypass_hwpt_id; +} + +static bool +smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, + Error **errp) +{ + SMMUv3AccelState *accel =3D s->s_accel; + struct iommu_hwpt_arm_smmuv3 bypass_data =3D { + .ste =3D { SMMU_STE_CFG_BYPASS | SMMU_STE_VALID, 0x0ULL }, + }; + struct iommu_hwpt_arm_smmuv3 abort_data =3D { + .ste =3D { SMMU_STE_VALID, 0x0ULL }, + }; + uint32_t s2_hwpt_id =3D idev->hwpt_id; + uint32_t viommu_id, hwpt_id; + IOMMUFDViommu *viommu; + + if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, + IOMMU_VIOMMU_TYPE_ARM_SMMUV3, + s2_hwpt_id, &viommu_id, errp)) { + return false; + } + + viommu =3D g_new0(IOMMUFDViommu, 1); + viommu->viommu_id =3D viommu_id; + viommu->s2_hwpt_id =3D s2_hwpt_id; + viommu->iommufd =3D idev->iommufd; + + /* + * Pre-allocate HWPTs for S1 bypass and abort cases. These will be att= ached + * later for guest STEs or GBPAs that require bypass or abort configur= ation. + */ + if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, viommu_id, + 0, IOMMU_HWPT_DATA_ARM_SMMUV3, + sizeof(abort_data), &abort_data, + &accel->abort_hwpt_id, errp)) { + goto free_viommu; + } + + if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, viommu_id, + 0, IOMMU_HWPT_DATA_ARM_SMMUV3, + sizeof(bypass_data), &bypass_data, + &accel->bypass_hwpt_id, errp)) { + goto free_abort_hwpt; + } + + /* Attach a HWPT based on SMMUv3 GBPA.ABORT value */ + hwpt_id =3D smmuv3_accel_gbpa_hwpt(s, accel); + if (!host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp)) { + goto free_bypass_hwpt; + } + accel->viommu =3D viommu; + return true; + +free_bypass_hwpt: + iommufd_backend_free_id(idev->iommufd, accel->bypass_hwpt_id); +free_abort_hwpt: + iommufd_backend_free_id(idev->iommufd, accel->abort_hwpt_id); +free_viommu: + iommufd_backend_free_id(idev->iommufd, viommu->viommu_id); + g_free(viommu); + return false; +} + +static bool smmuv3_accel_set_iommu_device(PCIBus *bus, void *opaque, int d= evfn, + HostIOMMUDevice *hiod, Error **e= rrp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(hiod); + SMMUState *bs =3D opaque; + SMMUv3State *s =3D ARM_SMMUV3(bs); + SMMUPciBus *sbus =3D smmu_get_sbus(bs, bus); + SMMUv3AccelDevice *accel_dev =3D smmuv3_accel_get_dev(bs, sbus, bus, d= evfn); + + if (!idev) { + return true; + } + + if (accel_dev->idev) { + if (accel_dev->idev !=3D idev) { + error_setg(errp, "Device already has an associated idev 0x%x", + idev->devid); + return false; + } + return true; + } + + if (s->s_accel->viommu) { + goto done; + } + + if (!smmuv3_accel_alloc_viommu(s, idev, errp)) { + error_append_hint(errp, "Unable to alloc vIOMMU: idev devid 0x%x: = ", + idev->devid); + return false; + } + +done: + accel_dev->idev =3D idev; + accel_dev->s_accel =3D s->s_accel; + QLIST_INSERT_HEAD(&s->s_accel->device_list, accel_dev, next); + trace_smmuv3_accel_set_iommu_device(devfn, idev->devid); + return true; +} + +static void smmuv3_accel_unset_iommu_device(PCIBus *bus, void *opaque, + int devfn) +{ + SMMUState *bs =3D opaque; + SMMUPciBus *sbus =3D g_hash_table_lookup(bs->smmu_pcibus_by_busptr, bu= s); + HostIOMMUDeviceIOMMUFD *idev; + SMMUv3AccelDevice *accel_dev; + SMMUv3AccelState *accel; + SMMUDevice *sdev; + + if (!sbus) { + return; + } + + sdev =3D sbus->pbdev[devfn]; + if (!sdev) { + return; + } + + accel_dev =3D container_of(sdev, SMMUv3AccelDevice, sdev); + idev =3D accel_dev->idev; + accel =3D accel_dev->s_accel; + /* Re-attach the default s2 hwpt id */ + if (!host_iommu_device_iommufd_attach_hwpt(idev, idev->hwpt_id, NULL))= { + error_report("Unable to attach the default HW pagetable: idev devi= d " + "0x%x", idev->devid); + } + + accel_dev->idev =3D NULL; + accel_dev->s_accel =3D NULL; + QLIST_REMOVE(accel_dev, next); + trace_smmuv3_accel_unset_iommu_device(devfn, idev->devid); + + if (QLIST_EMPTY(&accel->device_list)) { + iommufd_backend_free_id(accel->viommu->iommufd, accel->bypass_hwpt= _id); + iommufd_backend_free_id(accel->viommu->iommufd, accel->abort_hwpt_= id); + iommufd_backend_free_id(accel->viommu->iommufd, + accel->viommu->viommu_id); + g_free(accel->viommu); + accel->viommu =3D NULL; + } +} + /* * Only allow PCIe bridges, pxb-pcie roots, and GPEX roots so vfio-pci * endpoints can sit downstream. Accelerated SMMUv3 requires a vfio-pci @@ -145,6 +298,8 @@ static const PCIIOMMUOps smmuv3_accel_ops =3D { .supports_address_space =3D smmuv3_accel_supports_as, .get_address_space =3D smmuv3_accel_find_add_as, .get_viommu_flags =3D smmuv3_accel_get_viommu_flags, + .set_iommu_device =3D smmuv3_accel_set_iommu_device, + .unset_iommu_device =3D smmuv3_accel_unset_iommu_device, }; =20 static void smmuv3_accel_as_init(SMMUv3State *s) @@ -168,6 +323,7 @@ void smmuv3_accel_init(SMMUv3State *s) { SMMUState *bs =3D ARM_SMMU(s); =20 + s->s_accel =3D g_new0(SMMUv3AccelState, 1); bs->iommu_ops =3D &smmuv3_accel_ops; smmuv3_accel_as_init(s); } diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 0dc6b00d35..efb631db4f 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -10,10 +10,28 @@ #define HW_ARM_SMMUV3_ACCEL_H =20 #include "hw/arm/smmu-common.h" +#include "system/iommufd.h" +#ifdef CONFIG_LINUX +#include +#endif #include CONFIG_DEVICES =20 +/* + * Represents an accelerated SMMU instance backed by an iommufd vIOMMU obj= ect. + * Holds bypass and abort proxy HWPT IDs used for device attachment. + */ +typedef struct SMMUv3AccelState { + IOMMUFDViommu *viommu; + uint32_t bypass_hwpt_id; + uint32_t abort_hwpt_id; + QLIST_HEAD(, SMMUv3AccelDevice) device_list; +} SMMUv3AccelState; + typedef struct SMMUv3AccelDevice { SMMUDevice sdev; + HostIOMMUDeviceIOMMUFD *idev; + QLIST_ENTRY(SMMUv3AccelDevice) next; + SMMUv3AccelState *s_accel; } SMMUv3AccelDevice; =20 #ifdef CONFIG_ARM_SMMUV3_ACCEL diff --git a/hw/arm/trace-events b/hw/arm/trace-events index f3386bd7ae..2aaa0c40c7 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -66,6 +66,10 @@ smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotif= ier node for iommu mr=3D%s smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t i= ova, uint8_t tg, uint64_t num_pages, int stage) "iommu mr=3D%s asid=3D%d vm= id=3D%d iova=3D0x%"PRIx64" tg=3D%d num_pages=3D0x%"PRIx64" stage=3D%d" smmu_reset_exit(void) "" =20 +#smmuv3-accel.c +smmuv3_accel_set_iommu_device(int devfn, uint32_t devid) "devfn=3D0x%x (id= ev devid=3D0x%x)" +smmuv3_accel_unset_iommu_device(int devfn, uint32_t devid) "devfn=3D0x%x (= idev devid=3D0x%x)" + # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" strongarm_ssp_read_underrun(void) "SSP rx underrun" diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h index f644618f38..153310248d 100644 --- a/include/hw/arm/smmuv3-common.h +++ b/include/hw/arm/smmuv3-common.h @@ -100,6 +100,9 @@ REG32(STE_7, 28) #define STE_CFG_ABORT(config) (!(config & 0x4)) #define STE_CFG_BYPASS(config) (config =3D=3D 0x4) =20 +#define SMMU_STE_VALID (1ULL << 0) +#define SMMU_STE_CFG_BYPASS (1ULL << 3) + /* Update STE fields */ #define STE_SET_VALID(ste, v) = \ ((ste)->word[0] =3D FIELD_DP32((ste)->word[0], STE_0, VALID, (v))) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index bb7076286b..e54ece2d38 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -66,6 +66,7 @@ struct SMMUv3State { =20 /* SMMU has HW accelerator support for nested S1 + s2 */ bool accel; + struct SMMUv3AccelState *s_accel; }; =20 typedef enum { --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703012; cv=none; d=zohomail.com; s=zohoarc; b=SbeTCJVln3OLn6v+6m6WOApQiePwmxE3PI7mguQzpwlBNVBIO3t747xFSDlqFqMbZLv1AGY5H6UUXSIWt9frMTxup4D3rhEuwyBa+5buTDi3MYbajutVbF1VHkBfJl6NALQ2yRtkPSMFr6V4M/nfdw3wpA9tLJb3JP8+G7yh7e8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703012; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=m6kwUe9BaqDGblH1gyyZA8b9OoCTMLMEJsEiSmfNnrk=; b=P2TTzHfS3aibYKtaZ26MOgxXFSlaYwXLZYBW91jr1WOYaLB62IKWv9nwgj6d1fUL3a9jww6qO//Ys0CR3LXZa9MCJK21O89DcOBd0jdI+XJk4Zi+xM69tzETKKbPKYXLX9qa0GPJLPCOI2JchMuvf3R81bjew6AxXCIfzKF7l8o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703012864926.399220797646; Thu, 29 Jan 2026 08:10:12 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUaW-000095-BJ; Thu, 29 Jan 2026 11:09:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaR-00005l-1n for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:39 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaP-0006bn-6p for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:38 -0500 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-4359a302794so847197f8f.1 for ; Thu, 29 Jan 2026 08:09:36 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702976; x=1770307776; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=m6kwUe9BaqDGblH1gyyZA8b9OoCTMLMEJsEiSmfNnrk=; b=lz45EyudvP7ciMoY8hnKvnQgEnoU350bhDK0dR+qlTFhpzeXCyA3t09WsYTwwLl2ou iwSWjzlRHbYLLI/2kgboB+vjALK9mIqWw8xBRh+14Y9DtHexVNYn16scbip9AHJC+TIO NRxPmW2EeHAbseuGUoZ3EtxgziWYYbBs+/wpONnDok4RUhMZ+Yh/QtvNayFDlKQ4RnI2 qg9MT0AXSQKBmPQ85NPT/+eZMHQS9GAhyhsUGRqYTsv9fxg1NZIU6qcm4pYS0KOl1z9B lmRmNNb/OKUnqdYZxYkWCoYJy6VywsO22DVTtS0iYRnIC70HwdW5i2y+w0uGz+AtA5Mg LV0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702976; x=1770307776; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=m6kwUe9BaqDGblH1gyyZA8b9OoCTMLMEJsEiSmfNnrk=; b=h5QiuZfSf2PdGUC1779wFtdgqGpn102Otl3Ky4VqGSEamYhcc4nM/6tujn1/r+Lu22 kR0+rXXvXenvnjKGtqt4YK+mJvkikN3gALWAuqvgGzu42vw9NDofrrLNHi/mXRomQ8iW VBMRY0wZJMxJ0FZRHhSCyEN+hMcW1LnEhk5UHF2r5rXG9IHthnVco9tT3S9Pm7irdfvJ AOltp9BBNgzMtiibxVgx6N06nnZwbEK3NQO5U2C58QmgcfQkOL0Em8yjp15FZUWt8KuP ltyrDYRohXlrbAIDUQi3yhmr8NhmdoJtA2Fn4fLjmgvd1d+bLpgq0mBc2UzTTdSLBspi wjnw== X-Gm-Message-State: AOJu0YyCTHqNoBkprK5al/LskEr6zsRJz6kkVTKXokncf4OaENqZnA7h 9hwDjAcVLVG1kiVQmWin6ow/3kRdoXP3TR5Yw+9YUbhcANSvc6j93c7c3ULG+1hmS/IZ7HbrC8H F/HF5+IY= X-Gm-Gg: AZuq6aKUlGLgkn7w+6FK9yCb122MGv4R0itfzPRbIzFeObC2fmRw/amBL4ga4Rx3jul n61ydezaqjkuaNpgID4jJXka40iLWKDerxBWCXl0YKwWNSSvZav4AEJQ2ufoPes3PRMq5T0ATIs 2kMkwXMl0lGurwGZdFsB0dZEHCmmiUATcJxJyaS12rV/LXuGG6dTbJ94PCR9luGhCSNChsKXitX dtvk0c/4WPrwb+KICu0dnlJtNFqX9YubsZlqpeu38U7CHBQv1vA2xJvmJu6pQeCC2hRMd/Hyw6V 1YebSk5q0gVDukr2hl6apsfPIopoyEtRf3bUt2JhBQbGpVDlcJjyGZwbL6GNFANJzPI9dx/a+HJ GSiMcgXbWGqaOmttmjbzqW1UCRvjDxGKTHb/juVgJYlKt68rF9rmQ1Lp9l0dIctbDxP3iFF+uQv 5EiEuG5VDsa1ujQx3JkcmJ3qjNHxZT4A== X-Received: by 2002:a05:6000:2507:b0:431:a50:6ead with SMTP id ffacd0b85a97d-435f3a8654dmr180046f8f.20.1769702975456; Thu, 29 Jan 2026 08:09:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/43] hw/arm/smmuv3: propagate smmuv3_cmdq_consume() errors to caller Date: Thu, 29 Jan 2026 16:08:47 +0000 Message-ID: <20260129160917.1415092-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703013630154100 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum smmuv3_cmdq_consume() is updated to return detailed errors via errp. Although this is currently a no-op, it prepares the ground for accel SMMUv3 specific command handling where proper error reporting will be useful. Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Zhangfei Gao Reviewed-by: Jonathan Cameron Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-14-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 67 +++++++++++++++++++++++++++---------------------- 1 file changed, 37 insertions(+), 30 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 95d44f81ed..ade2b43ab8 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1279,7 +1279,7 @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd= , SMMUStage stage) } } =20 -static int smmuv3_cmdq_consume(SMMUv3State *s) +static int smmuv3_cmdq_consume(SMMUv3State *s, Error **errp) { SMMUState *bs =3D ARM_SMMU(s); SMMUCmdError cmd_error =3D SMMU_CERROR_NONE; @@ -1547,42 +1547,44 @@ static MemTxResult smmu_writell(SMMUv3State *s, hwa= ddr offset, static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset, uint64_t data, MemTxAttrs attrs) { + Error *local_err =3D NULL; + switch (offset) { case A_CR0: s->cr[0] =3D data; s->cr0ack =3D data & ~SMMU_CR0_RESERVED; /* in case the command queue has been enabled */ - smmuv3_cmdq_consume(s); - return MEMTX_OK; + smmuv3_cmdq_consume(s, &local_err); + break; case A_CR1: s->cr[1] =3D data; - return MEMTX_OK; + break; case A_CR2: s->cr[2] =3D data; - return MEMTX_OK; + break; case A_IRQ_CTRL: s->irq_ctrl =3D data; - return MEMTX_OK; + break; case A_GERRORN: smmuv3_write_gerrorn(s, data); /* * By acknowledging the CMDQ_ERR, SW may notify cmds can * be processed again */ - smmuv3_cmdq_consume(s); - return MEMTX_OK; + smmuv3_cmdq_consume(s, &local_err); + break; case A_GERROR_IRQ_CFG0: /* 64b */ s->gerror_irq_cfg0 =3D deposit64(s->gerror_irq_cfg0, 0, 32, data); - return MEMTX_OK; + break; case A_GERROR_IRQ_CFG0 + 4: s->gerror_irq_cfg0 =3D deposit64(s->gerror_irq_cfg0, 32, 32, data); - return MEMTX_OK; + break; case A_GERROR_IRQ_CFG1: s->gerror_irq_cfg1 =3D data; - return MEMTX_OK; + break; case A_GERROR_IRQ_CFG2: s->gerror_irq_cfg2 =3D data; - return MEMTX_OK; + break; case A_GBPA: /* * If UPDATE is not set, the write is ignored. This is the only @@ -1592,71 +1594,76 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwad= dr offset, /* Ignore update bit as write is synchronous. */ s->gbpa =3D data & ~R_GBPA_UPDATE_MASK; } - return MEMTX_OK; + break; case A_STRTAB_BASE: /* 64b */ s->strtab_base =3D deposit64(s->strtab_base, 0, 32, data); - return MEMTX_OK; + break; case A_STRTAB_BASE + 4: s->strtab_base =3D deposit64(s->strtab_base, 32, 32, data); - return MEMTX_OK; + break; case A_STRTAB_BASE_CFG: s->strtab_base_cfg =3D data; if (FIELD_EX32(data, STRTAB_BASE_CFG, FMT) =3D=3D 1) { s->sid_split =3D FIELD_EX32(data, STRTAB_BASE_CFG, SPLIT); s->features |=3D SMMU_FEATURE_2LVL_STE; } - return MEMTX_OK; + break; case A_CMDQ_BASE: /* 64b */ s->cmdq.base =3D deposit64(s->cmdq.base, 0, 32, data); s->cmdq.log2size =3D extract64(s->cmdq.base, 0, 5); if (s->cmdq.log2size > SMMU_CMDQS) { s->cmdq.log2size =3D SMMU_CMDQS; } - return MEMTX_OK; + break; case A_CMDQ_BASE + 4: /* 64b */ s->cmdq.base =3D deposit64(s->cmdq.base, 32, 32, data); - return MEMTX_OK; + break; case A_CMDQ_PROD: s->cmdq.prod =3D data; - smmuv3_cmdq_consume(s); - return MEMTX_OK; + smmuv3_cmdq_consume(s, &local_err); + break; case A_CMDQ_CONS: s->cmdq.cons =3D data; - return MEMTX_OK; + break; case A_EVENTQ_BASE: /* 64b */ s->eventq.base =3D deposit64(s->eventq.base, 0, 32, data); s->eventq.log2size =3D extract64(s->eventq.base, 0, 5); if (s->eventq.log2size > SMMU_EVENTQS) { s->eventq.log2size =3D SMMU_EVENTQS; } - return MEMTX_OK; + break; case A_EVENTQ_BASE + 4: s->eventq.base =3D deposit64(s->eventq.base, 32, 32, data); - return MEMTX_OK; + break; case A_EVENTQ_PROD: s->eventq.prod =3D data; - return MEMTX_OK; + break; case A_EVENTQ_CONS: s->eventq.cons =3D data; - return MEMTX_OK; + break; case A_EVENTQ_IRQ_CFG0: /* 64b */ s->eventq_irq_cfg0 =3D deposit64(s->eventq_irq_cfg0, 0, 32, data); - return MEMTX_OK; + break; case A_EVENTQ_IRQ_CFG0 + 4: s->eventq_irq_cfg0 =3D deposit64(s->eventq_irq_cfg0, 32, 32, data); - return MEMTX_OK; + break; case A_EVENTQ_IRQ_CFG1: s->eventq_irq_cfg1 =3D data; - return MEMTX_OK; + break; case A_EVENTQ_IRQ_CFG2: s->eventq_irq_cfg2 =3D data; - return MEMTX_OK; + break; default: qemu_log_mask(LOG_UNIMP, "%s Unexpected 32-bit access to 0x%"PRIx64" (WI)\n", __func__, offset); - return MEMTX_OK; + break; } + + if (local_err) { + error_report_err(local_err); + } + return MEMTX_OK; } =20 static MemTxResult smmu_write_mmio(void *opaque, hwaddr offset, uint64_t d= ata, --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703260; cv=none; d=zohomail.com; s=zohoarc; b=XO2PjBKoSbH2oxfKzHAZBfjxY91ROy/0JHnho1oyW8fv4KHwfRMnzvVV1mMTe+R6o1sH1dDpObqxOZSSRTqYU0zoQfPrdAWLR4G7WwvondDFxI7X5Uxm/o0InNx7Y2o7o2Oe9MkrG1sTpDhE8Gfh5owmVnrcJ0Mj+8hitlAo5h8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703260; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=gbHjOlzLfWfxUKKF85FGXZfJKzaeA9V1JqrwxVe2r64=; b=M/gE+lcmtKZV/tSYtU8H4C852lKwtlzh17yQH2viKoTQGyiMZnig8MOIxz9oE/K2W8mgOl0Mu2nVpP6jVq3V8nikpedexk9xma0eh94UmFIXh2aWRiue8Atl3AT7iycB/knDL1+vd/chuyE3UcjVHFlcdG8xTsO7sIBkRvkKDOY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703260758462.5673650852974; Thu, 29 Jan 2026 08:14:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUap-0000Yf-G3; Thu, 29 Jan 2026 11:10:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaT-000081-7d for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:41 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaQ-0006bt-Ah for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:40 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-435a517be33so824990f8f.0 for ; Thu, 29 Jan 2026 08:09:37 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702977; x=1770307777; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=gbHjOlzLfWfxUKKF85FGXZfJKzaeA9V1JqrwxVe2r64=; b=RLa/wvZ3lWcA6PoLAmfjxq411ejis1waTjTe3FS2p9acf8uqkFgfenCPIlYEuUuuwe v5tcU/7LRUqKDuVoJlXgQgGLlMID/64cqAEew1/cKMLKv257kwvGv8VwZmsNt5yP47po X9dRg94rEZSOunXBvvZbBVQUt6WqJ/d56gn7q3zuf2cCIPA2CUDdniZ3cH297eDkA2ZV qcnQziRDB/tXiNyj1rxHfx/OHaBtE+AAvSj0atZvFQ+qK3P2ZvPT584pGvhT2LAQZ0kQ eVrTw9bWTEQKpBM12NWaaXO++t34X6KQkNiZmUdKn+KIPP0ayO6Q7ON9ngKipzs147Hk nidw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702977; x=1770307777; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=gbHjOlzLfWfxUKKF85FGXZfJKzaeA9V1JqrwxVe2r64=; b=cmPr34pQ/h/2TEA08StPiGjKUarrQZzbHn0JHWJXOyXO1eeongnTf1oPe0ejrmPMXK 96lfDjwiWenGgkiLixQfu3d2hzJiVJMdyEqJfOdyeXLDb2fsr0KFE3O80XprdTOK6KXY l7xb5A8Lgosz/yQpXQU/0JMTcm0iiXA7AJ1PZ7mV+3AlTdB65Ll2PasRioychgDfDlG3 zJlma354rFQ0D3fRDFwA9NrJWmC/49+xDg23kcE8SaibKvUpm27ZdDMTqfhQBrhfa+/n t4/igKfsRmjG8xSIcYgHpJNtaK79IcKqut2GXz/MVsmAnD40SFxnl0uTAJW9laBACNeZ 6VRQ== X-Gm-Message-State: AOJu0Yxi5saVgTEB0+TGRDEDx6mSWFptHQcUwWSVIQKz7prgdJaItiCL DPzLCAZ7L8S7ex43ePRb+SBjmmHNdTyvDRdxwUqCD6AKKUyLms1MlOKiAD9927tNkOOsU76uqBl Xcgw7h3s= X-Gm-Gg: AZuq6aLp9EeHpggE+Zvc0pSls0dLvYQXpF3b/kTLBP3BquLw48etL/WZICkwULIruGe AzmABDdB65rMHcG7fkZEXS5sldw0Mu7n0FoCewAhMepNhjo1mpiiE3mVZ2v/7rcRLzYJ4FTLc7x 2cmsbGl6HH2iFVZqgQTkz0DwKrVADWO057LZ37fMZv33+e35m6PFBB5SX7m6AMFDDG1cmMoTZZ1 5fNhQhhgq4GVlZKkcdhM5b7PLZJxdiGj7k0HF9Vnngigfc74cOkOL0jJB7588ooGnOQsp1BCbd1 zuGpC6UoMxpjTFA3Pm6t3V8XTHkwReX7+kBBZ8JlsUTB72XdLfU/+0ueftBy9CAY5kBqrj2Y7E3 R9ixxkz+ZjL4/EysU5XxLcgK7sJL6tGgB52KoYc7/B9htRbdhoPeSGwhGT4a/uAvnK+ypxoWDyL 5ghlEswm4ZuSeSk7/GcfdiWaySWQR7GQ== X-Received: by 2002:a05:6000:1a87:b0:431:a0:7dea with SMTP id ffacd0b85a97d-435f3aa91d3mr165372f8f.40.1769702976756; Thu, 29 Jan 2026 08:09:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/43] hw/arm/smmuv3-accel: Add nested vSTE install/uninstall support Date: Thu, 29 Jan 2026 16:08:48 +0000 Message-ID: <20260129160917.1415092-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703262115158500 From: Nicolin Chen A device placed behind a vSMMU instance must have corresponding vSTEs (bypass, abort, or translate) installed. The bypass and abort proxy nested HWPTs are pre-allocated. For translat HWPT, a vDEVICE object is allocated and associated with the vIOMMU for each guest device. This allows the host kernel to establish a virtual SID to physical SID mapping, which is required for handling invalidations and event reporting. An translate HWPT is allocated based on the guest STE configuration and attached to the device when the guest issues SMMU_CMD_CFGI_STE or SMMU_CMD_CFGI_STE_RANGE, provided the STE enables S1 translation. If the guest STE is invalid or S1 translation is disabled, the device is attached to one of the pre-allocated ABORT or BYPASS HWPTs instead. While at it, export smmu_find_ste() for use here. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-15-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 197 +++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 22 ++++ hw/arm/smmuv3-internal.h | 1 + hw/arm/smmuv3.c | 11 +- hw/arm/trace-events | 2 + include/hw/arm/smmuv3-common.h | 18 +++ 6 files changed, 249 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 9c2b917a11..877b7e0e17 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -51,6 +51,188 @@ static uint32_t smmuv3_accel_gbpa_hwpt(SMMUv3State *s, = SMMUv3AccelState *accel) accel->abort_hwpt_id : accel->bypass_hwpt_id; } =20 +static bool +smmuv3_accel_alloc_vdev(SMMUv3AccelDevice *accel_dev, int sid, Error **err= p) +{ + SMMUv3AccelState *accel =3D accel_dev->s_accel; + HostIOMMUDeviceIOMMUFD *idev =3D accel_dev->idev; + IOMMUFDVdev *vdev =3D accel_dev->vdev; + uint32_t vdevice_id; + + if (!idev || vdev) { + return true; + } + + if (!iommufd_backend_alloc_vdev(idev->iommufd, idev->devid, + accel->viommu->viommu_id, sid, + &vdevice_id, errp)) { + return false; + } + + vdev =3D g_new(IOMMUFDVdev, 1); + vdev->vdevice_id =3D vdevice_id; + vdev->virt_id =3D sid; + accel_dev->vdev =3D vdev; + return true; +} + +static SMMUS1Hwpt * +smmuv3_accel_dev_alloc_translate(SMMUv3AccelDevice *accel_dev, STE *ste, + Error **errp) +{ + uint64_t ste_0 =3D (uint64_t)ste->word[0] | (uint64_t)ste->word[1] << = 32; + uint64_t ste_1 =3D (uint64_t)ste->word[2] | (uint64_t)ste->word[3] << = 32; + HostIOMMUDeviceIOMMUFD *idev =3D accel_dev->idev; + SMMUv3AccelState *accel =3D accel_dev->s_accel; + struct iommu_hwpt_arm_smmuv3 nested_data =3D { + .ste =3D { + cpu_to_le64(ste_0 & STE0_MASK), + cpu_to_le64(ste_1 & STE1_MASK), + }, + }; + uint32_t hwpt_id =3D 0, flags =3D 0; + SMMUS1Hwpt *s1_hwpt; + + if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, + accel->viommu->viommu_id, flags, + IOMMU_HWPT_DATA_ARM_SMMUV3, + sizeof(nested_data), &nested_data, + &hwpt_id, errp)) { + return NULL; + } + + s1_hwpt =3D g_new0(SMMUS1Hwpt, 1); + s1_hwpt->hwpt_id =3D hwpt_id; + trace_smmuv3_accel_translate_ste(accel_dev->vdev->virt_id, hwpt_id, + nested_data.ste[1], nested_data.ste[0= ]); + return s1_hwpt; +} + +bool smmuv3_accel_install_ste(SMMUv3State *s, SMMUDevice *sdev, int sid, + Error **errp) +{ + SMMUEventInfo event =3D {.type =3D SMMU_EVT_NONE, .sid =3D sid, + .inval_ste_allowed =3D true}; + SMMUv3AccelState *accel =3D s->s_accel; + SMMUv3AccelDevice *accel_dev; + HostIOMMUDeviceIOMMUFD *idev; + uint32_t config, hwpt_id =3D 0; + SMMUS1Hwpt *s1_hwpt =3D NULL; + const char *type; + STE ste; + + if (!accel || !accel->viommu) { + return true; + } + + accel_dev =3D container_of(sdev, SMMUv3AccelDevice, sdev); + if (!accel_dev->s_accel) { + return true; + } + + idev =3D accel_dev->idev; + if (!smmuv3_accel_alloc_vdev(accel_dev, sid, errp)) { + return false; + } + + if (smmu_find_ste(sdev->smmu, sid, &ste, &event)) { + /* No STE found, nothing to install */ + return true; + } + + /* + * Install the STE based on SMMU enabled/config: + * - attach a pre-allocated HWPT for abort/bypass + * - or a new HWPT for translate STE + * + * Note: The vdev remains associated with accel_dev even if HWPT + * attach/alloc fails, since the Guest=E2=80=93Host SID mapping stays + * valid as long as the device is behind the accelerated SMMUv3. + */ + if (!smmu_enabled(s)) { + hwpt_id =3D smmuv3_accel_gbpa_hwpt(s, accel); + } else { + config =3D STE_CONFIG(&ste); + + if (!STE_VALID(&ste) || STE_CFG_ABORT(config)) { + hwpt_id =3D accel->abort_hwpt_id; + } else if (STE_CFG_BYPASS(config)) { + hwpt_id =3D accel->bypass_hwpt_id; + } else if (STE_CFG_S1_TRANSLATE(config)) { + s1_hwpt =3D smmuv3_accel_dev_alloc_translate(accel_dev, &ste, = errp); + if (!s1_hwpt) { + return false; + } + hwpt_id =3D s1_hwpt->hwpt_id; + } + } + + if (!hwpt_id) { + error_setg(errp, "Invalid STE config for sid 0x%x", + smmu_get_sid(&accel_dev->sdev)); + return false; + } + + if (!host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp)) { + if (s1_hwpt) { + iommufd_backend_free_id(idev->iommufd, s1_hwpt->hwpt_id); + g_free(s1_hwpt); + } + return false; + } + + /* Free the previous s1_hwpt */ + if (accel_dev->s1_hwpt) { + iommufd_backend_free_id(idev->iommufd, accel_dev->s1_hwpt->hwpt_id= ); + g_free(accel_dev->s1_hwpt); + } + + accel_dev->s1_hwpt =3D s1_hwpt; + if (hwpt_id =3D=3D accel->abort_hwpt_id) { + type =3D "abort"; + } else if (hwpt_id =3D=3D accel->bypass_hwpt_id) { + type =3D "bypass"; + } else { + type =3D "translate"; + } + + trace_smmuv3_accel_install_ste(sid, type, hwpt_id); + return true; +} + +bool smmuv3_accel_install_ste_range(SMMUv3State *s, SMMUSIDRange *range, + Error **errp) +{ + SMMUv3AccelState *accel =3D s->s_accel; + SMMUv3AccelDevice *accel_dev; + Error *local_err =3D NULL; + bool all_ok =3D true; + + if (!accel || !accel->viommu) { + return true; + } + + QLIST_FOREACH(accel_dev, &accel->device_list, next) { + uint32_t sid =3D smmu_get_sid(&accel_dev->sdev); + + if (sid >=3D range->start && sid <=3D range->end) { + if (!smmuv3_accel_install_ste(s, &accel_dev->sdev, + sid, &local_err)) { + error_append_hint(&local_err, "Device 0x%x: Failed to inst= all " + "STE\n", sid); + error_report_err(local_err); + local_err =3D NULL; + all_ok =3D false; + } + } + } + + if (!all_ok) { + error_setg(errp, "Failed to install all STEs properly"); + } + return all_ok; +} + static bool smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, Error **errp) @@ -161,6 +343,7 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bus= , void *opaque, HostIOMMUDeviceIOMMUFD *idev; SMMUv3AccelDevice *accel_dev; SMMUv3AccelState *accel; + IOMMUFDVdev *vdev; SMMUDevice *sdev; =20 if (!sbus) { @@ -181,6 +364,20 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bu= s, void *opaque, "0x%x", idev->devid); } =20 + if (accel_dev->s1_hwpt) { + iommufd_backend_free_id(accel_dev->idev->iommufd, + accel_dev->s1_hwpt->hwpt_id); + g_free(accel_dev->s1_hwpt); + accel_dev->s1_hwpt =3D NULL; + } + + vdev =3D accel_dev->vdev; + if (vdev) { + iommufd_backend_free_id(accel->viommu->iommufd, vdev->vdevice_id); + g_free(vdev); + accel_dev->vdev =3D NULL; + } + accel_dev->idev =3D NULL; accel_dev->s_accel =3D NULL; QLIST_REMOVE(accel_dev, next); diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index efb631db4f..4e20b646dc 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -27,19 +27,41 @@ typedef struct SMMUv3AccelState { QLIST_HEAD(, SMMUv3AccelDevice) device_list; } SMMUv3AccelState; =20 +typedef struct SMMUS1Hwpt { + uint32_t hwpt_id; +} SMMUS1Hwpt; + typedef struct SMMUv3AccelDevice { SMMUDevice sdev; HostIOMMUDeviceIOMMUFD *idev; + SMMUS1Hwpt *s1_hwpt; + IOMMUFDVdev *vdev; QLIST_ENTRY(SMMUv3AccelDevice) next; SMMUv3AccelState *s_accel; } SMMUv3AccelDevice; =20 #ifdef CONFIG_ARM_SMMUV3_ACCEL void smmuv3_accel_init(SMMUv3State *s); +bool smmuv3_accel_install_ste(SMMUv3State *s, SMMUDevice *sdev, int sid, + Error **errp); +bool smmuv3_accel_install_ste_range(SMMUv3State *s, SMMUSIDRange *range, + Error **errp); #else static inline void smmuv3_accel_init(SMMUv3State *s) { } +static inline bool +smmuv3_accel_install_ste(SMMUv3State *s, SMMUDevice *sdev, int sid, + Error **errp) +{ + return true; +} +static inline bool +smmuv3_accel_install_ste_range(SMMUv3State *s, SMMUSIDRange *range, + Error **errp) +{ + return true; +} #endif =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 687ee6aaca..a6464425ec 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -353,6 +353,7 @@ typedef struct SMMUEventInfo { } while (0) =20 void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event); +int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *e= vent); =20 static inline int oas2bits(int oas_field) { diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index ade2b43ab8..7e29284267 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -630,8 +630,7 @@ bad_ste: * Supports linear and 2-level stream table * Return 0 on success, -EINVAL otherwise */ -static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, - SMMUEventInfo *event) +int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *e= vent) { dma_addr_t addr, strtab_base; uint32_t log2size; @@ -1341,6 +1340,10 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error= **errp) } =20 trace_smmuv3_cmdq_cfgi_ste(sid); + if (!smmuv3_accel_install_ste(s, sdev, sid, errp)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } smmuv3_flush_config(sdev); =20 break; @@ -1361,6 +1364,10 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error= **errp) sid_range.end =3D sid_range.start + mask; =20 trace_smmuv3_cmdq_cfgi_ste_range(sid_range.start, sid_range.en= d); + if (!smmuv3_accel_install_ste_range(s, &sid_range, errp)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } smmu_configs_inv_sid_range(bs, sid_range); break; } diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 2aaa0c40c7..8135c0c734 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -69,6 +69,8 @@ smmu_reset_exit(void) "" #smmuv3-accel.c smmuv3_accel_set_iommu_device(int devfn, uint32_t devid) "devfn=3D0x%x (id= ev devid=3D0x%x)" smmuv3_accel_unset_iommu_device(int devfn, uint32_t devid) "devfn=3D0x%x (= idev devid=3D0x%x)" +smmuv3_accel_translate_ste(uint32_t vsid, uint32_t hwpt_id, uint64_t ste_1= , uint64_t ste_0) "vSID=3D0x%x hwpt_id=3D0x%x ste=3D%"PRIx64":%"PRIx64 +smmuv3_accel_install_ste(uint32_t vsid, const char * type, uint32_t hwpt_i= d) "vSID=3D0x%x ste type=3D%s hwpt_id=3D0x%x" =20 # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h index 153310248d..415b7ccde5 100644 --- a/include/hw/arm/smmuv3-common.h +++ b/include/hw/arm/smmuv3-common.h @@ -99,10 +99,28 @@ REG32(STE_7, 28) #define STE_CFG_S2_ENABLED(config) (config & 0x2) #define STE_CFG_ABORT(config) (!(config & 0x4)) #define STE_CFG_BYPASS(config) (config =3D=3D 0x4) +#define STE_CFG_S1_TRANSLATE(config) (config =3D=3D 0x5) =20 #define SMMU_STE_VALID (1ULL << 0) #define SMMU_STE_CFG_BYPASS (1ULL << 3) =20 +#define STE0_V MAKE_64BIT_MASK(0, 1) +#define STE0_CONFIG MAKE_64BIT_MASK(1, 3) +#define STE0_S1FMT MAKE_64BIT_MASK(4, 2) +#define STE0_CTXPTR MAKE_64BIT_MASK(6, 50) +#define STE0_S1CDMAX MAKE_64BIT_MASK(59, 5) +#define STE0_MASK (STE0_S1CDMAX | STE0_CTXPTR | STE0_S1FMT | STE0_CONFI= G | \ + STE0_V) + +#define STE1_S1DSS MAKE_64BIT_MASK(0, 2) +#define STE1_S1CIR MAKE_64BIT_MASK(2, 2) +#define STE1_S1COR MAKE_64BIT_MASK(4, 2) +#define STE1_S1CSH MAKE_64BIT_MASK(6, 2) +#define STE1_S1STALLD MAKE_64BIT_MASK(27, 1) +#define STE1_EATS MAKE_64BIT_MASK(28, 2) +#define STE1_MASK (STE1_EATS | STE1_S1STALLD | STE1_S1CSH | STE1_S1COR= | \ + STE1_S1CIR | STE1_S1DSS) + /* Update STE fields */ #define STE_SET_VALID(ste, v) = \ ((ste)->word[0] =3D FIELD_DP32((ste)->word[0], STE_0, VALID, (v))) --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703190; cv=none; d=zohomail.com; s=zohoarc; b=bdg0YJCJ2LTIa9U7o51V9fzE5fmBuZrGE7qH5vtgobMsobypMSnrtL3Zrdlzlho4kxLRmfsnrzI3sXr379JxJjhKXzozyoBT8oUN5Au4GTIBNSZSXXg3Fznde5f5BOK8BoFDyavbWdjwvJzoC4HTjqyV67l8i9WpiUbkfhbpUbw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703190; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=3eIGgWv4cE1JjqWBb1edXamLBSm2sY55mhL4n7UNd+Q=; b=XLCrJ7V3SxNprE7leW6Y7VdN5k2DoNE6jOCEYFC9On1/gWwekKh+Yq9yf+n+GD2IkBfOWUsACnMRhZK7aq+RYyb8pIOU8weRrVaPlnQeNqkarNabr0zx0Uy6xjjr3mk3/85c6n1qWE9stMxrCZ1Xnh7evkdKH2OLsCzMFSm/geg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703190384462.7231725722114; Thu, 29 Jan 2026 08:13:10 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUaf-0000IE-Mt; Thu, 29 Jan 2026 11:09:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaT-000080-6v for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:41 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaR-0006cf-ES for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:40 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-47fedb7c68dso12127845e9.2 for ; Thu, 29 Jan 2026 08:09:39 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702978; x=1770307778; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3eIGgWv4cE1JjqWBb1edXamLBSm2sY55mhL4n7UNd+Q=; b=muEFbrZuemUhBfJXcxvxF6OLgZsPIDRH2rybAIWzkhFD0734HCBXK/GF//vu22Mh/2 WG1oxRbxb3+S6jN8guRWIl9cAHQmz32SLBEoVM5NSOsGhJbIMCZG96GyEVTDquOPkWz4 nOF+k3hdmAWOrmU1CYgkTb37jMK3lw7rGOxXx63zR2w0iMKHhTlC6ndqHamW3s7stiAe 8WOwyVJxIC+kmxKY3pD4QPQ4sqnpkS0irf/kpwGI3GhB7rdBp4n4stgPMCl0VfjfxqKd 5VZs9nw/60Sk+gpTOSZK2J4vefJhk2M92k3MERKjYeQNa04DIh1B+u+e44cgV75QNGXH hO/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702978; x=1770307778; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=3eIGgWv4cE1JjqWBb1edXamLBSm2sY55mhL4n7UNd+Q=; b=F7m7R6+QOFwhMJTmx1925C9yN6HmhCI4ryhIeC4wYzIXuD8Ckjxy4tViH+ixr5l4Cb 4B+jOkbq4sQz6m/NTncgF2T/FW3S7LW/I9lKJSR9oeTz1ZWmBjtU2sAQFE+QsenIQRMd i8Zn5A41MkuHrVXYWJ3J5jqaLD4lT0Wn5EqKWkcwzLy+2+oHCiLgb/aPw7BMLJCXKuiq KrQzIcVHCuKbh1IRFmCtqnuTs1TXTa2MG3mwBfswPMV38cXNO8kovn7d8j+8tVOpN6ya rHSspooXkRH+889wqavr0Bq0MW3YDIMZ8/V6aoEe/4a2L0YkBgceB8j8a5PG+Ca4Z2ep +cSQ== X-Gm-Message-State: AOJu0YzFEesR2CcJsbuLKrvQVkDkiTCvOrQbw9/0qkSZc5lrAkbVVvYZ 51LYN4b3dvbOmc05tfhzbughrkYPs6W5D5Vs4fCm0/wgiB0P8JQso2ZhoEpH3DFfppoMk42OyRA lVe9hQdc= X-Gm-Gg: AZuq6aJefxRNpB1jV9JHQw8dqEtJEZO6tFI/gvsrgEBhFSrDoD0kbJIoTIcwyznxmhQ MDquE/1YIExB8S7px6zNh3hgyvWuXtCc+5uFfAYdsGxT3HNNal98IeBbd025CeBx0++4t4ViWFW DXhOEZnhoJEe2PIPYDMa6mgmblcwyQSaxIl9F6m9lyO4O3iGys5JkrE7ypC6IbWC1H5IDtKUo2l CUO/QGsEaJ3A3eQ2Cy+hQiU7f/KqaMAjhB/UsyMQM3Ng9jdmB+iLsVEG2RC2jtSehhgnUvUF642 QfRr1ckjO47rs1jX7QjSvpjcE8rSscW57VQuhziLyHoE7CFPYi9ZRkMS9tWjy3LHNl/xe3IHrwO B6CI5icbk7UomcqSG0cycW9cSqW4I0iq2I+ObDKj/StgUfvStps19jPdvhH7v5BYb6JV9xEkZhg R/U9EC+yMWedEn1qb0INt1YkFViblLDQ== X-Received: by 2002:a05:600c:3e08:b0:47a:810f:1d06 with SMTP id 5b1f17b1804b1-48069bfac67mr110659635e9.4.1769702977877; Thu, 29 Jan 2026 08:09:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/43] hw/arm/smmuv3-accel: Install SMMUv3 GBPA based hwpt Date: Thu, 29 Jan 2026 16:08:49 +0000 Message-ID: <20260129160917.1415092-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703191758158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum On guest reboot or on GBPA update, attach a nested HWPT based on the GPBA.ABORT bit which either aborts all incoming transactions or bypasses them. Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Tested-by: Eric Auger Tested-by: Zhangfei Gao Reviewed-by: Jonathan Cameron Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-16-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 36 ++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 9 +++++++++ hw/arm/smmuv3.c | 2 ++ 3 files changed, 47 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 877b7e0e17..c125974d12 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -499,6 +499,42 @@ static const PCIIOMMUOps smmuv3_accel_ops =3D { .unset_iommu_device =3D smmuv3_accel_unset_iommu_device, }; =20 +/* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */ +bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error **errp) +{ + SMMUv3AccelState *accel =3D s->s_accel; + SMMUv3AccelDevice *accel_dev; + Error *local_err =3D NULL; + bool all_ok =3D true; + uint32_t hwpt_id; + + if (!accel || !accel->viommu) { + return true; + } + + hwpt_id =3D smmuv3_accel_gbpa_hwpt(s, accel); + QLIST_FOREACH(accel_dev, &accel->device_list, next) { + if (!host_iommu_device_iommufd_attach_hwpt(accel_dev->idev, hwpt_i= d, + &local_err)) { + error_append_hint(&local_err, "Failed to attach GBPA hwpt %u f= or " + "idev devid %u", hwpt_id, accel_dev->idev->d= evid); + error_report_err(local_err); + local_err =3D NULL; + all_ok =3D false; + } + } + if (!all_ok) { + error_setg(errp, "Failed to attach all GBPA based HWPTs properly"); + } + return all_ok; +} + +void smmuv3_accel_reset(SMMUv3State *s) +{ + /* Attach a HWPT based on GBPA reset value */ + smmuv3_accel_attach_gbpa_hwpt(s, NULL); +} + static void smmuv3_accel_as_init(SMMUv3State *s) { =20 diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 4e20b646dc..c7ed4dce3a 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -46,6 +46,8 @@ bool smmuv3_accel_install_ste(SMMUv3State *s, SMMUDevice = *sdev, int sid, Error **errp); bool smmuv3_accel_install_ste_range(SMMUv3State *s, SMMUSIDRange *range, Error **errp); +bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error **errp); +void smmuv3_accel_reset(SMMUv3State *s); #else static inline void smmuv3_accel_init(SMMUv3State *s) { @@ -62,6 +64,13 @@ smmuv3_accel_install_ste_range(SMMUv3State *s, SMMUSIDRa= nge *range, { return true; } +static inline bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error **e= rrp) +{ + return true; +} +static inline void smmuv3_accel_reset(SMMUv3State *s) +{ +} #endif =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 7e29284267..7a32afd800 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1600,6 +1600,7 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr= offset, if (data & R_GBPA_UPDATE_MASK) { /* Ignore update bit as write is synchronous. */ s->gbpa =3D data & ~R_GBPA_UPDATE_MASK; + smmuv3_accel_attach_gbpa_hwpt(s, &local_err); } break; case A_STRTAB_BASE: /* 64b */ @@ -1887,6 +1888,7 @@ static void smmu_reset_exit(Object *obj, ResetType ty= pe) } =20 smmuv3_init_regs(s); + smmuv3_accel_reset(s); } =20 static void smmu_realize(DeviceState *d, Error **errp) --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703054; cv=none; d=zohomail.com; s=zohoarc; b=GLBuaHOTqadrDCBXNOsfXj1WNr0B16y4M/cA6S1VPShNTzrUTsjcQdxXdb/Roop1H+K+Z//TDGJR8XNuoo+2R3no3qhujw963eZyN+7mXtzmhsh5TgooWo3m/fvqeQ+PvxTqQmqrFAMsXe592LympaPtzov84i9tVWAk2JwEtH4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703054; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=BHOEVBrGkeHnzIIkfAc0Zy0MYoZWsfrOamFR4imfJYM=; b=UqqXscHx+BRRWFOZyCupZ9HHNXOnzrCvtMJua+nuVe98C5AyLziIRmcKRdGg7IOYqDSUH/RbN/PdzbzYpG/d6kMcvJhAcAEZrqol9oGFW78K9Al+FO7pjftOgjBxFprjCza1rCo3pTA4O9oIlyfwBbWX6NEEQQYvfUOGtxnZnKk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703054889426.7729200590534; Thu, 29 Jan 2026 08:10:54 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUat-0000qL-UB; Thu, 29 Jan 2026 11:10:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaU-00008Q-Sp for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:43 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaS-0006cu-QT for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:42 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-47ff94b46afso10444545e9.1 for ; Thu, 29 Jan 2026 08:09:40 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702979; x=1770307779; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=BHOEVBrGkeHnzIIkfAc0Zy0MYoZWsfrOamFR4imfJYM=; b=r0AiUjZ+C/N4uuRdBaPLimqJlA35vh/D+EFp4rdLmvr3IeML0xkVUBsrk70cbi0pOu YkNqy7nMQ7B/lXMZKrF9aMkOPY2w8dmoX835TSzx8yc5AX3T+AXhK6DYTROcXl3aR0pl bWyvdlVpIf2Qrd6Ue6Vg6gYLEnTEn4/AOJ2fjEVtj+mVjNs2ELIHM4w5KeDhD/sYOAF0 /K3zwueinkdXxq7jp1+HuobbusZNCujw4QQBlvltM7/Lsx0G6T+V0tRCjCf8tIyftEM2 4VCycsUKXdzywzZ8O1pBWSICKEHaZyXa9u4ZKOIX5QOsfpEGWBUaSKZdjfewLfb18kpK Ht5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702979; x=1770307779; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=BHOEVBrGkeHnzIIkfAc0Zy0MYoZWsfrOamFR4imfJYM=; b=D90fku65bzoNJqeGD0t9VHsTqT2S5ayZ6QMJUFhl7P1oXSOpIy6rE1i7F82iQTQhG7 3scqtnwIkBZXtOiZF5X2VgLcqQy/dYfr2uCne+56/tsbgz8NGGGt62hKJp4CIzpOxKND kyGp8glzEwub7HhnDZnft3PRsUX7c3Iur3tA4UcJoBChiV4GvqUjDM4LxCVkadsncm1O 8+bTdMWT7UXnyEOqoKsiHzjsjUep4N50uoMQVuSpEcgkdUYtrKg/phTXVuJV8+WdOCxL +edIMJWFfqGT4VEVRPxyxwsVAmNig0IivcYS3+38z/R/QofNJQKNU1gM97ORnchq9WQy 11Yg== X-Gm-Message-State: AOJu0YyY8J/1974fQmF4HTobNU3ROpNDUXCeJb6QV7KO4dwydWr3iQE5 we69SO6RSnNLU+se7z7CcMdOuAZfGgyFBlljiQ2/2UvUBTaCfZreRkhakJd2KIWgI3hpdkdBId+ lA53WPdc= X-Gm-Gg: AZuq6aL9hDfI7dj5WeCc6hL51gCxrm7Uwtovv3zJOyaX7DyDj2lKLrUaockfqGhRdir Oxb4ZItDVfsizE102oy+UpE1kwBomeBlBgLHCbofTs/SFnc9qdi0XtRqabcsgP2T2zyfFwKrc0i SLkPjcEQ7zrNEXU8oBChK8FMpkguMZdqVXQXBFlTYYtOUHWvQcntOj0+kkOmOI8HCdiaeBfeY4G z/IY33Uasnm2seqh8t3rKHVUN8W/UYrngVnHa9yXnDx+DCh2Udt0MSLDVEfKu3yksJB/CoU2JOM 5hcZzW8S6s4aps5AHXhR0h1iXbIotgydjE0TFosfg1XR3qe7ADBT7tFpomkC5dHGUXmipod6YM+ KjkmZ0V3YatzHWfFkLl3R3PEM9j0MnUHIMynAK7FQBhQfGhnnofPJgs4ih5fdGBY2seD8lC6Ujb N++7drZ+i7fBuoVlYfw/cC47SebcoLcA== X-Received: by 2002:a05:600c:a10b:b0:47d:52ef:c572 with SMTP id 5b1f17b1804b1-480828745e6mr39149785e9.1.1769702979072; Thu, 29 Jan 2026 08:09:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/43] hw/pci/pci: Introduce a callback to retrieve the MSI doorbell GPA directly Date: Thu, 29 Jan 2026 16:08:50 +0000 Message-ID: <20260129160917.1415092-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703056339154100 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum For certain vIOMMU implementations, such as SMMUv3 in accelerated mode, the translation tables are programmed directly into the physical SMMUv3 in a nested configuration. While QEMU knows where the guest tables live, safely walking them in software would require trapping and ordering all guest invalidations on every command queue. Without this, QEMU could race with guest updates and walk stale or freed page tables. This constraint is fundamental to the design of HW-accelerated vSMMU when used with downstream vfio-pci endpoint devices, where QEMU must never walk guest translation tables and must rely on the physical SMMU for translation. Future accelerated vSMMU features, such as virtual CMDQ, will also prevent trapping invalidations, reinforcing this restriction. For vfio-pci endpoints behind such a vSMMU, the only translation QEMU needs is for the MSI doorbell used when setting up KVM MSI route tables. Instead of attempting a software walk, introduce an optional vIOMMU callback that returns the MSI doorbell GPA directly. kvm_arch_fixup_msi_route() uses this callback when available and ignores the guest provided IOVA in that case. If the vIOMMU does not implement the callback, we fall back to the existing IOMMU based address space translation path. This ensures correct MSI routing for accelerated SMMUv3 + VFIO passthrough while avoiding unsafe software walks of guest translation tables. As a related change, replace RCU_READ_LOCK_GUARD() with explicit rcu_read_lock()/rcu_read_unlock(). The introduction of an early goto (set_doorbell) path means the RCU read side critical section can no longer be safely scoped using RCU_READ_LOCK_GUARD(). Cc: Michael S. Tsirkin Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Reviewed-by: Michael S. Tsirkin Tested-by: Eric Auger Tested-by: Zhangfei Gao Reviewed-by: Jonathan Cameron Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-17-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/pci/pci.c | 17 +++++++++++++++++ include/hw/pci/pci.h | 17 +++++++++++++++++ target/arm/kvm.c | 18 +++++++++++++++++- 3 files changed, 51 insertions(+), 1 deletion(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 101e745bd5..9035caca92 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2979,6 +2979,23 @@ bool pci_device_get_iommu_bus_devfn(PCIDevice *dev, = PCIBus **piommu_bus, return aliased; } =20 +bool pci_device_iommu_msi_direct_gpa(PCIDevice *dev, hwaddr *out_doorbell) +{ + PCIBus *bus; + PCIBus *iommu_bus; + int devfn; + + pci_device_get_iommu_bus_devfn(dev, &iommu_bus, &bus, &devfn); + if (iommu_bus) { + if (iommu_bus->iommu_ops->get_msi_direct_gpa) { + *out_doorbell =3D iommu_bus->iommu_ops->get_msi_direct_gpa(bus, + iommu_bus->iommu_opaque, devfn); + return true; + } + } + return false; +} + AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) { PCIBus *bus; diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index ddb0c98e9f..d9835dfd0d 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -683,6 +683,22 @@ typedef struct PCIIOMMUOps { uint32_t pasid, bool priv_req, bool exec_req, hwaddr addr, bool lpig, uint16_t prgi, bool is= _read, bool is_write); + /** + * @get_msi_direct_gpa: get the guest physical address of MSI doorbell + * for the device on a PCI bus. + * + * Optional callback. If implemented, it must return a valid guest + * physical address for the MSI doorbell + * + * @bus: the #PCIBus being accessed. + * + * @opaque: the data passed to pci_setup_iommu(). + * + * @devfn: device and function number + * + * Returns: the guest physical address of the MSI doorbell. + */ + uint64_t (*get_msi_direct_gpa)(PCIBus *bus, void *opaque, int devfn); } PCIIOMMUOps; =20 bool pci_device_get_iommu_bus_devfn(PCIDevice *dev, PCIBus **piommu_bus, @@ -691,6 +707,7 @@ AddressSpace *pci_device_iommu_address_space(PCIDevice = *dev); bool pci_device_set_iommu_device(PCIDevice *dev, HostIOMMUDevice *hiod, Error **errp); void pci_device_unset_iommu_device(PCIDevice *dev); +bool pci_device_iommu_msi_direct_gpa(PCIDevice *dev, hwaddr *out_doorbell); =20 /** * pci_device_get_viommu_flags: get vIOMMU flags. diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 48f853fff8..0828e8b87b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1621,26 +1621,42 @@ int kvm_arch_fixup_msi_route(struct kvm_irq_routing= _entry *route, return 0; } =20 + /* + * We do have an IOMMU address space, but for some vIOMMU implementati= ons + * (e.g. accelerated SMMUv3) the translation tables are programmed into + * the physical SMMUv3 in the host (nested S1=3Dguest, S2=3Dhost). QEM= U cannot + * walk these tables in a safe way, so in that case we obtain the MSI + * doorbell GPA directly from the vIOMMU backend and ignore the gIOVA + * @address. + */ + if (pci_device_iommu_msi_direct_gpa(dev, &doorbell_gpa)) { + goto set_doorbell; + } + /* MSI doorbell address is translated by an IOMMU */ =20 - RCU_READ_LOCK_GUARD(); + rcu_read_lock(); =20 mr =3D address_space_translate(as, address, &xlat, &len, true, MEMTXATTRS_UNSPECIFIED); =20 if (!mr) { + rcu_read_unlock(); return 1; } =20 mrs =3D memory_region_find(mr, xlat, 1); =20 if (!mrs.mr) { + rcu_read_unlock(); return 1; } =20 doorbell_gpa =3D mrs.offset_within_address_space; memory_region_unref(mrs.mr); + rcu_read_unlock(); =20 +set_doorbell: route->u.msi.address_lo =3D doorbell_gpa; route->u.msi.address_hi =3D doorbell_gpa >> 32; =20 --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703258; cv=none; d=zohomail.com; s=zohoarc; b=ORF4Aeuh1GN6J5w43OJiGVuX4/p9noLhMuGkVjD2omQTYnDeJmSjbGhMuE+mqglzoO9g5jLIqFN8phzbwaty0EHXSd5jZCJcSgf1TTdlrSdhbzzbcL2hvi0cRqMWsoMNJ3AZmU90afgcNKMoZGZ/27WPY5HZAXQWAX2R6T270LY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703258; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=g7u4vFyrJCbAlZ8RKPYksrp2vL/fqFoBrZQZKiBf15A=; b=ms7YMOXLkYpvk4JxBgNaBSS2B9tKBFGsGxfeTI5xo1Wf+Hox50KH3Sz2fO0q4kEHF/qemaHbscrBqyKpE/D4L9Q3pG+aXMgKj/F7GD62+lb5vkI2nCXkVn412EGuKTcPvW12KkvFyErd50KoKYLesWM7DBdeTZjM6307WBmEc0g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703258588444.54211355207974; Thu, 29 Jan 2026 08:14:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUav-0000x0-0M; Thu, 29 Jan 2026 11:10:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaV-000096-S8 for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:44 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaU-0006dA-4n for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:43 -0500 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-435a11957f6so972533f8f.0 for ; Thu, 29 Jan 2026 08:09:41 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702980; x=1770307780; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=g7u4vFyrJCbAlZ8RKPYksrp2vL/fqFoBrZQZKiBf15A=; b=veu4X71E374WXEvR1FyrvPyjKNZUT45/dMAZGGqic7TakcPdIOMZobzDr2Sr3HW79f 5aeGCy4yvZYwX9g01OOdBTCr26EYzyNBd9/EJ0zZyd6N1/DX15euUIInPbuzcXYD8AxB 8VbgmTcE0KTOlXUYTlVGkKICat5+EwkiPxVM4WdH4avlUHvQQW0VrUnGJrcoLLl+6hTa 4lTuV9n3nKUeVAmm8kyQD1nbfxjcW+4xzo69cQkHMfYN9nKwarg7NC5dLlj0M+ZBzOU0 474L+uQWFEnKBEU25auH8c2XkDFI1HhJWkqbPyvYHUbzyZ3UaqvC2s9MF09Zq+r6gHtA A7nA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702980; x=1770307780; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=g7u4vFyrJCbAlZ8RKPYksrp2vL/fqFoBrZQZKiBf15A=; b=ShivfiklzsNoxFyqh/OOgimAGmcAO7gi3g72eXlnDVQAMOit088o+IAH0mInJrtAjp zynqzeOhzGc1LgYnsn5TfaxgAFCIiXlv6kZgpFgvam8ND0tk1MjShrGC/JL7gfvHMHff rEzAxcF7xlA5cq90Hs2LNCuJOw5ki3EEqjhY4Ck0r2A9kkD+6/VRXUGX1RGQNvJlLfHr +AnuLKa/3lXDWFQbzv5VKV5BQaPcHQ7NuySKTSkKZG1quB/at7EIMUUf09XUMA8V14zR 1hUfuaW3AJYXdNBrxjynq3ha9cG7thxNz1P5Kl1Up2TCuO/uoSfrJYp6Pt1S2BrIE35F MlZw== X-Gm-Message-State: AOJu0YwfFN7Tgarg/H6vMY3X4SLvH5NjRn5na9UlZRto+SspvPToueLJ ORDbfT+LCRC1dwdjEo6bBv5/Z7GFhZP9z4WC1CUII+9Yd1sWVOO8K+JVQ7F7hV5oOWNp4PdogLo 3sJgbQmE= X-Gm-Gg: AZuq6aK1jPJWr+ChFNL8QRxDmnHsCCwOY5ODV5Bp3tR9Gri0bSeShL5v9AaARvF8h9i hCjyR414GPJj6s2VKOzYdq9bt4UsSmhPCc0Q8FrUPq6UnpTvc7CNqUsYjDYZl6Mf7PwL2gyOfYo eCkDtdyoXs4vzb1QHt9YKGAhKRzC3uqQ+XaIndmOZgqy/I/R8AKiEFvamjxNKsohh+E7yK4q3W1 jVOdHhiY6UNgyID4dAaL1AnHlm6XajVXUy+FrH9WybhFqNH61gGzq1XEvBpUISKpGqHFCjUZZI/ t/GPdBeePH7uupHBSZeWBVxnyYX406A7BpLYizMpjrSwBNnkLJhk/sF0qCduybGoar3c8Jxaq/0 pm1VHX0uAM73U7G0ET5iT1d/ybwWxPEq9/j2WB3HNNQNO50aCH/L/yI9z4f+cxrRd2izRPlv4Ib MZX7Kv3mZpqc1F/7szxLtZIjo1xEhBaw== X-Received: by 2002:a5d:5e01:0:b0:435:95c9:687a with SMTP id ffacd0b85a97d-435f3a6b95fmr178387f8f.4.1769702980220; Thu, 29 Jan 2026 08:09:40 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/43] hw/arm/smmuv3-accel: Implement get_msi_direct_gpa callback Date: Thu, 29 Jan 2026 16:08:51 +0000 Message-ID: <20260129160917.1415092-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703261354154100 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Accelerated SMMUv3 instances rely on the physical SMMUv3 for nested translation (guest Stage-1, host Stage-2). In this mode, the guest Stage-1 tables are programmed directly into hardware, and QEMU must not attempt to walk them for translation, as doing so is not reliably safe. For vfio-pci endpoints behind such a vSMMU, the only translation QEMU needs to perform is for the MSI doorbell used during KVM MSI setup. Implement the callback so that kvm_arch_fixup_msi_route() can retrieve the MSI doorbell GPA directly, instead of attempting a software walk of the guest translation tables. Also introduce an SMMUv3 device property to carry the MSI doorbell GPA. This property will be set by the virt machine in a subsequent patch. Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Zhangfei Gao Reviewed-by: Jonathan Cameron Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-18-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 10 ++++++++++ hw/arm/smmuv3.c | 2 ++ include/hw/arm/smmuv3.h | 1 + 3 files changed, 13 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index c125974d12..c6ee123cdf 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -393,6 +393,15 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bu= s, void *opaque, } } =20 +static uint64_t smmuv3_accel_get_msi_gpa(PCIBus *bus, void *opaque, int de= vfn) +{ + SMMUState *bs =3D opaque; + SMMUv3State *s =3D ARM_SMMUV3(bs); + + g_assert(s->msi_gpa); + return s->msi_gpa; +} + /* * Only allow PCIe bridges, pxb-pcie roots, and GPEX roots so vfio-pci * endpoints can sit downstream. Accelerated SMMUv3 requires a vfio-pci @@ -497,6 +506,7 @@ static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_viommu_flags =3D smmuv3_accel_get_viommu_flags, .set_iommu_device =3D smmuv3_accel_set_iommu_device, .unset_iommu_device =3D smmuv3_accel_unset_iommu_device, + .get_msi_direct_gpa =3D smmuv3_accel_get_msi_gpa, }; =20 /* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 7a32afd800..6ed9914b1e 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1998,6 +1998,8 @@ static const Property smmuv3_properties[] =3D { * Defaults to stage 1 */ DEFINE_PROP_STRING("stage", SMMUv3State, stage), + /* GPA of MSI doorbell, for SMMUv3 accel use. */ + DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), }; =20 static void smmuv3_instance_init(Object *obj) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index e54ece2d38..5616a8a2be 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -67,6 +67,7 @@ struct SMMUv3State { /* SMMU has HW accelerator support for nested S1 + s2 */ bool accel; struct SMMUv3AccelState *s_accel; + uint64_t msi_gpa; }; =20 typedef enum { --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703192; cv=none; d=zohomail.com; s=zohoarc; b=Srp4FF/9RmFVnuIWcMr35guBXKADhXH7D80LTQPZqD6U0oaDL+QbPrFOuEjG89Qc9IHkxm+f7SslN0C7+9CLI5yqFIW/2QyHvEcBVpGSsiRgm/P8rB5Fd5XQLegd2zbRHWWTV3gHMYPId4NoRejHrV44UYplpOhs0iNwuH9jpRM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703192; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=nY2Fqtl39Acb1I/wBKQSDHm7rQ3asaK1/sWbD/R/7bc=; b=nBhp19/CeiS+hc1rxkG5F368xC9yakLYdSspgB4W4cmzEP0AZh9CURap4CMiYhohTNFNnn8X9DDWJaaqdFVc36AIKOtkE9jkK1fj+inPBKDOm8GZy/AnSB1cAOZj244tz415YbfFQOKNUtO0bRutXiRScH/XyG1HfOsc+TaDcsc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703192298738.1652577682647; Thu, 29 Jan 2026 08:13:12 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUad-0000Hd-S3; Thu, 29 Jan 2026 11:09:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaW-00009T-Iq for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:45 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaU-0006dY-Vg for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:44 -0500 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-432d2670932so1130949f8f.2 for ; Thu, 29 Jan 2026 08:09:42 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702981; x=1770307781; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=nY2Fqtl39Acb1I/wBKQSDHm7rQ3asaK1/sWbD/R/7bc=; b=sSBT605K9xObTml+iLU2QgtrTD4QTbKD7x/NwBluUSGUJJBKZDH4CVzkGV1qZ/h2Gc FSI/HHUUcKR0hiWtWLNujkjdylVVX+Njs0WqJA2TWm5ojegmLmKZ3l+eCTFzJGMdWKeX IhhZ6FIRhIK5uON6O8LRqq6x05lp7TJW1wre4B5Qk85l1oCXJLpWIl2bG/LixKAJrPRj Mbm2vYCAaIDOaRv3ns2DspNy0Bk3a8S/yaMHbWebqeCH4Xm7NZGJW8JObbYCAe9n45Jm BDmVxgpQec2SL4uy9gOrYuPPJhI9B2owSuP/INmMOpJprdLCa1D1n8ihKZdTyIItbiAv U/zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702981; x=1770307781; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=nY2Fqtl39Acb1I/wBKQSDHm7rQ3asaK1/sWbD/R/7bc=; b=jVhDYizgvzGmjuYIOCmdwv+oQ20kIx+am/yUkVUHmSFZW5a+X2I6g2ss+TaISzqUQ8 pWo+I71mup7UtYeLs7/Gckc6uczgwDP3D9rEc6E1xgk+mO79nhI4PFi90NtSM2fPso0J FNI+otVKeKvoghCHKQc2W4qbbpX8WrAeiE2ZYXQ7oIcBQkXcKoooVW1XbuJjJ3iHvJd7 5BDOyFu4Bq0Neny2/A1NSg+7wp9KX6SIU4bMVUXzyXvCdng5L3Ue3i7RgBH/CBaruJFJ HwQMMTxNW7PhQsQsDRLYXvHkkXMMFSh9YZxIf4xh1AgdIZ4BUBrZ4GFFcrRmWqGCJ3j0 vpCg== X-Gm-Message-State: AOJu0YxU1BKhmXHK4+OJCfbJ8ESAD9XltVvG+QrDLUuSsrYKRTzmgeUw bFlupm4ernSOAX2mDN8oXW6e1DEH2hvyeSJRP49LRFOeK8WY+h6hzRGrWsxSuWTl/pcbFxJG7Vc 54wJPd5Y= X-Gm-Gg: AZuq6aJLrGF2JqtwcIT3dcDdMIH5ls6AyS5Qj454htF9uypttdCtakREkzGdnjDMqYf 0dm7KGscoQSoOLiSqmPxkFLDD+qQ7+wtWLHE7J+sk+oqqPusmKvYzEE8WPJY3pC13qdH5BpVj/H KEByci2G2IeL5pjraapEfrIAWbOj7B7aFifnIYDyc/7rWbTWTi0WBDIY/3b3zZNYrd9ZNtA8dJE j8Ho9lfgCfXo7j3ZEkdt3vKoEyjk3SGZT4vL0QZL6RcX3zzHFQRVRbcZlVeyx1K7xl6jSog40Xg KkEsghd7Fe4JNz649BHvRIc5g+/hTHlqWqCooCrRxFxS4lMDX4ikW0n1cSsMsnEAMjGGJjS4xCC m6tWz6yAlDF7+2g19/A6dOOMp446LD+Zipq9HV67TJvAsqKI5tZ7Tqy49voJCe7JDAKCFIj6+gc juwxFW8LaU0Ru8mhKqJxoWGpTVNwvhlQ== X-Received: by 2002:a05:6000:1786:b0:435:dd81:4f4d with SMTP id ffacd0b85a97d-435f3a7bf2fmr203159f8f.26.1769702981438; Thu, 29 Jan 2026 08:09:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/43] hw/arm/virt: Set msi-gpa property Date: Thu, 29 Jan 2026 16:08:52 +0000 Message-ID: <20260129160917.1415092-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703193624158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Set the MSI doorbell GPA property for accelerated SMMUv3 devices for use by KVM MSI setup. Also, since any meaningful use of vfio-pci devices with an accelerated SMMUv3 requires both KVM and a kernel irqchip, ensure those are specified when accel=3Don is selected. Reviewed-by: Nicolin Chen Tested-by: Eric Auger Tested-by: Zhangfei Gao Reviewed-by: Jonathan Cameron Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-19-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/virt.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 4badc1a734..91fec582ed 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3061,6 +3061,26 @@ static void virt_machine_device_pre_plug_cb(HotplugH= andler *hotplug_dev, object_property_set_link(OBJECT(dev), "secure-memory", OBJECT(vms->secure_sysmem), NULL); } + if (object_property_find(OBJECT(dev), "accel") && + object_property_get_bool(OBJECT(dev), "accel", &error_abort)) { + hwaddr db_start =3D 0; + + if (!kvm_enabled() || !kvm_irqchip_in_kernel()) { + error_setg(errp, "SMMUv3 accel=3Don requires KVM with " + "kernel-irqchip=3Don support"); + return; + } + + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { + /* GITS_TRANSLATER page + offset */ + db_start =3D base_memmap[VIRT_GIC_ITS].base + 0x10000 + 0x= 40; + } else if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_GICV2M) { + /* MSI_SETSPI_NS page + offset */ + db_start =3D base_memmap[VIRT_GIC_V2M].base + 0x40; + } + object_property_set_uint(OBJECT(dev), "msi-gpa", db_start, + &error_abort); + } } } =20 --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703260; cv=none; d=zohomail.com; s=zohoarc; b=eV8I19oRESm6Tnrohy5tV9snz1OAujoLLnfRJWQxccV0NOu51S0EUI/vduC3jgFuWqzJMnjUMGlI8lBhY9/bdOnkCvRjqiE/ViHPJ4qQd+NvVa5UpSWG6aFw+q7hJSh4lDN+s+/6pbuScjG4cPPrMs9Q0O3gP/KcQy3mLQdFrOo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703260; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=1Skn1NkK+rIcRVPm41pJgvKglu9iuy67JyQUMi7ziwg=; b=aBK1rmXxgzNpgGRuBxSMbCd9YF6A3MdNHOXjHkVQIXYitBO8KTexZnxJvARTtYZ2Yu084kStFmtr16ZDNDIIhsB9OWuxlNFI8MrJbWfqwyvLHRpbLCcbhOWIPuRD+I7OdD1w90ZhQASPk16TrVn2BaK3rACG0nnpzRbAbty/p/8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703260131516.8463964174571; Thu, 29 Jan 2026 08:14:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUb1-0001UE-VP; Thu, 29 Jan 2026 11:10:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUad-0000Fi-FK for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:51 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaW-0006dm-3f for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:45 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-42fbc305882so823295f8f.0 for ; Thu, 29 Jan 2026 08:09:43 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702983; x=1770307783; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=1Skn1NkK+rIcRVPm41pJgvKglu9iuy67JyQUMi7ziwg=; b=af9db/WfNHVNJ3A+dWQxRTmhkaTs0Kyg8Xm/rtuCAK8IbiIQ6QaxRrk4MoWDBCk/Yt FD97itt/Yfu7CTRQQw1jrDKLsqvnvezUn/L/JzQRcuaYaiBDMW814kGSqpussudepxq6 8lnpDv/tJ7kptG45WBT01e72x5v3oDumnMKWbW57z8bEU/FJBNi5146+k4EsiMk/WWO4 CtPBeJXpjQCdwUm2nMUFJtd/XhWR7PSF+a6CntNNWWUIIHxALTraG6b2jTWiVE9Sf4Zg 5V2nNQ1LtO/IkeXThmIX0CR0r6Ys1ciPeUQc9pQhCbcmNy0CiW3L7zyrXEgiSrO+XRAW 8fvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702983; x=1770307783; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=1Skn1NkK+rIcRVPm41pJgvKglu9iuy67JyQUMi7ziwg=; b=e+iaJO/TqI62ba5OSpf/WyWCLnzHJ6JTLyKFMEdGAdlkGflybmCnTntbJqt4wah6aE xAkDalQLD+gMmq8qX+8lfmxJMvcUggCjektI69PidPZLIYVEr6k4SwLNuBIIknPUhBsh 0OHXX0aLarRIFBUFL2W6Ai1cckVCrd5R4hGMPEJDZAfWIJAeDXaxepNYST9rJin4NIjC BOAo2CuAIVxzJuDBrj61uPTSTaggbIrL/OZ1jgxq3l9Jvah7QD2SObC/+BFG6ymzabQk Y7FU1yN4nZkuW1ER6IlizYWgU1AGZGq1PmxpRA6z8FxAWA7waxq+o+JxYz5rEyVH3ax8 YQsw== X-Gm-Message-State: AOJu0Yz294PYola5MilatUPkpfRg4ME4FFzOx+wsTX5Ian93Le5z3Lyt 2zgL1qipaKKubwH6M0bD3cuVQfFJktHyNo6uRBvwT0K/mG5DS/prMuc41PZRDsnWPz6vPO9tAd3 +k9mid/0= X-Gm-Gg: AZuq6aKbVQOS3ipkev8m5RuNpphXMxTN+b6ick9CxOedia+gpkdvQcgG+tmoAigvd4g yUZ/lSdn3xZCGDGc1CWkJZ2CAQCZuGF/hDx50hDvPxVozs0iGgg0r89k6s3TynAwQmnrMIGOtn2 mSiJSS0Z7qWiCZH+W+GDjtNy0oV2M02VuLNcdEgiEXUcEiZFNlEJ5K0Oq4ILDT3fqPzSxAPynHw Ckn3x4Dr5w70ZBDBERyzHmQz3Hap6Dr7l+bvgG5SCI14oigqNlMpmKTdU77sM/21N76sy4+aMh+ rS7w3u+6M9gZ5TlGq0M8cVNJDnNySeoRBYpSOuiXfTUlsWPSv1vX2VQsDxRdb6JzX7mKMnTeMpB WyTaN5ZQi5ix7lntcAJ4LfTmwcFm31zOQrXFffzlvzambU6Fixx+vrkq6N5w4J+FpZUsAZrOQgz FRxorQiiC2XPAKi51Za9vsX48V/JVe0sYFGKGSHLHK X-Received: by 2002:a05:6000:4308:b0:435:a370:2d71 with SMTP id ffacd0b85a97d-435f3aaa9b8mr148089f8f.33.1769702982475; Thu, 29 Jan 2026 08:09:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/43] hw/arm/smmuv3-accel: Add support to issue invalidation cmd to host Date: Thu, 29 Jan 2026 16:08:53 +0000 Message-ID: <20260129160917.1415092-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703261364154100 From: Shameer Kolothum Provide a helper and use that to issue the invalidation cmd to host SMMUv3. We only issue one cmd at a time for now. Support for batching of commands=C2=A0will be added later after analysing t= he impact. Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-20-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 36 ++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 8 ++++++++ hw/arm/smmuv3.c | 16 ++++++++++++++++ 3 files changed, 60 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index c6ee123cdf..89dc6f991c 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -233,6 +233,42 @@ bool smmuv3_accel_install_ste_range(SMMUv3State *s, SM= MUSIDRange *range, return all_ok; } =20 +/* + * This issues the invalidation cmd to the host SMMUv3. + * + * sdev is non-NULL for SID based invalidations (e.g. CFGI_CD), and NULL f= or + * non SID invalidations such as SMMU_CMD_TLBI_NH_ASID and SMMU_CMD_TLBI_N= H_VA. + */ +bool smmuv3_accel_issue_inv_cmd(SMMUv3State *bs, void *cmd, SMMUDevice *sd= ev, + Error **errp) +{ + SMMUv3State *s =3D ARM_SMMUV3(bs); + SMMUv3AccelState *accel =3D s->s_accel; + uint32_t entry_num =3D 1; + + /* + * No accel or viommu means no VFIO/IOMMUFD devices, nothing to + * invalidate. + */ + if (!accel || !accel->viommu) { + return true; + } + + /* + * SID based invalidations (e.g. CFGI_CD) apply only to vfio-pci endpo= ints + * with a valid vIOMMU vdev. + */ + if (sdev && !container_of(sdev, SMMUv3AccelDevice, sdev)->vdev) { + return true; + } + + /* Single command (entry_num =3D 1); no need to check returned entry_n= um */ + return iommufd_backend_invalidate_cache( + accel->viommu->iommufd, accel->viommu->viommu_id, + IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3, + sizeof(Cmd), &entry_num, cmd, errp); +} + static bool smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, Error **errp) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index c7ed4dce3a..41b37e3122 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -47,6 +47,8 @@ bool smmuv3_accel_install_ste(SMMUv3State *s, SMMUDevice = *sdev, int sid, bool smmuv3_accel_install_ste_range(SMMUv3State *s, SMMUSIDRange *range, Error **errp); bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error **errp); +bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sde= v, + Error **errp); void smmuv3_accel_reset(SMMUv3State *s); #else static inline void smmuv3_accel_init(SMMUv3State *s) @@ -68,6 +70,12 @@ static inline bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3S= tate *s, Error **errp) { return true; } +static inline bool +smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sdev, + Error **errp) +{ + return true; +} static inline void smmuv3_accel_reset(SMMUv3State *s) { } diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 6ed9914b1e..4efef73373 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1388,6 +1388,10 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error= **errp) =20 trace_smmuv3_cmdq_cfgi_cd(sid); smmuv3_flush_config(sdev); + if (!smmuv3_accel_issue_inv_cmd(s, &cmd, sdev, errp)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } break; } case SMMU_CMD_TLBI_NH_ASID: @@ -1411,6 +1415,10 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error= **errp) trace_smmuv3_cmdq_tlbi_nh_asid(asid); smmu_inv_notifiers_all(&s->smmu_state); smmu_iotlb_inv_asid_vmid(bs, asid, vmid); + if (!smmuv3_accel_issue_inv_cmd(s, &cmd, NULL, errp)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } break; } case SMMU_CMD_TLBI_NH_ALL: @@ -1438,6 +1446,10 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error= **errp) trace_smmuv3_cmdq_tlbi_nsnh(); smmu_inv_notifiers_all(&s->smmu_state); smmu_iotlb_inv_all(bs); + if (!smmuv3_accel_issue_inv_cmd(s, &cmd, NULL, errp)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } break; case SMMU_CMD_TLBI_NH_VAA: case SMMU_CMD_TLBI_NH_VA: @@ -1446,6 +1458,10 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error= **errp) break; } smmuv3_range_inval(bs, &cmd, SMMU_STAGE_1); + if (!smmuv3_accel_issue_inv_cmd(s, &cmd, NULL, errp)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } break; case SMMU_CMD_TLBI_S12_VMALL: { --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703050; cv=none; d=zohomail.com; s=zohoarc; b=nXxebvasKc9HIhdPOuU+CQz34c5tjz+Hl7BxDpxl9n5Ld6o5X/OceIya4TVCQZ0YwInuglpeVnBx6u2/wA8eEQQ4kbSAXdsCHTkrZhfbKEiaYVsXpbKAogI3LalighoRInU4cOQJavDzOH5ITTbcqqCjF8LVUoQLNYanaqXQw7E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703050; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=8J4eY9wxv1cYUuMQ9c6DeC3OQdL9/UJSVtl7VAJyfKI=; b=P1lOSATfcwY2Lerj4EnU+7AmTfjXPdbSkRoW/G4iZkC1dsWqNgBPs8G1W9qubjHNd/zn94w0r4Q9kpLANSsEbmWfRrh5Y3tpY8QZI7FPTHzvbp4vwpyLdfZJN63l4/IjbM6DUyoXTkKZWnK25FszEU+Os6IKUn5xlJKd8GE7D6I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703050232259.7555679116748; Thu, 29 Jan 2026 08:10:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUax-0001BZ-6U; Thu, 29 Jan 2026 11:10:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUae-0000JJ-Qm for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:53 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUac-0006eG-LU for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:52 -0500 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-432d2c7a8b9so1159783f8f.2 for ; Thu, 29 Jan 2026 08:09:44 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702984; x=1770307784; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8J4eY9wxv1cYUuMQ9c6DeC3OQdL9/UJSVtl7VAJyfKI=; b=Az96hfw43lFu6Ug1d+QxrcQZEUdRvx1fYUbronjAIuzO9kc7kvwr6SnPwU/ovNbg10 tc8i7NimXSdCKu1TSF2hjUcPxYkGUHkexPu6/xE1SqvqohRcrPaBvgO9zaWpdhpLwY2x UOBiKqpI742or8cj0RPEVNOFRuN05BJw4KQaqfWpzpanHFplb7EBX5hXBl1P3uBOUApx BZBjclJjvtxW77BNkFfS8efuDQPo90CJCgS5x5OFzUfaNakG+nqZ11b8o0eTzy3T0ZcE 7Tdi9g6s1SNQ9/lHOw/Xg9xmflFWxtcFYi16LBGE9ZXPUUpDsgd5nSlnF59oipDmWJZ/ SQNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702984; x=1770307784; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=8J4eY9wxv1cYUuMQ9c6DeC3OQdL9/UJSVtl7VAJyfKI=; b=pgqXrmCVa4kD0hSflWMN5/1oavX1t0gOxVBfirkvZ0rp/ToAS3X3PggRChZ4l5CNwh TaWikHtQyu7b6A+KzvrZGIVchvX42kCf3Z9pSh1h6aaPp74gAm4GMFi2V49EVg57Rd+0 ZU+dwb80AluZB8eh2hToBP7M6rhu95TlpZgQz5U2T/5ctvcEV1ieDQuPtF8JRX06XEyw lPJ3MLg9G8R6zLFJ+kZlPB2GnWxz7ROccdX9p2HxJeHC9+PAQP5MnsnTx/sZCTHocKLA ykimz/xVUqAxVvS5ELKpeKZZyOsrIrVLNaIFUOxmComSgeHv72TG+nP+JPkkL9sNcIAi hyNw== X-Gm-Message-State: AOJu0YyMulYFoHKhlccG9jyFodEIbCV5WeXevPsnH3WSC7aEOM4tC+Jz U3xlq1DdcagExVHhLTdPAqg8NLzAhB/Hg5DPa+udyq60nM6F7BsHbFTk3enoURvboK0Lnzx3PfB GvLIxa/I= X-Gm-Gg: AZuq6aJPeSbcSfmV+4w+yELP478CJtrpSoZdqszXWu+GtboSvxNNkg4qiL+cy2Zbn5d NwhFdxbdNdy7ZCMNo2ip21XFbwact3oz8IfIMPxC5JDqLIBhzMS7L/3yUlznepldap9Vvh3VGjl +kqiV0YLl8RGBW0KS4oF94+ymXMJhiFjQvDUFhnj5p3rwUap55LDfYLXnyqeUWV3MkN/PWna4Ls 0aCgzYJrsSBJCFWnG311Ma8qhsktXDQ7nOAvHROmyuUvO4CneJcOCDOnk881Co20LwYhTp9aeSd vkLkoX1ByZ2C5O2xiAhG1HJQfTmVkw7yuUr30Sj5ML8JuPWYBwQc872ZuCqDlCffxjTENQSZ+/v x80hB7LhCYm7ZBWlGV21KFUx5hC7SJT7DdyKdcOQd1/P+iJDGEI7uTcbhPaKVSDq0PxW/CbVFst j6pRABlNcUUiEOmwnwhcBHxqQqWeAVsA== X-Received: by 2002:a5d:5d06:0:b0:435:e450:f05e with SMTP id ffacd0b85a97d-435f3abb7d7mr126369f8f.63.1769702983580; Thu, 29 Jan 2026 08:09:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/43] hw/arm/smmuv3: Initialize ID registers early during realize() Date: Thu, 29 Jan 2026 16:08:54 +0000 Message-ID: <20260129160917.1415092-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703050810158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Factor out ID register init into smmuv3_init_id_regs() and call it from realize(). This ensures ID registers are initialized early for use in the accelerated SMMUv3 path and will be utilized in subsequent patch. Other registers remain initialized in smmuv3_reset(). Reviewed-by: Nicolin Chen Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-21-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 4efef73373..e301bb467d 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -258,7 +258,12 @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo= *info) info->recorded =3D true; } =20 -static void smmuv3_init_regs(SMMUv3State *s) +/* + * Called during realize(), as the ID registers will be accessed early in = the + * SMMUv3 accel path for feature compatibility checks. The remaining regis= ters + * are initialized later in smmuv3_reset(). + */ +static void smmuv3_init_id_regs(SMMUv3State *s) { /* Based on sys property, the stages supported in smmu will be adverti= sed.*/ if (s->stage && !strcmp("2", s->stage)) { @@ -298,7 +303,11 @@ static void smmuv3_init_regs(SMMUv3State *s) s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1); s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1); s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1); + s->aidr =3D 0x1; +} =20 +static void smmuv3_reset(SMMUv3State *s) +{ s->cmdq.base =3D deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS); s->cmdq.prod =3D 0; s->cmdq.cons =3D 0; @@ -310,7 +319,6 @@ static void smmuv3_init_regs(SMMUv3State *s) =20 s->features =3D 0; s->sid_split =3D 0; - s->aidr =3D 0x1; s->cr[0] =3D 0; s->cr0ack =3D 0; s->irq_ctrl =3D 0; @@ -1903,7 +1911,7 @@ static void smmu_reset_exit(Object *obj, ResetType ty= pe) c->parent_phases.exit(obj, type); } =20 - smmuv3_init_regs(s); + smmuv3_reset(s); smmuv3_accel_reset(s); } =20 @@ -1935,6 +1943,7 @@ static void smmu_realize(DeviceState *d, Error **errp) sysbus_init_mmio(dev, &sys->iomem); =20 smmu_init_irq(s, dev); + smmuv3_init_id_regs(s); } =20 static const VMStateDescription vmstate_smmuv3_queue =3D { --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703126; cv=none; d=zohomail.com; s=zohoarc; b=i2xlmjb0+U06dKY0My7blZe10IlpK/xSC/Nr/4PsKuU+CCIz18T/PZDVpfyjlVQ86nHMyGPLRcEV7srciib/hRgj5rE6PtzJbOMVdXl+YZNIbZdx011UHEBc6JoUsBSztyPJFusT7aAOwDNPZOytAHR/OaI+6lR4owiPlZ8toTY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703126; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=SXWhyW9afnvWJxgYgWEwCAWLC5peiCBqo1W4LCVPCMY=; b=VhBqrLxnYy2kUwS8ON/SA8Jg1+ilOWpZB20vpxv7dRCqr6o34gMJFy4wVCEJMP8M/2YcDrFdPcl+SF6Z0qBpPPRoX7tj2t5DgL0fM1XO9iGWgG/GJnq5u9g1Uptthf1lqWJTlhEHWzBJDpozYJWyZTtdA+DvJtQXp9DHn1qilgM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703126902966.998219300068; Thu, 29 Jan 2026 08:12:06 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUax-0001Cy-EJ; Thu, 29 Jan 2026 11:10:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUag-0000KJ-I1 for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:55 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUad-0006el-5O for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:54 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-43591b55727so1042778f8f.3 for ; Thu, 29 Jan 2026 08:09:45 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702985; x=1770307785; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=SXWhyW9afnvWJxgYgWEwCAWLC5peiCBqo1W4LCVPCMY=; b=mfy3crysTUTfScP/EQnW4IfVQmYNc5KoghUnp2ldzbVsXVY/t4GhUOVURr0Tt8SutM 2H99gPWxm+XSBojNKYD4f4HWHxr+9ODhm3T7Tlfrsg27eoK1p1JhlD+o3zLzZgO0MU1H 0NFnIFgwz1HjYNZSYB7UVEz7RDnhi2DTT2eKAPuIKn3V6MOjRSLrPChGMfEbNufesJ4C fJJPz51k5ZJsAqJuqf1IQlwYt+oRfV62rFVV7Oi7azIhWxT3Lc6uGu9zlZ7GZ72FvLDr vb4xjwvYu/ZzRhYD3olesHdubOSc2c4HPyhO0+ImFPu3lz2ku2HNkMC8RzZr9g9tfCvP i4ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702985; x=1770307785; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=SXWhyW9afnvWJxgYgWEwCAWLC5peiCBqo1W4LCVPCMY=; b=et3wwQ9pn2i6eWz54pImbd0eGL25t+BjVvrzGl5sB/L+t2iqS8XWmWu/ML1vI2F9tj l++RDRdAdVvbngF7V6yk7Bra0prMTUjeEAu4irnzpBi46hfxDSklrncxhMk/11f0XB4D bG7eV03P71QXFgvboI4uEDuKiwczPoSPTBo52AJhQRPqliLuAnsUNoD/7Eb76q53c76t 4/PaIm+AxRNvXNztAd6DIA+WsSqHvLzRdp92VQPQJgas0c6AXWoCYbVkJPZIa6Pk3poH 3hfbdVR1bSlFpeQiRRERs9X3z2NUsxWy5dOyo21D7GGm6fr/L48SHwmKfM/B4cMB+faG 36eQ== X-Gm-Message-State: AOJu0YyTA/4Ul7LE+S6AZ/gVIl3GyF/kA7CfIZbzQOLWDyQs5eNdYdhp HgA6szJtz9q8EKvJNbDixVo6BkeMln0uz6TbYyQt4mOq3Z32I56TzJAjQGuLtuJfEmYQ96qu+0j 06JVTgRg= X-Gm-Gg: AZuq6aJAix+rJ/umRrG2o0PrY+kxH0eQjjCQxDensSS9regXv9UlL8yCkweI04z73el TkjTW3pXzgAuVZcZZzMBOxouo0Xl/hQ2fFkSq6a/Camv8+nT7yqViWQQSRMKzYEoei4nm64rEXl 594HPmMmg8hshgNfCXKhhnjMf+/6Zx1qshpJn5LWeFeoT4wVthAqjqlAgA61Mv271zEjCx1CKzC 2z0LCemgr94l/7Yar5As8AX89O4tbqW9yM22PqK1PypW/Mw73jAiQDI178LXMDJLcVvwOWjKr8k VCC5aTHrQhsOhMVSaRuC3Nfo5m5dq4fVCgwrGS24bFoKYsOw5MivNFu94HJ/mPIll1GjmHWPgd9 ZnTO7g5vue03KC+JISYtCUq4NmuCBWh20mcnOjBpZNT3Xk/eZs8eSqqvuZbt0aVAktIWrN/lKP+ 3ClkSSYSurVU//RDiXu4N3oOETTNJuuQ== X-Received: by 2002:a05:6000:24c3:b0:431:327:5dd4 with SMTP id ffacd0b85a97d-435f3ab000fmr128893f8f.46.1769702984642; Thu, 29 Jan 2026 08:09:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/43] hw/arm/smmuv3-accel: Get host SMMUv3 hw info and validate Date: Thu, 29 Jan 2026 16:08:55 +0000 Message-ID: <20260129160917.1415092-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703129600154100 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Just before the device gets attached to the SMMUv3, make sure QEMU SMMUv3 features are compatible with the host SMMUv3. Not all fields in the host SMMUv3 IDR registers are meaningful for userspac= e. Only the following fields can be used: - IDR0: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN, CD2L, ASID16, TTF - IDR1: SIDSIZE, SSIDSIZE - IDR3: BBML, RIL - IDR5: VAX, GRAN64K, GRAN16K, GRAN4K For now, the check is to make sure the features are in sync to enable basic accelerated SMMUv3 support. AIDR is not checked, as hardware implementations often provide a mix of architecture features regardless of the revision reported in AIDR. Note that SSIDSIZE check will be added later when support for PASID is introduced. Reviewed-by: Nicolin Chen Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-22-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 101 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 89dc6f991c..33011962e3 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -27,6 +27,99 @@ static MemoryRegion root, sysmem; static AddressSpace *shared_as_sysmem; =20 +static bool +smmuv3_accel_check_hw_compatible(SMMUv3State *s, + struct iommu_hw_info_arm_smmuv3 *info, + Error **errp) +{ + /* QEMU SMMUv3 supports both linear and 2-level stream tables */ + if (FIELD_EX32(info->idr[0], IDR0, STLEVEL) !=3D + FIELD_EX32(s->idr[0], IDR0, STLEVEL)) { + error_setg(errp, "Host SMMUv3 Stream Table format mismatch " + "(host STLEVEL=3D%u, QEMU STLEVEL=3D%u)", + FIELD_EX32(info->idr[0], IDR0, STLEVEL), + FIELD_EX32(s->idr[0], IDR0, STLEVEL)); + return false; + } + + /* QEMU SMMUv3 supports only little-endian translation table walks */ + if (FIELD_EX32(info->idr[0], IDR0, TTENDIAN) > + FIELD_EX32(s->idr[0], IDR0, TTENDIAN)) { + error_setg(errp, "Host SMMUv3 doesn't support Little-endian " + "translation table"); + return false; + } + + /* QEMU SMMUv3 supports only AArch64 translation table format */ + if (FIELD_EX32(info->idr[0], IDR0, TTF) < + FIELD_EX32(s->idr[0], IDR0, TTF)) { + error_setg(errp, "Host SMMUv3 doesn't support AArch64 translation " + "table format"); + return false; + } + + /* QEMU SMMUv3 supports SIDSIZE 16 */ + if (FIELD_EX32(info->idr[1], IDR1, SIDSIZE) < + FIELD_EX32(s->idr[1], IDR1, SIDSIZE)) { + error_setg(errp, "Host SMMUv3 SIDSIZE not compatible " + "(host=3D%u, QEMU=3D%u)", + FIELD_EX32(info->idr[1], IDR1, SIDSIZE), + FIELD_EX32(s->idr[1], IDR1, SIDSIZE)); + return false; + } + + /* QEMU SMMUv3 supports Range Invalidation by default */ + if (FIELD_EX32(info->idr[3], IDR3, RIL) !=3D + FIELD_EX32(s->idr[3], IDR3, RIL)) { + error_setg(errp, "Host SMMUv3 doesn't support Range Invalidation"); + return false; + } + + /* QEMU SMMUv3 supports GRAN4K/GRAN16K/GRAN64K translation granules */ + if (FIELD_EX32(info->idr[5], IDR5, GRAN4K) !=3D + FIELD_EX32(s->idr[5], IDR5, GRAN4K)) { + error_setg(errp, "Host SMMUv3 doesn't support 4K translation granu= le"); + return false; + } + if (FIELD_EX32(info->idr[5], IDR5, GRAN16K) !=3D + FIELD_EX32(s->idr[5], IDR5, GRAN16K)) { + error_setg(errp, "Host SMMUv3 doesn't support 16K translation gran= ule"); + return false; + } + if (FIELD_EX32(info->idr[5], IDR5, GRAN64K) !=3D + FIELD_EX32(s->idr[5], IDR5, GRAN64K)) { + error_setg(errp, "Host SMMUv3 doesn't support 64K translation gran= ule"); + return false; + } + + return true; +} + +static bool +smmuv3_accel_hw_compatible(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, + Error **errp) +{ + struct iommu_hw_info_arm_smmuv3 info; + uint32_t data_type; + uint64_t caps; + + if (!iommufd_backend_get_device_info(idev->iommufd, idev->devid, &data= _type, + &info, sizeof(info), &caps, errp)= ) { + return false; + } + + if (data_type !=3D IOMMU_HW_INFO_TYPE_ARM_SMMUV3) { + error_setg(errp, "Wrong data type (%d) for Host SMMUv3 device info= ", + data_type); + return false; + } + + if (!smmuv3_accel_check_hw_compatible(s, &info, errp)) { + return false; + } + return true; +} + static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *= sbus, PCIBus *bus, int devfn) { @@ -353,6 +446,14 @@ static bool smmuv3_accel_set_iommu_device(PCIBus *bus,= void *opaque, int devfn, return true; } =20 + /* + * Check the host SMMUv3 associated with the dev is compatible with the + * QEMU SMMUv3 accel. + */ + if (!smmuv3_accel_hw_compatible(s, idev, errp)) { + return false; + } + if (s->s_accel->viommu) { goto done; } --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703100; cv=none; d=zohomail.com; s=zohoarc; b=K9NvfFAdDrcr2yb4oov/3+3aY52TwD4kQIHkNYm3FjWGXbVaCgJzAs3jQZ5zk5Nd1isarCeL4wggtJq6obTaqAhKnnOvFag5Js3Ggot7LYPZGICpw9R0a9skwHrsmndxtSXLk7AYjOKNxb1H0fWmjIKNx/hsv2t+u+dXJmwZ0do= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703100; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=eMcVG4md74Ay1zuipzEe30vEGwsgGydjvAvH9T9QNys=; b=a+sbCrXSuda8JbMQt17qWx85ycWRuToducOf5E4s7BbydgJx0UzxAbC2kT9x0pPFgXTAUttoHKc8PTOTE8+NwI6PEJoxFFzVX0jPvwguo8eBypuFWYzTXgnMJyYfCe+GBCAwPaADWDtnxzphaaebZu4pmR7T7hOmLJIpkrsDRQg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703100207237.9234777609812; Thu, 29 Jan 2026 08:11:40 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUaw-000170-CT; Thu, 29 Jan 2026 11:10:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUag-0000KK-If for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:55 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUad-0006fM-5D for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:54 -0500 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-42fbc305914so1105565f8f.0 for ; Thu, 29 Jan 2026 08:09:47 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702986; x=1770307786; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=eMcVG4md74Ay1zuipzEe30vEGwsgGydjvAvH9T9QNys=; b=OfrBITATczyszCrhoxRt1gF4H1RnFVK7ZIN9iRLnfNTeV+/up0kzGjH1JZTXcO1dDa nlcaICTAnNsC1iCcUOlmtcdIOuCTiq9yPKulj6/AuzRsIH3slEWg/UQAZHZNSKdXpWYO +SA94XlPoKPM80NwUo6CnbC/kYziZiVGqdsYrQtpaS+3xXbeNwUZIYRCALBoE1a3RU/t DOWxNzzUS8cXjXSqU8v4jlU3eVnqq/zwcFdQDYf/Kz2rRCzL2zMpMDIuGbLq0dzOE+WO vBTRXJEdowOj56xbb2dpZmItbbglRsmBKtay1y59AU6UkqnyfQEa5ICMoQ/sKr0Ml16M 7PXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702986; x=1770307786; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=eMcVG4md74Ay1zuipzEe30vEGwsgGydjvAvH9T9QNys=; b=jsbt1ckUia1bRPgmNBCofDOFiC5s1OLST5UxU3IRVDuYWYf1/ptSA+s3GXZcLbc9JZ kYyyqG16fDyHlvTWD3zvwvVZHVdfptRIJ2LTxg9hbN0Lp7b0X6mRZti68WE84Hzn3SKj +w7FwkDE680LzQlQ7TH0pKeYBbN8FcifQn+wE7NWceP1ILpAk3TmDf+fh4alFF/OimUR UbaSp7Q7WIwyspWBIr6Tp6ENbZ34Rlt22Y6OWgnenYjghSWKFOjrkY93eJCNDZ3Z7+JT MvvoJqQDTCxd+ae9ZHh102UudKGczvOaNoxtc2ZUxlBMc01v6AadFq1YKiwkdiZGEKaz sSmg== X-Gm-Message-State: AOJu0Yz3RwNlFUMUVWuzmJmAxXoigqB9Dfz1k4e4rv4PhHDlz/LjmcFx 50R/Ch+qkOCE9rTgi9YGVuLr5hgRCybCju/gyfybAQWYdyV9pKTtNnWRY7f1ucRX8JLgmrBa/TG 2B3XaR3A= X-Gm-Gg: AZuq6aLcJ/g7zYYZtgTw8eYmYdl16mBjU4PBqsinCWDr2KskkcJPMCOzN/zJ6EOnMKl aSFyzuf+JmDVkgXVL6mQD3oGwye2pXp6s2zMOWRpzUxDoCMK+P/zuX4hTFN3ljJfsazVm7KDAg8 Y/L7E5YOAQcFBr3O+wAoaXVg2+CuCMMB66egsyHf76fEYlzRgIwDyAfKNzM/t1Llyd9tB7C+5wg 3PDvO7c03hXljX1j3aLfK8t7CYVWNjGmLlAwNIxeFAJUbM3aRLWyuI6mu0AOMRRf4wy+78miBSz Ft54eCpIa8/qeEzRXY3saJoQc7TJAtCTzefhNHM0sZd5HHkkJ6gZAWNxxQXO8GdL86+4OzUXIpr D8H5+q4VrXIUQAnoWKjo+P2Rdw/J+2PsR/9tPt/JpD1yuYl+v9OfI3TExqiFR5+KZfLbUiJ2EGi OseQIJ/FPQio6lj2cNcDG6kNFJgWf2UA== X-Received: by 2002:a05:6000:2489:b0:432:5b81:483 with SMTP id ffacd0b85a97d-435f3a9244bmr171355f8f.24.1769702986073; Thu, 29 Jan 2026 08:09:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/43] hw/pci-host/gpex: Allow to generate preserve boot config DSM #5 Date: Thu, 29 Jan 2026 16:08:56 +0000 Message-ID: <20260129160917.1415092-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703101157158500 From: Eric Auger Add a 'preserve_config' field in struct GPEXConfig and, if set, generate the _DSM function #5 for preserving PCI boot configurations. This will be used for SMMUv3 accel=3Don support in subsequent patch. When SMMUv3 acceleration (accel=3Don) is enabled, QEMU exposes IORT Reserved Memory Region (RMR) nodes to support MSI doorbell translations. As per the Arm IORT specification, using IORT RMRs mandates the presence of _DSM function #5 so that the OS retains the firmware-assigned PCI configuration. Hence, this patch adds conditional support for generating _DSM #5. According to the ACPI Specification, Revision 6.6, Section 9.1.1 - =E2=80=9C_DSM (Device Specific Method)=E2=80=9D, " If Function Index is zero, the return is a buffer containing one bit for each function index, starting with zero. Bit 0 indicates whether there is support for any functions other than function 0 for the specified UUID and Revision ID. If set to zero, no functions are supported (other than function zero) for the specified UUID and Revision ID. If set to one, at least one additional function is supported. For all other bits in the buffer, a bit is set to zero to indicate if that function index is not supported for the specific UUID and Revision ID. (For example, bit 1 set to 0 indicates that function index 1 is not supported for the specific UUID and Revision ID.) " Please refer PCI Firmware Specification, Revision 3.3, Section 4.6.5 =E2=80= =94 "_DSM for Preserving PCI Boot Configurations" for Function 5 of _DSM method. Also, while at it, move the byte_list declaration to the top of the function for clarity. At the moment, DSM generation is not yet enabled. The resulting AML when preserve_config=3Dtrue is: Method (_DSM, 4, NotSerialized) { If ((Arg0 =3D=3D ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d"= ))) { If ((Arg2 =3D=3D Zero)) { Return (Buffer (One) { 0x21 }) } If ((Arg2 =3D=3D 0x05)) { Return (Zero) } } ... } Cc: Michael S. Tsirkin Signed-off-by: Eric Auger Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Tested-by: Zhangfei Gao Tested-by: Eric Auger Reviewed-by: Jonathan Cameron Reviewed-by: Michael S. Tsirkin Message-id: 20260126104342.253965-23-skolothumtho@nvidia.com [Shameer: Removed possible duplicate _DSM creations] Signed-off-by: Shameer Kolothum Tested-by: Zhangfei Gao Reviewed-by: Jonathan Cameron Reviewed-by: Michael S. Tsirkin Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Signed-off-by: Peter Maydell --- hw/pci-host/gpex-acpi.c | 29 +++++++++++++++++++++++------ include/hw/pci-host/gpex.h | 1 + 2 files changed, 24 insertions(+), 6 deletions(-) diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index 4587baeb78..d9820f9b41 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -51,10 +51,11 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uin= t32_t irq, } } =20 -static Aml *build_pci_host_bridge_dsm_method(void) +static Aml *build_pci_host_bridge_dsm_method(bool preserve_config) { Aml *method =3D aml_method("_DSM", 4, AML_NOTSERIALIZED); Aml *UUID, *ifctx, *ifctx1, *buf; + uint8_t byte_list[1] =3D {0}; =20 /* PCI Firmware Specification 3.0 * 4.6.1. _DSM for PCI Express Slot Information @@ -64,10 +65,23 @@ static Aml *build_pci_host_bridge_dsm_method(void) UUID =3D aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); ifctx =3D aml_if(aml_equal(aml_arg(0), UUID)); ifctx1 =3D aml_if(aml_equal(aml_arg(2), aml_int(0))); - uint8_t byte_list[1] =3D {0}; + if (preserve_config) { + /* support functions other than 0, specifically function 5 */ + byte_list[0] =3D 0x21; + } buf =3D aml_buffer(1, byte_list); aml_append(ifctx1, aml_return(buf)); aml_append(ifctx, ifctx1); + if (preserve_config) { + Aml *ifctx2 =3D aml_if(aml_equal(aml_arg(2), aml_int(5))); + /* + * 0 - The operating system must not ignore the PCI configuration = that + * firmware has done at boot time. + */ + aml_append(ifctx2, aml_return(aml_int(0))); + aml_append(ifctx, ifctx2); + } + aml_append(method, ifctx); =20 byte_list[0] =3D 0; @@ -77,12 +91,13 @@ static Aml *build_pci_host_bridge_dsm_method(void) } =20 static void acpi_dsdt_add_host_bridge_methods(Aml *dev, - bool enable_native_pcie_hotp= lug) + bool enable_native_pcie_hotp= lug, + bool preserve_config) { /* Declare an _OSC (OS Control Handoff) method */ aml_append(dev, build_pci_host_bridge_osc_method(enable_native_pcie_hotplug= )); - aml_append(dev, build_pci_host_bridge_dsm_method()); + aml_append(dev, build_pci_host_bridge_dsm_method(preserve_config)); } =20 void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) @@ -152,7 +167,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *= cfg) build_cxl_osc_method(dev); } else { /* pxb bridges do not have ACPI PCI Hot-plug enabled */ - acpi_dsdt_add_host_bridge_methods(dev, true); + acpi_dsdt_add_host_bridge_methods(dev, true, + cfg->preserve_config); } =20 aml_append(scope, dev); @@ -227,7 +243,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *= cfg) } aml_append(dev, aml_name_decl("_CRS", rbuf)); =20 - acpi_dsdt_add_host_bridge_methods(dev, cfg->pci_native_hotplug); + acpi_dsdt_add_host_bridge_methods(dev, cfg->pci_native_hotplug, + cfg->preserve_config); =20 Aml *dev_res0 =3D aml_device("%s", "RES0"); aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h index 695886dedd..1da9c85bce 100644 --- a/include/hw/pci-host/gpex.h +++ b/include/hw/pci-host/gpex.h @@ -46,6 +46,7 @@ struct GPEXConfig { int irq; PCIBus *bus; bool pci_native_hotplug; + bool preserve_config; }; =20 typedef struct GPEXIrq GPEXIrq; --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703246; cv=none; d=zohomail.com; s=zohoarc; b=RIyDNTbhUS3IL0yJGBsT0Xsrxj7eKeV72wLpu5Ps7YFrG0CNSLJlOE/jNU1URzMD9DWfRlNXOkde7y4FusK8jYaPjTerW/UyLzB7NdVdjRJY3GU8fUKypu9tMSAXWzluwxZwnCS1pw/kLLSFcOJX6RNeP6p8WZgvt2Eq9rVAl5k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703246; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=P1FHnLGv0F1KpDJLLP83IUidm8bElFCZsHk7cWMFi/Q=; b=lDq3vTJvAShsTQgQqRyyuU3Y6j71NPdlQN+pcpE7tV/GkAn1tYMyvcNKW6N4MDBcDGOgqQj1FoPg9aYYCAs8XdaMyzsChAg0gCeVIyFHu4fA2KTGLWxvL2rAMMlfuphli6LvejEshbiFL7h0llKQVYaZC+TFkEbXvQr1U0PGrNg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703246600780.3752544675189; Thu, 29 Jan 2026 08:14:06 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUau-0000xH-V8; Thu, 29 Jan 2026 11:10:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUag-0000KI-9M for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:55 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUad-0006gr-51 for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:53 -0500 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-42fb2314eb0so1044055f8f.2 for ; Thu, 29 Jan 2026 08:09:48 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702987; x=1770307787; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=P1FHnLGv0F1KpDJLLP83IUidm8bElFCZsHk7cWMFi/Q=; b=gFbqZsPnlaG1pcG5Vrn6euayd/GMXxvyOg6f25ynz3s8xq3z+FrGk2wMjOYbbWg7ya xqmfRH3Zi18qyyFneZsOdlrwL3LdkFOYSBOUJadFD/staWutcJWkHRXhCFqGQVMvUg0O NgzNmKEfM3QdSHdsBuf7eYai6XKgJF29y7WQDpm4CEfaB2phgLG4WEIYtNQg3bt+8NDs 9o+ZCnhIUXzO/thdCxu9YY9hmVnIg5LhxnCrMgykdxj65gYI2gQlT0fSs7nnnPbwWksg r+rG1k6f0l8GqAh9Qu3a8LHAjAxHJhrlzxZ/XN/DwyTBWu3EHyDj8BrGPxvESGoDkDdr Fe1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702987; x=1770307787; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=P1FHnLGv0F1KpDJLLP83IUidm8bElFCZsHk7cWMFi/Q=; b=aLYB0504wdFryBzg7c5dCWL14OPRw16gtmLfRjbuNmUoficT15TNgTVuUnTLbQ/rpi fOGTVK1o7TMvI5ynTH7QmlRlfgdveg33hSVZQdO7jJn85xa6BgUdOEei3veuoZWDLuow dFB7AYTpcNm5vpZCn0EoTjr/rGouEKJnE38F7mfyij8KWtcVKcLU+M20BZ45Ekiyp+06 zDO1yf/GnCAxR6gMZUqlBZokzT8PKLt8i+VAjTGeOHZKMJvhxsxa4pzGLGdA9RJPT6Uc EF/u2Ar1LWERsgYp+BN7gUcDNZZnTU1WKq+PamlMrIRM7svwENAWIfDIZTZIMLzSIdYM g1OQ== X-Gm-Message-State: AOJu0YxGLnPK0ygtN0d9VhhATN6z0NiV9Evx5/5lQiTUO1lMBIk0mFhJ 1BQsy2N8lZ6Yo9jRqLH7pzov1yeoqmkzKvGStOznxw3EnCApuHDTGZSx+hNM38jIss2T4ObYgor WhU3j6JU= X-Gm-Gg: AZuq6aIbz4r5UA42FrwPdOW26aRJjUX6mO8ia+1da52fmiIDLbn79o0onJeAQeo6BzQ 9mMTk4TYuc+MTTSV09zGANK7hBlZN9vQ692YI8M7slAoL3A7+KrK2hnPAggnRRNy1q3W9rhOMn8 A9wqghDeOdT0lF2Qu83yv5yyF0M5eRuYMVsItR8zOODhHhoZvRCvGoVW+Znc+Cjr3TDi9SNcy8n D7jdSJyLrfFwm7lgN3XlY44Scy6kPgOGnZVhUzjhxQIgVmv2mSRqhU5fGfIW6VrhKa0VYfjTnmt QzaRHN817U83vOVUem0n+i6FIitNnl5wS08Owaz3hUPew3ji/5lxMjn/eHHPAIE4zEMlEeM9jUP +ycYirg0ca+e81DhxNdcFmchkoOQQQ2/MrYBC2bfboQ2tBm5E8vRfSa8jQbY/AOo1L5baqzhalh T4gi9sl8QVOUyTll8zlLAHtJhcLVJ6nw== X-Received: by 2002:a5d:5f94:0:b0:432:e00b:8687 with SMTP id ffacd0b85a97d-435f3aa7957mr159981f8f.31.1769702987178; Thu, 29 Jan 2026 08:09:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/43] hw/arm/virt: Set PCI preserve_config for accel SMMUv3 Date: Thu, 29 Jan 2026 16:08:57 +0000 Message-ID: <20260129160917.1415092-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703247962158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Introduce a new pci_preserve_config field in virt machine state which allows the generation of DSM #5. This field is only set if accel SMMU is instantiated. In a subsequent patch, SMMUv3 accel mode will make use of IORT RMR nodes to enable nested translation of MSI doorbell addresses. IORT RMR requires _DSM #5 to be set for the PCI host bridge so that the Guest kernel preserves the PCI boot configuration. Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao Reviewed-by: Eric Auger Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-24-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 8 ++++++++ hw/arm/virt.c | 1 + include/hw/arm/virt.h | 1 + 3 files changed, 10 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 03b4342574..9032a5df1c 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -164,6 +164,14 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMap= Entry *memmap, .pci_native_hotplug =3D !acpi_pcihp, }; =20 + /* + * Accel SMMU requires RMRs for MSI 1-1 mapping, which require _DSM + * function 5 (_DSM for Preserving PCI Boot Configurations). + */ + if (vms->pci_preserve_config) { + cfg.preserve_config =3D true; + } + if (vms->highmem_mmio) { cfg.mmio64 =3D memmap[VIRT_HIGH_PCIE_MMIO]; } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 91fec582ed..899b02e1f7 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3080,6 +3080,7 @@ static void virt_machine_device_pre_plug_cb(HotplugHa= ndler *hotplug_dev, } object_property_set_uint(OBJECT(dev), "msi-gpa", db_start, &error_abort); + vms->pci_preserve_config =3D true; } } } diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 5907d41dbb..3b382bdf49 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -182,6 +182,7 @@ struct VirtMachineState { bool legacy_smmuv3_present; MemoryRegion *sysmem; MemoryRegion *secure_sysmem; + bool pci_preserve_config; }; =20 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703067; cv=none; d=zohomail.com; s=zohoarc; b=D1yBWmazKFG1/A8bNIf8oZCsCaDfDDKH0l0bGnnPi2sf5YVcKy8VQxh3ukYBf7fqnHWFmwK3eE7F985vkdVPM9s18f2bm05yKQBPiq/Z+w19rk4FFYm0wk6eluHNQei91nP8BUJIJwBy7MpjZAD7/XgWgKrWlnMsJjSJMUP2jsc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703067; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=CDGtUlFBjW+MvjyohX5qDrWSkViGIe1RMZVwu2N7z9g=; b=YkBGb0b8lqiYZVE+S3mcnljqiraTM8D9E0BvJXTXC96r4kDWKKuGyI85ZZaGaam9XJ1Xyz/muHoyNhpWO4JDdv+bgeRctaimBekHUtYmATR7/ztH92MgF7q+8l4RaTDo68NaW4qLNN0vnyZ2T2LjxY+X6yM1l4G216+H1/ww/n0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703067505775.4604811542808; Thu, 29 Jan 2026 08:11:07 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUav-00010Y-DH; Thu, 29 Jan 2026 11:10:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUag-0000KF-0Y for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:55 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUad-0006gv-4P for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:53 -0500 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-43246af170aso797052f8f.0 for ; Thu, 29 Jan 2026 08:09:49 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702989; x=1770307789; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=CDGtUlFBjW+MvjyohX5qDrWSkViGIe1RMZVwu2N7z9g=; b=XovYe2VbJZRhgykXFoRHtbKW8TJZajqEXA7OfIXHMcsR05mi3ERi/VBNYcRFhRTpv2 jAhYI07Fn/OHViA23tZ8moBp/mkNlB7sPqGQJvRpPv8X+0xuVVGlVTaWJ0xcXNSyL+qn 5BT5DUIqYqqOqx4H9Z5w6ro5IwpneU1u60mu4hxsgNyW7j+p4Ei3xQ+yJHAQS7Tss5GQ K/CzuQJOn1g6YjaeHt5jeYyFrW+tYkYagE9wA8sYhQGKotNs0FVlKLoJ/wtSlsI2M35o HiNqUQam2R3i/ItAhM6onvbUqRv11wFWinlxX/WsMzNUB5UiiVvHfnRVXeT4zvnSrlYB zK7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702989; x=1770307789; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=CDGtUlFBjW+MvjyohX5qDrWSkViGIe1RMZVwu2N7z9g=; b=JzjCvljeMIZ2c0WrWl+TREGei9cy/LpHO1M76UqgxM2hFEVzOVW0Qa79xXqrVTkHq7 FJdH5qbIr+gdClGIFRzIP2+apBfRTghC4XT0Jt1wB53UKqF1cSsgOJnBWHQZT1nPBuCd v26PRIu0yxTglF0AtOht+Ygsp5c/j49m/YIs1EFrJxLdu/RtzhVSZf5zW36+qdyTozY3 QV3Yp6LnkGxw+2dWPziF+iErFuXac0+3iAJ6ep634LZgftK3EUWdivQIVcGabHDwTQwN /APo9RYvUWdz9/Fi59eBAiuxqVVeP7DKQ8M/YnikhLkKB5u9ldISEs41Xp+D1eCCcSua fUTQ== X-Gm-Message-State: AOJu0Yz4RMh17Jo46vWI7ahq9nhbKrWHYksQKYDQaS5xMMyu9fwUfYea b2ih1qQMhgA4wIObq7mRB5FkT5cePwDgJVEmtG48TFjrWpXqPksMUr4okZkPjNv7PogfylYY22U 8vmHiCx8= X-Gm-Gg: AZuq6aJZN0FJnZWtNe6l/Y31lWIP+A8kOBOFzpRnjlXK7zi8rfEZrQulXXKcctg3r3f pL55Co0aaScSmCbJa8MVcxNmtoRg3vb6HeTqX4ZRL/Jw0BK5zlz/9FhNrn2O3rhO9xZNA3U5mxt Mt3NGHNwGI1gYE5rTV1t7f1Bm2CGNYMGw4Vk+9jfOGY5mOPfOkpjF01F2bi6ZAhNZClL5xLaMBP VB9FQMkRyjzipgc0mUZ0qzcfxeQC6xFQqtpbqkLVmWe5Z0mZ4hx5VRc9lG8HEQF3dvohMpCbWUn NSfpkxXVEI353To7WD/clHzy8jtEtJvvN+1NgQywSeCQYRWoYLoK6SeGXPRfKM3grmH8Hc80WWV GeWrpnY5m5BE1dV/+50thg5LYhxugDOYYub3MjizQ2WDsaZpFEKwankvPTeptJSubIzAzDATuCx iZy+4r2NrU+h3ms4AR3XaM5sHPGYpXkA== X-Received: by 2002:a05:6000:1ace:b0:435:a135:777d with SMTP id ffacd0b85a97d-435ea09c3bamr4822319f8f.9.1769702988576; Thu, 29 Jan 2026 08:09:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/43] tests/qtest/bios-tables-test: Prepare for IORT revison upgrade Date: Thu, 29 Jan 2026 16:08:58 +0000 Message-ID: <20260129160917.1415092-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703068480154100 From: Shameer Kolothum Subsequent patch will upgrade IORT revision to 5 to add support for IORT RMR nodes. Add the affected IORT blobs to=C2=A0allowed-diff list for bios-table tests. Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-25-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test-allowed-diff.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..3279638ad0 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,5 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/aarch64/virt/IORT", +"tests/data/acpi/aarch64/virt/IORT.its_off", +"tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy", +"tests/data/acpi/aarch64/virt/IORT.smmuv3-dev", --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703238; cv=none; d=zohomail.com; s=zohoarc; b=VL7KYVwT+m/2neCT1xtvWcG2qY1Veuvr9PQMJ1yfnaNYZbqQQuKPVjHB/SD5BG2mhdzMbbB9jo2y1NfZ1gydqjuGkVRal/5oKylHgX9LVE82BaavEfe0yfaL3WSdzCMyh+FJDz65Cs3MZs9QL56/hA/CEeyhTJNCncXGfM11vL4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703238; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=7tnPJl/fdy53AJrKdl7gdXxzjONlXeX1A8lfCUG4COA=; b=K2sp6zWFpDu2nLJ9hFNg3rbnOEkvJ92tksNH+q/3lWeYLn+kWqs8eiXGLhHK5XejZt1wwLzrWb5/yQGOnbAI9u//IjrD4EFMCYPPtoefyqn/I3ruC08IFJvYWYDO9mvaPyry+crujZoDRu995RbTWWxFH3aNIxMlX/kNjngwSb0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176970323441389.69287413797827; Thu, 29 Jan 2026 08:13:54 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUay-0001Ht-CB; Thu, 29 Jan 2026 11:10:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaj-0000Tm-H0 for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:01 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUad-0006gz-BO for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:55 -0500 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-47ff94b46afso10446245e9.1 for ; Thu, 29 Jan 2026 08:09:50 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702990; x=1770307790; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7tnPJl/fdy53AJrKdl7gdXxzjONlXeX1A8lfCUG4COA=; b=siD4EmLeIJnR/NjcL0XZQw9tAJdV+igApkXVPQkqHqnEDvwyKS/Kn88cXE9KVlmt8Q DjNRxBgf/EpChXO/NLwsPjmxen8Tu+onQDLf4hKEQvV1cDMUBmT4hTWylnDnXMHEq+Ch Ell/CRsyvTbRb5ttgZcSOnc/MGh00ivMC6lmrxo7MG4aFe5uf3spfxpxbcvsquUQ5xeX Ot5hFTEVSG6y1Z95yrfCByqkvIkC1x+kJ3U1kbFcnYnSbhrNv/NkdriidNYqFJOxEyjC PqiiJHxfSwsjv16L5RcoqpYvPbKrc+S8hacm43fYe/Z0sl2XAZGkM6R2426JBKoc7QAk mOMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702990; x=1770307790; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=7tnPJl/fdy53AJrKdl7gdXxzjONlXeX1A8lfCUG4COA=; b=tFJotkXVzII128Oji5v7nHDbOsAq4/fXk+FvdCYTKz1mknbDsowG1EhKkfduOcUZMi +Im7ganU57ZgftadGJnk96eMdnv8Ogx0kaMXzcc0yDhP+L6jDiIcGO6H74OAAMcBeHaS Oi3kRGoyDm38ksDnTR3iKIvCR5lmH7lCAaOWVc3wITBxWLM+uABn1bfviq3Do1wumC/z 4Xr1+ltWSHQ5hwJcU2MO0y2atKv3U8xSjl4nDIUfvMJLCYuKCTE1W/WnHyE9MT09o5nu 2qDheM64E7/D5lkr+VNT2vAM1BZVLNPawwcxHbNTRsJgA3mS3D1mHJhJmXVc8NXslSzh hu9w== X-Gm-Message-State: AOJu0YwWYkbNaFygawhtDYHJz+xfuU/cNDfT83GqwvoMR7VF7VaoPGGN 5WZtE2cNmx5u4YOg3PcHl6X/m7Bqdgsk5cbwp6NOh1K3sBcG4DwqMAWgy4XI6pAGKo2yY143Nne BEW44npY= X-Gm-Gg: AZuq6aK9T3gY+vP37rRMIPDUWtcXR2Xypw3F+53+JlFe8JmouPSXnvTFXDf0pcVoYEO L2qrXTt8FHBBSqeL2GTtc33VLXGfU7DyzhmsYbFCjusqn0QFb82pI0ImOLDE3oTBUVS4N6F1frq hP5MkoOU7WpBRKkdq3xG4rIHBo6R8o4PA+zUlEHWbs6ixa/75U1+ugGG2T0IB9S8M/QO9PO3EmG Vku97239wPfvVX2G75oLpgpqVNlTV6cTpjRK9qWE1MBMSTa28vclliwAvD7+Uu638ZI2tFuDcwU MIigDhhUosST+r+hNiLHWSgB1mOElXF3ypn5ebjTlSBl75jLW0RGq5BodQiOc3ixykb3HOZ00Wm 7FPf6lxRsV+4ZxKc+5DbZScoicLRqOat1+KanWrBLjEq3kKfVRx9TbdSuT9TRa4Ri87RUWDawvI Fmxuqyl+48JtZO8Cn2vCx9nmlb294K/w== X-Received: by 2002:a05:600c:2dc8:b0:47e:e452:ec12 with SMTP id 5b1f17b1804b1-4808493b38cmr28292025e9.15.1769702989706; Thu, 29 Jan 2026 08:09:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/43] hw/arm/virt-acpi-build: Add IORT RMR regions to handle MSI nested binding Date: Thu, 29 Jan 2026 16:08:59 +0000 Message-ID: <20260129160917.1415092-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703243214154100 Content-Type: text/plain; charset="utf-8" From: Eric Auger To handle SMMUv3 accel=3Don mode(which configures the host SMMUv3 in nested mode), it is practical to expose the guest with reserved memory regions (RMRs) covering the IOVAs used by the host kernel to map physical MSI doorbells. Those IOVAs belong to [0x8000000, 0x8100000] matching MSI_IOVA_BASE and MSI_IOVA_LENGTH definitions in kernel arm-smmu-v3 driver. This is the window used to allocate IOVAs matching physical MSI doorbells. With those RMRs, the guest is forced to use a flat mapping for this range. Hence the assigned device is programmed with one IOVA from this range. Stage 1, owned by the guest has a flat mapping for this IOVA. Stage2, owned by the VMM then enforces a mapping from this IOVA to the physical MSI doorbell. The creation of those RMR nodes is only relevant if nested stage SMMU is in use, along with VFIO. As VFIO devices can be hotplugged, all RMRs need to be created in advance. Initialise AcpiIortSMMUv3Dev structures to avoid using uninitialised state when building the IORT, as legacy and device SMMUv3 paths populate different fields now(e.g. accel). Signed-off-by: Eric Auger Signed-off-by: Shameer Kolothum Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Zhangfei Gao Tested-by: Eric Auger Reviewed-by: Jonathan Cameron Message-id: 20260126104342.253965-26-skolothumtho@nvidia.com Suggested-by: Jean-Philippe Brucker Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Zhangfei Gao Reviewed-by: Jonathan Cameron Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 115 +++++++++++++++++++++++++++++++++++---- 1 file changed, 105 insertions(+), 10 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 9032a5df1c..4ae4cbc6cd 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -257,6 +257,29 @@ static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineS= tate *vms) #define ROOT_COMPLEX_ENTRY_SIZE 36 #define IORT_NODE_OFFSET 48 =20 +#define IORT_RMR_NUM_ID_MAPPINGS 1 +#define IORT_RMR_NUM_MEM_RANGE_DESC 1 +#define IORT_RMR_COMMON_HEADER_SIZE 28 +#define IORT_RMR_MEM_RANGE_DESC_SIZE 20 + +/* + * IORT RMR flags: + * Bit[0] =3D 0 Disallow remapping of reserved ranges + * Bit[1] =3D 0 Unprivileged access + * Bits[9:2] =3D 0x00 Device nGnRnE memory + */ +#define IORT_RMR_FLAGS 0 + +/* + * MSI doorbell IOVA window used by the host kernel SMMUv3 driver. + * Described in IORT RMR nodes to reserve the IOVA range where the host + * kernel maps physical MSI doorbells for devices. This ensures guests + * preserve a flat mapping for MSI doorbell in nested SMMUv3(accel=3Don) + * configurations. + */ +#define MSI_IOVA_BASE 0x8000000 +#define MSI_IOVA_LENGTH 0x100000 + /* * Append an ID mapping entry as described by "Table 4 ID mapping format" = in * "IO Remapping Table System Software on ARM Platforms", Chapter 3. @@ -265,7 +288,8 @@ static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineSt= ate *vms) * Note that @id_count gets internally subtracted by one, following the sp= ec. */ static void build_iort_id_mapping(GArray *table_data, uint32_t input_base, - uint32_t id_count, uint32_t out_ref) + uint32_t id_count, uint32_t out_ref, + uint32_t flags) { build_append_int_noprefix(table_data, input_base, 4); /* Input base */ /* Number of IDs - The number of IDs in the range minus one */ @@ -273,7 +297,7 @@ static void build_iort_id_mapping(GArray *table_data, u= int32_t input_base, build_append_int_noprefix(table_data, input_base, 4); /* Output base */ build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference= */ /* Flags */ - build_append_int_noprefix(table_data, 0 /* Single mapping (disabled) *= /, 4); + build_append_int_noprefix(table_data, flags, 4); } =20 struct AcpiIortIdMapping { @@ -321,6 +345,7 @@ typedef struct AcpiIortSMMUv3Dev { GArray *rc_smmu_idmaps; /* Offset of the SMMUv3 IORT Node relative to the start of the IORT */ size_t offset; + bool accel; } AcpiIortSMMUv3Dev; =20 /* @@ -330,7 +355,7 @@ typedef struct AcpiIortSMMUv3Dev { static int populate_smmuv3_legacy_dev(GArray *sdev_blob) { VirtMachineState *vms =3D VIRT_MACHINE(qdev_get_machine()); - AcpiIortSMMUv3Dev sdev; + AcpiIortSMMUv3Dev sdev =3D {0}; =20 sdev.rc_smmu_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMapp= ing)); object_child_foreach_recursive(object_get_root(), iort_host_bridges, @@ -362,10 +387,10 @@ static int smmuv3_dev_idmap_compare(gconstpointer a, = gconstpointer b) static int iort_smmuv3_devices(Object *obj, void *opaque) { VirtMachineState *vms =3D VIRT_MACHINE(qdev_get_machine()); + AcpiIortSMMUv3Dev sdev =3D {0}; GArray *sdev_blob =3D opaque; AcpiIortIdMapping idmap; PlatformBusDevice *pbus; - AcpiIortSMMUv3Dev sdev; int min_bus, max_bus; SysBusDevice *sbdev; PCIBus *bus; @@ -375,6 +400,9 @@ static int iort_smmuv3_devices(Object *obj, void *opaqu= e) } =20 bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); + if (object_property_find(obj, "accel")) { + sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort= ); + } pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); sbdev =3D SYS_BUS_DEVICE(obj); sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); @@ -448,10 +476,69 @@ static void create_rc_its_idmaps(GArray *its_idmaps, = GArray *smmuv3_devs) } } =20 +static void +build_iort_rmr_nodes(GArray *table_data, GArray *smmuv3_devices, uint32_t = *id) +{ + AcpiIortSMMUv3Dev *sdev; + AcpiIortIdMapping *idmap; + int i; + + for (i =3D 0; i < smmuv3_devices->len; i++) { + uint16_t rmr_len; + int bdf; + + sdev =3D &g_array_index(smmuv3_devices, AcpiIortSMMUv3Dev, i); + if (!sdev->accel) { + continue; + } + + /* + * Spec reference:Arm IO Remapping Table(IORT), ARM DEN 0049E.d, + * Section 3.1.1.5 "Reserved Memory Range node" + */ + idmap =3D &g_array_index(sdev->rc_smmu_idmaps, AcpiIortIdMapping, = 0); + bdf =3D idmap->input_base; + rmr_len =3D IORT_RMR_COMMON_HEADER_SIZE + + (IORT_RMR_NUM_ID_MAPPINGS * ID_MAPPING_ENTRY_SIZE) + + (IORT_RMR_NUM_MEM_RANGE_DESC * IORT_RMR_MEM_RANGE_DESC_= SIZE); + + /* Table 18 Reserved Memory Range Node */ + build_append_int_noprefix(table_data, 6 /* RMR */, 1); /* Type */ + /* Length */ + build_append_int_noprefix(table_data, rmr_len, 2); + build_append_int_noprefix(table_data, 3, 1); /* Revision */ + build_append_int_noprefix(table_data, (*id)++, 4); /* Identifier */ + /* Number of ID mappings */ + build_append_int_noprefix(table_data, IORT_RMR_NUM_ID_MAPPINGS, 4); + /* Reference to ID Array */ + build_append_int_noprefix(table_data, IORT_RMR_COMMON_HEADER_SIZE,= 4); + + /* RMR specific data */ + + /* Flags */ + build_append_int_noprefix(table_data, IORT_RMR_FLAGS, 4); + /* Number of Memory Range Descriptors */ + build_append_int_noprefix(table_data, IORT_RMR_NUM_MEM_RANGE_DESC,= 4); + /* Reference to Memory Range Descriptors */ + build_append_int_noprefix(table_data, IORT_RMR_COMMON_HEADER_SIZE + + (IORT_RMR_NUM_ID_MAPPINGS * ID_MAPPING_ENTRY_SIZE)= , 4); + build_iort_id_mapping(table_data, bdf, idmap->id_count, sdev->offs= et, + 1); + + /* Table 19 Memory Range Descriptor */ + + /* Physical Range offset */ + build_append_int_noprefix(table_data, MSI_IOVA_BASE, 8); + /* Physical Range length */ + build_append_int_noprefix(table_data, MSI_IOVA_LENGTH, 8); + build_append_int_noprefix(table_data, 0, 4); /* Reserved */ + } +} + /* * Input Output Remapping Table (IORT) * Conforms to "IO Remapping Table System Software on ARM Platforms", - * Document number: ARM DEN 0049E.b, Feb 2021 + * Document number: ARM DEN 0049E.d, Feb 2022 */ static void build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) @@ -465,7 +552,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) GArray *smmuv3_devs =3D g_array_new(false, true, sizeof(AcpiIortSMMUv3= Dev)); GArray *rc_its_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMa= pping)); =20 - AcpiTable table =3D { .sig =3D "IORT", .rev =3D 3, .oem_id =3D vms->oe= m_id, + AcpiTable table =3D { .sig =3D "IORT", .rev =3D 5, .oem_id =3D vms->oe= m_id, .oem_table_id =3D vms->oem_table_id }; /* Table 2 The IORT */ acpi_table_begin(&table, table_data); @@ -491,6 +578,13 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) nb_nodes++; /* ITS */ rc_mapping_count +=3D rc_its_idmaps->len; } + /* Calculate RMR nodes required. One per SMMUv3 with accelerated m= ode */ + for (i =3D 0; i < num_smmus; i++) { + sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + if (sdev->accel) { + nb_nodes++; + } + } } else { if (vms->its) { nb_nodes =3D 2; /* RC and ITS */ @@ -563,7 +657,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) /* Array of ID mappings */ if (smmu_mapping_count) { /* Output IORT node is the ITS Group node (the first node). */ - build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET= ); + build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET= , 0); } } =20 @@ -615,7 +709,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) AcpiIortIdMapping, j); /* Output IORT node is the SMMUv3 node. */ build_iort_id_mapping(table_data, range->input_base, - range->id_count, sdev->offset); + range->id_count, sdev->offset, 0); } } =20 @@ -628,7 +722,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) range =3D &g_array_index(rc_its_idmaps, AcpiIortIdMapping,= i); /* Output IORT node is the ITS Group node (the first node)= . */ build_iort_id_mapping(table_data, range->input_base, - range->id_count, IORT_NODE_OFFSET); + range->id_count, IORT_NODE_OFFSET, 0= ); } } } else { @@ -637,9 +731,10 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) * SMMU: RC -> ITS. * Output IORT node is the ITS Group node (the first node). */ - build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET); + build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET, 0); } =20 + build_iort_rmr_nodes(table_data, smmuv3_devs, &id); acpi_table_end(linker, &table); g_array_free(rc_its_idmaps, true); for (i =3D 0; i < num_smmus; i++) { --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703263; cv=none; d=zohomail.com; s=zohoarc; b=jjP/FF/rTd/34XOj0rw2D6xBWsd54h9zxoXhOuJmClQkX7HmCAV5oJ1ZD93T8aEZQZGDJ9V2o0fuQhg7sEKhRvkoqvCR9YlvhGfttyASQZNaeU2eqboxLdN4RSn12RWyhkVXGIuEmH9WgpYBLbKP6XVb85DpdCtadtZfzDhD9gk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703263; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=FyC+DgpopVeoLVyZLyXpQzH/bbdr6d5+zK8/TX4p6T4=; b=FhJS6H1HuWTxYcJ8LubHDjQC70/pL/UH/FFfsYABAxhGx5ddzoyW8AG8KvEhc29CXUM88GQXivSWBQIPc3IzLhanI0fiWsfk7s4X7IOJ900nr/o2k4pGPDGU/i/NlJAxlL4s8Mws6NLE4d9yXums2gmWN+yc6D4dX1cbbfASMv4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176970326327918.279845158193552; Thu, 29 Jan 2026 08:14:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUb1-0001Sp-GK; Thu, 29 Jan 2026 11:10:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaj-0000Tl-GV for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:01 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUae-0006hB-AE for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:55 -0500 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-4327555464cso973906f8f.1 for ; Thu, 29 Jan 2026 08:09:51 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702991; x=1770307791; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=FyC+DgpopVeoLVyZLyXpQzH/bbdr6d5+zK8/TX4p6T4=; b=kUQwT02L3A/sPldVtmREHBqKJiSV87FZ2RyjZbKh02DG21lmlJkFijYHr7KKEKl+vP SdClqpQ/FOb1k+eE0fS0FokJEFT0fgVBICy3hGiUVsiKV70VDtGpJ0QNxgE4TYt80d+S Kj0PPrxfob9lbRvh9zkZYhn1AfU5HpSlvdCH2x85Yh0kj6uKFyLQ6b+gxN42Owg/dEjD ZgsSXh9mi3kK0mK12C8hgtv5QjdK+Wjh9e06PH4f4cXAZg4vh7ssssZWU1vTW5NXIZRZ KlGYK3jKibmqgXBful4pf2YBoerWzTRbE9K087EZX0rP+fY+TLZS5yFFGm3wlIfTkeE3 ZQvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702991; x=1770307791; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=FyC+DgpopVeoLVyZLyXpQzH/bbdr6d5+zK8/TX4p6T4=; b=PCzcdZITrfWbyWZXJhX5F31SMTVfQilEwKyEI9BklI0v/q2B8hgYucf4Q4U03PAwnq i6P6R4owZsrchl4B4Qmhp+RQ9UwxTGaceyinXTxn/0vfQVEUXgmMubdVo8gOfSXJuo1k nrgNTDHiJUdZxnwrnciUs+Lnt14F3ylrqSbASm+ffZ1sakzcfxCLDbRnLHC71XQJCwvj U/adRGbUvI2fe1LXvSjHONZ2qZsHF/M7HyD5kQ90zbLFjHuhaTCjBNz0qXljNP+KxkfG enNqWuNuIizcd1/a19VHMKx2B+vEQoU7OP4hAkkZHXm7LTXxBWLMrwyHw+4NX/rh6cD4 iTpg== X-Gm-Message-State: AOJu0YyuByWnbc8xdwpjtE3l+VaV0RscACJFDwt8R3/mMOXm9nW865ds LFvejL0vm29ewe7+L/We3H8+IXdHKrrJFuJhuOyp0T4hzp1FRpOzq1v926QGlQuFF6YeGvakw7U Cqj0IM74= X-Gm-Gg: AZuq6aLo2UsDKBIKeFR0tAvk0GM1AXgFiEn2cgIoqBd64+7nSNTPEUknYeeMdf2K7F6 wzP/aN8Aj2R7GuOnA8PbBIdom3BfU10dCs5X46uRcs/E2pxocEk/JYNeHYQtPFB93ssUCphkHSv zwL1pu6YHlw+la8yIyAsDaWgRdDdHjtzI/0q4I4ol9VOYKfHSeBMNP3ik/huCNYbhBKwnZMIXNB U7aZSz27VzFhp2leMtZjsaPgAU7+Z1gQEr8WH6T+vvX1Fj1CB6LzhVEtJzlmsPd/alcvVtuOM7O huyKD9vJNLzgYllFOBRYP3S0Pyz+cvFP9ewW8VLP+QCY1wPAiD9wY8266hbZMsiwFrtCkjaf2fb 0FgwKjd9IR/XlDJ8YsJ6tKFBtbUX/gT3ICzUqtODkz54QSDSb2+i2EQh0ap6fmt2eQOKfgL0zvF ekaFT1LJUzy/Z+k62pz8DSkV3whvwWLw== X-Received: by 2002:a05:6000:2383:b0:432:5bf9:cf2e with SMTP id ffacd0b85a97d-435f3a6bab1mr180058f8f.13.1769702990702; Thu, 29 Jan 2026 08:09:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/43] tests/qtest/bios-tables-test: Update IORT blobs after revision upgrade Date: Thu, 29 Jan 2026 16:09:00 +0000 Message-ID: <20260129160917.1415092-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703263965158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Update the reference IORT blobs after revision upgrade for RMR node support. This affects the aarch64 'virt' IORT tests. IORT diff is the same for all the tests: /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20230628 (64-bit version) * Copyright (c) 2000 - 2023 Intel Corporation * - * Disassembly of tests/data/acpi/aarch64/virt/IORT, Mon Oct 20 14:42:41 2= 025 + * Disassembly of /tmp/aml-B4ZRE3, Mon Oct 20 14:42:41 2025 * * ACPI Data Table [IORT] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (i= n hex) */ [000h 0000 004h] Signature : "IORT" [IO Remapping Tab= le] [004h 0004 004h] Table Length : 00000080 -[008h 0008 001h] Revision : 03 -[009h 0009 001h] Checksum : B3 +[008h 0008 001h] Revision : 05 +[009h 0009 001h] Checksum : B1 [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 ... Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-27-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- tests/data/acpi/aarch64/virt/IORT | Bin 128 -> 128 bytes tests/data/acpi/aarch64/virt/IORT.its_off | Bin 172 -> 172 bytes tests/data/acpi/aarch64/virt/IORT.smmuv3-dev | Bin 364 -> 364 bytes tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy | Bin 276 -> 276 bytes tests/qtest/bios-tables-test-allowed-diff.h | 4 ---- 5 files changed, 4 deletions(-) diff --git a/tests/data/acpi/aarch64/virt/IORT b/tests/data/acpi/aarch64/vi= rt/IORT index 7efd0ce8a6b3928efa7e1373f688ab4c5f50543b..a234aae4c2d04668d34313836d3= 2ca20e19c0880 100644 GIT binary patch delta 18 ZcmZo*Y+&T_^bZPYU|?Wi-8hk}3;-#Q1d;#% delta 18 ZcmZo*Y+&T_^bZPYU|?Wi-aL`33;-#O1d;#% diff --git a/tests/data/acpi/aarch64/virt/IORT.its_off b/tests/data/acpi/aa= rch64/virt/IORT.its_off index c10da4e61dd00e7eb062558a2735d49ca0b20620..0cf52b52f671637bf4dbc9e0fc8= 0c3c73d0b01d3 100644 GIT binary patch delta 18 ZcmZ3(xQ3C-(?2L=3D4FdxM>(q%{ivTdM1ttIh delta 18 ZcmZ3(xQ3C-(?2L=3D4FdxM^Yn>aivTdK1ttIh diff --git a/tests/data/acpi/aarch64/virt/IORT.smmuv3-dev b/tests/data/acpi= /aarch64/virt/IORT.smmuv3-dev index 67be268f62afbf2d9459540984da5e9340afdaaa..43a15fe2bf6cc650ffcbceff869= 19ea892928c0e 100644 GIT binary patch delta 19 acmaFE^oEJc(?2LAhmnDS^~6T5Bt`%|fCYU3 delta 19 acmaFE^oEJc(?2LAhmnDS`P4?PBt`%|eg%C1 diff --git a/tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy b/tests/data/a= cpi/aarch64/virt/IORT.smmuv3-legacy index 41981a449fc306b80cccd87ddec3c593a8d72c07..5779d0e225a62b9cd70bebbacb7= fd1e519c9e3c4 100644 GIT binary patch delta 19 acmbQjG=3D+)F(?2Lggpq-P)oUXc7b5^FiUXej delta 19 acmbQjG=3D+)F(?2Lggpq-P*=3DHjc7b5^Fhy$Mh diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index 3279638ad0..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,5 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/aarch64/virt/IORT", -"tests/data/acpi/aarch64/virt/IORT.its_off", -"tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy", -"tests/data/acpi/aarch64/virt/IORT.smmuv3-dev", --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703088; cv=none; d=zohomail.com; s=zohoarc; b=Kazu9cYYvwOAg0Jl1tnn1RaQ4ZSPNJ1DZFdmBxQmRMMtz/XA2k8DmHnu7RGkpopWWEjtbfCLFC9gao+SW4ttQ6rqtrRUnFdwwP9GWCnC7FFQM8j+kdcQp81S1vCn3A1fkNTagA7liwyBaTsQF7pUxoHgFFkZZbnBgdBA5YgMPU4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703088; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Ht2blUch5J5UITDJcWny0wh5hUzdGhmPTt7vqIgV91o=; b=eT6udIEKUg+tC8a8POxEFU4ep/xXvA+1oG2oGZcWOnq+uWeBOOtwS2uXPSpYWkLr+w51rfdlgUDPDlgsonmR9tvNS2y4rQPNpcMO9vRYTfdVnfAUrNXmDn+KKyen3AV6r+trlTqd5zIs4Wt8OLMH4/iy05C0h1FUwwq7HpVKcmc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703088470940.7294253989453; Thu, 29 Jan 2026 08:11:28 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUbB-0001os-3m; Thu, 29 Jan 2026 11:10:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaj-0000Tn-GU for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:01 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaf-0006iz-IC for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:56 -0500 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-4327790c4e9so745677f8f.2 for ; Thu, 29 Jan 2026 08:09:53 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702992; x=1770307792; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Ht2blUch5J5UITDJcWny0wh5hUzdGhmPTt7vqIgV91o=; b=NEGSAaiDR4+0FreQZPgTB+cRrW/eYq174wqpZ0QVRB9RdOS7V2xN78mU4EC+KZVfk2 7cDKF9xoHsSSVd97BoGrVkO6JPWCl4B8T7Xfh1/ZsDNQh1z6MHNgwoyt+GaZbKqJOfC/ f2G3T7XjlHpRdmVHED/VjWOoWWT8CNdASUE+x+2NS6atgftTnYLGbzTKNbA5bm3dp+qp 4ESxgODdu1XhkjRjRXUyHxjOEa44kXHhwp+pAyR+YkkG4QuGjP+rremKLMAYD9BvtYNO j//IV4QlsgLfGJPQhKTOpCfM0N+Zo6JwblgWTuueTiqD8gQtjwJeLIQC0jUOX0gpLUSk XIpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702992; x=1770307792; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Ht2blUch5J5UITDJcWny0wh5hUzdGhmPTt7vqIgV91o=; b=Bi/Td5tQgPVft18oW0duEhjSNghmZlir8Dc9XSi/oKzVT6gZKxVspILa3wsvf9rIci UNnzt9gYx0NPQrpd2mT+Eo6VU3Rx9i9I4YqjYIkyRKz6uzGjHHPYXTSypBZFzgz5EG2h SoFu+tGoIjUbdG3ZEJkxjosdSqmKPU8a+1vDGvfs16va83reEtygrPP8lh/z9JIY49Ac C3vkKECWDHaa6qu1OghYvsK0hInUkAFTG1P93yY4xyHAxTpKUli9S+5HM/ZF6wvNtEIT JtgMO9rra9PpK07uFUh4Au85DM7Ck/aDlRs1LkAQJ02kDtf4pwn4mdKpTwSPRrHnLcBh F9cg== X-Gm-Message-State: AOJu0YxkCHZrw5eCU3TAqWGwAXFlfVzaOtpY+DoI5Bi0ZvNYXBCLimnm NQj+w2Zf/99GKwV2s8eAilF+lyS7ov1SwEVEW5/ZnPCMQtbYdB13n2lwup1jUjMHt3KAt+37/2g tvEyU0as= X-Gm-Gg: AZuq6aJsXT5dZ9Bccka50wJrVokHFxTQWyD4mLNHbrHB7ci3RwoWDXmpOJKbl+WUYXJ BEcbaNaqkhDqN1hKh33ucQklIWJ0hRXh0fGvvfDc54XVcUmBpEk3Ehf+Ld0CHERwe1Vvij6ck8j SqdpLh3o/buN4L8npBt6Ixt8Sy3OxxmoYBerWI5pc662Z3JpFvONz81F+n9n9AYVluEiruLMUbK KZ57ElRfXToqsUhMtEXihovLipyLTTFZSw/0AKFaYRKhOimhHGl7YD35z8uo/e7TXyCkLNVSaUh Dk4jPuwtK2vOL7h3Wcuf/g4pqJvOqddMoAOA/CJ+6xFtcBZD3ZkEdCODVqvrtXX+s8wCmbHvB5s /M5JC++4Yt6ondwHbnNvyDfbh/qdIzmvRzv+IzrfnD55945uBG30HTPxUOy8LAnpyJRql1Fff3Z eyhM/8ElFVWj5VdG9VbQqA8o+IsTNxOA== X-Received: by 2002:a05:6000:2310:b0:435:a594:33dd with SMTP id ffacd0b85a97d-435f3aafeb2mr165515f8f.46.1769702991802; Thu, 29 Jan 2026 08:09:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/43] hw/arm/smmuv3: Block migration when accel is enabled Date: Thu, 29 Jan 2026 16:09:01 +0000 Message-ID: <20260129160917.1415092-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703101464158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Live migration is not supported when the SMMUv3 accelerator mode is enabled. Add a migration blocker to prevent migration in this configuration. Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Zhangfei Gao Reviewed-by: Jonathan Cameron Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-28-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 6 ++++++ include/hw/arm/smmuv3.h | 1 + 2 files changed, 7 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index e301bb467d..2be056d792 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -20,6 +20,7 @@ #include "qemu/bitops.h" #include "hw/core/irq.h" #include "hw/core/sysbus.h" +#include "migration/blocker.h" #include "migration/vmstate.h" #include "hw/core/qdev-properties.h" #include "hw/core/qdev.h" @@ -1925,6 +1926,11 @@ static void smmu_realize(DeviceState *d, Error **err= p) =20 if (s->accel) { smmuv3_accel_init(s); + error_setg(&s->migration_blocker, "Migration not supported with SM= MUv3 " + "accelerator mode enabled"); + if (migrate_add_blocker(&s->migration_blocker, errp) < 0) { + return; + } } =20 c->parent_realize(d, &local_err); diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 5616a8a2be..9c39acd5ca 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -68,6 +68,7 @@ struct SMMUv3State { bool accel; struct SMMUv3AccelState *s_accel; uint64_t msi_gpa; + Error *migration_blocker; }; =20 typedef enum { --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703225; cv=none; d=zohomail.com; s=zohoarc; b=Z4Axsz/JgvM7fgMpqjY07JM9Cb4u4iXJ4ro6C/lRSDJ/cH8XSNDKxYGwqZgCAS9hlsWxRRNtwZH+JnTmeYj7Sdh/+SC4vlIgpdpw6eig50//SjnamO/ja+mbo/40Nlyl/zKDmFZpRAaURuyQf53sO20rv9ZXyRWyAHDdxZxn42c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703225; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=2hNnnuhJoXReHjv7HZ5YnfAyWFTMSOC7KF6TZhhOyb4=; b=AY/veO1WkIFTDq/VVngUr30YT9NTV/KhHC2Nf86bJhrB+U+/uJr5rzQYNJx8T2XjHTNX9oGgK5NLgwyqiL/wK9g4URDL64QS3+r80KA99hMIv4rp46fzDQlqyOhwkP+LPjCjRCMjq6WWdb7O0kf18qN89vMUG669Zc8JhJ1Wzic= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703225693883.9379770186633; Thu, 29 Jan 2026 08:13:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUav-000122-Uh; Thu, 29 Jan 2026 11:10:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaj-0000Tp-Or for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:01 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUag-0006jW-GG for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:57 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-47ee937ecf2so9717495e9.0 for ; Thu, 29 Jan 2026 08:09:54 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702993; x=1770307793; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2hNnnuhJoXReHjv7HZ5YnfAyWFTMSOC7KF6TZhhOyb4=; b=HeCn81qocPHnD9gnNV9SGdjvWHAVrOFHAJWG2KMi4yBN5SAs3cNYk2nDmupTiWFmU5 qZ+jBnJBJh8KUHEgs4l8+/bTg1N1ySkcDJhHyO4qOaO5FP/23v28bJNzt95YwQCquWn1 Jf8Pvf2djdKuomoc0pxJjqbKnsNEJclIBMzsP6K0YFlzpwkK4ht/BHg9JtOjikLYzYoN 8ahkMOuzFsw7B5lj7yOyr+RMGBEE/Go6GRuueoF50DqOwGRlhA6Ykg4XSN0n2OX5Cy4g 7+3qtdM/2U61LMGJnuUsY5doewY8mhP/6xbcZHdvIxbhDvH9kCknnM9bET9AMaUP6AX4 7Gdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702993; x=1770307793; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=2hNnnuhJoXReHjv7HZ5YnfAyWFTMSOC7KF6TZhhOyb4=; b=eKAb51/vmbYJnC7wcRECgQWTofGUDmvY7Mw+uYRHvTUsSWpLwExDBzQKpl5tOYsT+I pRIZp0iZw55IqLi947WUbPCCr4kvIwX96MaLeGmwNYIBt/+P8yTJlX5BrkyrQ5zc9TX8 FfbO61QgW5XzXTK9q1v4AxiTSp38xOu5VnNvenuAU8Rqz1sZ74I9KAE82W4gn52M9KUs 8oQI0OswGZqeAS0YMWPJFFwmi9m3WbQTpm2TSOg12kvM5gw8tTOfAGuT6RErfGLyNk2D razqhYLo0WAD/8Ure96TCgUdlCCiCWsA8wWdyVXbcdnXEKuSIXSRjR94Ef+Y94bHxa11 q7mQ== X-Gm-Message-State: AOJu0YwihYtYCzcWcR3IZqX9Hr4CV9BHhx/EiX9/hag+uXAQtDXFEze7 WSrVRSIwQUVFhsWp9hidzt1nIigrkAmaKVgnDj0ORLZODU5M2Cx7N9Ui+3ylyRZXyS4ExIi0tGA qT24uifU= X-Gm-Gg: AZuq6aILNfJp57OuKU942m1y/BBH7agmF7y30IbN5mY/5KZ/BCfkAYujXYpzTzmM2fm KmFpKFzn+D/wAY6bV0/Ip1joZpko63BF6Gbvga5cyd/a69Q24g9tOgMnMINaT4jRVysWLmCIzY6 9wx95mEj/OvvvJE1HXMi/W0/IFyd3Er2PNPXYRzASC2NlobKB9xF/bvGMQwz4bHMBBUSo/gA2v/ rCXezVXIuSyQLyq5aT79OZo7IuUIE2EA6Ad9+p8QiBuHOKS5WesnkarwB9q5othd3zcS2/3nPHc Dg9W4GawJPS3anVNLzMsqTsNz6ZLF6ZvplUgn4fo3/POY5ZXKUe3Sya2+qWfNDK557Kz4IXIyZ1 mMhrr711tQ3Bnaez5bKkd0TPvcisi/alcE2m+9sJIQ9qwV2gbEGi7TjzDdB/n+ATI6sMdiIG8XA eT2rd6CSf8TNvqSPgmQtkO6Dkue86qB7y2gnP8qLKV X-Received: by 2002:a05:600c:2dc8:b0:47e:e452:ec12 with SMTP id 5b1f17b1804b1-4808493b38cmr28293355e9.15.1769702992837; Thu, 29 Jan 2026 08:09:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/43] hw/arm/smmuv3: Add accel property for SMMUv3 device Date: Thu, 29 Jan 2026 16:09:02 +0000 Message-ID: <20260129160917.1415092-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703227907158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Add an "accel" property to enable SMMUv3 accelerator mode. Accelerator mode relies on IORT RMR entries for MSI support and is therefore not supported when booting with a device tree. In this mode, the host SMMUv3 operates in nested translation (Stage-1 + Stage-2), with the guest owning the Stage-1 page tables. Expose only Stage-1 to the guest to ensure it uses the correct page table format Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Zhangfei Gao Reviewed-by: Jonathan Cameron Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-29-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 32 ++++++++++++++++++++++++++++++++ hw/arm/virt-acpi-build.c | 4 +--- hw/arm/virt.c | 22 +++++++++++++--------- 3 files changed, 46 insertions(+), 12 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 2be056d792..8ca1d4ad35 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1916,6 +1916,29 @@ static void smmu_reset_exit(Object *obj, ResetType t= ype) smmuv3_accel_reset(s); } =20 +static bool smmu_validate_property(SMMUv3State *s, Error **errp) +{ +#ifndef CONFIG_ARM_SMMUV3_ACCEL + if (s->accel) { + error_setg(errp, "accel=3Don support not compiled in"); + return false; + } +#endif + + if (!s->accel) { + return true; + } + + /* If no stage specified, SMMUv3 defaults to stage 1 */ + if (s->stage && strcmp(s->stage, "1")) { + error_setg(errp, + "Only stage1 is supported for SMMUv3 with accel=3Don"); + return false; + } + + return true; +} + static void smmu_realize(DeviceState *d, Error **errp) { SMMUState *sys =3D ARM_SMMU(d); @@ -1924,6 +1947,10 @@ static void smmu_realize(DeviceState *d, Error **err= p) SysBusDevice *dev =3D SYS_BUS_DEVICE(d); Error *local_err =3D NULL; =20 + if (!smmu_validate_property(s, errp)) { + return; + } + if (s->accel) { smmuv3_accel_init(s); error_setg(&s->migration_blocker, "Migration not supported with SM= MUv3 " @@ -2029,6 +2056,7 @@ static const Property smmuv3_properties[] =3D { * Defaults to stage 1 */ DEFINE_PROP_STRING("stage", SMMUv3State, stage), + DEFINE_PROP_BOOL("accel", SMMUv3State, accel, false), /* GPA of MSI doorbell, for SMMUv3 accel use. */ DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), }; @@ -2052,6 +2080,10 @@ static void smmuv3_class_init(ObjectClass *klass, co= nst void *data) device_class_set_props(dc, smmuv3_properties); dc->hotpluggable =3D false; dc->user_creatable =3D true; + + object_class_property_set_description(klass, "accel", + "Enable SMMUv3 accelerator support. Allows host SMMUv3 to be " + "configured in nested mode for vfio-pci dev assignment"); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 4ae4cbc6cd..3126aca42c 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -400,9 +400,7 @@ static int iort_smmuv3_devices(Object *obj, void *opaqu= e) } =20 bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); - if (object_property_find(obj, "accel")) { - sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort= ); - } + sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort); pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); sbdev =3D SYS_BUS_DEVICE(obj); sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 899b02e1f7..390845c503 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1491,8 +1491,8 @@ static void create_smmuv3_dt_bindings(const VirtMachi= neState *vms, hwaddr base, g_free(node); } =20 -static void create_smmuv3_dev_dtb(VirtMachineState *vms, - DeviceState *dev, PCIBus *bus) +static void create_smmuv3_dev_dtb(VirtMachineState *vms, DeviceState *dev, + PCIBus *bus, Error **errp) { PlatformBusDevice *pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); SysBusDevice *sbdev =3D SYS_BUS_DEVICE(dev); @@ -1500,10 +1500,15 @@ static void create_smmuv3_dev_dtb(VirtMachineState = *vms, hwaddr base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); MachineState *ms =3D MACHINE(vms); =20 - if (!(vms->bootinfo.firmware_loaded && virt_is_acpi_enabled(vms)) && - strcmp("pcie.0", bus->qbus.name)) { - warn_report("SMMUv3 device only supported with pcie.0 for DT"); - return; + if (!(vms->bootinfo.firmware_loaded && virt_is_acpi_enabled(vms))) { + if (object_property_get_bool(OBJECT(dev), "accel", &error_abort)) { + error_setg(errp, "SMMUv3 with accel=3Don not supported for DT"= ); + return; + } + if (strcmp("pcie.0", bus->qbus.name)) { + warn_report("SMMUv3 device only supported with pcie.0 for DT"); + return; + } } base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; @@ -3061,8 +3066,7 @@ static void virt_machine_device_pre_plug_cb(HotplugHa= ndler *hotplug_dev, object_property_set_link(OBJECT(dev), "secure-memory", OBJECT(vms->secure_sysmem), NULL); } - if (object_property_find(OBJECT(dev), "accel") && - object_property_get_bool(OBJECT(dev), "accel", &error_abort)) { + if (object_property_get_bool(OBJECT(dev), "accel", &error_abort)) { hwaddr db_start =3D 0; =20 if (!kvm_enabled() || !kvm_irqchip_in_kernel()) { @@ -3117,7 +3121,7 @@ static void virt_machine_device_plug_cb(HotplugHandle= r *hotplug_dev, return; } =20 - create_smmuv3_dev_dtb(vms, dev, bus); + create_smmuv3_dev_dtb(vms, dev, bus, errp); } } =20 --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703106; cv=none; d=zohomail.com; s=zohoarc; b=mwfJpLD2WyrNbo1z3n4DGSEvrvGKzBFcmuKg+pyaFlU1Gis65Yl35Ii92AyCyvma1Jyfvtv1CGRD74Qb0mBfnuQN6G8E30yiL1eAkuBw54vuA/dAlmhRM4LPYWkiQdr9cs75sslZ5FAaKKaJwbw+RspDZ/mTfK/w3bw1bWA6Fig= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703106; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=rUUn70ACpFYfs/QMQvOGgsBMv/EAn6IBhP2oNBQRff0=; b=Rj8w1cgGOGYvynkSrx9O7uVWc9r6nAAe3zmCH4rYIT6NkyBPicR/c4p9l80uHK/Z9WfcI7HJaezaFxIbBrd8WpYUSfhAlGHChWtIf5vCnm5rTQnKdtc3YKjSZzMPrcU4Qpb84SXBzSSNKVJbyxTKI/H4ZEb2Sj99+/baMxghmEs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703106813805.0397034394806; Thu, 29 Jan 2026 08:11:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUax-0001Dn-Lr; Thu, 29 Jan 2026 11:10:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUal-0000UW-MZ for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:01 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUah-0006k0-Oz for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:58 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4806cc07ce7so10485195e9.1 for ; Thu, 29 Jan 2026 08:09:55 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702994; x=1770307794; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=rUUn70ACpFYfs/QMQvOGgsBMv/EAn6IBhP2oNBQRff0=; b=sVykaeiCsihP/ChS7pJmT8n6EIjOy/4X8NxqUhXMWnEGWEmkR6qkr4tWH6lDF4k4y2 qUQLTTGeURzRg8XGyGaw6y1ESXJbXWOeyHoKHFiOAvJYakMfUPd8869F0oSt6FvEONLU BtM5yBkxSacBeY+ZVctfg0R2B/DxlHPWfZf0yjPYeh0vB5pq6tbTyOhpBxU4tzvlQpC6 DNf7tL129MDzjFETc4QtK/OJrdvqstjTX2v97dOeipc9OGTckPEHRg2HvA0/hDfnOnDl ePMLm0ib4D4retEqASniYKd7AM//qwd261cxiCn137yVmNKfv0onAqKN6ZcSPG+SvqDX kfLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702994; x=1770307794; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=rUUn70ACpFYfs/QMQvOGgsBMv/EAn6IBhP2oNBQRff0=; b=wBOGb0DBGfpWtd3mga8kDxJY+hzoq8qBOYvOn0BDU8I27W2juZ3zADOMEvFqtgMcR7 ra3WfS1wbIHmClVJxFyf3jG4TCgWYkDhK7k8LbM2xglcIytm5cFcMa5aNZnIv9FGkqos uBK1o36TxEqPiiN7g3Z+n02SKPXPjjvW0O0yezurMQ4EeOYBXQ/QdHsjL1GoHa2pkQQ7 zGk3p1FHsQ2JI9QBMe5oRddvmVaXZ9Go8K4ZIRJdVCygcfSoIP9gxwzBtNRBEBrpJ8Vw rdoKbGfDLr0T6fEIBBAGPXkWMjKZefz0aEq7kzR8yvXDiY5HuuSslCMhvPuQZSWjCTpP hkLA== X-Gm-Message-State: AOJu0Yy+GXCi4fb6Ra2earWHEMSCE3ZPQsBQSXXhprpNKrhI0aoGgBF2 1fucJW3SOzjngQcuIZZiMOQcUdafctwcna3jJHblvZDGIHkzTc+spClw7avycRN/ZKUUrFOTcC8 fX8quQx4= X-Gm-Gg: AZuq6aIA1Ke0RV7oYfE2M+56lW7loFwwk711ZCOIJ75gLn7+7gaty2dHC9pK926AlP7 bflkGWojdJN+BoR+gljeq9S0AeuLv6xqRIXO12LRlXtUV+0OcRuLsL881ZEy0HTZDhXAChSQ7KY n2VjH0+/8FAQ4kha9yF/cytQCedQJTybqM1DHLMbvI6QZll+ws4OR2peCCwuIfVvOeuwPzKTcmy bPvWLX3WIhZC7oiNSgMSUzGrPoEC4f9WrbSr/y/MK6q8bWtL3bdMpQydE+j6r3wHUdGZFhEbgBw fOzLpPX4gdzCPBBOfGBbYlY3shn43eJTZXbKhe/qLUu3tP4ZPEfVe6CQD9e/jz2u/Y0DzGtzZ73 wGiLTf0FQHoyIo6TlatMUn4B08yb57Fsu4Ou8t5+q6B3aAsLF7x3HszA4qfIcx05EFFW058oaKv Z3kStNcnAkPu6Rnoxb2B1lUowUh8GUOg== X-Received: by 2002:a05:600c:450b:b0:477:9cdb:e32e with SMTP id 5b1f17b1804b1-48069c206c8mr113310115e9.9.1769702993930; Thu, 29 Jan 2026 08:09:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/43] hw/arm/smmuv3-accel: Add a property to specify RIL support Date: Thu, 29 Jan 2026 16:09:03 +0000 Message-ID: <20260129160917.1415092-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703109192154100 From: Shameer Kolothum Currently QEMU SMMUv3 has RIL support by default. But if accelerated mode is enabled, RIL has=C2=A0to be compatible with host SMMUv3 support. Add a property so that the user can specify this. Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-30-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 14 ++++++++++++-- hw/arm/smmuv3-accel.h | 4 ++++ hw/arm/smmuv3.c | 9 +++++++++ include/hw/arm/smmuv3.h | 1 + 4 files changed, 26 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 33011962e3..df82f1e32a 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -68,8 +68,8 @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s, return false; } =20 - /* QEMU SMMUv3 supports Range Invalidation by default */ - if (FIELD_EX32(info->idr[3], IDR3, RIL) !=3D + /* User can disable QEMU SMMUv3 Range Invalidation support */ + if (FIELD_EX32(info->idr[3], IDR3, RIL) < FIELD_EX32(s->idr[3], IDR3, RIL)) { error_setg(errp, "Host SMMUv3 doesn't support Range Invalidation"); return false; @@ -646,6 +646,16 @@ static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_msi_direct_gpa =3D smmuv3_accel_get_msi_gpa, }; =20 +void smmuv3_accel_idr_override(SMMUv3State *s) +{ + if (!s->accel) { + return; + } + + /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it= */ + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, s->ril); +} + /* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */ bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error **errp) { diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 41b37e3122..a8a64802ec 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -49,6 +49,7 @@ bool smmuv3_accel_install_ste_range(SMMUv3State *s, SMMUS= IDRange *range, bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error **errp); bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sde= v, Error **errp); +void smmuv3_accel_idr_override(SMMUv3State *s); void smmuv3_accel_reset(SMMUv3State *s); #else static inline void smmuv3_accel_init(SMMUv3State *s) @@ -76,6 +77,9 @@ smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMM= UDevice *sdev, { return true; } +static inline void smmuv3_accel_idr_override(SMMUv3State *s) +{ +} static inline void smmuv3_accel_reset(SMMUv3State *s) { } diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 8ca1d4ad35..cb619f19df 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -305,6 +305,7 @@ static void smmuv3_init_id_regs(SMMUv3State *s) s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1); s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1); s->aidr =3D 0x1; + smmuv3_accel_idr_override(s); } =20 static void smmuv3_reset(SMMUv3State *s) @@ -1926,6 +1927,10 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) #endif =20 if (!s->accel) { + if (!s->ril) { + error_setg(errp, "ril can only be disabled if accel=3Don"); + return false; + } return true; } =20 @@ -2059,6 +2064,8 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_BOOL("accel", SMMUv3State, accel, false), /* GPA of MSI doorbell, for SMMUv3 accel use. */ DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), + /* RIL can be turned off for accel cases */ + DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2084,6 +2091,8 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) object_class_property_set_description(klass, "accel", "Enable SMMUv3 accelerator support. Allows host SMMUv3 to be " "configured in nested mode for vfio-pci dev assignment"); + object_class_property_set_description(klass, "ril", + "Disable range invalidation support (for accel=3Don)"); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 9c39acd5ca..533a2182e8 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -69,6 +69,7 @@ struct SMMUv3State { struct SMMUv3AccelState *s_accel; uint64_t msi_gpa; Error *migration_blocker; + bool ril; }; =20 typedef enum { --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703104; cv=none; d=zohomail.com; s=zohoarc; b=IVlq7Nfe+ji/AQhlXDYudp6OLYmYEbeIPieWblMOqWKXqDPVZJUx4C/wn3FSz4yv1FP8KRgJvDDAvbO5gc5ds6y3398to+AXjPDUiVEUtYKr/nkPZPxt6YYN1NH8nJrX5X9leDz0cCqh9BEold/33rb3sVPPLTKIMkBMHMKGNR8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703104; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=erO1JdZYmv8Pfd/7xs/k34qsisbhKkUpc7RaxG5e6+o=; b=dSKFHO8vuogvn2M4kvpfXRREipbdiOcTCAEzB5bDceKcjLldjg5USczwU8Taek9ZDt9gOhb7Tcw2fi1Dk3LARyFDDS/uc4e7PiRP2rgscoj+b5HwBwPrOgZfaCn94+S6Tn9wWPFqNt4n3q9nNn1uWHvuH3G7DErlt9uHPgiBcDg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703104472182.91101337030045; Thu, 29 Jan 2026 08:11:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUbB-0001rY-Jx; Thu, 29 Jan 2026 11:10:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUal-0000UU-MK for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:01 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaj-0006lZ-6j for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:09:58 -0500 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-430f3ef2d37so992261f8f.3 for ; Thu, 29 Jan 2026 08:09:56 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702995; x=1770307795; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=erO1JdZYmv8Pfd/7xs/k34qsisbhKkUpc7RaxG5e6+o=; b=uzFksaLdGSYauoNXH2ZEbwV45pyFisDW3UYXr78H05RhHLXwWtvmZRZ0VYKp4DmsWE U1xqcYafAUloGyHwhzHYcP8cegXEeq+GZvqi1fF7VjXESMRfF368VvsWeasJRFotchTO R3UYgR8gZ8WJkiTZJCIwsVAjCGhPHarSjbONvrE0Pgnz3UeUXyKl67Y3c7HVpTKEQg3F 3bQPyfyg1XfeJtdbg1LZ5bkdyJM29vZEGHgYTQ0vl5p9RjHFjJJnHuJimz3/wJ2YRT8A b8R27gAKAvFSWS+pidslmsCr5EOaWFOxjnJns+Yd+Qr4jipTiQawJuQh20NOi2bzoAki kIng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702995; x=1770307795; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=erO1JdZYmv8Pfd/7xs/k34qsisbhKkUpc7RaxG5e6+o=; b=MhzMMDjLJ4j26LySKhTD8tKjBW+3idbJk9HJiuPoLTWJoLw1ikUjYxzSae4j0sgeXW ymFz3BL/7vsbeJB14VzWdvcEDGtG4Eu+XuJc2FNYW2EZolOi05X3YjXB0tQBzk/ffBvE TTaCgAfUEpHPq64NxA2XzH6cYx8nOYTuNC1jtp/IVBlD26s/4FBuLECz3cA4v18YAVG2 gWl5GruasyQbSHToGXMBrdyJAK58UAnpszIvTD/PUboT5/b87y3lj/Bqgj5HOBOJ6ghN qBZ5armFt3YcY7Fh/Z9MrTou9iSTONgV9z4q3OkGLT1/gfxCCY84lxad9OIeCgvgSDAI 4dXQ== X-Gm-Message-State: AOJu0Yx/Z0QIDKsnfahZNpLM4t4G62etLOFdK1kQc5jWXWzqDm723F5W erRULO5Z3yuBIfchdeU+zVNX9glW92Y3KO/uxBT6QQ5ZwfP36dqH+/wfjm0o2IfODXp/Lx0wqPz 3On9Gx04= X-Gm-Gg: AZuq6aI3hB90d7ZFk30XzCCSGnsXN5Q81n4OQxCR+8c51cdS7l2GLZYVRUyti4omEMz gC12bzfquBd9RmnMNfNrwutqIOQE1Sw85SN5l4S5SZUGZ84h/3HtNA21iDFMNjTfVngrySk+eCD BUaO/CSZunEmugKG3YWVZjaloP521CdwMR9xeaZw60/Lr0yzBc0BKmBpuIpaEznXLW2KPiZQI2p ykxOukaD4SU+wIpO+Xeg6T2S59jUcZ7v82p1oJIMQvknzcXJvASAzRFQ7mzw75BcGSbUEBQvqaN du+dR57YJZ/1ZG0f8L/tkMNzVuh3XLYfzMIH9EWe6OIo+9g2kjC3b6WDyqnCvAFfDrJupcd44N6 YaN3NnIufnrB0gLfqvtJ2LvjvTaJ07xAI6Vla2fmO4FTpXPwFmDxtlZDcgRJcEOwus09fycxWwK /wEorT+HzhhomEekSNvRuzZ2hz63YadA== X-Received: by 2002:a05:6000:220d:b0:435:dd9e:9704 with SMTP id ffacd0b85a97d-435f3a62928mr188239f8f.8.1769702995051; Thu, 29 Jan 2026 08:09:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/43] hw/arm/smmuv3-accel: Add support for ATS Date: Thu, 29 Jan 2026 16:09:04 +0000 Message-ID: <20260129160917.1415092-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703107173154100 From: Shameer Kolothum QEMU SMMUv3 does not enable ATS (Address Translation Services) by default. When accelerated mode is enabled and the host SMMUv3 supports ATS, it can be useful to report ATS capability to the guest so it can take advantage of it if the device also supports ATS. Note: ATS support cannot be reliably detected from the host SMMUv3 IDR registers alone, as firmware ACPI IORT tables may override them. The user must therefore ensure the support before enabling it. The ATS support enabled here is only relevant for vfio-pci endpoints, as SMMUv3 accelerated mode does not support emulated endpoint devices. QEMU=E2=80=99s SMMUv3 implementation still lacks support for handling ATS translation requests, which would be required for emulated endpoints. Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-31-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 3 +++ hw/arm/smmuv3.c | 24 +++++++++++++++++++++++- hw/arm/virt-acpi-build.c | 10 ++++++++-- include/hw/arm/smmuv3.h | 1 + 4 files changed, 35 insertions(+), 3 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index df82f1e32a..a97abc1f79 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -654,6 +654,9 @@ void smmuv3_accel_idr_override(SMMUv3State *s) =20 /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it= */ s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, s->ril); + + /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */ + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, s->ats); } =20 /* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index cb619f19df..ca086ba00a 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1498,13 +1498,27 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Erro= r **errp) */ smmuv3_range_inval(bs, &cmd, SMMU_STAGE_2); break; + case SMMU_CMD_ATC_INV: + { + SMMUDevice *sdev =3D smmu_find_sdev(bs, CMD_SID(&cmd)); + + if (!sdev || !s->ats) { + trace_smmuv3_unhandled_cmd(type); + break; + } + + if (!smmuv3_accel_issue_inv_cmd(s, &cmd, sdev, errp)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + break; + } case SMMU_CMD_TLBI_EL3_ALL: case SMMU_CMD_TLBI_EL3_VA: case SMMU_CMD_TLBI_EL2_ALL: case SMMU_CMD_TLBI_EL2_ASID: case SMMU_CMD_TLBI_EL2_VA: case SMMU_CMD_TLBI_EL2_VAA: - case SMMU_CMD_ATC_INV: case SMMU_CMD_PRI_RESP: case SMMU_CMD_RESUME: case SMMU_CMD_STALL_TERM: @@ -1931,6 +1945,10 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "ril can only be disabled if accel=3Don"); return false; } + if (s->ats) { + error_setg(errp, "ats can only be enabled if accel=3Don"); + return false; + } return true; } =20 @@ -2066,6 +2084,7 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), /* RIL can be turned off for accel cases */ DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), + DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2093,6 +2112,9 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "configured in nested mode for vfio-pci dev assignment"); object_class_property_set_description(klass, "ril", "Disable range invalidation support (for accel=3Don)"); + object_class_property_set_description(klass, "ats", + "Enable/disable ATS support (for accel=3Don). Please ensure host " + "platform has ATS support before enabling this"); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 3126aca42c..c145678185 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -346,6 +346,7 @@ typedef struct AcpiIortSMMUv3Dev { /* Offset of the SMMUv3 IORT Node relative to the start of the IORT */ size_t offset; bool accel; + bool ats; } AcpiIortSMMUv3Dev; =20 /* @@ -401,6 +402,7 @@ static int iort_smmuv3_devices(Object *obj, void *opaqu= e) =20 bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort); + sdev.ats =3D object_property_get_bool(obj, "ats", &error_abort); pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); sbdev =3D SYS_BUS_DEVICE(obj); sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); @@ -544,6 +546,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) int i, nb_nodes, rc_mapping_count; AcpiIortSMMUv3Dev *sdev; size_t node_size; + bool ats_needed =3D false; int num_smmus =3D 0; uint32_t id =3D 0; int rc_smmu_idmaps_len =3D 0; @@ -579,6 +582,9 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) /* Calculate RMR nodes required. One per SMMUv3 with accelerated m= ode */ for (i =3D 0; i < num_smmus; i++) { sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + if (sdev->ats) { + ats_needed =3D true; + } if (sdev->accel) { nb_nodes++; } @@ -678,8 +684,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, 0, 2); /* Reserved */ /* Table 15 Memory Access Flags */ build_append_int_noprefix(table_data, 0x3 /* CCA =3D CPM =3D DACS =3D = 1 */, 1); - - build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */ + /* ATS Attribute */ + build_append_int_noprefix(table_data, ats_needed, 4); /* MCFG pci_segment */ build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */ =20 diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 533a2182e8..242d6429ed 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -70,6 +70,7 @@ struct SMMUv3State { uint64_t msi_gpa; Error *migration_blocker; bool ril; + bool ats; }; =20 typedef enum { --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703049; cv=none; d=zohomail.com; s=zohoarc; b=NZLupXK5nHmZSYGw6Xb+rSghPYwhwj1xnc6JQs/PBqVAUFB0H8BVQKAtAXIDgf2NmY0BtuNQ4AWqhLldmkDFGA2EHYzgJjIlQG+OTMVMbomB/FSfDvE+7MaTUiIUtUKHIRGdWp5zfGkjYPH8tlZF8QPNxQ1s9mYmYnUpoYuUT4M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703049; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=OJP/2NJ9gFVt5VZ/DFu9x7R1zrkd3AlIv3rZU6uB/Nc=; b=nuT2OJ4dGJWgufFdOqhx4GxFE0GJRtY37KFJbegnZk3Vd8quo+b3ifx5O2wtEJtIEClKJIiaqjyTZAk7ougMFVaBrRwNKXPLMTtpC9gIZ/XkjCOuT/i7y8iCl69oC1PswO5Z9opnRuXxKFTQH1wpWO9aO/Bv2VL/SuiChlvl9GE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703049343426.04482860766007; Thu, 29 Jan 2026 08:10:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUb3-0001ag-UQ; Thu, 29 Jan 2026 11:10:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUan-0000YB-Kw for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:02 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUak-0006mN-1a for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:01 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4805ef35864so9518255e9.0 for ; Thu, 29 Jan 2026 08:09:57 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702996; x=1770307796; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=OJP/2NJ9gFVt5VZ/DFu9x7R1zrkd3AlIv3rZU6uB/Nc=; b=n7L6OhoOeknHBBWAeMICwwyGyt4veX8q2v/udC4td6hgHbpVshnqV1BpaQp58I3NND uePvgLXNn4898zptcW41u1fZglAItryFaTG21Z7zbJkCFBry3iHWTciLw+ewJkch0L+X 9uL+wPbQFeiTR0GvtSmm2NNG2l9CjzhF8hWbhpx+oa1p7ghQhUFDxTOKO88Fug1teoot d4hTEDtd8G4cTtSI7emkMsJ7Hpgmzuv9q2PeZzct7w58LoAPObV4tCGoaswXo7qnAud0 wUOrqwVtnPAmItf9p0kt5BYgq2EK6gFd1IfdL28h/rfZJZvDVzkq1sbozt+5XPy/OubY nJ5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702996; x=1770307796; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=OJP/2NJ9gFVt5VZ/DFu9x7R1zrkd3AlIv3rZU6uB/Nc=; b=lCvRVDLkxqan/BdDEQXO1Z6+om0H87eVkJgf7f63XbV/Jb9vnbY+Z22TZXhHq1dZAH MtcoKHrAYjVv1xJr4pEGbYyVygqYVhoJ91v1StV1myEmDM+BIfkTO4RTD7w5KHSqgHRk zrHadIHpVv0Dprf4PoAyOBllo3mgjQ4+DV+EemNEsrs3loxr1B8W2YlJwlVWJBe0n3gK B//DpmHMaJ3TAuvSJMTU8OwkM1SemuA3Xe4nKbybM4ZXyYNhOXNGHR6J3dSuuBmZAGlj fL6OWL9pv+TnLOtx0t/WX/voxGz1onE289/awDgPSlkz5Z7veOsEBTIGb9Gs6A1b7SD+ W+5A== X-Gm-Message-State: AOJu0Yyo3kAyHE9niY+qpM5qVK9hGl+OZq2vcxazynXruekvLT31EFvE YmKcv0YqrorAz5g0stF2bbyp0mPLRXoTbxkyMwyeLBDnNq4aRztczePgqSXvQjOzaHsX6mgnz5s d6fA/EaM= X-Gm-Gg: AZuq6aJ7tpMkO8X5CxLep4pN8sq+NqED/GkCvkOFavi320qtwVw01Z8HHztS/AEBMsA L8hkwxRXK9q+Ic9nuwXAvEg/sJFbKenr3G/uTH+pfCypRAIKRbu7AF6ePDoZDbpj7Sau1jTG9oT SdlTSSUCWysGfbyHeJBaPZlt+N+u+NuVkiCVDjTAP07zOni1ibI96tGBguEcI3bUNgoB304iOTN G0DFzzYGsxuJjeqSP30GfA6akosZMtkOCK7OQeYJiSjSXPYug7wk9tb/MTW43xffhxR5eDP2GWm 18xER4YVK552GZAgzF6dgZ+Hxm3VeUCu772YRZws7/bpWhKN0KiVWaq6Of5zdnLF+EczdVrRVYO cqhxSH4PcWqSvwAa5b4E8Svc3o27eRSUdrzoQASOXDJxjEm7QjYxibFxgX+7ByZ9+Ap4iZGotDV PoYoKp9AA2yK0ZMaNxwm9gyE9E0gIy+g== X-Received: by 2002:a05:600c:620b:b0:480:39ad:3b7c with SMTP id 5b1f17b1804b1-48069c16922mr126645725e9.16.1769702996181; Thu, 29 Jan 2026 08:09:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/43] hw/arm/smmuv3-accel: Add property to specify OAS bits Date: Thu, 29 Jan 2026 16:09:05 +0000 Message-ID: <20260129160917.1415092-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703050820158500 From: Shameer Kolothum QEMU SMMUv3 currently sets the output address size (OAS) to 44 bits. With accelerator mode enabled, a device may use SVA, where CPU page tables are shared with the SMMU, requiring an OAS at least as large as the CPU=E2=80=99s output address size. A user option is added to configure this. However, the OAS value advertised by the virtual SMMU must remain compatible with the capabilities of the host SMMUv3. In accelerated mode, the host SMMU performs stage-2 translation and must be able to consume the intermediate physical addresses (IPA) produced by stage-1. The OAS exposed by the virtual SMMU defines the maximum IPA width that stage-1 translations may generate. For AArch64 implementations, the maximum usable IPA size on the host SMMU is determined by its own OAS. Check that the configured OAS does not exceed what the host SMMU can safely support. Tested-by: Zhangfei Gao Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Reviewed-by: Jonathan Cameron Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-32-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 22 ++++++++++++++++++++++ hw/arm/smmuv3.c | 16 +++++++++++++++- include/hw/arm/smmuv3-common.h | 5 ++++- include/hw/arm/smmuv3.h | 1 + 4 files changed, 42 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index a97abc1f79..ea420afeb7 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -27,6 +27,14 @@ static MemoryRegion root, sysmem; static AddressSpace *shared_as_sysmem; =20 +static int smmuv3_oas_bits(uint32_t oas) +{ + static const int map[] =3D { 32, 36, 40, 42, 44, 48, 52, 56 }; + + g_assert(oas < ARRAY_SIZE(map)); + return map[oas]; +} + static bool smmuv3_accel_check_hw_compatible(SMMUv3State *s, struct iommu_hw_info_arm_smmuv3 *info, @@ -74,6 +82,15 @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s, error_setg(errp, "Host SMMUv3 doesn't support Range Invalidation"); return false; } + /* Check OAS value opted is compatible with Host SMMUv3 IPA */ + if (FIELD_EX32(info->idr[5], IDR5, OAS) < + FIELD_EX32(s->idr[5], IDR5, OAS)) { + error_setg(errp, "Host SMMUv3 supports only %d-bit IPA, but the vS= MMU " + "OAS implies %d-bit IPA", + smmuv3_oas_bits(FIELD_EX32(info->idr[5], IDR5, OAS)), + smmuv3_oas_bits(FIELD_EX32(s->idr[5], IDR5, OAS))); + return false; + } =20 /* QEMU SMMUv3 supports GRAN4K/GRAN16K/GRAN64K translation granules */ if (FIELD_EX32(info->idr[5], IDR5, GRAN4K) !=3D @@ -657,6 +674,11 @@ void smmuv3_accel_idr_override(SMMUv3State *s) =20 /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */ s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, s->ats); + + /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */ + if (s->oas =3D=3D SMMU_OAS_48BIT) { + s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS_48); + } } =20 /* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index ca086ba00a..cb02184d2d 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -299,7 +299,8 @@ static void smmuv3_init_id_regs(SMMUv3State *s) s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, 1); s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, BBML, 2); =20 - s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 b= its */ + /* OAS: 44 bits */ + s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS_44); /* 4K, 16K and 64K granule support */ s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1); s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1); @@ -1949,6 +1950,10 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "ats can only be enabled if accel=3Don"); return false; } + if (s->oas !=3D SMMU_OAS_44BIT) { + error_setg(errp, "OAS must be 44 bits when accel=3Doff"); + return false; + } return true; } =20 @@ -1959,6 +1964,11 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) return false; } =20 + if (s->oas !=3D SMMU_OAS_44BIT && s->oas !=3D SMMU_OAS_48BIT) { + error_setg(errp, "OAS can only be set to 44 or 48 bits"); + return false; + } + return true; } =20 @@ -2085,6 +2095,7 @@ static const Property smmuv3_properties[] =3D { /* RIL can be turned off for accel cases */ DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false), + DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2115,6 +2126,9 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) object_class_property_set_description(klass, "ats", "Enable/disable ATS support (for accel=3Don). Please ensure host " "platform has ATS support before enabling this"); + object_class_property_set_description(klass, "oas", + "Specify Output Address Size (for accel=3Don). Supported values " + "are 44 or 48 bits. Defaults to 44 bits"); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h index 415b7ccde5..abe3565357 100644 --- a/include/hw/arm/smmuv3-common.h +++ b/include/hw/arm/smmuv3-common.h @@ -342,7 +342,10 @@ REG32(IDR5, 0x14) FIELD(IDR5, VAX, 10, 2); FIELD(IDR5, STALL_MAX, 16, 16); =20 -#define SMMU_IDR5_OAS 4 +#define SMMU_OAS_44BIT 44 +#define SMMU_OAS_48BIT 48 +#define SMMU_IDR5_OAS_44 4 +#define SMMU_IDR5_OAS_48 5 =20 REG32(IIDR, 0x18) REG32(AIDR, 0x1c) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 242d6429ed..d488a39cd0 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -71,6 +71,7 @@ struct SMMUv3State { Error *migration_blocker; bool ril; bool ats; + uint8_t oas; }; =20 typedef enum { --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703222; cv=none; d=zohomail.com; s=zohoarc; b=aJmhBDBde46fUnM8WAuOWghiIigzfYiWy+wYQ0ZJk4xq4ddi6Ekg2JHY9QWzJLzeWUh9mo3CET1APVqcsCNhbddXsZWvNDrCZTqReJxcu4yRSFNXN5Hrk1T1YplGTabsjHhr8zOa4FjEPX+SGbbUbkj6pzEblCUDdVEk/oeIKss= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703222; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=HyUsZEQsdn3K2mNkG80GmLcIjlyjULxDGM4SHbQzwtI=; b=cl6ckshxjQiH+1kac8FcfmX0jUuxveiaQLmGqDqNsIlhDBADw0TUiI+vKgHRNFAFYPOd4NXTjSYvhCbwDSyv69jfUvErKOY+/qIBPdydgUxDrdzlfLGRT1vpG09spJm6FqldJxZlkJMEkGTLFXdLmrHDGDmuE70Bj2VDZneyDYA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176970322233151.853334024378796; Thu, 29 Jan 2026 08:13:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUbD-0001zv-1H; Thu, 29 Jan 2026 11:10:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUan-0000Xt-Jb for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:02 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUal-0006n7-Ei for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:00 -0500 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-4806ce0f97bso10072505e9.0 for ; Thu, 29 Jan 2026 08:09:58 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702997; x=1770307797; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=HyUsZEQsdn3K2mNkG80GmLcIjlyjULxDGM4SHbQzwtI=; b=eFyULnozWeeAeLy2AE07oSH869ESTIib4IpSyEaxvs56xHTUiaX2nraBlTnK6aJqa4 AS7n/1fEdeQLiJWGZ5hW9vf62GtzimtEtEOkpg2B0yRdN3uUk8cY9DoiQcjX48T1u662 wJbBIMgcnBueExJMCfwwh11IluUAlGs7A1EVRqY8TxGA50DGJoDxO6zCT9qs9d8Dr1ql bvB+OxsaTGw97wQIJqoMdKXg8kaZT/1DicOxHv5rrzJT4L2uSiFuyrEcGcE7QYiB8iSB TkaRxol2jjbEZKap/bPmcMLHdS+TzKYgEICq4E75nm0HDkFydlz90fj/lXRCF7P1jfGz XQqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702997; x=1770307797; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=HyUsZEQsdn3K2mNkG80GmLcIjlyjULxDGM4SHbQzwtI=; b=UguGk/hYkBzj7al8ZTmDZQyrkLGXKGUZ1N9iHA4Y6D9pURCKVpOdty2P28QFjHKjf1 Lz+6gibL0WSa3zzo+djwNM1qHkp4TeO7cmrQYmqwajZy/JQMsXA5Qebc70CYxnh2T41I YjvvumyRy8+5Uod1Ft1qUxyZp9zIbYG1miFs1GqQLJcM6YOcHl2tkL2fV1WIZ8o4pj+Q X42O/5fbLc3iBU1byaNYXBEQmbMxAo4NN09P4vMFM1ceYOr1WmdcNbiSZm1hgVLWz6BW r374Yv4fX9cRtx4CbuzM+sqosFenVIT6fydsxq4tkYmiPw9PG29BJXbWNChJiTTMRTg9 hMrA== X-Gm-Message-State: AOJu0Yyc7mOofaNufr7a9Gl2gGPEkePPsX3NpZmKzUb0x9GFgoRyDL78 1S9/mI1S4DzZPz04xMy6dQGzHUkvWSmBKbNplu3LC/4qGcjTHX1o6u+9sMT+stQhhXK74P02mSz TUNzO/Qs= X-Gm-Gg: AZuq6aKlNVTYW0lyghKm0hcEuLj1PQNQ5OnpP4WmD1GnuNzkQkAqJqpCmRVg3wEB4i8 oFEjxoMUlTtPk1fbIwuvpPd3Je0NfAfyxHMqVtrfXd/J7jeooHm9LEiCAcInB/6GF6D15vHl6eN h86emiqeolJmarwpZqwUGd4UM/jMYJmwijNGmrwWCtLo32kqgj8TlKvduP6dm2C05Z0/MW9WnsR 0e3wF06V35pE1AHBEbG6it8CoHTsPCilLh56snU6fE0+U9RkqKC5e4UO6CX5UQyNBDCSNPNswkQ vYVo1BN9rgiawMYPdNGfwtDR3Xq0KHRwY9BViADC7R1xIgeDseO8I4iezbvumyblabVZ+gRw8CM 897vk50zPoRktyctwkg5zoAMcF9xyP72uPYCKO+sh3LjX2lavMjV8cy3gFqnRzgdgM8lIjZ3OmF v44WxzZ7jAcsbbxRYuc9fgrof0Xqo6Uw== X-Received: by 2002:a05:600c:154c:b0:480:32da:f33e with SMTP id 5b1f17b1804b1-48069c6978fmr129222925e9.17.1769702997263; Thu, 29 Jan 2026 08:09:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/43] backends/iommufd: Retrieve PASID width from iommufd_backend_get_device_info() Date: Thu, 29 Jan 2026 16:09:06 +0000 Message-ID: <20260129160917.1415092-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703224822154100 From: Shameer Kolothum Retrieve PASID width from iommufd_backend_get_device_info() and store it in HostIOMMUDeviceCaps for later use. Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Zhangfei Gao Reviewed-by: Nicolin Chen Reviewed-by: C=C3=A9dric Le Goater Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Reviewed-by: Yi Liu Message-id: 20260126104342.253965-33-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- backends/iommufd.c | 6 +++++- hw/arm/smmuv3-accel.c | 3 ++- hw/vfio/iommufd.c | 6 ++++-- include/system/host_iommu_device.h | 3 +++ include/system/iommufd.h | 3 ++- 5 files changed, 16 insertions(+), 5 deletions(-) diff --git a/backends/iommufd.c b/backends/iommufd.c index e3a3c1480e..9b63d74083 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -389,7 +389,8 @@ bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *b= e, =20 bool iommufd_backend_get_device_info(IOMMUFDBackend *be, uint32_t devid, uint32_t *type, void *data, uint32_t = len, - uint64_t *caps, Error **errp) + uint64_t *caps, uint8_t *max_pasid_lo= g2, + Error **errp) { struct iommu_hw_info info =3D { .size =3D sizeof(info), @@ -408,6 +409,9 @@ bool iommufd_backend_get_device_info(IOMMUFDBackend *be= , uint32_t devid, g_assert(caps); *caps =3D info.out_capabilities; =20 + if (max_pasid_log2) { + *max_pasid_log2 =3D info.out_max_pasid_log2; + } return true; } =20 diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index ea420afeb7..342944da23 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -121,7 +121,8 @@ smmuv3_accel_hw_compatible(SMMUv3State *s, HostIOMMUDev= iceIOMMUFD *idev, uint64_t caps; =20 if (!iommufd_backend_get_device_info(idev->iommufd, idev->devid, &data= _type, - &info, sizeof(info), &caps, errp)= ) { + &info, sizeof(info), &caps, NULL, + errp)) { return false; } =20 diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 2947e1b80f..131612eb83 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -398,7 +398,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vb= asedev, */ if (!iommufd_backend_get_device_info(vbasedev->iommufd, vbasedev->devi= d, &type, &caps, sizeof(caps), &hw_c= aps, - errp)) { + NULL, errp)) { return false; } =20 @@ -939,19 +939,21 @@ static bool hiod_iommufd_vfio_realize(HostIOMMUDevice= *hiod, void *opaque, HostIOMMUDeviceCaps *caps =3D &hiod->caps; VendorCaps *vendor_caps =3D &caps->vendor_caps; enum iommu_hw_info_type type; + uint8_t max_pasid_log2; uint64_t hw_caps; =20 hiod->agent =3D opaque; =20 if (!iommufd_backend_get_device_info(vdev->iommufd, vdev->devid, &type, vendor_caps, sizeof(*vendor_caps), - &hw_caps, errp)) { + &hw_caps, &max_pasid_log2, errp))= { return false; } =20 hiod->name =3D g_strdup(vdev->name); caps->type =3D type; caps->hw_caps =3D hw_caps; + caps->max_pasid_log2 =3D max_pasid_log2; =20 idev =3D HOST_IOMMU_DEVICE_IOMMUFD(hiod); idev->iommufd =3D vdev->iommufd; diff --git a/include/system/host_iommu_device.h b/include/system/host_iommu= _device.h index ab849a4a82..bfb2b60478 100644 --- a/include/system/host_iommu_device.h +++ b/include/system/host_iommu_device.h @@ -30,6 +30,8 @@ typedef union VendorCaps { * @hw_caps: host platform IOMMU capabilities (e.g. on IOMMUFD this repres= ents * the @out_capabilities value returned from IOMMU_GET_HW_INFO i= octl) * + * @max_pasid_log2: width of PASIDs supported by host IOMMU device + * * @vendor_caps: host platform IOMMU vendor specific capabilities (e.g. on * IOMMUFD this represents a user-space buffer filled by ker= nel * with host IOMMU @type specific hardware information data) @@ -37,6 +39,7 @@ typedef union VendorCaps { typedef struct HostIOMMUDeviceCaps { uint32_t type; uint64_t hw_caps; + uint8_t max_pasid_log2; VendorCaps vendor_caps; } HostIOMMUDeviceCaps; #endif diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 567dfb7b1d..80d72469a9 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -71,7 +71,8 @@ int iommufd_backend_unmap_dma(IOMMUFDBackend *be, uint32_= t ioas_id, hwaddr iova, uint64_t size); bool iommufd_backend_get_device_info(IOMMUFDBackend *be, uint32_t devid, uint32_t *type, void *data, uint32_t = len, - uint64_t *caps, Error **errp); + uint64_t *caps, uint8_t *max_pasid_lo= g2, + Error **errp); bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint32_t dev_id, uint32_t pt_id, uint32_t flags, uint32_t data_type, uint32_t data_len, --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703075; cv=none; d=zohomail.com; s=zohoarc; b=mW3OKmHa2WL7OEl07vvX3q7R4vADPpLjsiVdjSo830NAINzXyd8mpeMdPZoYNbuo9YXlac8Mbl6O5CEQRde5otxyL29FxEMpfi6SeVHBf8LIJMGLBYwyeZfrz9Ufg2pTOibcTxEIQLfOo72YzfKQlrouzDRzpJs3+BpWZjybIBQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703075; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=u3uV6GSWr+BEGrx5YGtZDjy8LLlQ8HkEC6LhLpQIb3I=; b=EW6bjFUUzvJhPRuHZMV+fMaDl5gGkminNb+NpRVx6muPqvMfZ8n+rDBA1kpQVoHORhL7pqZ0A5Vlv0yqW1wbIKPbhkzaqWlLu+Oj87ZjDree8yo5/QMZF6tX4l9bNLTNFQrck6aeMAzp0uLAXd3CgyZKs/KukOCK1PztuL1Fqn4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703075437440.3632719975094; Thu, 29 Jan 2026 08:11:15 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUb5-0001cT-Sy; Thu, 29 Jan 2026 11:10:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUap-0000bH-LP for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:05 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUam-0006nH-0P for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:02 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-4806dffc64cso9063125e9.1 for ; Thu, 29 Jan 2026 08:09:59 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702998; x=1770307798; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=u3uV6GSWr+BEGrx5YGtZDjy8LLlQ8HkEC6LhLpQIb3I=; b=onP+s88xHsCmQ8HOso8d9j4hpl1eKYEvZUPfKoQ/Z3Fw4hJDdhi823cwml35l8zgso LJnXo7NhdEpkKSuESSKShAZUvI/Yuj3G85qg2oQL3HX6dCTApFqEA2IId3To0/AEJvrJ mlsJifApNVxey67Den87VrZyIp4ibjg7tudNZbNN8jb8LhCBHmrhiwR5iCHM72r3pLsY FAfBtPOKRYqlgF2RAR+VLKiWx85EzMrkppyCTJkoIX2kuwSSEKXcTMSlMBJ9vTIZYSNV rL0KjQZ+HJuXQ+GJTMTihl7U44Nqq9QlYoLL1j7dOkvzH7KzKrRpwAqKJgZEzCYoXdzo bbbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702998; x=1770307798; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=u3uV6GSWr+BEGrx5YGtZDjy8LLlQ8HkEC6LhLpQIb3I=; b=eJZer+o9Av5JC4M/TDJw4GooiO0KSV7JX2PSm7e3u8pQKBV/w9NVOftI5lbm7V4Zm7 XQpla5NEN7aWDy5+hCgAfqOnqUdQR5gtOZ0MR/VqO8GkCdEoMjz5XRVPLej1Y65BLIV2 72+Y06Tf90ecE+k4UNyegkfqQhOM7oz0Nk4kPI4Fb6QeNa8/uichttCi4YmjTs8/69fu Z8ktWByy67XWobD5jxGxBMzJt+fm3UyJGLByBhCTB8OUtFcI0nM4z+/MbtfhIvXxRDFL eiI8NCQvm9r1bVZogI9u9k0ZXcNPFLWgVkBn1iyPL4O+Qca4X6q71E3psjF1iW+IkxCZ bCAg== X-Gm-Message-State: AOJu0Yyb+yT057qnuebN3lhEJJzzJNlrW+fQ27QVL4E7Wpn/k8ZGatuW lRWGw8sQbWv6HKQiKVvBJe3slevjIwzK8plszxxvx6b4jadRAHA7CYkd8R/olkHLGvbq1ufckQ1 2Vqfue2U= X-Gm-Gg: AZuq6aKNYwS2lnoMjlwsfL8QTmL7kUpTcpTw4Y7IfzHCVDQ71Fn4QyqrIFRTpi7eChc zlU/tbEonNaTU/gXGRBJT10QJ7anWWSvCbA2e8NJSN9A4vaZBqiYebzqo4mhgrh0RX+cd3ALjGF PQvndwbYRZCOQSJm/+LIJB2OYUyHdNsSES1cAI+zEp6gFUaX0ims6MAaRUPXMQY8I3/13GyAEeZ 9WElDr84botcc8gc6ag349WQ7Kru6/w7vdk/drf0f17itEoS2+wkf4aQr10oS65I/ETrCehX+/r QIGIDemS5AlQpkK1nmuIz8pJ/VDjoHYgZeyY2S7gn+xccQ5ICFBMGMdlPNeTE4lA87gc6H0UoiY aUz57q6/V8zzFvrpmZ2Ob+2ep5n8xzvXzhF1JAvFsewq8/4qzi1L1KAxz8wjIZYkw/FnR0mXc+n A3Fs3os1zGIbe8sNoWRNxwoVZjOew/5g== X-Received: by 2002:a05:600c:8208:b0:47d:92bb:2723 with SMTP id 5b1f17b1804b1-48069bfa957mr118140905e9.3.1769702998389; Thu, 29 Jan 2026 08:09:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/43] backends/iommufd: Add get_pasid_info() callback Date: Thu, 29 Jan 2026 16:09:07 +0000 Message-ID: <20260129160917.1415092-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703076648154100 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum The get_pasid_info callback retrieves PASID capability information when the HostIOMMUDevice backend supports it. Currently, only the Linux IOMMUFD backend provides this information. This will be used by a subsequent patch to synthesize a PASID capability for vfio-pci devices behind a vIOMMU that supports PASID. Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Zhangfei Gao Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum Reviewed-by: Yi Liu Message-id: 20260126104342.253965-34-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- backends/iommufd.c | 17 +++++++++++++++++ include/system/host_iommu_device.h | 17 +++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/backends/iommufd.c b/backends/iommufd.c index 9b63d74083..13822df82f 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -539,11 +539,28 @@ static int hiod_iommufd_get_cap(HostIOMMUDevice *hiod= , int cap, Error **errp) } } =20 +static bool hiod_iommufd_get_pasid_info(HostIOMMUDevice *hiod, + PasidInfo *pasid_info) +{ + HostIOMMUDeviceCaps *caps =3D &hiod->caps; + + if (!caps->max_pasid_log2) { + return false; + } + + g_assert(pasid_info); + pasid_info->exec_perm =3D (caps->hw_caps & IOMMU_HW_CAP_PCI_PASID_EXEC= ); + pasid_info->priv_mod =3D (caps->hw_caps & IOMMU_HW_CAP_PCI_PASID_PRIV); + pasid_info->max_pasid_log2 =3D caps->max_pasid_log2; + return true; +} + static void hiod_iommufd_class_init(ObjectClass *oc, const void *data) { HostIOMMUDeviceClass *hioc =3D HOST_IOMMU_DEVICE_CLASS(oc); =20 hioc->get_cap =3D hiod_iommufd_get_cap; + hioc->get_pasid_info =3D hiod_iommufd_get_pasid_info; }; =20 static const TypeInfo types[] =3D { diff --git a/include/system/host_iommu_device.h b/include/system/host_iommu= _device.h index bfb2b60478..f000301583 100644 --- a/include/system/host_iommu_device.h +++ b/include/system/host_iommu_device.h @@ -59,6 +59,12 @@ struct HostIOMMUDevice { #endif }; =20 +typedef struct PasidInfo { + bool exec_perm; + bool priv_mod; + uint8_t max_pasid_log2; +} PasidInfo; + /** * struct HostIOMMUDeviceClass - The base class for all host IOMMU devices. * @@ -116,6 +122,17 @@ struct HostIOMMUDeviceClass { * @hiod: handle to the host IOMMU device */ uint64_t (*get_page_size_mask)(HostIOMMUDevice *hiod); + /** + * @get_pasid_info: Return the PASID information associated with the + * @hiod Host IOMMU device. + * + * @hiod: handle to the host IOMMU device + * + * @pasid_info: If success, returns the PASID related information. + * + * Returns: true on success, false on failure. + */ + bool (*get_pasid_info)(HostIOMMUDevice *hiod, PasidInfo *pasid_info); }; =20 /* --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703260; cv=none; d=zohomail.com; s=zohoarc; b=MTMPONLutIb3B2cgf1E8wBRgTlTS7rK9anJkSkQhvY8CFe1uy5isN5DDJgddsUmwBdMPraiXf0CmrCoH8efr9d/6Mwl8p4OxK2cE8JOZwezjhcnRbUkuY509Ed6BGCgr/qm21OChL2RWOGtoTwSl6PaV42WNJso28+NmY1kBvCo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703260; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=veysRNauk8VXncuyC7/h3gsWbA6jttORlD+vMEjZXSs=; b=WTZ/v7S+Ht8Etr4+/DmG7QIVHAFwEpjE+GcG557TNLJNMgbcO806eqLvC6AEnvkyALlKaEd1M3cDpE4+FZyjIpUE5SIlnYZKNsfjKFdh73asJoId2Z11uXisc99bd8jLKE9YM1veGgHIxv5a0fsysv4kxKMrvEqMv4c762L2BLc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703260012376.24138465909004; Thu, 29 Jan 2026 08:14:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUb4-0001bH-5w; Thu, 29 Jan 2026 11:10:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUap-0000bK-MS for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:05 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUan-0006oT-A4 for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:03 -0500 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-47ee07570deso9935305e9.1 for ; Thu, 29 Jan 2026 08:10:00 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702999; x=1770307799; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=veysRNauk8VXncuyC7/h3gsWbA6jttORlD+vMEjZXSs=; b=idRjtUezipt7uuQuAxMtSYPBybyU1PX3cM6idE8mwmDZBMWYNf53lgHa702uIaWWMg C7zJMFMm3toQBnaG1tq0HhjgEynvpY9CUI/8j9SoEus+YAEOtg1up/pndew+AqUQcTiC eFqZOMCDZTETpz+IqGbJHFkBnAAv3/4Sg6nISh03QpNKMKv+oEwzsMOhNJTOUWDrR+lH eupuGOwfvdRLFoDVxflXmldA32QO/UUGL6DAWjPQd6T+sA/Lo5pcKMkjPZh/4v+T9rVG 43XL4V8mnqfwb6WGA4ovy5CDgMK3oZMEmkXbrWXS2GfY39rYIDErcQ4A24Y9IdYoUxyz e8ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702999; x=1770307799; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=veysRNauk8VXncuyC7/h3gsWbA6jttORlD+vMEjZXSs=; b=KudNK5FodWy6fIUnoaZImFlJBxo6sBf+jexmkSC9fEEUyp25FvDepgFbR8J0jangy7 NXJaDv3F7vYZx7ZwzoDg5wUyrV9oTSzGOweH1IKR7Y73rgMCpzJ+FuwxbOutvmDgz8Fm uDay+1jqL8nWchgmuLLJY8l/VCIN4Oj04Sr5fd5foCvZu394gXRLSzf4xJ4EbbqGOnJh 5X1acuCM8LcXIN1B+otnXywpOxc+Tws2Bxx0dTekwElEiICqO+XaQItnkJcUSs64bAMU bu0FU8dCEOgQiYPIYzOvmMGxuaEbSITc3E4iM7UW8odCpeIjCGx5x0u84qB0bzn2piqn KeUw== X-Gm-Message-State: AOJu0YyiUEcUf+LRHECNoWcYA+iUNksNOGHmpODAzw8xkY8DXJMJJS5+ zGV6YdLW81th/XtS6x08YR/dRkpp+ucO+T5wX0984ye1PHTo7UDDwtSV7Jln640MkoDbyP7tJ/D 254oamsA= X-Gm-Gg: AZuq6aIZQ/nVv6XmsVL1ogNkiaqp6hupRtY3me2zo9LKfHrO/FYhXGKJFqyx0jSx6/t NBbnkMqQcv3iVqXTuMasr7PSdQGV9+244nBoSsCYJqyx5jRc2EZ2zTV33phoH1JrBnYKUA0+upD jx4EF92lvOemNndzov6JxTH332qPzu/E4NYbEgqrz1uOFXGR+7jprRAvBK8bTWcXp8eNp0rueyx CDc6Rg14x51M8ak3Gscsp+eK6s24ozS6jjAsaw9/3NvqDaB9XSzLEaC5cWH/jXMljmGIfAlcmwq qxLoLs0txYP/SFIY26qlb8GI1/NFEB6R/PmH62XyqJ7WmyCE9pmHIt5BFgIj2EGNIpxeJEXxDT1 WV35Fwe2hUdm44gdXi3FrGHQW+HzxhOHJ13ROQxhe8ILl6uOHzk5hmqD5mRBdsePHePu0THw0+Y KAuiacziGsz8a1B1eXEN39hbhEQGEQqA== X-Received: by 2002:a05:600c:4e90:b0:477:582e:7a81 with SMTP id 5b1f17b1804b1-48069c2a907mr103774265e9.4.1769702999460; Thu, 29 Jan 2026 08:09:59 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/43] hw/pci: Add helper to insert PCIe extended capability at a fixed offset Date: Thu, 29 Jan 2026 16:09:08 +0000 Message-ID: <20260129160917.1415092-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703262028158502 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Add pcie_insert_capability(), a helper to insert a PCIe extended capability into an existing extended capability list at a caller specified offset. Unlike pcie_add_capability(), which always appends a capability to the end of the list, this helper preserves the existing list ordering while allowing insertion at an arbitrary offset. The helper only validates that the insertion does not overwrite an existing PCIe extended capability header, since corrupting a header would break the extended capability linked list. Validation of overlaps with other configuration space registers or capability-specific register blocks is left to the caller. Reviewed-by: Michael S. Tsirkin Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Zhangfei Gao Reviewed-by: Jonathan Cameron Signed-off-by: Shameer Kolothum Reviewed-by: Yi Liu Message-id: 20260126104342.253965-35-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/pci/pcie.c | 69 +++++++++++++++++++++++++++++++++++++++++++ include/hw/pci/pcie.h | 2 ++ 2 files changed, 71 insertions(+) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index b302de6419..aa9024e532 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -1050,6 +1050,75 @@ static void pcie_ext_cap_set_next(PCIDevice *dev, ui= nt16_t pos, uint16_t next) pci_set_long(dev->config + pos, header); } =20 +/* + * Insert a PCIe extended capability at a given offset. + * + * This helper only validates that the insertion does not overwrite an + * existing PCIe extended capability header, as corrupting a header would + * break the extended capability linked list. + * + * The caller must ensure that (offset, size) does not overlap with other + * registers or capability-specific register blocks. Overlaps with + * capability-specific registers are not checked and are considered a + * user-controlled override. + * + * Note: Best effort helper. The PCIe spec does not require extended + * capabilities to be ordered, but most devices use a forward-linked list. + * Devices that do not consistently use a forward-linked list may cause + * insertion to fail. + */ +bool pcie_insert_capability(PCIDevice *dev, uint16_t cap_id, uint8_t cap_v= er, + uint16_t offset, uint16_t size) +{ + uint16_t pos =3D PCI_CONFIG_SPACE_SIZE, prev =3D 0; + uint32_t header; + + assert(pci_is_express(dev)); + + if (!QEMU_IS_ALIGNED(offset, PCI_EXT_CAP_ALIGN) || + size < 8 || + offset < PCI_CONFIG_SPACE_SIZE || + offset >=3D PCIE_CONFIG_SPACE_SIZE || + offset + size > PCIE_CONFIG_SPACE_SIZE) { + return false; + } + + header =3D pci_get_long(dev->config + pos); + if (!header) { + /* No extended capability present, insertion must be at the ECAP h= ead */ + if (offset !=3D pos) { + return false; + } + pci_set_long(dev->config + pos, PCI_EXT_CAP(cap_id, cap_ver, 0)); + goto out; + } + + while (header && pos && offset >=3D pos) { + uint16_t next =3D PCI_EXT_CAP_NEXT(header); + + /* Reject insertion inside an existing ECAP header (4 bytes) */ + if (offset < pos + PCI_EXT_CAP_ALIGN) { + return false; + } + + prev =3D pos; + pos =3D next; + header =3D pos ? pci_get_long(dev->config + pos) : 0; + } + + pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, pos)); + if (prev) { + pcie_ext_cap_set_next(dev, prev, offset); + } + +out: + /* Make capability read-only by default */ + memset(dev->wmask + offset, 0, size); + memset(dev->w1cmask + offset, 0, size); + /* Check capability by default */ + memset(dev->cmask + offset, 0xFF, size); + return true; +} /* * Caller must supply valid (offset, size) such that the range wouldn't * overlap with other capability or other registers. diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index c880ae1e04..d68bfa6257 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -133,6 +133,8 @@ uint16_t pcie_find_capability(PCIDevice *dev, uint16_t = cap_id); void pcie_add_capability(PCIDevice *dev, uint16_t cap_id, uint8_t cap_ver, uint16_t offset, uint16_t size); +bool pcie_insert_capability(PCIDevice *dev, uint16_t cap_id, uint8_t cap_v= er, + uint16_t offset, uint16_t size); void pcie_sync_bridge_lnk(PCIDevice *dev); =20 void pcie_acs_init(PCIDevice *dev, uint16_t offset); --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703237; cv=none; d=zohomail.com; s=zohoarc; b=Y59tzA5nIck5MCUVjYVEeQpDDVoF4raj0M59tuza36a5XV94zVw/YprXqs5DHH5OZ2MUh/+3xOjGE4Qjs6o4h00CYuiMjCfuh1Lz3wswnUYSe+1gwJ9PV3OakB/68tf7e0NlEidvdbeEtHxjNY5XDl17ZewJR3LJbqd43cHy+Zk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703237; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=4G9TaBDcJtKUE+2eI7zOEpG9xRehne4XFIMepLbMDs8=; b=cSP4LV1DkdlTyFGENo6UtRYMEmBgEBeCJxQ1wMfU6fy6WlcWPG958ylstM/CtyeAJJsgNcqwWGm8AXo/1PBDFT5obSHeGfQ/aMJz8cajUt/FBLkd0liIO/reQM2WmQAE+7nouQHZcCbpUsJtqleXVdXOoSdlFO8pGK+HItgwCFw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703237472675.6187501913481; Thu, 29 Jan 2026 08:13:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUbD-00025v-Rz; Thu, 29 Jan 2026 11:10:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUar-0000gT-D5 for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:07 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUap-0006ov-Df for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:05 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-4358fb60802so717958f8f.1 for ; Thu, 29 Jan 2026 08:10:01 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769703001; x=1770307801; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4G9TaBDcJtKUE+2eI7zOEpG9xRehne4XFIMepLbMDs8=; b=nCdDTb2YqTTQ5ryGwxH3hKFvtI0z8hp+ADFMUU7GbcS2N/WhVfkMSZn20FmpXSMlZ+ kBgcF+m0MfY0qj2/6mdytQMzppIuNntKEDrHB+hTp1ajEIQdKFo3wBAm8NGwnvR729aF cN7OMGxOqBvqLXx4GNY3yrMBsarc5E2H+vSi7bpamuYBN2+xWd70Kh6/xgv2+vrqL5+7 1PBj8oI5d8npnz8UsFq174mWFL5QF9C6nUiO/PLQIYNK2+4kfnqozAFmsGSvNd2wwNSl 8LTCBSl43GtPw64yYO9qsd1CLs0mQAWpMekVzCXPGC14iLEIL7eR0r1b5+yJlNGROXV6 X8xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769703001; x=1770307801; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=4G9TaBDcJtKUE+2eI7zOEpG9xRehne4XFIMepLbMDs8=; b=cq989IEOft1qZQgKF1IBVXW+Z44A/wg5mzxVvdDMGchWO8J/OMCBnGT1Y9SSuyWTpC ygkezGhLWWCBw+qx/5gkoUgnZwaBuD8OK142eLCWABmWZ7cTigPGQFhvhI3BkrxrfZKn hQ5jgI7iEeV3p3Xx9kG5dZw7yKztg7NvvluENmtdUoP8NWJjmxHWlRQu5PlwDGwPYhWp OvcSeDC6WXX9mY4DFoj5ISWL/jFNNnOGb+aYk21/gU2YBwV/GQYgp+Msus+ZXPifiT4N 7F/lfRHa4Q19lVxugbtja6PsOrn4xwWkwgedQLAKUREde4OPGHZKvi8T6cKJ5B9JkyB9 ZrIg== X-Gm-Message-State: AOJu0Yz3D2xzBXpQ8+YG9Uksl5sJ40qmM8Teqg/LsjjcBRJglAlWmXJN jwazxYj8Va6/Oot8jWbILlzgRwaRIZpTKWpiemjTEY2UtTlaa5Ediibw0isvRfN3AesSMEEcIhK lWn+Z2iY= X-Gm-Gg: AZuq6aLdMx8bXDSnxew8xRI3SVubVcoOwXF4Qa/zZTWj6rFqzmS8EWOsgvmC11ITQNX dw35jKynvq/itzNBRrRxTy4dYN57tMIt1bHbklCmcgyfOMwkf/VWTqHq6n9yppQNrf1evCx4NAV ACmv1oCdQkS5mahOXRQhQWuUnDmKaSQk2VD6cR+jiK3eD2yK9iCHh1BqD4fD14OkTPIUHvMecpv xtCk+0hQXo7oTlKfeXLV7Ju8aNV2W78el7DnaayTxJSj0JKXOt/T1jf//N488iGYnmNRnt6xYyn rUc1dl3D/oV65j5VBK4YA5jqG/Lj50zn6LuIGfvrPpsXX/XYObHC0Y/muyKehgXjmIzGrBEdHpG pyzjb0Kk2MdlcbGTZ9zmMsL6DBlc6ulNvjvoGmLGYwvVgblKErgtP6dVglxmj5vXH3f+Grgwijr 2NXoPmIcwacX9tred3T73AfnGA9ibtoA== X-Received: by 2002:a5d:5f82:0:b0:435:97ff:7d35 with SMTP id ffacd0b85a97d-435ea064626mr5437391f8f.4.1769703000661; Thu, 29 Jan 2026 08:10:00 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/43] hw/pci: Factor out common PASID capability initialization Date: Thu, 29 Jan 2026 16:09:09 +0000 Message-ID: <20260129160917.1415092-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703237832158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Refactor PCIe PASID capability initialization by moving the common register init into a new helper, pcie_pasid_common_init(). Subsequent patch to synthesize a vPASID will make use of this helper. No functional change intended. Cc: Michael S. Tsirkin Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Reviewed-by: Michael S. Tsirkin Tested-by: Eric Auger Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum Reviewed-by: Yi Liu Message-id: 20260126104342.253965-36-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/pci/pcie.c | 19 ++++++++++++------- include/hw/pci/pcie.h | 2 ++ 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index aa9024e532..c481c16c0f 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -1284,18 +1284,13 @@ void pcie_acs_reset(PCIDevice *dev) } } =20 -/* PASID */ -void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, - bool exec_perm, bool priv_mod) +void pcie_pasid_common_init(PCIDevice *dev, uint16_t offset, + uint8_t pasid_width, bool exec_perm, bool priv= _mod) { static const uint16_t control_reg_rw_mask =3D 0x07; uint16_t capability_reg; =20 assert(pasid_width <=3D PCI_EXT_CAP_PASID_MAX_WIDTH); - - pcie_add_capability(dev, PCI_EXT_CAP_ID_PASID, PCI_PASID_VER, offset, - PCI_EXT_CAP_PASID_SIZEOF); - capability_reg =3D ((uint16_t)pasid_width) << PCI_PASID_CAP_WIDTH_SHIF= T; capability_reg |=3D exec_perm ? PCI_PASID_CAP_EXEC : 0; capability_reg |=3D priv_mod ? PCI_PASID_CAP_PRIV : 0; @@ -1307,6 +1302,16 @@ void pcie_pasid_init(PCIDevice *dev, uint16_t offset= , uint8_t pasid_width, pci_set_word(dev->wmask + offset + PCI_PASID_CTRL, control_reg_rw_mask= ); =20 dev->exp.pasid_cap =3D offset; + +} + +/* PASID */ +void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, + bool exec_perm, bool priv_mod) +{ + pcie_add_capability(dev, PCI_EXT_CAP_ID_PASID, PCI_PASID_VER, offset, + PCI_EXT_CAP_PASID_SIZEOF); + pcie_pasid_common_init(dev, offset, pasid_width, exec_perm, priv_mod); } =20 /* PRI */ diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index d68bfa6257..fc02aeb169 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -155,6 +155,8 @@ void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_de= v, DeviceState *dev, void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp); =20 +void pcie_pasid_common_init(PCIDevice *dev, uint16_t offset, + uint8_t pasid_width, bool exec_perm, bool priv= _mod); void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, bool exec_perm, bool priv_mod); void pcie_pri_init(PCIDevice *dev, uint16_t offset, uint32_t outstanding_p= r_cap, --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703222; cv=none; d=zohomail.com; s=zohoarc; b=HU4/rghdUbWsCXIB564GtYIXq1mh2kTSJU69/N3+ST1mENfUtanC7v2gEIWWCgPgQuBa0dHLCnyDmyLoQgefoXVQ7LaU3j72k3W2CEoTjHYjYbPhXkyPf3+An1OCP633jyvOCmCPNeoS5kbYuntkkbDXo3vCPdrCdsrlAyXD+cg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703222; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=pWS8UbYXRtwCE4I3yw4CO/HHOucmFzMniAylHRoWl7w=; b=HvwuqUoKse+lLq7wu6xChYgYejaJPDLFLQouLA9z8Ka4e08cQ25tHp76bcb0sPDAY0PvtR4n9jMKjBQU92Kb5CbxoUNMM8EWN1SpBqREiyjxs2IpOOP/NZSBwqjGEgIbWA8szzd189tusrxr9r4CVnwK+G/w7wRTi81y9UWhn+c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703222642718.7627605588876; Thu, 29 Jan 2026 08:13:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUb0-0001KS-5o; Thu, 29 Jan 2026 11:10:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUar-0000i0-Kl for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:07 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUap-0006rD-FD for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:05 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4806fbc6bf3so12226455e9.2 for ; Thu, 29 Jan 2026 08:10:03 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.10.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:10:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769703002; x=1770307802; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=pWS8UbYXRtwCE4I3yw4CO/HHOucmFzMniAylHRoWl7w=; b=OZfDxyKlTT98jLOx/OkSZfAGmfsxVmFuY8S92t1Rp17W6imzUNL7CDSQYNafp+KNH3 77PCqfsARi4O9awQ/4+tKpnAzbh2jXbtgmGcLXFZsI/DSI8t8GbVsSSxVRAw/7i39x1a CtrFtQnLhvy5DI5tOmGT8/b+KIHPEaiitKlg4KPP9V9wkxrkg3hNriiH9Y4EWv1jnGez YPMDKsahqxCcEzzQz4fk7AouIVPZ3CADgYgdzOv12FJHIV+siHPm8OBfozVcv1uJc73u gb6QahYlWttqbxWOto5iZY6rgMji21fMf7B5t9TsOBooQEKCaqe/0o/1o1VNDpRemmc4 BYAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769703002; x=1770307802; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=pWS8UbYXRtwCE4I3yw4CO/HHOucmFzMniAylHRoWl7w=; b=IRTYBDqCgPAfqsiPDH/EKZYIxsYlrVdjmH05L0Uo9xC0fPkNFJBMGZVmxj4VTXYJDB qMedYcQy8hziGOKiBAMUmqN9FpDxNK8Qj2TgN/gb8ApBsLIji6i7kKtbih556MEPb9B5 aD/f4nGVRUMqWVU2SqTcBgqn+lqCqVnMjI1T9bgQT1l8SkpuwaB4FbQDkCoPyhStg5bX MrOVAiJxshZ+kXXNT7vXO9vB/ZTfKULKXt4LgMYfGOraYktROQFd+AIMR63v3eQH9AxP C3MD5yc7TeM1gfhTe2QR/ShWK7W7ZhFZPUMfYCfkRxwAW/CgCVG/VtbP1fvFz8SyDXYP +KqA== X-Gm-Message-State: AOJu0YxiYtuK0mNzUm0fZhdSk+kpdA9SQmHk8FQwBV3rTL/Gl9fmXZBQ GtwATssv3FxqNP59uzU7LrVDA6IzEONpZm4Hg1B9LFGOTicLT3Oe2Nrc9EuB9zxDFIiFIlGbGsP MkNEde0Q= X-Gm-Gg: AZuq6aKg9xyWLJNL01y/8LXwu3OGIyXowmeFE/TdAVmeDNQ2I+wSQhGaApZ9nIOT0zV 8FmpBYc842Ba0Y/1wVLBKojw3JnDhfVk7PKssPYK66DxIJtudJxBy50m7P4RfX9J4v70p4D3kta 5s2EZAZemZP1FfPhQSznEIgVCY1YMHOgjgq7tsWXRO252gQy3IAXGTEdObyUbXJ7kkuli/R+k6l A2bkBOEOg3s6Am8A9bSWHH8dzT3+WPVxygBc0MhJvhbc5gOQC8OYacaK/H+XWigB1Xk1MA3As9/ Vaec+6iAEn5F+wKrBecU8tsEgrhuQfPP0I7JZZQdReVRo7ZAabAkxaqArk7RVX+pSgQLuFYT6Oa MoouOP2bmyhw0OneBdz2Vl5RQW4az6+TrJHZF3k2MTK8GSEqE3Uet6ZHtjnHnQ2zHwMFoj0g1Fo friGC+SQAR/GqQsYHK2PM7xcB4KI9S9A== X-Received: by 2002:a05:600c:4e94:b0:477:639d:bca2 with SMTP id 5b1f17b1804b1-48069c0e146mr121154135e9.4.1769703001777; Thu, 29 Jan 2026 08:10:01 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/43] hw/vfio/pci: Synthesize PASID capability for vfio-pci devices Date: Thu, 29 Jan 2026 16:09:10 +0000 Message-ID: <20260129160917.1415092-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703224882154100 From: Shameer Kolothum Add support for synthesizing a PCIe PASID extended capability for vfio-pci devices when PASID is enabled via a vIOMMU and supported by the host IOMMU backend. PASID capability parameters are retrieved via IOMMUFD APIs and the capability is inserted into the PCIe extended capability list using the insertion helper. A new x-vpasid-cap-offset property allows explicit control over the placement; by default the capability is placed at the end of the PCIe extended configuration space. If the kernel does not expose PASID information or insertion fails, the device continues without PASID support. Reviewed-by: Jonathan Cameron Tested-by: Eric Auger Tested-by: Zhangfei Gao Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Shameer Kolothum Reviewed-by: Yi Liu Message-id: 20260126104342.253965-37-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/vfio/pci.c | 75 +++++++++++++++++++++++++++++++++++++++++ hw/vfio/pci.h | 1 + hw/vfio/trace-events | 1 + include/hw/core/iommu.h | 1 + 4 files changed, 78 insertions(+) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index c734472721..36d8fbe872 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -24,6 +24,7 @@ #include =20 #include "hw/core/hw-error.h" +#include "hw/core/iommu.h" #include "hw/pci/msi.h" #include "hw/pci/msix.h" #include "hw/pci/pci_bridge.h" @@ -2498,9 +2499,62 @@ static int vfio_setup_rebar_ecap(VFIOPCIDevice *vdev= , uint16_t pos) return 0; } =20 +/* + * Try to retrieve PASID capability information via IOMMUFD APIs and, + * if supported, synthesize a PASID PCIe extended capability for the + * VFIO device. + * + * Use user-specified PASID capability offset if provided, otherwise + * place it at the end of the PCIe extended configuration space. + */ +static bool vfio_pci_synthesize_pasid_cap(VFIOPCIDevice *vdev, Error **err= p) +{ + HostIOMMUDevice *hiod =3D vdev->vbasedev.hiod; + HostIOMMUDeviceClass *hiodc; + PasidInfo pasid_info; + PCIDevice *pdev =3D PCI_DEVICE(vdev); + uint16_t pasid_offset; + + if (!hiod) { + return true; + } + + hiodc =3D HOST_IOMMU_DEVICE_GET_CLASS(hiod); + if (!hiodc || !hiodc->get_pasid_info || + !hiodc->get_pasid_info(hiod, &pasid_info) || + !(pci_device_get_viommu_flags(pdev) & VIOMMU_FLAG_PASID_SUPPORTED)= ) { + return true; + } + + /* Use user-specified offset if set, otherwise place PASID at the end.= */ + if (vdev->vpasid_cap_offset) { + pasid_offset =3D vdev->vpasid_cap_offset; + } else { + pasid_offset =3D PCIE_CONFIG_SPACE_SIZE - PCI_EXT_CAP_PASID_SIZEOF; + } + + if (!pcie_insert_capability(pdev, PCI_EXT_CAP_ID_PASID, PCI_PASID_VER, + pasid_offset, PCI_EXT_CAP_PASID_SIZEOF)) { + error_setg(errp, "vfio: Placing PASID capability at offset 0x%x fa= iled", + pasid_offset); + return false; + } + trace_vfio_pci_synthesize_pasid_cap(vdev->vbasedev.name, pasid_offset); + + pcie_pasid_common_init(pdev, pasid_offset, pasid_info.max_pasid_log2, + pasid_info.exec_perm, pasid_info.priv_mod); + + /* PASID capability is fully emulated by QEMU */ + memset(vdev->emulated_config_bits + pdev->exp.pasid_cap, 0xff, + PCI_EXT_CAP_PASID_SIZEOF); + return true; +} + static void vfio_add_ext_cap(VFIOPCIDevice *vdev) { PCIDevice *pdev =3D PCI_DEVICE(vdev); + bool pasid_cap_added =3D false; + Error *err =3D NULL; uint32_t header; uint16_t cap_id, next, size; uint8_t cap_ver; @@ -2578,12 +2632,24 @@ static void vfio_add_ext_cap(VFIOPCIDevice *vdev) pcie_add_capability(pdev, cap_id, cap_ver, next, size); } break; + /* + * VFIO kernel does not expose the PASID CAP today. We may synthes= ize + * one later through IOMMUFD APIs. If VFIO ever starts exposing it, + * record its presence here so we do not create a duplicate CAP. + */ + case PCI_EXT_CAP_ID_PASID: + pasid_cap_added =3D true; + /* fallthrough */ default: pcie_add_capability(pdev, cap_id, cap_ver, next, size); } =20 } =20 + if (!pasid_cap_added && !vfio_pci_synthesize_pasid_cap(vdev, &err)) { + error_report_err(err); + } + /* Cleanup chain head ID if necessary */ if (pci_get_word(pdev->config + PCI_CONFIG_SPACE_SIZE) =3D=3D 0xFFFF) { pci_set_word(pdev->config + PCI_CONFIG_SPACE_SIZE, 0); @@ -3756,6 +3822,8 @@ static const Property vfio_pci_properties[] =3D { TYPE_IOMMUFD_BACKEND, IOMMUFDBackend *), #endif DEFINE_PROP_BOOL("skip-vsc-check", VFIOPCIDevice, skip_vsc_check, true= ), + DEFINE_PROP_UINT16("x-vpasid-cap-offset", VFIOPCIDevice, + vpasid_cap_offset, 0), }; =20 #ifdef CONFIG_IOMMUFD @@ -3913,6 +3981,13 @@ static void vfio_pci_class_init(ObjectClass *klass, = const void *data) "destination when doing live " "migration of device state via " "multifd channels"); + object_class_property_set_description(klass, /* 11.0 */ + "x-vpasid-cap-offset", + "PCIe extended configuration spa= ce offset at which to place a " + "synthetic PASID extended capabi= lity when PASID is enabled via " + "a vIOMMU. A value of 0 (default= ) places the capability at the " + "end of the extended configurati= on space. The offset must be " + "4-byte aligned and within the P= CIe extended configuration space"); } =20 static const TypeInfo vfio_pci_info =3D { diff --git a/hw/vfio/pci.h b/hw/vfio/pci.h index 0f78cf9cdb..d6495d7f29 100644 --- a/hw/vfio/pci.h +++ b/hw/vfio/pci.h @@ -187,6 +187,7 @@ struct VFIOPCIDevice { bool defer_kvm_irq_routing; bool clear_parent_atomics_on_exit; bool skip_vsc_check; + uint16_t vpasid_cap_offset; VFIODisplay *dpy; Notifier irqchip_change_notifier; VFIOPCICPR cpr; diff --git a/hw/vfio/trace-events b/hw/vfio/trace-events index 466695507b..846e3625c5 100644 --- a/hw/vfio/trace-events +++ b/hw/vfio/trace-events @@ -40,6 +40,7 @@ vfio_pci_hot_reset_result(const char *name, const char *r= esult) "%s hot reset: % vfio_pci_populate_device_config(const char *name, unsigned long size, unsi= gned long offset, unsigned long flags) "Device '%s' config: size: 0x%lx, of= fset: 0x%lx, flags: 0x%lx" vfio_pci_populate_device_get_irq_info_failure(const char *errstr) "VFIO_DE= VICE_GET_IRQ_INFO failure: %s" vfio_mdev(const char *name, bool is_mdev) " (%s) is_mdev %d" +vfio_pci_synthesize_pasid_cap(const char *name, uint16_t offset) "%s off= set: 0x%x" vfio_add_ext_cap_dropped(const char *name, uint16_t cap, uint16_t offset) = "%s 0x%x@0x%x" vfio_pci_reset(const char *name) " (%s)" vfio_pci_reset_flr(const char *name) "%s FLR/VFIO_DEVICE_RESET" diff --git a/include/hw/core/iommu.h b/include/hw/core/iommu.h index d5401a397b..86af315c15 100644 --- a/include/hw/core/iommu.h +++ b/include/hw/core/iommu.h @@ -20,6 +20,7 @@ enum viommu_flags { /* vIOMMU needs nesting parent HWPT to create nested HWPT */ VIOMMU_FLAG_WANT_NESTING_PARENT =3D BIT_ULL(0), + VIOMMU_FLAG_PASID_SUPPORTED =3D BIT_ULL(1), }; =20 /* Host IOMMU quirks. Extracted from host IOMMU capabilities */ --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703221; cv=none; d=zohomail.com; s=zohoarc; b=IRSiJoHuDiPYcPIw/LaGszGX+W7SAZ4XfQw+Ri0I45EPhBnm35pgrqSsfInvMdGPhCwaB+vwaMuoFIb68Ge5gr5q9AIK/CayxLp7Kieq88wnIghFNDLtbY0tK8f8aBNLBv8f/7x1v7+g1RInigUYHPLaKLxN1JkjsJrGjtKW+9k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703221; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=DUXXViwauWLkh3b067d+qkCc8ZKPqxtPhuKZgFQ3Zck=; b=gFaPqSPaQrLBDLrJJN7/LgbLAY7eThXJOhHu9YCchT2UJ3IZQpS1xksIlfDjhJWq1U+s64ZVPGxgAFaIQN8IkdkEVRkijrVrAdkufgN61Dbv/ln7260DM2isS9ptFV8PvU0XcbWaZsoUaRkYBaB6AR9RuvfEJOLHgNeB+MBJXt0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703221770378.8068808250355; Thu, 29 Jan 2026 08:13:41 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUb0-0001Ms-F0; Thu, 29 Jan 2026 11:10:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUat-0000ms-44 for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:07 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUaq-0006tm-Eh for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:06 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-42fb6ce71c7so1085748f8f.1 for ; Thu, 29 Jan 2026 08:10:03 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.10.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:10:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769703003; x=1770307803; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DUXXViwauWLkh3b067d+qkCc8ZKPqxtPhuKZgFQ3Zck=; b=wLRATYbCCU3cnYBik7NPC/wS4sEhdu26GdBCTycmXNsVlZmAbQoUpjPQRzp8SpP6zk Xhgu0X5PfI3HMVo4RPSPNTxgJAhdQfWB3OReb9tmeHFOUkXTVTD2sBVjNu350/2ROOFK Cb98xe9blK3rrx0eNAid82wvZ++znHg6yeeMJU78Gxe0OqlPL1yImNgdsPAV5yIHS9yk zzJW+uQ/poKweshP0gECsnlzrhO5SXB6myj8P6rVkeG95ZELAroLQv2Al4uGYc+oUXzx UQD3CJtsw66WlLnAUa2QAUCKwqdmQljLCIB+xUQZkRGdcR/NG4fVXqYA7nNLeK+cVwRr U6fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769703003; x=1770307803; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=DUXXViwauWLkh3b067d+qkCc8ZKPqxtPhuKZgFQ3Zck=; b=OsF1y60cEtxEXX2P4ELHWOVD2X9wg4MzuC5lsfLOCpFDwjhP6SaRFu01h0+2zLl94O 7qwtD1HEMPl8ru5Wazee4tXiCR6/bmYJdNjxWpMyLCCiYQ+2TH74UjNPw3nB/uhIhV7b vu7ylCDrP54oE3c+TffXsvN0I+FeqYmKzNe93KSS04gf+J+DMkruG5oHgsVDBDtfO6mx 30S6VCwAxdRM2yHjYQf7dpkdfCngiFaVim9Qu3Z9nm/rVe9HO5tt0LFmZXTHjnIXZzCh r9R+mkbpmJ2BvODYIvXzRoAXRyQESZV4UV7RRYANjBh6O2m0nsk2ACJTZQAVNRWoy7nj Kzsg== X-Gm-Message-State: AOJu0Yyxhe138Cvn7leSWGBrMvwesExk4ukgZ9MXgCSzPYOTskpfPxKV DizL4TCRIiGT1TXbtQg0GwryhPSwt3Zs3/+an3yZcnAu3UwKFcsbPL6J/EhrNsggLwRAjbCr9mY zwoo/BNU= X-Gm-Gg: AZuq6aJtWDfa3btKaqXqrLtT0GZy6yimo2ImLdbN0/XsrRZTugb8Fxislt3JfFMsMpg CwpzGR6qatoy4vwGqKYFXAFh4MUKiDTUxVRVY3FgVY4i7FcgOl23Rod+Am6HPq1DMA1mVzoHUn6 NYxpH2TsXYWCb0T3ruoR3ebvnMjtprsnr6F3fv0ib4oydW820xfWEwGQ5rzeggxPqJJ7kZnte6L dVmB6jwCcazPmooaN3Heqs4nYcrGViIO+1V1VCJDP9cgix6cPymcByNF8DHo86cGEztHhycLN1W CU3L1r1P11av0miCpZxQXxdXi36SAMhhCQXCiOqxrtQMiVpuuBQ/hCPK+zS9ySiKmoJhxXDd+pP r3ZOid5U0gTmnmdxPulzQfGuwBbVhIRQkIyi/qF3zf8xk2MsgO06/f51v5eV0kk5sbiH9qKia3l gxepjmB2hhMzzI0TCCqVwg/6mZXAD5JA== X-Received: by 2002:a05:6000:2004:b0:430:f9c2:8500 with SMTP id ffacd0b85a97d-435f3aae815mr144730f8f.43.1769703002868; Thu, 29 Jan 2026 08:10:02 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/43] hw/arm/smmuv3-accel: Make SubstreamID support configurable Date: Thu, 29 Jan 2026 16:09:11 +0000 Message-ID: <20260129160917.1415092-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703223829158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum QEMU SMMUv3 currently reports no SubstreamID support, forcing SSID to zero. This prevents accelerated use cases such as Shared Virtual Addressing (SVA), which require multiple Stage-1 context descriptors indexed by SubstreamID. Add a new "ssidsize" property to explicitly configure the number of bits used for SubstreamIDs. A value greater than zero enables SubstreamID support and advertises PASID capability to the vIOMMU. The requested SSIDSIZE is validated against host SMMUv3 capabilities and is only supported when accel=3Don. Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Tested-by: Eric Auger Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-38-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 25 ++++++++++++++++++++++++- hw/arm/smmuv3.c | 22 ++++++++++++++++++++-- include/hw/arm/smmuv3-common.h | 1 + include/hw/arm/smmuv3.h | 1 + 4 files changed, 46 insertions(+), 3 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 342944da23..f5cd4df336 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -76,6 +76,16 @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s, return false; } =20 + /* Check SSIDSIZE value opted-in is compatible with Host SMMUv3 SSIDSI= ZE */ + if (FIELD_EX32(info->idr[1], IDR1, SSIDSIZE) < + FIELD_EX32(s->idr[1], IDR1, SSIDSIZE)) { + error_setg(errp, "Host SMMUv3 SSIDSIZE not compatible " + "(host=3D%u, QEMU=3D%u)", + FIELD_EX32(info->idr[1], IDR1, SSIDSIZE), + FIELD_EX32(s->idr[1], IDR1, SSIDSIZE)); + return false; + } + /* User can disable QEMU SMMUv3 Range Invalidation support */ if (FIELD_EX32(info->idr[3], IDR3, RIL) < FIELD_EX32(s->idr[3], IDR3, RIL)) { @@ -652,7 +662,14 @@ static uint64_t smmuv3_accel_get_viommu_flags(void *op= aque) * The real HW nested support should be reported from host SMMUv3 and = if * it doesn't, the nesting parent allocation will fail anyway in VFIO = core. */ - return VIOMMU_FLAG_WANT_NESTING_PARENT; + uint64_t flags =3D VIOMMU_FLAG_WANT_NESTING_PARENT; + SMMUState *bs =3D opaque; + SMMUv3State *s =3D ARM_SMMUV3(bs); + + if (s->ssidsize) { + flags |=3D VIOMMU_FLAG_PASID_SUPPORTED; + } + return flags; } =20 static const PCIIOMMUOps smmuv3_accel_ops =3D { @@ -680,6 +697,12 @@ void smmuv3_accel_idr_override(SMMUv3State *s) if (s->oas =3D=3D SMMU_OAS_48BIT) { s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS_48); } + + /* + * By default QEMU SMMUv3 has no SubstreamID support. Update IDR1 if u= ser + * has enabled it. + */ + s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, s->ssidsize); } =20 /* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index cb02184d2d..c08d58c579 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -611,9 +611,11 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cf= g, } } =20 - if (STE_S1CDMAX(ste) !=3D 0) { + /* Multiple context descriptors require SubstreamID support */ + if (!s->ssidsize && STE_S1CDMAX(ste) !=3D 0) { qemu_log_mask(LOG_UNIMP, - "SMMUv3 does not support multiple context descriptor= s yet\n"); + "SMMUv3: multiple S1 context descriptors require Substream= ID support. " + "Configure ssidsize > 0 (requires accel=3Don)\n"); goto bad_ste; } =20 @@ -1954,6 +1956,10 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "OAS must be 44 bits when accel=3Doff"); return false; } + if (s->ssidsize) { + error_setg(errp, "ssidsize can only be set if accel=3Don"); + return false; + } return true; } =20 @@ -1968,6 +1974,11 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "OAS can only be set to 44 or 48 bits"); return false; } + if (s->ssidsize > SMMU_SSID_MAX_BITS) { + error_setg(errp, "ssidsize must be in the range 0 to %d", + SMMU_SSID_MAX_BITS); + return false; + } =20 return true; } @@ -2096,6 +2107,7 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), + DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2129,6 +2141,12 @@ static void smmuv3_class_init(ObjectClass *klass, co= nst void *data) object_class_property_set_description(klass, "oas", "Specify Output Address Size (for accel=3Don). Supported values " "are 44 or 48 bits. Defaults to 44 bits"); + object_class_property_set_description(klass, "ssidsize", + "Number of bits used to represent SubstreamIDs (SSIDs). " + "A value of N allows SSIDs in the range [0 .. 2^N - 1]. " + "Valid range is 0-20, where 0 disables SubstreamID support. " + "Defaults to 0. A value greater than 0 is required to enable " + "PASID support."); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h index abe3565357..67a23fbeaa 100644 --- a/include/hw/arm/smmuv3-common.h +++ b/include/hw/arm/smmuv3-common.h @@ -311,6 +311,7 @@ REG32(IDR1, 0x4) FIELD(IDR1, TABLES_PRESET, 30, 1) FIELD(IDR1, ECMDQ, 31, 1) =20 +#define SMMU_SSID_MAX_BITS 20 #define SMMU_IDR1_SIDSIZE 16 #define SMMU_CMDQS 19 #define SMMU_EVENTQS 19 diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index d488a39cd0..26b2fc42fd 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -72,6 +72,7 @@ struct SMMUv3State { bool ril; bool ats; uint8_t oas; + uint8_t ssidsize; }; =20 typedef enum { --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703107; cv=none; d=zohomail.com; s=zohoarc; b=geRWLA5hIn01DDu8k+/GNO3UpLLG0fbIKQYY68+zmkmeve/FqxvspllVu6iMNjqChEnQWS+PJ/oSfHfO8dEj1qVSFxkMOtSL+KqJVJwxHImFZfdATv2Xg3r01QbaOk5o/2uP4qWO9RERUibzN12Ub1KfzFOMQn4dNX7vaPjQL/A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703107; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=iDghPW5CxBXO9mC8DhlYzxtsMzpsZXCT4re3Q+rFilk=; b=RgW1AU2ejL2z5kk3bVclQTlDGcU8AGAlNgz5WP7iD2msXFQ8lsTP/hkHcVryactGgfU/4oLFw+cFSru8TtxaNnIwmx24IF8FIhEhG7UFDO5wUc1Dw6eqjfjdal1PXyqQs1PZIAc/jymqHnmaJku8yoXKByBBoUesiK+c7z2e8zk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703107673259.37571560723177; Thu, 29 Jan 2026 08:11:47 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUaw-00017a-HY; Thu, 29 Jan 2026 11:10:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUat-0000p5-Lg for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:07 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUar-00074g-P9 for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:07 -0500 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-42fbc305552so1139943f8f.0 for ; Thu, 29 Jan 2026 08:10:05 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.10.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:10:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769703004; x=1770307804; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=iDghPW5CxBXO9mC8DhlYzxtsMzpsZXCT4re3Q+rFilk=; b=rjSc977exSI85yvG6YiLTsfVHaOB0Lcl08lYehocANIP/oi4ZS5vrXwIUG/DQzSepV rKflxrWbPEiYGreoBdncw4IjLFdOhO8SewnQ/D8Iwok8aGbX74NgaOg1OfwQm+1Hw7pK fiN8D3xJl8AIl1UlzY4eiaiiolqYlV6NcIoCTLDYsVT8ag7eI8lrwCfX3vjsY5LVDAlF S6y5oYezrwddCQvW5+i9x/Pfcf5lxw7R7TNH41eC9UZFJXhdIBXFfVcIO437+7YVmKxM dEcCgdYNPt4ESNMcvy419VAl1h633HrIqKWOz5SSvsUASlbdy2C5sbqcFZj2Jyzn/aOY MEoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769703004; x=1770307804; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=iDghPW5CxBXO9mC8DhlYzxtsMzpsZXCT4re3Q+rFilk=; b=hpIEFWREkBMbdWj/N56VKGq6ZrkDOYpUdGXFibtIRp+qumNLsF3I7rURHNflPiMMeK I+eVZTVyS380NW+nOts9cctoMinD9TuxnL6TYTr5T+05PsOkbetNFuwmawZzKFXPPgU+ dK3qb10yRjrDlQ9NzxTbjCnE95YRNgV52+B+KHLZKx/wu81nx1O+dpBG/WKldsCqb77M FGPwZYiNVoKQiU2klifWj8EATMx5d0PG60I5lb4dkrc11cIVH3D2nCYfRpybslNKvkw2 0kTckleE8hgmj4RcnWxwwsJS5oxJav8C6AyF5/CNuPWAyvxQ/vXW+THKhFjKE3wLrnP4 6JbQ== X-Gm-Message-State: AOJu0Yxg9gb7jPAykAPj62SkoSQkhrX/p0I0GqphhAvjgEZ4t8kMbbZs zZVDKOPG0BEfLvT8MKTxUAGXApUHaIPkjXdjlX+R/+Fka8jNeccX+SZgrj7N5j8i0stNKZCI7+J wf9kfetM= X-Gm-Gg: AZuq6aLwCd+o31eRYzjW+ROhpTj1qvu9key91SbsNchzkV8LzkpUq15YSW5cUSOTjlV z1eqNASJTKrBZiwYnBFTFEGUn6eI6ME4H+yfbldE82Dk2xptWOogPWuOo5bBuoNUYsB0AH2LUi1 mdwAqxqmhl4Asa9LZKF6lIbpGDtxoA4GwlX8B68fiOV6NDxMQAXAnCFu94vTB+SbzPNcCmR4lzg D+iYeTe8IQEFta3pneI6RSLWUkCWsDsuWiwUypvP+JeKqJRH3kzTb/6WT/rulXD3QebZyrB/cjW V4JtaDFeXJgGDjyUN0wHUDQvI+CeoHu4OcL1Bivfv+GHmmzN1dVGFAHtbyplFJLxTggQmMC4QSp nYFjOU9MuDKSjvsP71XSLMWerDhyPnytxsh/Bc1JXcwUmnLZYhnrKkuEzfdot0aBj6GD+slgzFn ZsLLUyTkWa+CcnE9hxXG99pacWUxKopzuV9xBggO/d X-Received: by 2002:a05:6000:310c:b0:435:9770:9ec8 with SMTP id ffacd0b85a97d-435f3aa9ec7mr154863f8f.32.1769703004022; Thu, 29 Jan 2026 08:10:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/43] target/arm/hvf: Move hvf_sysreg_[read, write]_cp() functions around Date: Thu, 29 Jan 2026 16:09:12 +0000 Message-ID: <20260129160917.1415092-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703109238158500 From: Philippe Mathieu-Daud=C3=A9 Next commit will use these functions prototype earlier. Rather than forward-declaring them, move them around. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Akihiko Odaki Message-id: 20260118215945.46693-2-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 142 +++++++++++++++++++++---------------------- 1 file changed, 71 insertions(+), 71 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index e4c0d936f1..fcb7fa3b30 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -423,6 +423,77 @@ static const hv_sys_reg_t hvf_sreg_list[] =3D { =20 #undef DEF_SYSREG =20 +static uint32_t hvf_reg2cp_reg(uint32_t reg) +{ + return ENCODE_AA64_CP_REG((reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, + (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK, + (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, + (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, + (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK); +} + +static bool hvf_sysreg_read_cp(CPUState *cpu, const char *cpname, + uint32_t reg, uint64_t *val) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + const ARMCPRegInfo *ri; + + ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); + if (ri) { + if (!cp_access_ok(1, ri, true)) { + return false; + } + if (ri->accessfn) { + if (ri->accessfn(env, ri, true) !=3D CP_ACCESS_OK) { + return false; + } + } + if (ri->type & ARM_CP_CONST) { + *val =3D ri->resetvalue; + } else if (ri->readfn) { + *val =3D ri->readfn(env, ri); + } else { + *val =3D raw_read(env, ri); + } + trace_hvf_emu_reginfo_read(cpname, ri->name, *val); + return true; + } + + return false; +} + +static bool hvf_sysreg_write_cp(CPUState *cpu, const char *cpname, + uint32_t reg, uint64_t val) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + const ARMCPRegInfo *ri; + + ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); + + if (ri) { + if (!cp_access_ok(1, ri, false)) { + return false; + } + if (ri->accessfn) { + if (ri->accessfn(env, ri, false) !=3D CP_ACCESS_OK) { + return false; + } + } + if (ri->writefn) { + ri->writefn(env, ri, val); + } else { + raw_write(env, ri, val); + } + + trace_hvf_emu_reginfo_write(cpname, ri->name, val); + return true; + } + + return false; +} + int hvf_arch_get_registers(CPUState *cpu) { ARMCPU *arm_cpu =3D ARM_CPU(cpu); @@ -1161,46 +1232,6 @@ static bool is_id_sysreg(uint32_t reg) SYSREG_CRM(reg) < 8; } =20 -static uint32_t hvf_reg2cp_reg(uint32_t reg) -{ - return ENCODE_AA64_CP_REG((reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, - (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK, - (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, - (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, - (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK); -} - -static bool hvf_sysreg_read_cp(CPUState *cpu, const char *cpname, - uint32_t reg, uint64_t *val) -{ - ARMCPU *arm_cpu =3D ARM_CPU(cpu); - CPUARMState *env =3D &arm_cpu->env; - const ARMCPRegInfo *ri; - - ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); - if (ri) { - if (!cp_access_ok(1, ri, true)) { - return false; - } - if (ri->accessfn) { - if (ri->accessfn(env, ri, true) !=3D CP_ACCESS_OK) { - return false; - } - } - if (ri->type & ARM_CP_CONST) { - *val =3D ri->resetvalue; - } else if (ri->readfn) { - *val =3D ri->readfn(env, ri); - } else { - *val =3D raw_read(env, ri); - } - trace_hvf_emu_reginfo_read(cpname, ri->name, *val); - return true; - } - - return false; -} - static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint64_t *val) { ARMCPU *arm_cpu =3D ARM_CPU(cpu); @@ -1454,37 +1485,6 @@ static void pmswinc_write(CPUARMState *env, uint64_t= value) } } =20 -static bool hvf_sysreg_write_cp(CPUState *cpu, const char *cpname, - uint32_t reg, uint64_t val) -{ - ARMCPU *arm_cpu =3D ARM_CPU(cpu); - CPUARMState *env =3D &arm_cpu->env; - const ARMCPRegInfo *ri; - - ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); - - if (ri) { - if (!cp_access_ok(1, ri, false)) { - return false; - } - if (ri->accessfn) { - if (ri->accessfn(env, ri, false) !=3D CP_ACCESS_OK) { - return false; - } - } - if (ri->writefn) { - ri->writefn(env, ri, val); - } else { - raw_write(env, ri, val); - } - - trace_hvf_emu_reginfo_write(cpname, ri->name, val); - return true; - } - - return false; -} - static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) { ARMCPU *arm_cpu =3D ARM_CPU(cpu); --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703270; cv=none; d=zohomail.com; s=zohoarc; b=FIScoGEdIKFtuQhm+BT5hqa3eZ3WZpT+SWUbLEMdQQS3YmEjUbTKgxLQlUo8efYnrIwXpV7BtK9VjOsRjexJF3+rZ15FLLmBHsXtWKVybmzXLjqK9VrruKGrmj2eJqUIrncCQc4oR/FSjO14zlsJ7iZsy6olnWCk19qmFNCQTCE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703270; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=VWa2vbvC4oNt+Jo6t0zGuSn96CV4yI+L2pkpAeUn8YY=; b=AUOh2/hJ1xhtxV6lxZ97Hcavh/VYcsUz/Gisceduc40izwh7k0oWMlA+u/dhCJOfEivjLQuO0rgK4FwlMFMKr+CdqlpXRA4zpFIg4SyOdtPr85RRX7gTfnP0hg4sXhr1ws+dqFgqi8X1V1W1fzjaL88/3yR35ZlZ7NmwcSnYdc0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703270952660.5680390672509; Thu, 29 Jan 2026 08:14:30 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUb1-0001TC-IO; Thu, 29 Jan 2026 11:10:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUau-0000xF-Me for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:08 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUas-00075F-Vi for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:08 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-42fb2314f52so733451f8f.0 for ; Thu, 29 Jan 2026 08:10:06 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.10.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:10:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769703005; x=1770307805; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VWa2vbvC4oNt+Jo6t0zGuSn96CV4yI+L2pkpAeUn8YY=; b=gKVW7aRHjq2x2X+cjjX+2tP4aIVruoGl7CCfwptp+lycEFV+OcnHB+smewLF58Aa9T Rhnf7KtsRzHHxacUgtTZJac4uv0Cp+Epz5M66bqDg4avdXDaAwaHzqmnXgtxoS5JbZ9I tuuetnHKJmPPikNc1I1xbB0QkHqsHeFUrC4DkqzDEVu/+7qepFe93Zz1viD57iaZAZms NffyHdy5nYe20zgyDG0Ch6BQk8a3eRYstcIRsGq+RrmJeNVF5r4nevy6tC7F/Y+FKG5a t9Ey51Iyq8svX6hxqSwNZ/7qgokj8qfm6nCduxAlYqKp2wgvyfVRX6S0YxCsBw6ZqhpW q6FQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769703005; x=1770307805; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=VWa2vbvC4oNt+Jo6t0zGuSn96CV4yI+L2pkpAeUn8YY=; b=SxWZjCbIwA4373ELepcKmMoX528cdBEl0lZXQvY81m+M/jkKalMqxfCJum5NOSKN18 AFUA7mqhzAc981SNT5zxBHXQfKQJi6UeU0ipb5p9PWA7ntNzGOsPKGMZleGb60QewRtp XZ4me/cezi/n3DYpvDw4O5vSg7cAD4ePObOaTO1SUEPwo74HmMBp/b2M8cEbFOKTrfMI sPU7HcYdPoO3t20s//Ylb1W9yJ3rSZzmy9GsYC0a30mbhmdfGHoO07tOQ5BqLCrTLCnU gBoJnwRsa0/iUw0o/ACo1cngu6/A/eLrnpolS5eobNEH0qB/6my5D1BR3yTcuwtNk65I dKEw== X-Gm-Message-State: AOJu0Yx59ciXrYi4qS0EGNdnavDrj7ax5pCb5rSlL3tzwOgiHQaAc21m lCdZly0SKN+iv4lRcg+DhMEcVY5zncJRHOOVWkWdSx/s52boZevBNBcKuRDnu/BgtXPxoy1Y6Mp nEn+AFvA= X-Gm-Gg: AZuq6aJPqrmB42j0/4xA23JnYujFaKO43yK1hRNZXla3mn08P1A4hv3hlJ86CwLiyVY qKP8WQ6dZTZHzb3xBEY6OOGLkXBUkVMOX5teea/VIRCln5qBoe+XKDJ1hXz8wrVf0uE+CMy3xBQ 07NVf+Qxf3aAOk68PkSXAEvR0YGirufphwQHbB8S00cWFJvEbGNTiIyIiEnitBKcvg7BZf/YCS/ bO3sYjacfiFfhuuD2Tn/AFHK17mPEKmZVCZRaIL7kdN8/JBGnE7HvDij2ppEmc+SNC4hZ9ixKzt 0cki0J/CopfQelBHhMJMTkXzztGw0WwmKZXdo5HELaCiSQINq3uRUDyN5CvUaO834s9frymfnW2 maxno5MrKpqm1QK9AviDZhFQZn6Z9jKNNAQqModYX4AvQLnOf26mv9sQ/stDHR14SjlpKNcI7Hm 0PH9BA6uoh9HFAOcgsFL2XjmjuAiITuA== X-Received: by 2002:a05:6000:3103:b0:435:dbbe:1130 with SMTP id ffacd0b85a97d-435f3a6ca95mr206198f8f.11.1769703005251; Thu, 29 Jan 2026 08:10:05 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/43] target/arm/hvf: Sync CNTV_CTL_EL0 & CNTV_CVAL_EL0 Date: Thu, 29 Jan 2026 16:09:13 +0000 Message-ID: <20260129160917.1415092-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703272026158500 From: Philippe Mathieu-Daud=C3=A9 Keep CNTV_CTL_EL0 and CNTV_CVAL_EL0 synchronized with the host hardware accelerator. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Akihiko Odaki Message-id: 20260118215945.46693-3-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index fcb7fa3b30..9ce720793d 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -200,6 +200,9 @@ void hvf_arm_init_debug(void) #define SYSREG_PMCEID0_EL0 SYSREG(3, 3, 9, 12, 6) #define SYSREG_PMCEID1_EL0 SYSREG(3, 3, 9, 12, 7) #define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0) + +#define SYSREG_CNTV_CTL_EL0 SYSREG(3, 3, 14, 3, 1) +#define SYSREG_CNTV_CVAL_EL0 SYSREG(3, 3, 14, 3, 2) #define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7) =20 #define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 12, 8, 4) @@ -502,6 +505,7 @@ int hvf_arch_get_registers(CPUState *cpu) uint64_t val; hv_simd_fp_uchar16_t fpval; int i, n; + bool b; =20 for (i =3D 0; i < ARRAY_SIZE(hvf_reg_match); i++) { ret =3D hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val= ); @@ -631,6 +635,16 @@ int hvf_arch_get_registers(CPUState *cpu) =20 aarch64_restore_sp(env, arm_current_el(env)); =20 + ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CVAL_EL0, = &val); + assert_hvf_ok(ret); + b =3D hvf_sysreg_write_cp(cpu, "VTimer", SYSREG_CNTV_CVAL_EL0, val); + assert(b); + + ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &= val); + assert_hvf_ok(ret); + b =3D hvf_sysreg_write_cp(cpu, "VTimer", SYSREG_CNTV_CTL_EL0, val); + assert(b); + return 0; } =20 @@ -642,6 +656,7 @@ int hvf_arch_put_registers(CPUState *cpu) uint64_t val; hv_simd_fp_uchar16_t fpval; int i, n; + bool b; =20 for (i =3D 0; i < ARRAY_SIZE(hvf_reg_match); i++) { val =3D *(uint64_t *)((void *)env + hvf_reg_match[i].offset); @@ -756,6 +771,16 @@ int hvf_arch_put_registers(CPUState *cpu) ret =3D hv_vcpu_set_vtimer_offset(cpu->accel->fd, hvf_state->vtimer_of= fset); assert_hvf_ok(ret); =20 + b =3D hvf_sysreg_read_cp(cpu, "VTimer", SYSREG_CNTV_CVAL_EL0, &val); + assert(b); + ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CVAL_EL0, = val); + assert_hvf_ok(ret); + + b =3D hvf_sysreg_read_cp(cpu, "VTimer", SYSREG_CNTV_CTL_EL0, &val); + assert(b); + ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, v= al); + assert_hvf_ok(ret); + return 0; } =20 --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703089; cv=none; d=zohomail.com; s=zohoarc; b=DHHf+Dq3yAhEuVvN7HEacmkv13INUcw0DV7bM5kXBXga6EijiTx2epF+P3xz5PwKzL2jhrMmmaThJC4rcPpGKt0aHHK38UaZHxLwYv9Omj8ITa50OxnJO+QZPc4c070FOVvQGw2jrwEGK5oklEelmfvz4ZGdnasjPYgMCDdThvg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703089; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=3Ho/I25FOA6chejNv9Tw0n7zZKd605wODU6AjbZ1BZA=; b=VdKpvurHipSlro8wFkWKo2OliPWc5VXmO/YIs2FlestHKBF6IKjV2LKI1xt97oTK+LcVkCuOYh+Xf9cFfDwyaBhgbgmnfmAedC72Zr4Mw72vbS5FDSw4Awk7KcW0QB9sEG/O9VPx5jIvFq8Ulpw2HnBrpQrMIMKkmh896SXv67g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703089458455.9385483468243; Thu, 29 Jan 2026 08:11:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUbN-0002Vj-Pw; Thu, 29 Jan 2026 11:10:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUav-00011b-GI for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:09 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUat-00075r-Sk for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:09 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-47edd6111b4so12005095e9.1 for ; Thu, 29 Jan 2026 08:10:07 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.10.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:10:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769703006; x=1770307806; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3Ho/I25FOA6chejNv9Tw0n7zZKd605wODU6AjbZ1BZA=; b=Cs6tyMRaVsGVWry+40QdAaAtJ5WqPURp+3aMOD0xqVq6Zj77YceLead+uxXIE374iL pLJc9tsUxvqTRlUx+PMTvWCqSHRlXagHkQ9y3p4Bc5S5SdEJpZgxarfRckpHCM/4giIU qgc7ilYI0TJgRX+ONE3oUvx19hJlUs1J+VryhgqNkl3zGgtgVdhr4ZGI0Di5TbLGRoqR TQBlZx/S2/R7KTqsth/2lE2bZZkWDCEU8QzpEC6kEPGYF1cbDClqftWJPI7fYiU57Zkw +A1MqHOwejkVjcHqafqy5Wbh63ZUW7VUuKoKcaVX8KHtPV4MDVBN+Ihi+20k6Kcl1tqD fCMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769703006; x=1770307806; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=3Ho/I25FOA6chejNv9Tw0n7zZKd605wODU6AjbZ1BZA=; b=Jr4Wp0HCfHTiHLK0jlz5OHR2U+LSx2fzREjjHV4fh2ACOeBPiOmK7IzoKxNXsu3df7 3baBX/fRlAeCv+tIqGJFT03IJXbENXPfgStQ2fekKJE0DKNFZnE4qAHGHyFrCagssICc FrHevRpClNdAP/jX/14tGLSVlJY4kone5QmYV4qskBl59NCA2lhw5JpWT3f5ujzcmjmy 105Ksoir8u4G4lhaEuoi2QHzy2wDkR2w/JOHSJiNgsztb7dV5BMEFworNB5GaPblAtXf gnHk2Fq19kuRcilEiRC8KTrb0wvgCWrM7oJL6r04ouJ5aLG8AKCfDIx4xk5/R2PZSGIj eliQ== X-Gm-Message-State: AOJu0YwQy8pZiivG5xsvB5mklww2zU/h3tmVAm3ayjMTVZ6kDL6iL+EX AeKkHOC9Z7G4ENnahZppS7U2L7gnBb8/TmMqQyT9h3aM1xtROYF4KCojeeeponK8s4MSKFQ7PUM GiRhCNIE= X-Gm-Gg: AZuq6aKY0oTKRXXWWvvfefBtVxKMqSmLo3yVsK5nDa4Zop+MtCqKy/URii2CeRUGm53 UiaqZwl/R+/0tnGGuINv30+Th7o42WKjurwOhcCAXy+m67XDE0J4gOS2f/7gfdwt7XTV047g2Rb EMfgi7jwexLk5YuaDZYpnY3ZHMi9+gVI9T1v/K/0VXgairH/HbjI7imkJGCVoy9cpVjwP/7qr/D oS1vMb0PgOgNGuFHsnC5LbN/NFj8U/rU1Y8NJfCDgFHN7MEBY4FO61X6v21dAPU0/pabwA5cNw1 TFy6C3hU5CChnuXu3GXvrJ88kOXPkZhMEoOkm8nWx0KTB7akerKDc9azZdoyRFIla3GGUhF5xfr fjynUPT9u7+OCJHCDf2nvwLZyswhd1ZoKUyKiF5MrdUp97zKC37Ny55dii3TZAGEDCpvJfT1Gbf aGlM+wIE08SBAOwjZV2pk3tOsDrscBww== X-Received: by 2002:a05:6000:420d:b0:427:526:16aa with SMTP id ffacd0b85a97d-435f3aba02dmr140492f8f.58.1769703006289; Thu, 29 Jan 2026 08:10:06 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/43] MAINTAINERS: add emulation.rst to ARM TCG CPUs Date: Thu, 29 Jan 2026 16:09:14 +0000 Message-ID: <20260129160917.1415092-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703090807154100 From: Alex Benn=C3=A9e This is updated as Arm architectural features are added so we should catch changes to the docs as well. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Pierrick Bouvier Message-id: 20260127145928.3073826-1-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index dccdf47888..9b7ed4fccb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -213,6 +213,7 @@ F: hw/cpu/a*mpcore.c F: include/hw/cpu/a*mpcore.h F: docs/system/target-arm.rst F: docs/system/arm/cpu-features.rst +F: docs/system/arm/emulation.rst F: gdb-xml/arm*.xml F: gdb-xml/aarch64*.xml =20 --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703105; cv=none; d=zohomail.com; s=zohoarc; b=lJKYD6XQlzwn/zqxN2qmt8leihqVj2K+xZ+6j47I9X58PSrIN9RBfdkJAxd9PVpMm0hlX1Yk4cjb92kTXUxvxZT2rHghFaAQyQcAEJC0d2Som+U9ziLyprqioM8Z3invaQqoN5mS8R2+uy9xO8QOVw3jbPwUxyyqLx5YGXROuo4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703105; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=DYhBXb9tZ9nUut1dqHb9Y0oo8fziSVA1dkINPePndao=; b=X+z15s2o5ICB3zHH+F1GJSLZ7k6Fut+cxAiNNK+izc8qFSDMwYOMzzQjRZzIigzxVA3+2/lPVKoXF6YfUzA2MlZFrA8bH5ZhqA6DE+oueN2Hf32m2QGx0T6c06nybCALQdnKp8qSrYcCow1oneE/PBgmqQ1txBPJFijRC/g5ny8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703105508448.3008036158759; Thu, 29 Jan 2026 08:11:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUbN-0002Ok-Ly; Thu, 29 Jan 2026 11:10:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUaw-00017X-EH for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:10 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUau-00076I-OD for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:10 -0500 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-42fb5810d39so843289f8f.2 for ; Thu, 29 Jan 2026 08:10:08 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.10.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:10:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769703007; x=1770307807; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DYhBXb9tZ9nUut1dqHb9Y0oo8fziSVA1dkINPePndao=; b=vx5FKgxXZOxcFEXBLQ7xGgGLpIbhJLmXeOG3xQeK325193FmDXWch3RZlQ7yes83sO 9dDOqF7cXtc2m0PldMLy6JLIM8g0qZeLvHLCQeT4i9OeUcoE8caJB5rzMHBlZUJlCoVV YOStByVLv/ptqGjy632zZFdRxZrjlj6M9diHQYY0RidECndQkkHQ9pGxP7qIh893dF+K U2gmykdZEBslNsE8w7HyM3/TYl60tnFegTDajt75qnQlJ0MPs8SBUvH+IwpEnkJZBvf1 oxvXTn/ALnZh7FNd1hFgpr5XnT1bdGPWEr5/J9hMV6ae8LTl/CzsPz33Xz1ka3E+1/ob mRVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769703007; x=1770307807; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=DYhBXb9tZ9nUut1dqHb9Y0oo8fziSVA1dkINPePndao=; b=IXI4yLo/A1H0R3WKI9eI16qJmB8TS8nG1Bc5GmMsvTnF1KawUiQC9SgPDiGiB2XyFI roQQ8azSdkS551aWjM/Trtrzj0FnufkbbxCii8YEOrvOHvCBlYAJUEqCrm5XDApylmYu JtIsavqyXblTKAnYWs8a9kn36nHrZZt4O5L5fEolLOPdIEMYD2u4m1NsXeCNwnfBkHCG wnrZ2bcPQlKbmChHoYy1wCfcp8v6vU3Afsa+pOWvjatm7a3abll9PRI9O+gnMSTFXHrw kWwyY+4AvZDz9UcmkLfBMJ2cy+qTWAE+CebnQtBJGVgAQ5zCYGLPN1QzAP23SypzDl6N LkNQ== X-Gm-Message-State: AOJu0YxaYaB0ox5q5oXgPp0y+JLi6KGJ2r+ua/lRbLl6Rn3lXQ58TqeU dxXdROfWtl33uT+Y+P1b/+V2u6ftWlLX03vW4zwxqBRIfvNfxCe5dX577upse02qQWP7jIYimDS eK4gGZuM= X-Gm-Gg: AZuq6aIsrrE3Ckl5+UgcdMWKT+Sx5w/4SrLOqsLyK+FNqjyhE186SIVDR3wLhlDDVCJ pMjky6M8/nDry+W0VjmAaeqIhfmfvAFHJFPt9cDCS2QJWLO9yl9cFqhtqWhOc/9XZ2Zvlmf1IYM wvZxQmFz2GOoXfl17mUUK/fD4dTG2DrR3J5V3hd/jn9AD0TnwPzPQ2byGObWYOUmhKpddEUbthw QLStpoWhJ5ie74chSIGdf0GWKfblhDo7uBaOSoLlFYyT1RbsqBnakN9f75gOO7q59fnlvc1nDka HR5tclStCtCzUHGXxsni3xP7HQ8hIUnVpNg/nkjbUinFroCdSNIBGxps6+XluO7AuCgwvJ1gado nuolHiGSsssuwyWwX5BDV8SbsoHol/AGpyyMbDDDR2jaojr3A4uL4bnW09iTqRZQczbIPi9CSie E9U5fXgGuQKxWqXLU9+EKs/slonB15CA== X-Received: by 2002:a5d:5d84:0:b0:435:6c8d:d017 with SMTP id ffacd0b85a97d-435f3aa8ff7mr149019f8f.32.1769703007237; Thu, 29 Jan 2026 08:10:07 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 41/43] docs/system: update FEAT_BBML[12] references Date: Thu, 29 Jan 2026 16:09:15 +0000 Message-ID: <20260129160917.1415092-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703107090158500 From: Alex Benn=C3=A9e It looks like the features were renamed to include the levels at some point. To make it easier to match features up to the Arm ARM update to use the full name. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Pierrick Bouvier --- docs/system/arm/emulation.rst | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 3f30ea5a30..e0d5f9886e 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -26,7 +26,8 @@ the following architecture extensions: - FEAT_ASID16 (16 bit ASID) - FEAT_ASID2 (Concurrent use of two ASIDs) - FEAT_ATS1A (Address Translation operations that ignore stage 1 permissio= ns) -- FEAT_BBM at level 2 (Translation table break-before-make levels) +- FEAT_BBML1 (Translation table break-before-make level 1) +- FEAT_BBML2 (Translation table break-before-make level 2) - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) - FEAT_CCIDX (Extended cache index) --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703034; cv=none; d=zohomail.com; s=zohoarc; b=VGt5GBCrtD7FPuYYhrT5uvr5/T+AFfAxw6uI+YM5lCNzAX1lqRX6B38wa5XeTuJy8cLS888KmGZTQfW2eSqOa1/fdg/U7UQP2JSdmFLttLLuqSF/kfE2EQaYWLlBjQB0XheTUZjS32iS/IXYO1sJYHKdEExlVCz4fgBqLlxvUPw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703034; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Uaq9ElfQysU2NonbTWFmHpCaaanArhtXeyoJNinjHBs=; b=myxevTQA6QFV+LcB68I7goHZvGD9nfCqhI090HoXOxLx8SVR2rQfWR1shfTJMisbamFuGn9Mcszc7YeGtCUIYVszWokroo/95NLTBijmENGoc7Qbz2vOpZihkIxdKcxR7VTDAhPhV3zw971SqTBIKcQolKLJfA/9Qfut+rEOotE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769703034485257.07961682639893; Thu, 29 Jan 2026 08:10:34 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUb9-0001hP-4i; Thu, 29 Jan 2026 11:10:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUay-0001IK-9W for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:12 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUav-00076W-Vp for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:11 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-432d28870ddso771925f8f.3 for ; Thu, 29 Jan 2026 08:10:09 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.10.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:10:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769703008; x=1770307808; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Uaq9ElfQysU2NonbTWFmHpCaaanArhtXeyoJNinjHBs=; b=be1dosV6Oeh4g40egzR50Q1ROl6lIx6ZM7/qcz9hJPV0DbonwjYm/BEf0nH6q0Ffxq gJtgKlQmCvbxNpabLpol7vifcb27o6Q4DimXkwmcnoLOz2815aB1o81NbMo5vx0woLRX BGP0NRFWbqwhiGaXkhXMaV5XBGdzC1WkHc9VsWmpwdzcCS1lODmthf9q363RwBKYpHnp Rl9dEwWKggrDgLJ33YeZXPqpGeBHQmE8OuqE56COuUUZJWsg1qcCRCyQfhBK+HkVZfHJ fvM7yuw+Uic7hT/BDMaOwvrf/6ZT9PvDvL+TGtRdStkAIeDrJxguLHBB8QbkleXDqBfR Wthg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769703008; x=1770307808; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Uaq9ElfQysU2NonbTWFmHpCaaanArhtXeyoJNinjHBs=; b=wG7EPl8ZmYexBoI4DLmd3sg0fKMgPKASvpcH5wgWDf5V3HpOsmDCb8GqWy4HB1QN8B soxkjCn3cYwCgV30FMTDKkkC384djHI0ucAPQ00ftj/3clQ7oBkUwBCUv7R0gHkf8ZCh Vg9Dj6g/T6MnAQqJtDA7a9WAaXFDlPw23zETdZxqsKnTT+q7sAAYxndfHsLzVcNnGwdF Z13NeA4lcVB+eQbs+6o5/r+E/HolPpUXtUmGKYGvqI88kumn5pClinl7Hg8kpEIaGe7P Am2KveT0CX4VajvE7/dceyExIcEA9o2nXnTO9+nfO8r2J4bR/24EIsxOKa2ddHg7hDUm +Y1Q== X-Gm-Message-State: AOJu0YzhZDmUamxWHXlWBmHZsbcopnbY3KdrRfIomGvw3CZykCP+pbUa uG16nGmN+jnC03kGVsjHl9t9q8i6q7JZVu372YUpfIAkjcdJ/0R4UPOWDlYlTm2cvolkdUIgfkp gOwxESCU= X-Gm-Gg: AZuq6aL50Rw7f0ApArhGiwvMX19iDaWTOQDZNgGTcEooTpe7LDzo7tugiCtckvQBnm+ YeaYHOjXa7DOrcmeTak3Zp+qc8+lFmodCjpvOLyyAIvaa5LsthAnZJYSrw66okPVdbSI1FJSr4q nlD8qfEd15wXLWsE4BnOVM8/rcyrhjykAUkU/6ymurDaThZ3RQTii/pFsVuPTZVK/8LNJEoJTnc iL/YK50a58XAJQ0gqzN5HMudkN0OiAfhOYqsE7TEHyPCXPGXQ/pTP1zm+2/MuRo+eirFivaFX2h DhjV14TuSkV9FVcsss3THcwySd3BsVVMHPyxWHlVefZrQDRLavRVi8o0O/t7FDRl43uRbtMGEmT W8ek0fDEq7t71V1qS7NXmt4gdTEU9xvg1HtxnXZyq3cJbQIxRqRPyZq/j3N019deXVHf8cB/Qo4 VPAQv9DK21NDIoTMByw5Cz3dCtJO7z8d2ySQitoUEo X-Received: by 2002:a05:6000:401e:b0:430:96bd:411b with SMTP id ffacd0b85a97d-435f3ad5929mr137100f8f.58.1769703008344; Thu, 29 Jan 2026 08:10:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 42/43] arm: add {get,set}_dczid_bs helpers Date: Thu, 29 Jan 2026 16:09:16 +0000 Message-ID: <20260129160917.1415092-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703036176154100 Content-Type: text/plain; charset="utf-8" From: Cornelia Huck Most accesses to cpu->dcz_blocksize really care about DCZID_EL0.BS (i.e. the part of the register that does not change at different EL.) Wean them off directly dealing with cpu->dcz_blocksize so that we can switch to handling DCZID_EL0 differently in a followup patch. Signed-off-by: Cornelia Huck Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Message-id: 20260105154119.59853-2-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu.c | 2 +- target/arm/cpu.h | 10 ++++++++++ target/arm/cpu64.c | 4 ++-- target/arm/helper.c | 1 + target/arm/tcg/cpu64.c | 22 +++++++++++----------- target/arm/tcg/helper-a64.c | 2 +- target/arm/tcg/mte_helper.c | 4 ++-- target/arm/tcg/translate-a64.c | 2 +- 8 files changed, 29 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6e1cbf3d61..586202071d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2175,7 +2175,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) #endif =20 if (tcg_enabled()) { - int dcz_blocklen =3D 4 << cpu->dcz_blocksize; + int dcz_blocklen =3D 4 << get_dczid_bs(cpu); =20 /* * We only support DCZ blocklen that fits on one page. diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1eaf5a3fdd..019f4e6147 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1179,6 +1179,16 @@ struct ARMCPUClass { ResettablePhases parent_phases; }; =20 +static inline uint8_t get_dczid_bs(ARMCPU *cpu) +{ + return cpu->dcz_blocksize; +} + +static inline void set_dczid_bs(ARMCPU *cpu, uint8_t bs) +{ + cpu->dcz_blocksize =3D bs; +} + /* Callback functions for the generic timer's timers. */ void arm_gt_ptimer_cb(void *opaque); void arm_gt_vtimer_cb(void *opaque); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index bf30381370..4dfc03973e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -689,7 +689,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, = 2); /* 2048KB L2 cache */ cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, = 7); - cpu->dcz_blocksize =3D 4; /* 64 bytes */ + set_dczid_bs(cpu, 4); /* 64 bytes */ cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; @@ -751,7 +751,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 1, 64, 32 * KiB, = 2); /* 1024KB L2 cache */ cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, = 7); - cpu->dcz_blocksize =3D 4; /* 64 bytes */ + set_dczid_bs(cpu, 4); /* 64 bytes */ cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; diff --git a/target/arm/helper.c b/target/arm/helper.c index dce648b482..4acaee407d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3318,6 +3318,7 @@ static uint64_t aa64_dczid_read(CPUARMState *env, con= st ARMCPRegInfo *ri) if (aa64_zva_access(env, NULL, false) =3D=3D CP_ACCESS_OK) { dzp_bit =3D 0; } + return cpu->dcz_blocksize | dzp_bit; } =20 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 611838171b..fa80e48d2b 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -72,7 +72,7 @@ static void aarch64_a35_initfn(Object *obj) SET_IDREG(isar, ID_AA64MMFR0, 0x00101122); SET_IDREG(isar, ID_AA64MMFR1, 0); SET_IDREG(isar, CLIDR, 0x0a200023); - cpu->dcz_blocksize =3D 4; + set_dczid_bs(cpu, 4); =20 /* From B2.4 AArch64 Virtual Memory control registers */ cpu->reset_sctlr =3D 0x00c50838; @@ -219,7 +219,7 @@ static void aarch64_a55_initfn(Object *obj) /* Ordered by B2.4 AArch64 registers by functional group */ SET_IDREG(isar, CLIDR, 0x82000023); cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ - cpu->dcz_blocksize =3D 4; /* 64 bytes */ + set_dczid_bs(cpu, 4); /* 64 bytes */ SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull); SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); @@ -325,7 +325,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, = 2); /* 1MB L2 cache */ cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, = 7); - cpu->dcz_blocksize =3D 4; /* 64 bytes */ + set_dczid_bs(cpu, 4); /* 64 bytes */ cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; @@ -352,7 +352,7 @@ static void aarch64_a76_initfn(Object *obj) /* Ordered by B2.4 AArch64 registers by functional group */ SET_IDREG(isar, CLIDR, 0x82000023); cpu->ctr =3D 0x8444C004; - cpu->dcz_blocksize =3D 4; + set_dczid_bs(cpu, 4); SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull); SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); @@ -424,7 +424,7 @@ static void aarch64_a78ae_initfn(Object *obj) /* Ordered by 3.2.4 AArch64 registers by functional group */ SET_IDREG(isar, CLIDR, 0x82000023); cpu->ctr =3D 0x9444c004; - cpu->dcz_blocksize =3D 4; + set_dczid_bs(cpu, 4); SET_IDREG(isar, ID_AA64DFR0, 0x0000000110305408ull); SET_IDREG(isar, ID_AA64ISAR0, 0x0010100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000001200031ull); @@ -517,7 +517,7 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB,= 2); /* 8MB L2 cache */ cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 256, 8 * MiB,= 7); - cpu->dcz_blocksize =3D 6; /* 256 bytes */ + set_dczid_bs(cpu, 6); /* 256 bytes */ cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; @@ -673,7 +673,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) /* Ordered by B2.4 AArch64 registers by functional group */ SET_IDREG(isar, CLIDR, 0x82000023); cpu->ctr =3D 0x8444c004; - cpu->dcz_blocksize =3D 4; + set_dczid_bs(cpu, 4); SET_IDREG(isar, ID_AA64DFR0, 0x0000000110305408ull); SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); @@ -749,7 +749,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) /* Ordered by 3.2.4 AArch64 registers by functional group */ SET_IDREG(isar, CLIDR, 0x82000023); cpu->ctr =3D 0xb444c004; /* With DIC and IDC set */ - cpu->dcz_blocksize =3D 4; + set_dczid_bs(cpu, 4); SET_IDREG(isar, ID_AA64AFR0, 0x00000000); SET_IDREG(isar, ID_AA64AFR1, 0x00000000); SET_IDREG(isar, ID_AA64DFR0, 0x000001f210305519ull); @@ -1011,7 +1011,7 @@ static void aarch64_a710_initfn(Object *obj) SET_IDREG(isar, CLIDR, 0x0000001482000023ull); cpu->gm_blocksize =3D 4; cpu->ctr =3D 0x000000049444c004ull; - cpu->dcz_blocksize =3D 4; + set_dczid_bs(cpu, 4); /* TODO FEAT_MPAM: mpamidr_el1 =3D 0x0000_0001_0006_003f */ =20 /* Section B.5.2: PMCR_EL0 */ @@ -1113,7 +1113,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) SET_IDREG(isar, CLIDR, 0x0000001482000023ull); cpu->gm_blocksize =3D 4; cpu->ctr =3D 0x00000004b444c004ull; - cpu->dcz_blocksize =3D 4; + set_dczid_bs(cpu, 4); /* TODO FEAT_MPAM: mpamidr_el1 =3D 0x0000_0001_001e_01ff */ =20 /* Section B.7.2: PMCR_EL0 */ @@ -1381,7 +1381,7 @@ void aarch64_max_tcg_initfn(Object *obj) * blocksize since we don't have to follow what the hardware does. */ cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ - cpu->dcz_blocksize =3D 7; /* 512 bytes */ + set_dczid_bs(cpu, 7); /* 512 bytes */ #endif cpu->gm_blocksize =3D 6; /* 256 bytes */ =20 diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index ba1d775d81..e4d2c2e392 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -792,7 +792,7 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) * (which matches the usual QEMU behaviour of not implementing either * alignment faults or any memory attribute handling). */ - int blocklen =3D 4 << env_archcpu(env)->dcz_blocksize; + int blocklen =3D 4 << get_dczid_bs(env_archcpu(env)); uint64_t vaddr =3D vaddr_in & ~(blocklen - 1); int mmu_idx =3D arm_env_mmu_index(env); void *mem; diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index bb48fe359b..08b8e7176a 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -545,7 +545,7 @@ void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr,= uint64_t val) * i.e. 32 bytes, which is an unreasonably small dcz anyway, * to make sure that we can access one complete tag byte here. */ - log2_dcz_bytes =3D env_archcpu(env)->dcz_blocksize + 2; + log2_dcz_bytes =3D get_dczid_bs(env_archcpu(env)) + 2; log2_tag_bytes =3D log2_dcz_bytes - (LOG2_TAG_GRANULE + 1); dcz_bytes =3D (intptr_t)1 << log2_dcz_bytes; tag_bytes =3D (intptr_t)1 << log2_tag_bytes; @@ -945,7 +945,7 @@ uint64_t HELPER(mte_check_zva)(CPUARMState *env, uint32= _t desc, uint64_t ptr) * i.e. 32 bytes, which is an unreasonably small dcz anyway, to make * sure that we can access one complete tag byte here. */ - log2_dcz_bytes =3D env_archcpu(env)->dcz_blocksize + 2; + log2_dcz_bytes =3D get_dczid_bs(env_archcpu(env)) + 2; log2_tag_bytes =3D log2_dcz_bytes - (LOG2_TAG_GRANULE + 1); dcz_bytes =3D (intptr_t)1 << log2_dcz_bytes; tag_bytes =3D (intptr_t)1 << log2_tag_bytes; diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index cde22a5cca..7a8cd99e00 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10712,7 +10712,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; dc->features =3D env->features; - dc->dcz_blocksize =3D arm_cpu->dcz_blocksize; + dc->dcz_blocksize =3D get_dczid_bs(arm_cpu); dc->gm_blocksize =3D arm_cpu->gm_blocksize; =20 #ifdef CONFIG_USER_ONLY --=20 2.43.0 From nobody Mon Feb 9 10:54:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769703079; cv=none; d=zohomail.com; s=zohoarc; b=hNEBksAoZ+YcHc0UnmDmsIuA7fro6LlQfCYrAQi9qxTZBlDXLdG7xgqQENhQHdhGbgUzfTo44ws+CCrFme76VYjIWMu4Ss9K8MR50pvF53XnmqQSnGWLPDDyhW7kepKTOJzsoWH0+E8r+ACNcX0ZppeE0rgXORA1pM3MJZu2Qbc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769703079; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=IlsBtCnmhIZFl3u2JK0/ew3XW8UoDsMuJkmGhR98BWo=; b=bSXnCIbIxOniHaXYUa6EBXiEN1TbId6durTN3qC0/e79abNDpQbGYuWOuKI+iCgvURxjffHv1h+YWsp3fXt0ScdvaOFdkhTeybfbijd0r3hJf6Suy5zCAy0FZqVN66Qt1M19XxGdjBzgGG7e4DCZVKxmWzaPyPHesW4lKNdoqk0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176970307907616.98952300958001; Thu, 29 Jan 2026 08:11:19 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vlUbB-0001pa-B4; Thu, 29 Jan 2026 11:10:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vlUay-0001Kn-Ux for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:13 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vlUax-00076n-02 for qemu-devel@nongnu.org; Thu, 29 Jan 2026 11:10:12 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-47f5c2283b6so9409185e9.1 for ; Thu, 29 Jan 2026 08:10:10 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.10.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:10:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769703009; x=1770307809; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=IlsBtCnmhIZFl3u2JK0/ew3XW8UoDsMuJkmGhR98BWo=; b=eHJexbK+3Oaqaa3rfAfTsSTLZnxAt3gjUxcUDhlM1xBuuiWzMsZ51AuKjOrVOndw3k m4mMcLiBYQhZ/IIA1NQUh5joctXJxJVJRn/v4ckQ7AlqSw7qS51mo4HhXI8dJqpPrbnP C9SlUrXdmxv/tzwSzp/tJVWamB7BPa5WDCCe8M0igOQGR0VwBphOblqx1s6ajseyi6R3 CKMTa9SV90vMCGSegMUpk3lNoPf77p2k9d4+wSBM7LiOoX815cf/aNSpMVpLTULVWgq2 R/6VoPSPj5ocdo1EQF7y3PMUQkdkGznFzJt1vOb1Qm5ZRB+HaNrQ2Q26LudeQetpNl1E Ihqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769703009; x=1770307809; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=IlsBtCnmhIZFl3u2JK0/ew3XW8UoDsMuJkmGhR98BWo=; b=URM3AVMrKGiSj6wvv+k2IaIXLyaKV/9IGXVKx5dCrlF8mx7BKDYArd+K1DcsMSQqAq YPan4Ktp+9kFehZuhpHN0yQucGSbeMrfvI5bXYOt4fCwg5pPih1t6ptfKP1WIjhO+oso 0lhIkt1WsARcxGlc399X2LFZ2h1F2cYLMw8AKsL6gu2H9WUVi9Wd3oxodB4VBdPEw+1Z rplfKFKt+XFrqxeoVqyRpd4aGgc8sBvfZbqsxF1iME4ESA3gUVoCL97pWlSW0xpdtQzS pfuTSwfJKLdQIMGZXXKMAX2ibqrJ5Gtf4UNB0DOp1q7awSRVK1+G6+R4wQ5ZORRY9Fto DxWg== X-Gm-Message-State: AOJu0Yx+f32kPsXBTkROLexbJ3w38ojS1qB0dkT5cXz1dzK8L1xfO3OU nOAAJaXYWuaoGfrc5Z/q+jLkljjuk+/55jUjPURNXuj8tRTKm4zG1no2jieFgAeEAfT0NJlzxBf 6gF9Ro78= X-Gm-Gg: AZuq6aKZNDCPd6jfvb1qNJNLh3uKfYIzL+BCcZA5s5ukDsqxYv6Wwp4l1vkxwYnB1r4 9m2OYdERpwf3nDuTYFHLoq5SYnc27ei1d083OGHMGPo/78i6lEhT8Ax0Wa743DQ2OtHzbz+Da/5 oxcctjx7pD5l3zn2t91/gu8znvhwVe2iqOoX5bKBMNIo0SvCA7t2UFvcIqxActCCDvPC30gzg+5 6T58jO8AM1SVhdiVA3aIVH+Qsl+pfTb8QgYhehjqmObgyJLWVY+UxmWQLiD1+DAT1g0tEy8bnW1 qbmLoDyil6XIyGDzj+a2TWEpsn+qC40JSrwySGWb7AsVgV8IQtFt4zhqjeCaIKqIKtecRlBxjhY liHvc0x26HFc8XdEZKtEPonCRSMB+58lVvJ3M/7cSmifl4LVDwtlgbIoCR1NknTPDNKBNHY0hhh RfMFzBWp7rgtDpmbcCaYlKGjcnkHrCYw== X-Received: by 2002:a05:600c:e40b:b0:47a:9560:ec28 with SMTP id 5b1f17b1804b1-4806a5bef7bmr114557085e9.13.1769703009487; Thu, 29 Jan 2026 08:10:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 43/43] arm: add DCZID_EL0 to idregs array Date: Thu, 29 Jan 2026 16:09:17 +0000 Message-ID: <20260129160917.1415092-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703080996158500 Content-Type: text/plain; charset="utf-8" From: Cornelia Huck Continue moving ID registers to the idregs array, so that we eventually can switch to an autogenerated cpu-sysregs.h.inc. This requires a bit of care, since we still have to handle the EL specific part (DCZID_EL0.DZP). The value previously saved in cpu->dcz_blocksize is now kept in DCZID_EL.BS (transparent to callers using the wrappers.) KVM currently does not support DCZID_EL0 via ONE_REG, assert that we're not trying to do anything with it until it does. Signed-off-by: Cornelia Huck Reviewed-by: Sebastian Ott Message-id: 20260105154119.59853-3-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu-sysregs.h.inc | 1 + target/arm/cpu.h | 8 ++++---- target/arm/helper.c | 4 +++- target/arm/tcg/translate.h | 2 +- 4 files changed, 9 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index 2ba49d8478..3d1ed40f04 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -40,3 +40,4 @@ DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) DEF(CLIDR_EL1, 3, 1, 0, 0, 1) DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) DEF(CTR_EL0, 3, 3, 0, 0, 1) +DEF(DCZID_EL0, 3, 3, 0, 0, 7) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 019f4e6147..21fee5e840 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1112,8 +1112,6 @@ struct ArchCPU { bool prop_pauth_qarma5; bool prop_lpa2; =20 - /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ - uint8_t dcz_blocksize; /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ uint8_t gm_blocksize; =20 @@ -1181,12 +1179,14 @@ struct ARMCPUClass { =20 static inline uint8_t get_dczid_bs(ARMCPU *cpu) { - return cpu->dcz_blocksize; + return extract64(cpu->isar.idregs[DCZID_EL0_IDX], 0, 4); } =20 static inline void set_dczid_bs(ARMCPU *cpu, uint8_t bs) { - cpu->dcz_blocksize =3D bs; + /* keep dzp unchanged */ + cpu->isar.idregs[DCZID_EL0_IDX] =3D + deposit64(cpu->isar.idregs[DCZID_EL0_IDX], 0, 4, bs); } =20 /* Callback functions for the generic timer's timers. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 4acaee407d..e86ceb130c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3314,12 +3314,14 @@ static uint64_t aa64_dczid_read(CPUARMState *env, c= onst ARMCPRegInfo *ri) ARMCPU *cpu =3D env_archcpu(env); int dzp_bit =3D 1 << 4; =20 + assert(!kvm_enabled()); + /* DZP indicates whether DC ZVA access is allowed */ if (aa64_zva_access(env, NULL, false) =3D=3D CP_ACCESS_OK) { dzp_bit =3D 0; } =20 - return cpu->dcz_blocksize | dzp_bit; + return cpu->isar.idregs[DCZID_EL0_IDX] | dzp_bit; } =20 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *= ri, diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index b62104b4ae..1e30d7c77c 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -193,7 +193,7 @@ typedef struct DisasContext { * < 0, set by the current instruction. */ int8_t btype; - /* A copy of cpu->dcz_blocksize. */ + /* A copy of DCZID_EL0.BS. */ uint8_t dcz_blocksize; /* A copy of cpu->gm_blocksize. */ uint8_t gm_blocksize; --=20 2.43.0