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a="73462354" X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="73462354" X-CSE-ConnectionGUID: sh1uBdSpQ7ak5CJQl2wDHA== X-CSE-MsgGUID: 0sB7ehxMQbiQhy6+npxnnA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="208001794" From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: Xiaoyao Li , Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH V2 11/11] target/i386: Disable guest PEBS capability when not enabled Date: Wed, 28 Jan 2026 15:09:48 -0800 Message-ID: <20260128231003.268981-12-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260128231003.268981-1-zide.chen@intel.com> References: <20260128231003.268981-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.13; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1769642338566154101 Content-Type: text/plain; charset="utf-8" When PMU is disabled, guest CPUID must not advertise Debug Store support. Clear both CPUID.01H:EDX[21] (DS) and CPUID.01H:ECX[2] (DS64) in this case. Set IA32_MISC_ENABLE[12] (PEBS_UNAVAILABLE) when Debug Store is not exposed to the guest. Note: Do not infer that PEBS is unsupported from IA32_PERF_CAPABILITIES[11:8] (PEBS_FMT) being 0. A value of 0 is a valid PEBS record format on some CPUs. Signed-off-by: Zide Chen --- V2: - New patch. target/i386/cpu.c | 6 ++++++ target/i386/cpu.h | 1 + 2 files changed, 7 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ec6f49916de3..445361ab7a06 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9180,6 +9180,10 @@ static void x86_cpu_reset_hold(Object *obj, ResetTyp= e type) env->msr_ia32_misc_enable |=3D MSR_IA32_MISC_ENABLE_MWAIT; } =20 + if (!(env->features[FEAT_1_EDX] & CPUID_DTS)) { + env->msr_ia32_misc_enable |=3D MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL; + } + memset(env->dr, 0, sizeof(env->dr)); env->dr[6] =3D DR6_FIXED_1; env->dr[7] =3D DR7_FIXED_1; @@ -9474,6 +9478,8 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **err= p) env->features[FEAT_1_ECX] &=3D ~CPUID_EXT_PDCM; } =20 + env->features[FEAT_1_ECX] &=3D ~CPUID_EXT_DTES64; + env->features[FEAT_1_EDX] &=3D ~CPUID_DTS; env->features[FEAT_7_0_EDX] &=3D ~CPUID_7_0_EDX_ARCH_LBR; } =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 5ab107dfa29f..0fecf561173e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -483,6 +483,7 @@ typedef enum X86Seg { /* Indicates good rep/movs microcode on some processors: */ #define MSR_IA32_MISC_ENABLE_FASTSTRING (1ULL << 0) #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) +#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) #define MSR_IA32_MISC_ENABLE_DEFAULT (MSR_IA32_MISC_ENABLE_FASTSTRING = |\ MSR_IA32_MISC_ENABLE_BTS_UNAVAIL) --=20 2.52.0