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a="73462310" X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="73462310" X-CSE-ConnectionGUID: thiR9T5xQ02UQxzDyTEXYA== X-CSE-MsgGUID: BuWH7TluS5mABVm+PPRu5A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="208001760" From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: Xiaoyao Li , Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH V2 01/11] target/i386: Disable unsupported BTS for guest Date: Wed, 28 Jan 2026 15:09:38 -0800 Message-ID: <20260128231003.268981-2-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260128231003.268981-1-zide.chen@intel.com> References: <20260128231003.268981-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.13; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1769642322609154100 Content-Type: text/plain; charset="utf-8" BTS (Branch Trace Store), enumerated by IA32_MISC_ENABLE.BTS_UNAVAILABLE (bit 11), is deprecated and has been superseded by LBR and Intel PT. KVM yields control of the above mentioned bit to userspace since KVM commit 9fc222967a39 ("KVM: x86: Give host userspace full control of MSR_IA32_MISC_ENABLES"). However, QEMU does not set this bit, which allows guests to write the BTS and BTINT bits in IA32_DEBUGCTL. Since KVM doesn't support BTS, this may lead to unexpected MSR access errors. Signed-off-by: Zide Chen --- V2: - Address Dapeng's comments. - Remove mention of VMState version_id from the commit message. target/i386/cpu.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 2bbc977d9088..f02812bfd19f 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -474,8 +474,11 @@ typedef enum X86Seg { =20 #define MSR_IA32_MISC_ENABLE 0x1a0 /* Indicates good rep/movs microcode on some processors: */ -#define MSR_IA32_MISC_ENABLE_DEFAULT 1 +#define MSR_IA32_MISC_ENABLE_FASTSTRING (1ULL << 0) +#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) +#define MSR_IA32_MISC_ENABLE_DEFAULT (MSR_IA32_MISC_ENABLE_FASTSTRING = |\ + MSR_IA32_MISC_ENABLE_BTS_UNAVAIL) =20 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) --=20 2.52.0 From nobody Sat Feb 7 07:25:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1769642358; cv=none; d=zohomail.com; s=zohoarc; b=ZLaffSZs1R4DtuSebKm+shO3QnN4MvVAvnBKQUWqfX4CKUe7BEmKso1fl9XI+0/wh4jqiYECTOMpGBoPAiR7HNOFrNEo8612OXc9HHu94p0ndpHSZO4cZp2c4zVBZiN+eOJA9+uPvrqtQmjfw4ogoOvqq8RxRzZgm8cjII0fmrw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769642358; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=215hWirFKJ44tixjf89cJBIL4cBxJq0rTj1ataV6k8c=; b=WhacSpj+JJf2ii8YlGgXuKOCWAbkZv+HtA39/TzSFyF3O+GLLUbjvz0NayGSJMBNKfvGK7EaKk6jF5MYmLeYGFtm/u+QKSjicHWBdl3Q0yF5QGhfic2GxYwRkwAD42u/wlIwDpKlKPI/msUSR8ZsVrZ5pfKw9GMx6KPCUIL/S3g= ARC-Authentication-Results: i=1; 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Wed, 28 Jan 2026 18:17:45 -0500 Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2026 15:17:38 -0800 Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2026 15:17:37 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769642262; x=1801178262; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=X6eVlD0wWTJwoNEwxzsqjt1g8gKZ9ft2Xlc5mBum9NY=; b=iqu6csBAzoVPv7S5PkcsBXV9XMPOriGArCbT8ZNrxlx4n8NAbf9uQLww puMUOToCAPkaKGsi3ed1nwW14c7GP2kYlMvYCmQHP0nBs8P5hwHRrFgd1 gp7bl8KUnVLi/L35+EJSdHkNVSNN4zKSiVNgtJ/k2ghEXCm/9d3jzHKhY vtlB0k07P436fCC3QB9mbH0sGydxhiHFSDrYf7llrtd0+xvDygqQKVI5h oDeJlne7hRAriYG36EPyEEhe6SzexA0yGyzsvDQgZVfqqXLrpDZOnQe6M 1tPgu5dius3miGKz3i43SvFrgfOFPcmIkzKjLFoFFvIOl2vaM3TtW5EK0 g==; X-CSE-ConnectionGUID: w9Ey/INOToa2+DkDf3weJQ== X-CSE-MsgGUID: HAJIED4ySly4aGzESzfqWw== X-IronPort-AV: E=McAfee;i="6800,10657,11685"; a="73462314" X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="73462314" X-CSE-ConnectionGUID: 2FkKWPuER+ml+TpE6QAjEg== X-CSE-MsgGUID: HdmXgQTDRBeyAmnBuEbHGA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="208001763" From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: Xiaoyao Li , Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH V2 02/11] target/i386: Don't save/restore PERF_GLOBAL_OVF_CTRL MSR Date: Wed, 28 Jan 2026 15:09:39 -0800 Message-ID: <20260128231003.268981-3-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260128231003.268981-1-zide.chen@intel.com> References: <20260128231003.268981-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.13; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1769642359030158500 Content-Type: text/plain; charset="utf-8" From: Dapeng Mi MSR_CORE_PERF_GLOBAL_OVF_CTRL is a write-only MSR and reads always return zero. Saving and restoring this MSR is therefore unnecessary. Replace VMSTATE_UINT64 with VMSTATE_UNUSED in the VMStateDescription to ignore env.msr_global_ovf_ctrl during migration. This avoids the need to bump version_id and does not introduce any migration incompatibility. Signed-off-by: Dapeng Mi Signed-off-by: Zide Chen --- V2: - No changes. target/i386/cpu.h | 1 - target/i386/kvm/kvm.c | 6 ------ target/i386/machine.c | 4 ++-- 3 files changed, 2 insertions(+), 9 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index f02812bfd19f..f6e9b274e2ff 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2086,7 +2086,6 @@ typedef struct CPUArchState { uint64_t msr_fixed_ctr_ctrl; uint64_t msr_global_ctrl; uint64_t msr_global_status; - uint64_t msr_global_ovf_ctrl; uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; uint64_t msr_gp_counters[MAX_GP_COUNTERS]; uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 7b9b740a8e5a..cffbc90d1c50 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4069,8 +4069,6 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState leve= l) if (has_architectural_pmu_version > 1) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, env->msr_global_status); - kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, - env->msr_global_ovf_ctrl); =20 /* Now start the PMU. */ kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, @@ -4588,7 +4586,6 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0); - kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0); } for (i =3D 0; i < num_architectural_pmu_fixed_counters; i++) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0); @@ -4917,9 +4914,6 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_CORE_PERF_GLOBAL_STATUS: env->msr_global_status =3D msrs[i].data; break; - case MSR_CORE_PERF_GLOBAL_OVF_CTRL: - env->msr_global_ovf_ctrl =3D msrs[i].data; - break; case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_F= IXED_COUNTERS - 1: env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] =3D = msrs[i].data; break; diff --git a/target/i386/machine.c b/target/i386/machine.c index c9139612813b..1125c8a64ec5 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -666,7 +666,7 @@ static bool pmu_enable_needed(void *opaque) int i; =20 if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl || - env->msr_global_status || env->msr_global_ovf_ctrl) { + env->msr_global_status) { return true; } for (i =3D 0; i < MAX_FIXED_COUNTERS; i++) { @@ -692,7 +692,7 @@ static const VMStateDescription vmstate_msr_architectur= al_pmu =3D { VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU), VMSTATE_UINT64(env.msr_global_ctrl, X86CPU), VMSTATE_UINT64(env.msr_global_status, X86CPU), - VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU), + VMSTATE_UNUSED(sizeof(uint64_t)), VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COU= NTERS), VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS), VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS), --=20 2.52.0 From nobody Sat Feb 7 07:25:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="73462318" X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="73462318" X-CSE-ConnectionGUID: QQvBP4kiTpykiVbyP/BrTQ== X-CSE-MsgGUID: ncoN2kERSCaQLjeOvJY2MA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="208001766" From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: Xiaoyao Li , Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH V2 03/11] target/i386: Gate enable_pmu on kvm_enabled() Date: Wed, 28 Jan 2026 15:09:40 -0800 Message-ID: <20260128231003.268981-4-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260128231003.268981-1-zide.chen@intel.com> References: <20260128231003.268981-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.13; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1769642322938154100 Content-Type: text/plain; charset="utf-8" Guest PMU support requires KVM. Clear cpu->enable_pmu when KVM is not enabled, so PMU-related code can rely solely on cpu->enable_pmu. This reduces duplication and avoids bugs where one of the checks is missed. For example, cpu_x86_cpuid() enables CPUID.0AH when cpu->enable_pmu is set but does not check kvm_enabled(). This is implicitly fixed by this patch: if (cpu->enable_pmu) { x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); } Also fix two places that check kvm_enabled() but not cpu->enable_pmu. Reviewed-by: Dapeng Mi Signed-off-by: Zide Chen --- V2: - Replace a tab with spaces. target/i386/cpu.c | 9 ++++++--- target/i386/kvm/kvm.c | 4 ++-- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 37803cd72490..d3e9d3c40b0a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8671,7 +8671,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *ecx =3D 0; *edx =3D 0; if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || - !kvm_enabled()) { + !cpu->enable_pmu) { break; } =20 @@ -9018,7 +9018,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, case 0x80000022: *eax =3D *ebx =3D *ecx =3D *edx =3D 0; /* AMD Extended Performance Monitoring and Debug */ - if (kvm_enabled() && cpu->enable_pmu && + if (cpu->enable_pmu && (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFM= ON_V2)) { *eax |=3D CPUID_8000_0022_EAX_PERFMON_V2; *ebx |=3D kvm_arch_get_supported_cpuid(cs->kvm_state, index, c= ount, @@ -9642,7 +9642,7 @@ static bool x86_cpu_filter_features(X86CPU *cpu, bool= verbose) * are advertised by cpu_x86_cpuid(). Keep these two in sync. */ if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && - kvm_enabled()) { + cpu->enable_pmu) { x86_cpu_get_supported_cpuid(0x14, 0, &eax_0, &ebx_0, &ecx_0, &edx_0); x86_cpu_get_supported_cpuid(0x14, 1, @@ -9790,6 +9790,9 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) Error *local_err =3D NULL; unsigned requested_lbr_fmt; =20 + if (!kvm_enabled()) + cpu->enable_pmu =3D false; + #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) /* Use pc-relative instructions in system-mode */ tcg_cflags_set(cs, CF_PCREL); diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index cffbc90d1c50..e81fa46ed66c 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4222,7 +4222,7 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState leve= l) env->msr_xfd_err); } =20 - if (kvm_enabled() && cpu->enable_pmu && + if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { uint64_t depth; int ret; @@ -4698,7 +4698,7 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0); } =20 - if (kvm_enabled() && cpu->enable_pmu && + if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { uint64_t depth; =20 --=20 2.52.0 From nobody Sat Feb 7 07:25:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1769642367; cv=none; d=zohomail.com; s=zohoarc; b=IaxonB9Wa57gM7j6FfpDey6U0jYQy6apu9YWr5fdiUJ8GZTX3xhIS0F1i1/Ie/g99IdUwJVBEBaP5i6nLkh9kOitLolwvDSQaeru3vBAZIF1WG7RsEp95jDve8iTlEjfC4ELHsaiY1Cy02tpp1x9vnDgiFSX7SrlGykKwUnKGYE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769642367; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: 7T71++fgQN+wHDCGWv2X8Q== X-CSE-MsgGUID: yA6HMWAqQfupbC6bsfxL3g== X-IronPort-AV: E=McAfee;i="6800,10657,11685"; a="73462322" X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="73462322" X-CSE-ConnectionGUID: Hh8IxSJ1SCu0vF0FTVPKpA== X-CSE-MsgGUID: UoNBvUz8QoGKlSt0qHQIzQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="208001769" From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: Xiaoyao Li , Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH V2 04/11] target/i386: Support full-width writes for perf counters Date: Wed, 28 Jan 2026 15:09:41 -0800 Message-ID: <20260128231003.268981-5-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260128231003.268981-1-zide.chen@intel.com> References: <20260128231003.268981-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.13; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1769642369081158500 Content-Type: text/plain; charset="utf-8" From: Dapeng Mi If IA32_PERF_CAPABILITIES.FW_WRITE (bit 13) is set, each general- purpose counter IA32_PMCi (starting at 0xc1) is accompanied by a corresponding 64-bit alias MSR starting at 0x4c1 (IA32_A_PMC0). The legacy IA32_PMCi MSRs are not full-width and their effective width is determined by CPUID.0AH:EAX[23:16]. Since these MSRs are architectural aliases, when IA32_A_PMCi is supported it is safe to use it for save/restore instead of the legacy IA32_PMCi MSRs. Full-width write is a user-visible feature and can be disabled individually. Reduce MAX_GP_COUNTERS from 18 to 15 to avoid conflicts between the full-width MSR range and MSR_MCG_EXT_CTL. Current CPUs support at most 10 general-purpose counters, so 15 is sufficient for now and leaves room for future expansion. Bump minimum_version_id to avoid migration from older QEMU, as this may otherwise cause VMState overflow. This also requires bumping version_id, which prevents migration to older QEMU as well. Signed-off-by: Dapeng Mi Signed-off-by: Zide Chen --- V2: - Slightly improve the commit message wording. - Update the comment for MSR_IA32_PMC0 definition. target/i386/cpu.h | 5 ++++- target/i386/kvm/kvm.c | 19 +++++++++++++++++-- target/i386/machine.c | 4 ++-- 3 files changed, 23 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index f6e9b274e2ff..812d53e22c41 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -421,6 +421,7 @@ typedef enum X86Seg { =20 #define MSR_IA32_PERF_CAPABILITIES 0x345 #define PERF_CAP_LBR_FMT 0x3f +#define PERF_CAP_FULL_WRITE (1U << 13) =20 #define MSR_IA32_TSX_CTRL 0x122 #define MSR_IA32_TSCDEADLINE 0x6e0 @@ -448,6 +449,8 @@ typedef enum X86Seg { #define MSR_IA32_SGXLEPUBKEYHASH3 0x8f =20 #define MSR_P6_PERFCTR0 0xc1 +/* Alias MSR range for full-width general-purpose performance counters */ +#define MSR_IA32_PMC0 0x4c1 =20 #define MSR_IA32_SMBASE 0x9e #define MSR_SMI_COUNT 0x34 @@ -1740,7 +1743,7 @@ typedef struct { #endif =20 #define MAX_FIXED_COUNTERS 3 -#define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) +#define MAX_GP_COUNTERS 15 =20 #define NB_OPMASK_REGS 8 =20 diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index e81fa46ed66c..530f50e4b218 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4049,6 +4049,12 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState lev= el) } =20 if (has_architectural_pmu_version > 0) { + uint32_t perf_cntr_base =3D MSR_P6_PERFCTR0; + + if (env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_FULL_WRIT= E) { + perf_cntr_base =3D MSR_IA32_PMC0; + } + if (has_architectural_pmu_version > 1) { /* Stop the counter. */ kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); @@ -4061,7 +4067,7 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState leve= l) env->msr_fixed_counters[i]); } for (i =3D 0; i < num_architectural_pmu_gp_counters; i++) { - kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, + kvm_msr_entry_add(cpu, perf_cntr_base + i, env->msr_gp_counters[i]); kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, env->msr_gp_evtsel[i]); @@ -4582,6 +4588,12 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1); } if (has_architectural_pmu_version > 0) { + uint32_t perf_cntr_base =3D MSR_P6_PERFCTR0; + + if (env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_FULL_WRITE) { + perf_cntr_base =3D MSR_IA32_PMC0; + } + if (has_architectural_pmu_version > 1) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); @@ -4591,7 +4603,7 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0); } for (i =3D 0; i < num_architectural_pmu_gp_counters; i++) { - kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0); + kvm_msr_entry_add(cpu, perf_cntr_base + i, 0); kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0); } } @@ -4920,6 +4932,9 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1: env->msr_gp_counters[index - MSR_P6_PERFCTR0] =3D msrs[i].data; break; + case MSR_IA32_PMC0 ... MSR_IA32_PMC0 + MAX_GP_COUNTERS - 1: + env->msr_gp_counters[index - MSR_IA32_PMC0] =3D msrs[i].data; + break; case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] =3D msrs[i].data; break; diff --git a/target/i386/machine.c b/target/i386/machine.c index 1125c8a64ec5..7d08a05835fc 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -685,8 +685,8 @@ static bool pmu_enable_needed(void *opaque) =20 static const VMStateDescription vmstate_msr_architectural_pmu =3D { .name =3D "cpu/msr_architectural_pmu", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .needed =3D pmu_enable_needed, .fields =3D (const VMStateField[]) { VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU), --=20 2.52.0 From nobody Sat Feb 7 07:25:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; 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d="scan'208";a="208001772" From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: Xiaoyao Li , Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH V2 05/11] target/i386: Increase MSR_BUF_SIZE and split KVM_[GET/SET]_MSRS calls Date: Wed, 28 Jan 2026 15:09:42 -0800 Message-ID: <20260128231003.268981-6-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260128231003.268981-1-zide.chen@intel.com> References: <20260128231003.268981-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.13; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1769642331266158500 Content-Type: text/plain; charset="utf-8" Newer Intel server CPUs support a large number of PMU MSRs. Currently, QEMU allocates cpu->kvm_msr_buf as a single-page buffer, which is not sufficient to hold all possible MSRs. Increase MSR_BUF_SIZE to 8192 bytes, providing space for up to 511 MSRs. This is sufficient even for the theoretical worst case, such as architectural LBR with a depth of 64. KVM_[GET/SET]_MSRS is limited to 255 MSRs per call. Raising this limit to 511 would require changes in KVM and would introduce backward compatibility issues. Instead, split requests into multiple KVM_[GET/SET]_MSRS calls when the number of MSRs exceeds the API limit. Signed-off-by: Zide Chen --- V2: - No changes. target/i386/kvm/kvm.c | 109 +++++++++++++++++++++++++++++++++++------- 1 file changed, 92 insertions(+), 17 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 530f50e4b218..a2cf9b5df35d 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -98,9 +98,12 @@ #define KVM_APIC_BUS_CYCLE_NS 1 #define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS) =20 -/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus - * 255 kvm_msr_entry structs */ -#define MSR_BUF_SIZE 4096 +/* A 8192-byte buffer can hold the 8-byte kvm_msrs header, plus + * 511 kvm_msr_entry structs */ +#define MSR_BUF_SIZE 8192 + +/* Maximum number of MSRs in one single KVM_[GET/SET]_MSRS call. */ +#define KVM_MAX_IO_MSRS 255 =20 typedef bool QEMURDMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t *val); typedef bool QEMUWRMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t val); @@ -3878,23 +3881,102 @@ static void kvm_msr_entry_add_perf(X86CPU *cpu, Fe= atureWordArray f) } } =20 -static int kvm_buf_set_msrs(X86CPU *cpu) +static int __kvm_buf_set_msrs(X86CPU *cpu, struct kvm_msrs *msrs) { - int ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); + int ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, msrs); if (ret < 0) { return ret; } =20 - if (ret < cpu->kvm_msr_buf->nmsrs) { - struct kvm_msr_entry *e =3D &cpu->kvm_msr_buf->entries[ret]; + if (ret < msrs->nmsrs) { + struct kvm_msr_entry *e =3D &msrs->entries[ret]; error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx6= 4, (uint32_t)e->index, (uint64_t)e->data); } =20 - assert(ret =3D=3D cpu->kvm_msr_buf->nmsrs); + assert(ret =3D=3D msrs->nmsrs); + return ret; +} + +static int __kvm_buf_get_msrs(X86CPU *cpu, struct kvm_msrs *msrs) +{ + int ret; + + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, msrs); + if (ret < 0) { + return ret; + } + + if (ret < msrs->nmsrs) { + struct kvm_msr_entry *e =3D &msrs->entries[ret]; + error_report("error: failed to get MSR 0x%" PRIx32, + (uint32_t)e->index); + } + + assert(ret =3D=3D msrs->nmsrs); + return ret; +} + +static int kvm_buf_set_or_get_msrs(X86CPU *cpu, bool is_write) +{ + struct kvm_msr_entry *entries =3D cpu->kvm_msr_buf->entries; + struct kvm_msrs *buf =3D NULL; + int current, remaining, ret =3D 0; + size_t buf_size; + + buf_size =3D KVM_MAX_IO_MSRS * sizeof(struct kvm_msr_entry) + + sizeof(struct kvm_msrs); + buf =3D g_malloc(buf_size); + + remaining =3D cpu->kvm_msr_buf->nmsrs; + current =3D 0; + while (remaining) { + size_t size; + + memset(buf, 0, buf_size); + + if (remaining > KVM_MAX_IO_MSRS) { + buf->nmsrs =3D KVM_MAX_IO_MSRS; + } else { + buf->nmsrs =3D remaining; + } + + size =3D buf->nmsrs * sizeof(entries[0]); + memcpy(buf->entries, &entries[current], size); + + if (is_write) { + ret =3D __kvm_buf_set_msrs(cpu, buf); + } else { + ret =3D __kvm_buf_get_msrs(cpu, buf); + } + + if (ret < 0) { + goto out; + } + + if (!is_write) + memcpy(&entries[current], buf->entries, size); + + current +=3D buf->nmsrs; + remaining -=3D buf->nmsrs; + } + +out: + g_free(buf); + return ret < 0 ? ret : cpu->kvm_msr_buf->nmsrs; +} + +static int kvm_buf_set_msrs(X86CPU *cpu) +{ + kvm_buf_set_or_get_msrs(cpu, true); return 0; } =20 +static int kvm_buf_get_msrs(X86CPU *cpu) +{ + return kvm_buf_set_or_get_msrs(cpu, false); +} + static void kvm_init_msrs(X86CPU *cpu) { CPUX86State *env =3D &cpu->env; @@ -3928,7 +4010,7 @@ static void kvm_init_msrs(X86CPU *cpu) if (has_msr_ucode_rev) { kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev); } - assert(kvm_buf_set_msrs(cpu) =3D=3D 0); + kvm_buf_set_msrs(cpu); } =20 static int kvm_put_msrs(X86CPU *cpu, KvmPutState level) @@ -4746,18 +4828,11 @@ static int kvm_get_msrs(X86CPU *cpu) } } =20 - ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf); + ret =3D kvm_buf_get_msrs(cpu); if (ret < 0) { return ret; } =20 - if (ret < cpu->kvm_msr_buf->nmsrs) { - struct kvm_msr_entry *e =3D &cpu->kvm_msr_buf->entries[ret]; - error_report("error: failed to get MSR 0x%" PRIx32, - (uint32_t)e->index); - } - - assert(ret =3D=3D cpu->kvm_msr_buf->nmsrs); /* * MTRR masks: Each mask consists of 5 parts * a 10..0: must be zero --=20 2.52.0 From nobody Sat Feb 7 07:25:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="73462330" X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="73462330" X-CSE-ConnectionGUID: gD39TRv0RxC2vmW5Pk31AA== X-CSE-MsgGUID: U5A0iZnPTZ2eh10rtiNbUQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="208001775" From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: Xiaoyao Li , Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH V2 06/11] target/i386: Save/Restore DS based PEBS specfic MSRs Date: Wed, 28 Jan 2026 15:09:43 -0800 Message-ID: <20260128231003.268981-7-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260128231003.268981-1-zide.chen@intel.com> References: <20260128231003.268981-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.13; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1769642332468154100 Content-Type: text/plain; charset="utf-8" From: Dapeng Mi DS-based PEBS introduces three MSRs: MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, and MSR_IA32_PEBS_ENABLE. Save and restore these MSRs when legacy DS PEBS is enabled. Signed-off-by: Dapeng Mi Signed-off-by: Zide Chen --- V2: - No changes. target/i386/cpu.h | 9 +++++++++ target/i386/kvm/kvm.c | 25 +++++++++++++++++++++++++ target/i386/machine.c | 27 ++++++++++++++++++++++++++- 3 files changed, 60 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 812d53e22c41..3e2222e105bc 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -422,6 +422,7 @@ typedef enum X86Seg { #define MSR_IA32_PERF_CAPABILITIES 0x345 #define PERF_CAP_LBR_FMT 0x3f #define PERF_CAP_FULL_WRITE (1U << 13) +#define PERF_CAP_PEBS_BASELINE (1U << 14) =20 #define MSR_IA32_TSX_CTRL 0x122 #define MSR_IA32_TSCDEADLINE 0x6e0 @@ -512,6 +513,11 @@ typedef enum X86Seg { #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 =20 +/* Legacy DS based PEBS MSRs */ +#define MSR_IA32_PEBS_ENABLE 0x3f1 +#define MSR_PEBS_DATA_CFG 0x3f2 +#define MSR_IA32_DS_AREA 0x600 + #define MSR_MC0_CTL 0x400 #define MSR_MC0_STATUS 0x401 #define MSR_MC0_ADDR 0x402 @@ -2089,6 +2095,9 @@ typedef struct CPUArchState { uint64_t msr_fixed_ctr_ctrl; uint64_t msr_global_ctrl; uint64_t msr_global_status; + uint64_t msr_ds_area; + uint64_t msr_pebs_data_cfg; + uint64_t msr_pebs_enable; uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; uint64_t msr_gp_counters[MAX_GP_COUNTERS]; uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index a2cf9b5df35d..a72e4d60dfa2 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4143,6 +4143,15 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState lev= el) kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); } =20 + if (env->features[FEAT_1_EDX] & CPUID_DTS) { + kvm_msr_entry_add(cpu, MSR_IA32_DS_AREA, env->msr_ds_area); + } + + if (env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_PEBS_BASE= LINE) { + kvm_msr_entry_add(cpu, MSR_IA32_PEBS_ENABLE, env->msr_pebs= _enable); + kvm_msr_entry_add(cpu, MSR_PEBS_DATA_CFG, env->msr_pebs_da= ta_cfg); + } + /* Set the counter values. */ for (i =3D 0; i < num_architectural_pmu_fixed_counters; i++) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, @@ -4688,6 +4697,13 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, perf_cntr_base + i, 0); kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0); } + if (env->features[FEAT_1_EDX] & CPUID_DTS) { + kvm_msr_entry_add(cpu, MSR_IA32_DS_AREA, 0); + } + if (env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_PEBS_BASELINE= ) { + kvm_msr_entry_add(cpu, MSR_IA32_PEBS_ENABLE, 0); + kvm_msr_entry_add(cpu, MSR_PEBS_DATA_CFG, 0); + } } =20 if (env->mcg_cap) { @@ -5013,6 +5029,15 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] =3D msrs[i].data; break; + case MSR_IA32_DS_AREA: + env->msr_ds_area =3D msrs[i].data; + break; + case MSR_PEBS_DATA_CFG: + env->msr_pebs_data_cfg =3D msrs[i].data; + break; + case MSR_IA32_PEBS_ENABLE: + env->msr_pebs_enable =3D msrs[i].data; + break; case HV_X64_MSR_HYPERCALL: env->msr_hv_hypercall =3D msrs[i].data; break; diff --git a/target/i386/machine.c b/target/i386/machine.c index 7d08a05835fc..7f45db1247b1 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -659,6 +659,27 @@ static const VMStateDescription vmstate_msr_ia32_featu= re_control =3D { } }; =20 +static bool ds_pebs_enabled(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return (env->msr_ds_area || env->msr_pebs_enable || + env->msr_pebs_data_cfg); +} + +static const VMStateDescription vmstate_msr_ds_pebs =3D { + .name =3D "cpu/msr_ds_pebs", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D ds_pebs_enabled, + .fields =3D (const VMStateField[]){ + VMSTATE_UINT64(env.msr_ds_area, X86CPU), + VMSTATE_UINT64(env.msr_pebs_data_cfg, X86CPU), + VMSTATE_UINT64(env.msr_pebs_enable, X86CPU), + VMSTATE_END_OF_LIST()} +}; + static bool pmu_enable_needed(void *opaque) { X86CPU *cpu =3D opaque; @@ -697,7 +718,11 @@ static const VMStateDescription vmstate_msr_architectu= ral_pmu =3D { VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS), VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS), VMSTATE_END_OF_LIST() - } + }, + .subsections =3D (const VMStateDescription * const []) { + &vmstate_msr_ds_pebs, + NULL, + }, }; =20 static bool mpx_needed(void *opaque) --=20 2.52.0 From nobody Sat Feb 7 07:25:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1769642382; cv=none; d=zohomail.com; s=zohoarc; b=dlte1r8fg5HVmJIBiQZQdLNwagDQGP+6cVRMV50E/HL5YIG2dz1IWkVZUHVwcjN2Aj2AlPGcqCZwPo+Y+P257Zhp6yJUV3xMYq/oDLsyLLPlCFJQQVNsjIULSWBS3+H5xpT1o134yXoSXK5ESKAcCBcI+kj4ZoDFNeXsf0mcCyk= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.13; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1769642383076158500 Content-Type: text/plain; charset="utf-8" Populate selected PEBS feature names in FEAT_PERF_CAPABILITIES to make the corresponding bits user-visible CPU feature knobs, allowing them to be explicitly enabled or disabled via -cpu +/-. Once named, these bits become part of the guest CPU configuration contract. If a VM is configured with such a feature enabled, migration to a destination that does not support the feature may fail, as the destination cannot honor the guest-visible CPU model. The PEBS_FMT bits are not exposed, as target/i386 currently does not support multi-bit CPU properties. Co-developed-by: Dapeng Mi Signed-off-by: Dapeng Mi Signed-off-by: Zide Chen --- V2: - Add the missing comma after "pebs-arch-reg". - Simplify the PEBS_FMT description in the commit message. target/i386/cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d3e9d3c40b0a..f2c83b4f259c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1618,10 +1618,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = =3D { .type =3D MSR_FEATURE_WORD, .feat_names =3D { NULL, NULL, NULL, NULL, + NULL, NULL, "pebs-trap", "pebs-arch-reg", NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, "full-width-write", NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, "full-width-write", "pebs-baseline", NULL, + NULL, "pebs-timing-info", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, --=20 2.52.0 From nobody Sat Feb 7 07:25:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="73462339" X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="73462339" X-CSE-ConnectionGUID: eFMJHCByREqk9Vkmu5E7eA== X-CSE-MsgGUID: baSQ/vM4SuSE2jwU1xiMYg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="208001782" From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: Xiaoyao Li , Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH V2 08/11] target/i386: Clean up LBR format handling Date: Wed, 28 Jan 2026 15:09:45 -0800 Message-ID: <20260128231003.268981-9-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260128231003.268981-1-zide.chen@intel.com> References: <20260128231003.268981-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.13; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1769642363820154100 Content-Type: text/plain; charset="utf-8" Since the lbr-fmt property is masked with PERF_CAP_LBR_FMT in DEFINE_PROP_UINT64_CHECKMASK(), there is no need to explicitly validate user-requested lbr-fmt values. The PMU feature is only supported when running under KVM, so initialize cpu->lbr_fmt in kvm_cpu_instance_init(). Use -1 as the default lbr-fmt, rather than initializing it with ~PERF_CAP_LBR_FMT, which is misleading as it suggests a semantic relationship that does not exist. Rename requested_lbr_fmt to a more generic guest_fmt. When lbr-fmt is not specified and cpu->migratable is false, the guest lbr_fmt value is not user-requested. Signed-off-by: Zide Chen --- V2: - New patch. target/i386/cpu.c | 18 ++++++------------ target/i386/kvm/kvm-cpu.c | 2 ++ 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f2c83b4f259c..09180c718d58 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9788,7 +9788,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) X86CPUClass *xcc =3D X86_CPU_GET_CLASS(dev); CPUX86State *env =3D &cpu->env; Error *local_err =3D NULL; - unsigned requested_lbr_fmt; + unsigned guest_fmt; =20 if (!kvm_enabled()) cpu->enable_pmu =3D false; @@ -9828,11 +9828,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT * with user-provided setting. */ - if (cpu->lbr_fmt !=3D ~PERF_CAP_LBR_FMT) { - if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) !=3D cpu->lbr_fmt) { - error_setg(errp, "invalid lbr-fmt"); - return; - } + if (cpu->lbr_fmt !=3D -1) { env->features[FEAT_PERF_CAPABILITIES] &=3D ~PERF_CAP_LBR_FMT; env->features[FEAT_PERF_CAPABILITIES] |=3D cpu->lbr_fmt; } @@ -9841,9 +9837,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=3Don and * 3)vPMU LBR format matches that of host setting. */ - requested_lbr_fmt =3D - env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; - if (requested_lbr_fmt && kvm_enabled()) { + guest_fmt =3D env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; + if (guest_fmt) { uint64_t host_perf_cap =3D x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIE= S); unsigned host_lbr_fmt =3D host_perf_cap & PERF_CAP_LBR_FMT; @@ -9852,10 +9847,10 @@ static void x86_cpu_realizefn(DeviceState *dev, Err= or **errp) error_setg(errp, "vPMU: LBR is unsupported without pmu=3Don"); return; } - if (requested_lbr_fmt !=3D host_lbr_fmt) { + if (guest_fmt !=3D host_lbr_fmt) { error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not matc= h " "the host value (0x%x).", - requested_lbr_fmt, host_lbr_fmt); + guest_fmt, host_lbr_fmt); return; } } @@ -10279,7 +10274,6 @@ static void x86_cpu_initfn(Object *obj) object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); =20 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); - cpu->lbr_fmt =3D ~PERF_CAP_LBR_FMT; object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); =20 if (xcc->model) { diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index 33a8c26bc27c..b4500ab69f82 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -231,6 +231,8 @@ static void kvm_cpu_instance_init(CPUState *cs) kvm_cpu_max_instance_init(cpu); } =20 + cpu->lbr_fmt =3D -1; + kvm_cpu_xsave_init(); } =20 --=20 2.52.0 From nobody Sat Feb 7 07:25:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; 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d="scan'208";a="208001786" From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: Xiaoyao Li , Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH V2 09/11] target/i386: Refactor LBR format handling Date: Wed, 28 Jan 2026 15:09:46 -0800 Message-ID: <20260128231003.268981-10-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260128231003.268981-1-zide.chen@intel.com> References: <20260128231003.268981-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.13; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1769642351005158500 Content-Type: text/plain; charset="utf-8" Detach x86_cpu_pmu_realize() from x86_cpu_realizefn() to keep the latter focused and easier to follow. Introduce a dedicated helper, x86_cpu_apply_lbr_pebs_fmt(), in preparation for adding PEBS format support without duplicating code. Convert PERF_CAP_LBR_FMT into separate mask and shift macros to allow x86_cpu_apply_lbr_pebs_fmt() to be shared with PEBS format handling. No functional change intended Signed-off-by: Zide Chen --- V2: - New patch. target/i386/cpu.c | 94 +++++++++++++++++++++++++++++++---------------- target/i386/cpu.h | 3 +- 2 files changed, 65 insertions(+), 32 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 09180c718d58..54f04adb0b48 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9781,6 +9781,66 @@ static bool x86_cpu_update_smp_cache_topo(MachineSta= te *ms, X86CPU *cpu, } #endif =20 +static bool x86_cpu_apply_lbr_pebs_fmt(X86CPU *cpu, uint64_t host_perf_cap, + uint64_t user_req, bool is_lbr_fmt, + Error **errp) +{ + CPUX86State *env =3D &cpu->env; + uint64_t mask; + unsigned shift; + unsigned user_fmt; + const char *name; + + if (is_lbr_fmt) { + mask =3D PERF_CAP_LBR_FMT_MASK; + shift =3D PERF_CAP_LBR_FMT_SHIFT; + name =3D "lbr"; + } else { + return false; + } + + if (user_req !=3D -1) { + env->features[FEAT_PERF_CAPABILITIES] &=3D ~(mask << shift); + env->features[FEAT_PERF_CAPABILITIES] |=3D (user_req << shift); + } + + user_fmt =3D (env->features[FEAT_PERF_CAPABILITIES] >> shift) & mask; + + if (user_fmt) { + unsigned host_fmt =3D (host_perf_cap >> shift) & mask; + + if (!cpu->enable_pmu) { + error_setg(errp, "vPMU: %s is unsupported without pmu=3Don", n= ame); + return false; + } + if (user_fmt !=3D host_fmt) { + error_setg(errp, "vPMU: the %s-fmt value (0x%x) does not match= " + "the host value (0x%x).", + name, user_fmt, host_fmt); + return false; + } + } + + return true; +} + +static int x86_cpu_pmu_realize(X86CPU *cpu, Error **errp) +{ + uint64_t host_perf_cap =3D + x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); + + /* + * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT + * with user-provided setting. + */ + if (!x86_cpu_apply_lbr_pebs_fmt(cpu, host_perf_cap, + cpu->lbr_fmt, true, errp)) { + return -EINVAL; + } + + return 0; +} + static void x86_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -9788,7 +9848,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) X86CPUClass *xcc =3D X86_CPU_GET_CLASS(dev); CPUX86State *env =3D &cpu->env; Error *local_err =3D NULL; - unsigned guest_fmt; =20 if (!kvm_enabled()) cpu->enable_pmu =3D false; @@ -9824,35 +9883,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) goto out; } =20 - /* - * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT - * with user-provided setting. - */ - if (cpu->lbr_fmt !=3D -1) { - env->features[FEAT_PERF_CAPABILITIES] &=3D ~PERF_CAP_LBR_FMT; - env->features[FEAT_PERF_CAPABILITIES] |=3D cpu->lbr_fmt; - } - - /* - * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=3Don and - * 3)vPMU LBR format matches that of host setting. - */ - guest_fmt =3D env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; - if (guest_fmt) { - uint64_t host_perf_cap =3D - x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIE= S); - unsigned host_lbr_fmt =3D host_perf_cap & PERF_CAP_LBR_FMT; - - if (!cpu->enable_pmu) { - error_setg(errp, "vPMU: LBR is unsupported without pmu=3Don"); - return; - } - if (guest_fmt !=3D host_lbr_fmt) { - error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not matc= h " - "the host value (0x%x).", - guest_fmt, host_lbr_fmt); - return; - } + if (x86_cpu_pmu_realize(cpu, errp)) { + return; } =20 if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpui= d)) { @@ -10445,7 +10477,7 @@ static const Property x86_cpu_properties[] =3D { #endif DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), - DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_= FMT), + DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_= FMT_MASK), =20 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, HYPERV_SPINLOCK_NEVER_NOTIFY), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 3e2222e105bc..aa3c24e0ba13 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -420,7 +420,8 @@ typedef enum X86Seg { #define ARCH_CAP_TSX_CTRL_MSR (1<<7) =20 #define MSR_IA32_PERF_CAPABILITIES 0x345 -#define PERF_CAP_LBR_FMT 0x3f +#define PERF_CAP_LBR_FMT_MASK 0x3f +#define PERF_CAP_LBR_FMT_SHIFT 0x0 #define PERF_CAP_FULL_WRITE (1U << 13) #define PERF_CAP_PEBS_BASELINE (1U << 14) =20 --=20 2.52.0 From nobody Sat Feb 7 07:25:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 28 Jan 2026 18:18:01 -0500 Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2026 15:17:43 -0800 Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2026 15:17:42 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769642279; x=1801178279; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lBhmgOoCeHBQeHkVFHU09ZVdbzQMPRSBW0jjTwRm2OU=; b=MBV7VDzaaYuJFIBMLIJfrwa/O7Fs7nSr+exwCW2w+8SdPw+NQnNbEm/t 1Py/7WzMkzEtJIPoxnxgte3kZbJDlFDEq5XCmIh/G/65rKvcfZ1pJk03N ZchkpfA+hIjHRcbb327toAWErD4KQorQ5vuErmyBnnxXxatmJUTHtPNdl eX1b5pvY0or+yRXbYl7ZmZbSenUuUT++ksZCRiRpGALVvGiDKp5kg3kNA KxLVOC+Sej3SVP49OZRyfb3KJkm82Lbs6Cn0TnFokGdJAFbE7XXAZhmnI hHn1WY1U/Ma2/gRl9wv79wgmoHW2CPQO6S6MstabS8Tuz7r8vQiau/bNE Q==; X-CSE-ConnectionGUID: Xc6TaxecSIKmgh3dmrV2Ig== X-CSE-MsgGUID: 81v+N9y5QOCbX3vMhsHK/Q== X-IronPort-AV: E=McAfee;i="6800,10657,11685"; a="73462350" X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="73462350" X-CSE-ConnectionGUID: zpxgtPShSSOfhBkhCTjQ/Q== X-CSE-MsgGUID: CCQLBDU8TNeu5lOAgoME6A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="208001791" From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: Xiaoyao Li , Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH V2 10/11] target/i386: Add pebs-fmt CPU option Date: Wed, 28 Jan 2026 15:09:47 -0800 Message-ID: <20260128231003.268981-11-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260128231003.268981-1-zide.chen@intel.com> References: <20260128231003.268981-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.13; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1769642322960158500 Content-Type: text/plain; charset="utf-8" Similar to lbr-fmt, target/i386 does not support multi-bit CPU properties, so the PEBS record format cannot be exposed as a user-visible CPU feature. Add a pebs-fmt option to allow users to specify the PEBS format via the command line. Since the PEBS state is part of the vmstate, this option is considered migratable. With this option, PEBS can be enabled when migratable=3Don. Signed-off-by: Zide Chen --- V2: New patch target/i386/cpu.c | 11 ++++++++++- target/i386/cpu.h | 5 +++++ target/i386/kvm/kvm-cpu.c | 1 + 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 54f04adb0b48..ec6f49916de3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9796,7 +9796,9 @@ static bool x86_cpu_apply_lbr_pebs_fmt(X86CPU *cpu, u= int64_t host_perf_cap, shift =3D PERF_CAP_LBR_FMT_SHIFT; name =3D "lbr"; } else { - return false; + mask =3D PERF_CAP_PEBS_FMT_MASK; + shift =3D PERF_CAP_PEBS_FMT_SHIFT; + name =3D "pebs"; } =20 if (user_req !=3D -1) { @@ -9838,6 +9840,11 @@ static int x86_cpu_pmu_realize(X86CPU *cpu, Error **= errp) return -EINVAL; } =20 + if (!x86_cpu_apply_lbr_pebs_fmt(cpu, host_perf_cap, + cpu->pebs_fmt, false, errp)) { + return -EINVAL; + } + return 0; } =20 @@ -10307,6 +10314,7 @@ static void x86_cpu_initfn(Object *obj) =20 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); + object_property_add_alias(obj, "pebs_fmt", obj, "pebs-fmt"); =20 if (xcc->model) { x86_cpu_load_model(cpu, xcc->model); @@ -10478,6 +10486,7 @@ static const Property x86_cpu_properties[] =3D { DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_= FMT_MASK), + DEFINE_PROP_UINT64_CHECKMASK("pebs-fmt", X86CPU, pebs_fmt, PERF_CAP_PE= BS_FMT_MASK), =20 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, HYPERV_SPINLOCK_NEVER_NOTIFY), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index aa3c24e0ba13..5ab107dfa29f 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -422,6 +422,8 @@ typedef enum X86Seg { #define MSR_IA32_PERF_CAPABILITIES 0x345 #define PERF_CAP_LBR_FMT_MASK 0x3f #define PERF_CAP_LBR_FMT_SHIFT 0x0 +#define PERF_CAP_PEBS_FMT_MASK 0xf +#define PERF_CAP_PEBS_FMT_SHIFT 0x8 #define PERF_CAP_FULL_WRITE (1U << 13) #define PERF_CAP_PEBS_BASELINE (1U << 14) =20 @@ -2399,6 +2401,9 @@ struct ArchCPU { */ uint64_t lbr_fmt; =20 + /* PEBS_FMT bits in IA32_PERF_CAPABILITIES MSR. */ + uint64_t pebs_fmt; + /* LMCE support can be enabled/disabled via cpu option 'lmce=3Don/off'= . It is * disabled by default to avoid breaking migration between QEMU with * different LMCE configurations. diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index b4500ab69f82..7029629a9d09 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -232,6 +232,7 @@ static void kvm_cpu_instance_init(CPUState *cs) } =20 cpu->lbr_fmt =3D -1; + cpu->pebs_fmt =3D -1; =20 kvm_cpu_xsave_init(); } --=20 2.52.0 From nobody Sat Feb 7 07:25:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1769642336; cv=none; d=zohomail.com; s=zohoarc; b=bDQSSY9TNin2yWsJ3Feo6kYwvMLZ2p7yfRaG355K7XA4zSTA9aztlf6IcJlqLhRkJIsGuhkqwywk+KiKbY2EZJIuVA1/5qwSsbJPGgYwxwznS8kuuXLy7N7uSZlzCzDg4AgPfA6QkqeIAF0tvBRxqIMBzS6Dyy1LIMxT012BJDs= ARC-Message-Signature: i=1; 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bh=6+39BohlqHVgxOCjKzqyCTw+ClCJeAPxpVGdX6TNBB4=; b=AujTmIFuu8DbyLPcbsg/4JjBaZO421ax9bClmeePQfjD9bO0c6uA3hgD NJBYtdCMG+6IAi7pgGy9ItrGVvR5XbLVGHPsm0g+tUz3JxZMlNnVjcH54 g3L6VfStw0S+w6H2/tXe5x7ES3cHU+7CpWgVujMKfcA3fBfeIH5Mzi4Ih myiT1OOqbr3ZX6YVlEPLtRNb/0SBVvm8HtSBqhb82W/DeL+sFOHk1sqlw k9bSLqSJPyQt4V1wPabOBVdXR/B/Grg2zwXvJ4hHGiLB2A0gBbgmEm6Ko s7id1Z9i7MPe2PCtgfehVI51rw9JXBFnXJdkP96qrpLYb2zj862ch7WOY w==; X-CSE-ConnectionGUID: dcUP9UnqQAiROYFvvC1i+A== X-CSE-MsgGUID: E++6xh7lTgKc+0N1WxorlQ== X-IronPort-AV: E=McAfee;i="6800,10657,11685"; a="73462354" X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="73462354" X-CSE-ConnectionGUID: sh1uBdSpQ7ak5CJQl2wDHA== X-CSE-MsgGUID: 0sB7ehxMQbiQhy6+npxnnA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="208001794" From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: Xiaoyao Li , Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH V2 11/11] target/i386: Disable guest PEBS capability when not enabled Date: Wed, 28 Jan 2026 15:09:48 -0800 Message-ID: <20260128231003.268981-12-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260128231003.268981-1-zide.chen@intel.com> References: <20260128231003.268981-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.13; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1769642338566154101 Content-Type: text/plain; charset="utf-8" When PMU is disabled, guest CPUID must not advertise Debug Store support. Clear both CPUID.01H:EDX[21] (DS) and CPUID.01H:ECX[2] (DS64) in this case. Set IA32_MISC_ENABLE[12] (PEBS_UNAVAILABLE) when Debug Store is not exposed to the guest. Note: Do not infer that PEBS is unsupported from IA32_PERF_CAPABILITIES[11:8] (PEBS_FMT) being 0. A value of 0 is a valid PEBS record format on some CPUs. Signed-off-by: Zide Chen --- V2: - New patch. target/i386/cpu.c | 6 ++++++ target/i386/cpu.h | 1 + 2 files changed, 7 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ec6f49916de3..445361ab7a06 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9180,6 +9180,10 @@ static void x86_cpu_reset_hold(Object *obj, ResetTyp= e type) env->msr_ia32_misc_enable |=3D MSR_IA32_MISC_ENABLE_MWAIT; } =20 + if (!(env->features[FEAT_1_EDX] & CPUID_DTS)) { + env->msr_ia32_misc_enable |=3D MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL; + } + memset(env->dr, 0, sizeof(env->dr)); env->dr[6] =3D DR6_FIXED_1; env->dr[7] =3D DR7_FIXED_1; @@ -9474,6 +9478,8 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **err= p) env->features[FEAT_1_ECX] &=3D ~CPUID_EXT_PDCM; } =20 + env->features[FEAT_1_ECX] &=3D ~CPUID_EXT_DTES64; + env->features[FEAT_1_EDX] &=3D ~CPUID_DTS; env->features[FEAT_7_0_EDX] &=3D ~CPUID_7_0_EDX_ARCH_LBR; } =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 5ab107dfa29f..0fecf561173e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -483,6 +483,7 @@ typedef enum X86Seg { /* Indicates good rep/movs microcode on some processors: */ #define MSR_IA32_MISC_ENABLE_FASTSTRING (1ULL << 0) #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) +#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) #define MSR_IA32_MISC_ENABLE_DEFAULT (MSR_IA32_MISC_ENABLE_FASTSTRING = |\ MSR_IA32_MISC_ENABLE_BTS_UNAVAIL) --=20 2.52.0