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Tsirkin" , Roman Bolshakov , qemu-arm@nongnu.org, Ani Sinha , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Akihiko Odaki , Marcel Apfelbaum , Pedro Barbuda , Richard Henderson , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Shannon Zhao , Igor Mammedov , Cameron Esfahani , Alexander Graf , Peter Maydell , Eduardo Habkost , Phil Dennis-Jordan Subject: [PATCH v18 04/22] hw: arm: virt: rework MSI-X configuration Date: Tue, 27 Jan 2026 19:27:44 +0100 Message-ID: <20260127182805.73212-5-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260127182805.73212-1-mohamed@unpredictable.fr> References: <20260127182805.73212-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: u5NV0GV9FvmOVeFF2LQIw4QK53u0QnUa X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI3MDE1MCBTYWx0ZWRfXzB3YcezwbAld fRbMlJLDZXQ/BZ/f7fER/fT87glQVupDklF7uw5tDvkvLXDXbon/+6yqYAfVeTRwH6Ovg4osNms HnpvFUvwsilvlSM+pkImt8XlNwn2DtBIP+akvm7pe9jd8BRJrFRQ649NdWTlJuSqfD1X+sdQS6A IM7bhLNf6nt9RDlxx6GZuztNY3ZMKHhGnScvcWfrALffei20Ul67DX1dj9ek9tYYqDRAY6LY6kf pQ/EV7bcNb3+e3c84pprXUWQ/lxNGGiWP8baQVvBg8IDYo3JOuAHoe/rzB/LAqjyOYvxEbIf+4T dOSh3cdLXn0dxahjoUDTDwkjfCe48/D/xhaAsxNOeyoionf3upH2nQ+P3Z4MKE= X-Authority-Info-Out: v=2.4 cv=ZeUQ98VA c=1 sm=1 tr=0 ts=697903d0 cx=c_apl:c_apl_out:c_pps a=9OgfyREA4BUYbbCgc0Y0oA==:117 a=9OgfyREA4BUYbbCgc0Y0oA==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VD-kO_21I_MDUkMFtFkA:9 X-Proofpoint-GUID: u5NV0GV9FvmOVeFF2LQIw4QK53u0QnUa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-27_04,2026-01-27_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 spamscore=0 mlxlogscore=999 clxscore=1030 mlxscore=0 bulkscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 classifier=spam authscore=0 adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601270150 X-JNJ: AAAAAAAB4P70EILiCkv1yARKv4O7u8pA0DlY+j6rbVjdaoby5UpDwajoJeSsONRRnfath9Pu9UcoDe1P4SJorIA8/KKgxkhAWXKDJ+d74zyWRtYOvjSl6Uu92Kk6ih0B4KQJJjN6MHLXSj6sZSFsypc4Q0v+zv8awhGnk9DPQxAQcxyM5Fbc6ow3cvhYsrs901uuaOR10o8IOjj8CG1mguSanSbc9BSy02lgZp9WHkbnSTMx+GBak3//9TS94XinUY/z/lpNcuyxr4HRDvGbnEyGuHqqiZyHQrmgCOj1D32/gQaSrl9UGPeFXhn0ZrNDMBsc4XOyukd9khDvZzj45nKTv985sbiSVC854EQ3S+7I/DgUNHEYgUBza4ScgbnuDebZ4AMwZCc+YLz64upwdg7vR0LYmRC5iwcwf4QcLGc9WT0USGLUZ6+uiVB4nCIIudpB6jSJdD/A8GYOlMD6xVEb3fWcbS5elROyatLPb7oQzyBcB8BOhIBqE2wSF4lB/vLyz1w1Qd8CHAHn5crFizUOhc5laspJsIRV+zboXH7IJOR1aIXQK5+4pW7l5TPVw7piYUVn1y1X9z6bfxXaK4PjhrlifyfVgzrYfmx9fOWbN3JWkAgaBhKtP0sajH7yaW9hdLJUTO/eDKyJeY+m7gvtHa8ugUpws9fTLGzzrBFPuiOiUuv/kC1h+SwhXeCx4lzzsOhJAmXGoPX9EDUTUrHIdTgeifK6BxKFC2pgrr11QLfSk4pPb/VSEFiaJ9T5rXHO7sgOE4jNkfpjNq6pN/8V2yKmx5o2h0iPVIFI3XWuae3Ws8VIg2qxMWTjkcgA2u+wa803zzDEVjG4IMyFxEaQmlvWqACmfPQodcs12cmCnnOEPpR8TDbJvYz5tobNWEbf+Uqd8gmQp6PpbLNrsjd5RIzLiaw= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.71.92; envelope-from=mohamed@unpredictable.fr; helo=outbound.mr.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1769538964392158500 Content-Type: text/plain; charset="utf-8" Introduce a -M msi=3D argument to be able to control MSI-X support independ= ently from ITS, as part of supporting GICv3 + GICv2m platforms. Remove vms->its as it's no longer needed after that change. Signed-off-by: Mohamed Mediouni --- hw/arm/virt-acpi-build.c | 20 ++++--- hw/arm/virt.c | 112 ++++++++++++++++++++++++++++++++++++--- include/hw/arm/virt.h | 5 +- 3 files changed, 121 insertions(+), 16 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 03b4342574..f87bf1bf2f 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -473,7 +473,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) nb_nodes =3D num_smmus + 1; /* RC and SMMUv3 */ rc_mapping_count =3D rc_smmu_idmaps_len; =20 - if (vms->its) { + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { /* * Knowing the ID ranges from the RC to the SMMU, it's possibl= e to * determine the ID ranges from RC that go directly to ITS. @@ -484,7 +484,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) rc_mapping_count +=3D rc_its_idmaps->len; } } else { - if (vms->its) { + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { nb_nodes =3D 2; /* RC and ITS */ rc_mapping_count =3D 1; /* Direct map to ITS */ } else { @@ -499,7 +499,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ =20 - if (vms->its) { + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { /* Table 12 ITS Group Format */ build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Ty= pe */ node_size =3D 20 /* fixed header size */ + 4 /* 1 GIC ITS Identif= ier */; @@ -518,7 +518,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) int smmu_mapping_count, offset_to_id_array; int irq =3D sdev->irq; =20 - if (vms->its) { + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { smmu_mapping_count =3D 1; /* ITS Group node */ offset_to_id_array =3D SMMU_V3_ENTRY_SIZE; /* Just after the h= eader */ } else { @@ -611,7 +611,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } } =20 - if (vms->its) { + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { /* * Map bypassed (don't go through the SMMU) RIDs (input) to * ITS Group node directly: RC -> ITS. @@ -629,7 +629,9 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) * SMMU: RC -> ITS. * Output IORT node is the ITS Group node (the first node). */ - build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET); + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { + build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET= ); + } } =20 acpi_table_end(linker, &table); @@ -946,7 +948,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) memmap[VIRT_HIGH_GIC_REDIST2].si= ze); } =20 - if (vms->its) { + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { /* * ACPI spec, Revision 6.0 Errata A * (original 6.0 definition has invalid Length) @@ -960,7 +962,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].bas= e, 8); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ } - } else { + } + + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_GICV2M) { const uint16_t spi_base =3D vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BA= SE; =20 /* 5.2.12.16 GIC MSI Frame Structure */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 4badc1a734..3d7f02ce0e 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -737,7 +737,7 @@ static void create_its(VirtMachineState *vms) { DeviceState *dev; =20 - assert(vms->its); + assert(vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS); if (!kvm_irqchip_in_kernel() && !vms->tcg_its) { /* * Do nothing if ITS is neither supported by the host nor emulated= by @@ -957,9 +957,9 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) =20 fdt_add_gic_node(vms); =20 - if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && vms->its) { + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { create_its(vms); - } else if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { + } else if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_GICV2M) { create_v2m(vms); } } @@ -2132,6 +2132,36 @@ static void finalize_gic_version(VirtMachineState *v= ms) gics_supported, max_cpus); } =20 +static void finalize_msi_controller(VirtMachineState *vms) +{ + if (vms->msi_controller =3D=3D VIRT_MSI_LEGACY_OPT_ITS_OFF) { + if (vms->gic_version =3D=3D 2) { + vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; + } + else { + vms->msi_controller =3D VIRT_MSI_CTRL_NONE; + } + } + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_AUTO) { + if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { + vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; + } + else { + vms->msi_controller =3D VIRT_MSI_CTRL_ITS; + } + } + + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { + if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { + /* Older Qemu releases accepted this, but better to error. */ + error_report("GICv2 + ITS is an invalid configuration."); + exit(1); + } + } + + assert(vms->msi_controller !=3D VIRT_MSI_CTRL_AUTO); +} + /* * virt_post_cpus_gic_realized() must be called after the CPUs and * the GIC have both been realized. @@ -2251,6 +2281,7 @@ static void machvirt_init(MachineState *machine) * KVM is not available yet */ finalize_gic_version(vms); + finalize_msi_controller(vms); =20 if (vms->secure) { /* @@ -2700,18 +2731,76 @@ static void virt_set_highmem_mmio_size(Object *obj,= Visitor *v, extended_memmap[VIRT_HIGH_PCIE_MMIO].size =3D size; } =20 +static char *virt_get_msi(Object *obj, Error **errp) +{ + VirtMachineState *vms =3D VIRT_MACHINE(obj); + const char *val; + + switch (vms->msi_controller) { + case VIRT_MSI_CTRL_NONE: + case VIRT_MSI_LEGACY_OPT_ITS_OFF: + val =3D "off"; + break; + case VIRT_MSI_CTRL_ITS: + val =3D "its"; + break; + case VIRT_MSI_CTRL_GICV2M: + val =3D "gicv2m"; + break; + case VIRT_MSI_CTRL_AUTO: + val =3D "auto"; + break; + default: + g_assert_not_reached(); + } + return g_strdup(val); +} + +static void virt_set_msi(Object *obj, const char *value, Error **errp) +{ + ERRP_GUARD(); + VirtMachineState *vms =3D VIRT_MACHINE(obj); + + if (!strcmp(value, "auto")) { + vms->msi_controller =3D VIRT_MSI_CTRL_AUTO; /* Will be overriden l= ater */ + } else if (!strcmp(value, "its")) { + vms->msi_controller =3D VIRT_MSI_CTRL_ITS; + } else if (!strcmp(value, "gicv2m")) { + vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; + } else if (!strcmp(value, "none")) { + vms->msi_controller =3D VIRT_MSI_CTRL_NONE; + } else { + error_setg(errp, "Invalid msi value"); + error_append_hint(errp, "Valid values are auto, gicv2m, its, off\n= "); + } +} + static bool virt_get_its(Object *obj, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); =20 - return vms->its; + switch (vms->msi_controller) { + case VIRT_MSI_CTRL_AUTO: + case VIRT_MSI_CTRL_ITS: + return true; + case VIRT_MSI_CTRL_NONE: + case VIRT_MSI_CTRL_GICV2M: + case VIRT_MSI_LEGACY_OPT_ITS_OFF: + return false; + default: + g_assert_not_reached(); + } } =20 static void virt_set_its(Object *obj, bool value, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); =20 - vms->its =3D value; + if (value) { + vms->msi_controller =3D VIRT_MSI_CTRL_ITS; + } else { + vms->msi_controller =3D VIRT_MSI_LEGACY_OPT_ITS_OFF; + } } =20 static bool virt_get_dtb_randomness(Object *obj, Error **errp) @@ -3038,6 +3127,9 @@ static void virt_machine_device_pre_plug_cb(HotplugHa= ndler *hotplug_dev, db_start =3D base_memmap[VIRT_GIC_V2M].base; db_end =3D db_start + base_memmap[VIRT_GIC_V2M].size - 1; break; + case VIRT_MSI_CTRL_AUTO: + case VIRT_MSI_LEGACY_OPT_ITS_OFF: + g_assert_not_reached(); } resv_prop_str =3D g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", db_start, db_end, @@ -3438,6 +3530,12 @@ static void virt_machine_class_init(ObjectClass *oc,= const void *data) "Set on/off to enable/disable " "ITS instantiation"); =20 + object_class_property_add_str(oc, "msi", virt_get_msi, + virt_set_msi); + object_class_property_set_description(oc, "msi", + "Set MSI settings. " + "Valid values are auto/gicv2m/it= s/off"); + object_class_property_add_bool(oc, "dtb-randomness", virt_get_dtb_randomness, virt_set_dtb_randomness); @@ -3493,8 +3591,8 @@ static void virt_instance_init(Object *obj) vms->highmem_mmio =3D true; vms->highmem_redists =3D true; =20 - /* Default allows ITS instantiation */ - vms->its =3D true; + /* Default allows ITS instantiation if available */ + vms->msi_controller =3D VIRT_MSI_CTRL_AUTO; /* Allow ITS emulation if the machine version supports it */ vms->tcg_its =3D !vmc->no_tcg_its; =20 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 5907d41dbb..d384355c4a 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -101,6 +101,10 @@ typedef enum VirtIOMMUType { =20 typedef enum VirtMSIControllerType { VIRT_MSI_CTRL_NONE, + /* This value is overriden at runtime.*/ + VIRT_MSI_CTRL_AUTO, + /* Legacy option: its=3Doff provides a GICv2m when using GICv2 */ + VIRT_MSI_LEGACY_OPT_ITS_OFF, VIRT_MSI_CTRL_GICV2M, VIRT_MSI_CTRL_ITS, } VirtMSIControllerType; @@ -146,7 +150,6 @@ struct VirtMachineState { bool highmem_ecam; bool highmem_mmio; bool highmem_redists; - bool its; bool tcg_its; bool virt; bool ras; --=20 2.50.1 (Apple Git-155)