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[114.35.142.126]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-353f5f96293sm1414175a91.0.2026.01.26.22.37.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 22:37:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1769495876; x=1770100676; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fSipeGHekKq/Th8UdKMG6p6qZH5c26imSBj5IlO1nPg=; b=IxeVzypCDEYfEwSuEXG+MlnxLITo4+zMRIMS60RXSx2Iy7AY93jyY6vpfdEFEdeDtN GvyKKmvJDS+J2PaY18CTsIpr1usM9kOsD2QO8+ki+O60Z0FTrq8/G7M7ozZiYpCLD7Co hXI3X2vsc9FAJ9Gfs1nm1Fg0hjWu3zjk8bxxGHVVzjnjbEqHcHgr2Vv+IJiMtg3WModo cLp712o72IVPCn+uK2/xFuNVOoqFhP+iGmVeJF3XZqVzHNaAOvdX/Z6U5MYcWxqa2Pd/ lCgmyUM7D/2XjN4RMJD2S/XnK1LLqT+EDXHXCuJ8W5fJwkC6kfjuY8ibaJmPn93WTpKO cWSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769495876; x=1770100676; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=fSipeGHekKq/Th8UdKMG6p6qZH5c26imSBj5IlO1nPg=; b=fXRPuUL30F6ov1+/DKrVmZkZgRnk2y0pZToi3Wu5PKB+/MEfRNxJ2ueLkCPxHoT9E2 5aEROpoRKx5BWZ9n83VoDUk1ptxQ4Zi18sEIbo1w8YTbktI1xrCxyWSBR9KW/gIMnAAP Ac9xgPMV9wDCtxae6mZQY629YDYnAFm/exrOHgqqdy/JbmXH2A+0S743228hXVnMaeG6 T/wIlzk2wCiZ0YsRTB5zGyIlP62CPDBbg5E92kt1tDP5T8sx2S+4gtGCIZ9RPO9z7Kky n5CHSTOn/I8DW0EBTfSz0UeLCsT2+AeqINPxmwdATMoul4UXPJg6HPGhe1bbyObAmUaf qGBA== X-Gm-Message-State: AOJu0Yy7zqVrVLbRW5uJcQ9VF84dj0onWzzTAYRy2MCgCcx1IUR6k5Ii /3jzbQs+6lSmW3nqNXVTs+K02Oh4ilHUAdnwswR6QYbcmoK3Dcpp+fqyvrvyf+F6cytfDgsohRf fjA0wB0DVbe7d1+eM70hIaUZXvKpwNGFNi/gZe0UKvYhpy6KdCMhElXCLg+pUo26HRfxBUkwHOA wV2BEYU4B9iPNFCx9wUMolsiPFk6mAYZHMWhQMFae6lg== X-Gm-Gg: AZuq6aKWW20+lCdzbjQygvTZbOTofAK5LmObOXTfNllV9x1S0nwN0OTeSEz9FmHnL+f eNJjdxrHBaNbfPBAwppEIlkW4ODBb5JKYFWSc3iJsjSLUfME1uCY0tyCv7Gmltfdc8Lq04hunli seFijkJ7t9JEoqiWMC3V1ypvVS4P1KPNi9X8TujGq1AFZ6fHoBMldwCy3o+rkTvSJKX++WPucMl PhfAOBCeNtT4AIHYdzYpgKbmnoyGA9hDUNQAfDtk2pKvTYYzOUDkftGiDcukX6qgNkJnPOuYI2O O4mbzeFkrFkNUIh6dd0jSpT2K+jKSN0InDOtu+/R86kb7NjtHsWF6R+ClG4inOBXFemAIRzkvx7 noQbA+420nWOrt8wAm8WxSHWWisZy65/3tUOWeOj0uH0+k326q5vtpoMDcQtyAqIrVG3hVqnLyN P2GI9bsh84hi8Iq6Im847Na+bo0L9LaV/3gKp8fGVaWEdtsoz+WZynMuwITao2i84oVwU59N440 wsCIO3E/EXOJxU= X-Received: by 2002:a17:903:906:b0:2a7:c340:4c3d with SMTP id d9443c01a7336-2a870d58b2fmr6918555ad.13.1769495876008; Mon, 26 Jan 2026 22:37:56 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Aurelien Jarno , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , richard.henderson@linaro.org, Max Chou , Alistair Francis Subject: [PATCH v2 10/17] target/riscv: rvv: Add vfncvt.f.f.q and vfncvt.sat.f.f.q instructions for Zvfofp8min extension Date: Tue, 27 Jan 2026 14:37:16 +0800 Message-ID: <20260127063723.442734-11-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260127063723.442734-1-max.chou@sifive.com> References: <20260127063723.442734-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=max.chou@sifive.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1769496014920154100 Content-Type: text/plain; charset="utf-8" The vfncvt.f.f.q and vfncvt.sat.f.f.q instructions convert a vector of FP32 elements to a vector of OFP8 elements. The vfncvt.sat.f.fq instruction converts a vector of FP32 elements to a vector of OFP8 elements with satura= tion. The VTYPE.altfmt field is used to select the OFP8 format. * altfmt =3D 0: FP32 to OFP8.e4m3 * altfmt =3D 1: FP32 to OFP8.e5m2 Signed-off-by: Max Chou --- target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvofp8.c.inc | 63 ++++++++++++++++++++++ target/riscv/insn_trans/trans_rvv.c.inc | 39 ++++++++++++++ 3 files changed, 104 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 49201c0c20..f2b413c7d4 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -974,6 +974,8 @@ vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 101011= 1 @r_vm vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm =20 # *** Zvfofp8min Extension *** +vfncvt_f_f_q 010010 . ..... 11001 001 ..... 1010111 @r2_vm +vfncvt_sat_f_f_q 010010 . ..... 11011 001 ..... 1010111 @r2_vm vfncvtbf16_sat_f_f_w 010010 . ..... 11111 001 ..... 1010111 @r2_vm =20 # *** Zvbc vector crypto extension *** diff --git a/target/riscv/insn_trans/trans_rvofp8.c.inc b/target/riscv/insn= _trans/trans_rvofp8.c.inc index f1a7b0affd..8851209660 100644 --- a/target/riscv/insn_trans/trans_rvofp8.c.inc +++ b/target/riscv/insn_trans/trans_rvofp8.c.inc @@ -12,6 +12,13 @@ } \ } while (0) =20 +static bool zvfofp8min_narrow_quad_check(DisasContext *s, arg_rmr *a) +{ + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_sq(s, a->rd, a->rs2, a->vm) && + (s->sew =3D=3D MO_8); +} =20 static bool trans_vfncvtbf16_sat_f_f_w(DisasContext *ctx, arg_rmr *a) { @@ -41,3 +48,59 @@ static bool trans_vfncvtbf16_sat_f_f_w(DisasContext *ctx= , arg_rmr *a) return false; } =20 +static bool trans_vfncvt_f_f_q(DisasContext *ctx, arg_rmr *a) +{ + REQUIRE_FPU; + REQUIRE_ZVFOFP8MIN(ctx); + + if (zvfofp8min_narrow_quad_check(ctx, a)) { + gen_helper_gvec_3_ptr *fn; + uint32_t data =3D 0; + + fn =3D ctx->altfmt ? gen_helper_vfncvt_f_f_q_ofp8e5m2 : + gen_helper_vfncvt_f_f_q_ofp8e4m3; + + gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); + + data =3D FIELD_DP32(data, VDATA, VM, a->vm); + data =3D FIELD_DP32(data, VDATA, LMUL, ctx->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, ctx->vta); + data =3D FIELD_DP32(data, VDATA, VMA, ctx->vma); + tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), + vreg_ofs(ctx, a->rs2), tcg_env, + ctx->cfg_ptr->vlenb, + ctx->cfg_ptr->vlenb, data, fn); + finalize_rvv_inst(ctx); + return true; + } + return false; +} + +static bool trans_vfncvt_sat_f_f_q(DisasContext *ctx, arg_rmr *a) +{ + REQUIRE_FPU; + REQUIRE_ZVFOFP8MIN(ctx); + + if (zvfofp8min_narrow_quad_check(ctx, a)) { + gen_helper_gvec_3_ptr *fn; + uint32_t data =3D 0; + + fn =3D ctx->altfmt ? gen_helper_vfncvt_sat_f_f_q_ofp8e5m2 : + gen_helper_vfncvt_sat_f_f_q_ofp8e4m3; + + gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); + + data =3D FIELD_DP32(data, VDATA, VM, a->vm); + data =3D FIELD_DP32(data, VDATA, LMUL, ctx->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, ctx->vta); + data =3D FIELD_DP32(data, VDATA, VMA, ctx->vma); + tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), + vreg_ofs(ctx, a->rs2), tcg_env, + ctx->cfg_ptr->vlenb, + ctx->cfg_ptr->vlenb, data, fn); + finalize_rvv_inst(ctx); + return true; + } + return false; +} + diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index bcd45b0aa3..9053b9fb57 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -621,6 +621,45 @@ static bool vext_check_sds(DisasContext *s, int vd, in= t vs1, int vs2, int vm) require_align(vs1, s->lmul); } =20 +/* + * Common check function for vector narrowing instructions + * of single-width result (SEW) and quad-width source (4*SEW). + * + * Rules to be checked here: + * 1. The largest vector register group used by an instruction + * can not be greater than 8 vector registers + * (Section 31.5.2) + * 2. Quad-width SEW cannot greater than ELEN. + * (Section 31.2) + * 3. Source vector register number is multiples of 4 * LMUL. + * (Section 31.3.4.2) + * 4. Destination vector register number is multiples of LMUL. + * (Section 31.3.4.2) + * 5. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 31.5.3) + * risc-v unprivileged spec + */ +static bool vext_quad_narrow_check_common(DisasContext *s, int vd, int vs2, + int vm) +{ + return (s->lmul <=3D 1) && + (s->sew < MO_32) && + ((s->sew + 2) <=3D (s->cfg_ptr->elen >> 4)) && + require_align(vs2, s->lmul + 2) && + require_align(vd, s->lmul) && + require_vm(vm, vd); +} + +static bool vext_check_sq(DisasContext *s, int vd, int vs, int vm) +{ + bool ret =3D vext_quad_narrow_check_common(s, vd, vs, vm); + if (vd !=3D vs) { + ret &=3D require_noover(vd, s->lmul, vs, s->lmul + 2); + } + return ret; +} + /* * Check function for vector reduction instructions. * --=20 2.52.0