From nobody Sat Feb 7 07:11:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1769484379; cv=none; d=zohomail.com; s=zohoarc; b=JS7RB/u/+yiZVfCPbyJ2yxzrIm5+IY2lTx+bmphnFOtl4OoB/fvyvCBPYLYiQK8sJtxNiHOEC7QZGjxcSJ8XGftDpm5TIOZTYFRXgSlnS4tV7nWr8qyojVlJC+LJT4UkcILomtVyNm2jTyP5lCb/d9ghRnTZcBq0Bmq+TtnWEgc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769484379; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=VSYqENRb+XbovmHlJuduCVf2XK4u0MR/Q77XeZeOePs=; b=kUlePwxEZvWR3dSOypf0lNhqUTMRfqHbvYtzw+Iru4XVCkO4jlbRpgVqEPc3nhlJdCco1HvFxsqb86q/k+snarf+mgEgis9ode7TbVrz1Z8ooeQp+P3NYaDMnf8fZ4y+zmH/m4cPnKJxSyHDlf5lC7JLeagFeyDpiNCzbMlehPk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769484379004122.78128745297863; Mon, 26 Jan 2026 19:26:19 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkZgW-0004Hp-Jo; Mon, 26 Jan 2026 22:24:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkZgV-0004Gn-2m; Mon, 26 Jan 2026 22:24:07 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkZgT-0003Z2-Lp; Mon, 26 Jan 2026 22:24:06 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 27 Jan 2026 11:23:49 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 27 Jan 2026 11:23:49 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 3/7] hw/pci-host/aspeed_pcie: Drop AST2600 RC_H root-bus remap and bus-nr property Date: Tue, 27 Jan 2026 11:23:39 +0800 Message-ID: <20260127032348.2238527-4-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260127032348.2238527-1-jamin_lin@aspeedtech.com> References: <20260127032348.2238527-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1769484380022158500 Content-Type: text/plain; charset="utf-8" The original AST2600 PCIe design supported both RC_L and RC_H, using root b= us number 0 for RC_L and 0x80 for RC_H. In that model, the root port appeared = as 80:08.0 and QEMU carried a "bus-nr" property plus a config-space bus remap = to translate bus 0x80 to bus 0x00 for PCI enumeration. Linux mainline has since dropped RC_L support and updated the RC_H root bus number to start at 0. The root port is now enumerated as 00:08.0, matching = the default QEMU PCIe subsystem root bus numbering. Remove the bus number setting and the AST2600 bus remap logic, and drop the corresponding "bus-nr"/rc_bus_nr fields and property plumbing. QEMU now rel= ies on the default root bus 0 behavior. Signed-off-by: Jamin Lin --- include/hw/pci-host/aspeed_pcie.h | 2 -- hw/pci-host/aspeed_pcie.c | 19 +------------------ 2 files changed, 1 insertion(+), 20 deletions(-) diff --git a/include/hw/pci-host/aspeed_pcie.h b/include/hw/pci-host/aspeed= _pcie.h index fde5816ea3..143b356591 100644 --- a/include/hw/pci-host/aspeed_pcie.h +++ b/include/hw/pci-host/aspeed_pcie.h @@ -69,7 +69,6 @@ struct AspeedPCIERcState { uint64_t dram_base; uint32_t msi_addr; uint32_t rp_addr; - uint32_t bus_nr; char name[16]; qemu_irq irq; =20 @@ -102,7 +101,6 @@ struct AspeedPCIECfgClass { =20 uint32_t rc_msi_addr; uint32_t rc_rp_addr; - uint64_t rc_bus_nr; uint64_t nr_regs; bool rc_has_rd; }; diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c index 4fdda95939..4f896f855c 100644 --- a/hw/pci-host/aspeed_pcie.c +++ b/hw/pci-host/aspeed_pcie.c @@ -268,7 +268,7 @@ static const char *aspeed_pcie_rc_root_bus_path(PCIHost= State *host_bridge, AspeedPCIECfgState *cfg =3D container_of(rc, AspeedPCIECfgState, rc); =20 - snprintf(rc->name, sizeof(rc->name), "%04x:%02x", cfg->id, rc->bus_nr); + snprintf(rc->name, sizeof(rc->name), "%04x:00", cfg->id); =20 return rc->name; } @@ -283,7 +283,6 @@ static void aspeed_pcie_rc_instance_init(Object *obj) } =20 static const Property aspeed_pcie_rc_props[] =3D { - DEFINE_PROP_UINT32("bus-nr", AspeedPCIERcState, bus_nr, 0), DEFINE_PROP_UINT32("rp-addr", AspeedPCIERcState, rp_addr, 0), DEFINE_PROP_UINT32("msi-addr", AspeedPCIERcState, msi_addr, 0), DEFINE_PROP_UINT64("dram-base", AspeedPCIERcState, dram_base, 0), @@ -490,17 +489,6 @@ static void aspeed_pcie_cfg_readwrite(AspeedPCIECfgSta= te *s, offset =3D cfg_addr & 0xffc; =20 pci =3D PCI_HOST_BRIDGE(rc); - - /* - * On the AST2600, the RC_H bus number range from 0x80 to 0xFF, with t= he - * root device and root port assigned to bus 0x80 instead of the stand= ard - * 0x00. To allow the PCI subsystem to correctly discover devices on t= he - * root bus, bus 0x80 is remapped to 0x00. - */ - if (bus =3D=3D rc->bus_nr) { - bus =3D 0; - } - pdev =3D pci_find_device(pci->bus, bus, devfn); if (!pdev) { s->regs[desc->rdata_reg] =3D ~0; @@ -650,9 +638,6 @@ static void aspeed_pcie_cfg_realize(DeviceState *dev, E= rror **errp) apc->nr_regs << 2); sysbus_init_mmio(sbd, &s->mmio); =20 - object_property_set_int(OBJECT(&s->rc), "bus-nr", - apc->rc_bus_nr, - &error_abort); object_property_set_int(OBJECT(&s->rc), "rp-addr", apc->rc_rp_addr, &error_abort); @@ -691,7 +676,6 @@ static void aspeed_pcie_cfg_class_init(ObjectClass *kla= ss, const void *data) apc->reg_map =3D &aspeed_regmap; apc->nr_regs =3D 0x100 >> 2; apc->rc_msi_addr =3D 0x1e77005C; - apc->rc_bus_nr =3D 0x80; apc->rc_rp_addr =3D PCI_DEVFN(8, 0); } =20 @@ -811,7 +795,6 @@ static void aspeed_2700_pcie_cfg_class_init(ObjectClass= *klass, apc->reg_map =3D &aspeed_2700_regmap; apc->nr_regs =3D 0x100 >> 2; apc->rc_msi_addr =3D 0x000000F0; - apc->rc_bus_nr =3D 0; apc->rc_rp_addr =3D PCI_DEVFN(0, 0); } =20 --=20 2.43.0