From nobody Sat Feb 7 07:11:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1769484315; cv=none; d=zohomail.com; s=zohoarc; b=QW5jNCGHnFs4zt2qxqJTES6vc5Jh2GPj7CcBl/ZpuE8KbTHGz63MfBA9IBtKs3xBuJC49imOwwNH++zh6KfF/nJVLoND1dNMktvV5cBF7VKPYAoE90WN0Ds+NgXePNoraJJFvcoRnZ0Dz1frtlOpkNuwQHsHdMmchAZ2n5LpOGM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769484315; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=uugYBQfRqmZfondB1bjZ+aLEvX7lIJlpl0QW9ezrXds=; b=Bww2vnie9Mxmeid3VD/Zzc9NbzZrCvh3ycsgDeS6zSLO9IhN0Fx/ryjZgR68ArzKigqVw5yY1Mt95t5GADKijeYRqxxhQDJrSjcDbIjt8ra3LnqBGaY+lhMRLsXcjs0JhSWosZta2y1AWMJuMNvJOiyQbduYUhtvTbO0eeGGI5M= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769484315259456.22717873588874; Mon, 26 Jan 2026 19:25:15 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkZgU-0004GB-K6; Mon, 26 Jan 2026 22:24:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkZgS-0004FV-Sz; Mon, 26 Jan 2026 22:24:04 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkZgR-0003Z2-Ar; Mon, 26 Jan 2026 22:24:04 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 27 Jan 2026 11:23:49 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 27 Jan 2026 11:23:49 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 2/7] hw/pci-host/aspeed_pcie: Drop AST2600 PCIe root device Date: Tue, 27 Jan 2026 11:23:38 +0800 Message-ID: <20260127032348.2238527-3-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260127032348.2238527-1-jamin_lin@aspeedtech.com> References: <20260127032348.2238527-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1769484318052158500 Content-Type: text/plain; charset="utf-8" AST2600 PCIe previously exposed a root bus at 0x80 with both a root device at 80:00.0 and a root port at 80:08.0. Recent ASPEED SDK PCIe driver updates decided to remove the root device and keep only a single root port. This behavior has already been accepted by the upstream Linux kernel. Update the QEMU PCIe model accordingly by dropping the root device implementation and related properties. AST2600 now matches the AST2700 PCIe topology and no longer supports the legacy RC_L layout. Signed-off-by: Jamin Lin --- include/hw/pci-host/aspeed_pcie.h | 9 ----- hw/pci-host/aspeed_pcie.c | 57 ------------------------------- 2 files changed, 66 deletions(-) diff --git a/include/hw/pci-host/aspeed_pcie.h b/include/hw/pci-host/aspeed= _pcie.h index e660119a45..fde5816ea3 100644 --- a/include/hw/pci-host/aspeed_pcie.h +++ b/include/hw/pci-host/aspeed_pcie.h @@ -50,13 +50,6 @@ typedef struct AspeedPCIERootPortState { PCIESlot parent_obj; } AspeedPCIERootPortState; =20 -#define TYPE_ASPEED_PCIE_ROOT_DEVICE "aspeed.pcie-root-device" -OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERootDeviceState, ASPEED_PCIE_ROOT_DEV= ICE); - -struct AspeedPCIERootDeviceState { - PCIBridge parent_obj; -}; - #define TYPE_ASPEED_PCIE_RC "aspeed.pcie-rc" OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERcState, ASPEED_PCIE_RC); =20 @@ -78,10 +71,8 @@ struct AspeedPCIERcState { uint32_t rp_addr; uint32_t bus_nr; char name[16]; - bool has_rd; qemu_irq irq; =20 - AspeedPCIERootDeviceState root_device; AspeedPCIERootPortState root_port; }; =20 diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c index 83a1c7075c..4fdda95939 100644 --- a/hw/pci-host/aspeed_pcie.c +++ b/hw/pci-host/aspeed_pcie.c @@ -26,44 +26,6 @@ #include "hw/pci/msi.h" #include "trace.h" =20 -/* - * PCIe Root Device - * This device exists only on AST2600. - */ - -static void aspeed_pcie_root_device_class_init(ObjectClass *klass, - const void *data) -{ - PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); - DeviceClass *dc =3D DEVICE_CLASS(klass); - - set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); - dc->desc =3D "ASPEED PCIe Root Device"; - k->vendor_id =3D PCI_VENDOR_ID_ASPEED; - k->device_id =3D 0x2600; - k->class_id =3D PCI_CLASS_BRIDGE_HOST; - k->subsystem_vendor_id =3D k->vendor_id; - k->subsystem_id =3D k->device_id; - k->revision =3D 0; - - /* - * PCI-facing part of the host bridge, - * not usable without the host-facing part - */ - dc->user_creatable =3D false; -} - -static const TypeInfo aspeed_pcie_root_device_info =3D { - .name =3D TYPE_ASPEED_PCIE_ROOT_DEVICE, - .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(AspeedPCIERootDeviceState), - .class_init =3D aspeed_pcie_root_device_class_init, - .interfaces =3D (const InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, -}; - /* * PCIe Root Port */ @@ -291,18 +253,6 @@ static void aspeed_pcie_rc_realize(DeviceState *dev, E= rror **errp) &rc->dram_alias); pci_setup_iommu(pci->bus, &aspeed_pcie_rc_iommu_ops, rc); =20 - /* setup root device */ - if (rc->has_rd) { - object_initialize_child(OBJECT(rc), "root_device", &rc->root_devic= e, - TYPE_ASPEED_PCIE_ROOT_DEVICE); - qdev_prop_set_int32(DEVICE(&rc->root_device), "addr", - PCI_DEVFN(0, 0)); - qdev_prop_set_bit(DEVICE(&rc->root_device), "multifunction", false= ); - if (!qdev_realize(DEVICE(&rc->root_device), BUS(pci->bus), errp)) { - return; - } - } - /* setup root port */ qdev_prop_set_int32(DEVICE(&rc->root_port), "addr", rc->rp_addr); qdev_prop_set_uint16(DEVICE(&rc->root_port), "chassis", cfg->id); @@ -334,7 +284,6 @@ static void aspeed_pcie_rc_instance_init(Object *obj) =20 static const Property aspeed_pcie_rc_props[] =3D { DEFINE_PROP_UINT32("bus-nr", AspeedPCIERcState, bus_nr, 0), - DEFINE_PROP_BOOL("has-rd", AspeedPCIERcState, has_rd, 0), DEFINE_PROP_UINT32("rp-addr", AspeedPCIERcState, rp_addr, 0), DEFINE_PROP_UINT32("msi-addr", AspeedPCIERcState, msi_addr, 0), DEFINE_PROP_UINT64("dram-base", AspeedPCIERcState, dram_base, 0), @@ -704,9 +653,6 @@ static void aspeed_pcie_cfg_realize(DeviceState *dev, E= rror **errp) object_property_set_int(OBJECT(&s->rc), "bus-nr", apc->rc_bus_nr, &error_abort); - object_property_set_bool(OBJECT(&s->rc), "has-rd", - apc->rc_has_rd, - &error_abort); object_property_set_int(OBJECT(&s->rc), "rp-addr", apc->rc_rp_addr, &error_abort); @@ -746,7 +692,6 @@ static void aspeed_pcie_cfg_class_init(ObjectClass *kla= ss, const void *data) apc->nr_regs =3D 0x100 >> 2; apc->rc_msi_addr =3D 0x1e77005C; apc->rc_bus_nr =3D 0x80; - apc->rc_has_rd =3D true; apc->rc_rp_addr =3D PCI_DEVFN(8, 0); } =20 @@ -867,7 +812,6 @@ static void aspeed_2700_pcie_cfg_class_init(ObjectClass= *klass, apc->nr_regs =3D 0x100 >> 2; apc->rc_msi_addr =3D 0x000000F0; apc->rc_bus_nr =3D 0; - apc->rc_has_rd =3D false; apc->rc_rp_addr =3D PCI_DEVFN(0, 0); } =20 @@ -1041,7 +985,6 @@ static const TypeInfo aspeed_2700_pcie_phy_info =3D { static void aspeed_pcie_register_types(void) { type_register_static(&aspeed_pcie_rc_info); - type_register_static(&aspeed_pcie_root_device_info); type_register_static(&aspeed_pcie_root_port_info); type_register_static(&aspeed_pcie_cfg_info); type_register_static(&aspeed_2700_pcie_cfg_info); --=20 2.43.0