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[114.35.142.126]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-353f6129426sm660121a91.7.2026.01.26.17.42.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 17:42:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1769478175; x=1770082975; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K9tuNH0GIG9QMRuzBZRQlmu2VdYAe2paJMYHOeqOgYg=; b=l5tqqbS9ioihzvWo6Lxm/MSil9IAnX0mattW9v0YUQQIBnK8CD+MjV9Nzs1l5zBwLJ dTjU+JH2y8bgtobbQRDXpFp7Hmgzsr0iD7G9sAzg/yIVb1vU507Mp8iMgZe7VeKAFIb2 1rohRRUubKQEdtcBBu5w2l8bjxn9ETJG/u5hMzsMJIe7w/aiF/vXuPqbd50JQOhrMEhr DEOxPRje1QAavq6bEQJ4kFaDBLjtoANy/vT6u02GAECDesukvbpdqy+seAwVRtNcXqjX FB5AWtbKEPf+wtRDxlLj836qsyv1UEqp8RLBuDUAoXlGL36NDviElXYsYTkgGgZl3Ymw lG/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769478175; x=1770082975; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=K9tuNH0GIG9QMRuzBZRQlmu2VdYAe2paJMYHOeqOgYg=; b=VQh+RmLibWtWs3INOnJaljG3HMFaJWOzfE52yd4mDDvvHQmrbGSdvqZ57RPcCnhdAq OjAotS9bXxLXeRX3JrtMrV4UgJpTljzrKsITlYKChUMKCy3tDT7YQqkCTyc+vicALTGJ v3E4XdCTh/o2vVAiUIi+ckCxbCVUGpsLXVM9LBtnZus5mLlN/lzGBiwXamcpojpRD5JG C+SF1t8sJUhlmpSy1RXf1GYElMQYStHqxyhemq6UOlqF635/5b1krUK3m+qmnfG0fo4a koLJPvpqQiJCVbuh8WMtvVLmy7qvAHdg1kepIRtdc5dRN+jWeHar5sbAKrgRWjpCTDrQ poVA== X-Gm-Message-State: AOJu0Yx4/6rWGQzcyoimqnFg70hhQtbVv9BaRad4vaUmaOaENYTzmrnw x0QNYDvlh1H7EdNk3YOjwlfGjR3XRcNCIu84nuqfiwn4cHdkwM2CC2o9WjiWzH6l7H6vIUGy8H9 n7jyLLApXz8u9tcy1xphnPs6oKgFVkg4rur507mXBVTzGZah8aYrz2uhZGIBKAMTiAfa2pjtUdM yvQ5vVHVT5jmvUimABvuQzsJbl09NE+E8pC944tjCvaw== X-Gm-Gg: AZuq6aKRJDSsVjFeL9Ft+lsBtrHBzX1n+i/pceWxKgfrTqTX5iIVkQ3OoiqK94/rgxg +br+eUxM68etnQOaUKfm1NM+IJTatOq7GBk0QVrPDtKkQLeNNQRh9Z0XnsxBWooxWBdUk3UiX6j 0o61invzPtapcPjCJgpvdHkjHiQTGrkxxPh0V2L3HJcFN5ez3Y83zP+PICaWR6kYtRq8PeRnRPm sQUjFM8fRvDJTrk/d60inSgstFt/GeG79lrXl68HuDnusTdfx+iuJajn4NHKAop1v+vlxAbkQlD ggOrByp5xOmEUzMjn9BlAUSMrsNFO4EHPMpFtnKGYh5HT2MoE10geZtdJrwrC1AWz4cuh6nmNMM b2pnu8HduB6m6DQ5wplTiGFBagj/4yjLynSHcF3jP+LklwX4hB0u8Z3L1QtsYIvC0yy8gaI/hGc Hdi9ng8OksgtjiWntKKkuYbhW/A9RL542jOh4p5TrBBPvPgcX2RhA7gSFBBs1YxoLy1/nW0vKzH EZmcIrfyj5Mw5U= X-Received: by 2002:a17:90b:1e51:b0:340:d578:f299 with SMTP id 98e67ed59e1d1-353fecdd09dmr223896a91.3.1769478175276; Mon, 26 Jan 2026 17:42:55 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Max Chou Subject: [PATCH v3 3/9] target/riscv: rvv: Add new VTYPE CSR field - altfmt Date: Tue, 27 Jan 2026 09:42:21 +0800 Message-ID: <20260127014227.406653-4-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260127014227.406653-1-max.chou@sifive.com> References: <20260127014227.406653-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=max.chou@sifive.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1769478329873154100 Content-Type: text/plain; charset="utf-8" According to the Zvfbfa ISA spec v0.1, the vtype CSR adds a new field: altfmt for BF16 support. This update changes the layout of the vtype CSR fields. - Removed VEDIV field (bits 8-9) since EDIV extension is not planned to be part of the base V extension - Added ALTFMT field at bit 8 - Changed RESERVED field to start from bit 9 instead of bit 10 When Zvfbfa is disabled, bits 8+ are treated as reserved (preserving existing behavior for altfmt bit). When Zvfbfa is enabled, only bits 9+ are reserved. Reference: - https://github.com/riscvarchive/riscv-v-spec/blob/master/ediv.adoc Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou --- target/riscv/cpu.h | 4 ++-- target/riscv/vector_helper.c | 29 ++++++++++++++++++++++++----- 2 files changed, 26 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 35d1f6362c..962cc45073 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -191,8 +191,8 @@ FIELD(VTYPE, VLMUL, 0, 3) FIELD(VTYPE, VSEW, 3, 3) FIELD(VTYPE, VTA, 6, 1) FIELD(VTYPE, VMA, 7, 1) -FIELD(VTYPE, VEDIV, 8, 2) -FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) +FIELD(VTYPE, ALTFMT, 8, 1) +FIELD(VTYPE, RESERVED, 9, sizeof(target_ulong) * 8 - 10) =20 typedef struct PMUCTRState { /* Current value of a counter */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 2de3358ee8..525a47bf66 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -33,6 +33,22 @@ #include "vector_internals.h" #include =20 +static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype) +{ + int xlen =3D riscv_cpu_xlen(env); + target_ulong reserved =3D 0; + + if (riscv_cpu_cfg(env)->ext_zvfbfa) { + reserved =3D vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, + xlen - 1 - R_VTYPE_RESERVED_SHI= FT); + } else { + reserved =3D vtype & MAKE_64BIT_MASK(R_VTYPE_ALTFMT_SHIFT, + xlen - 1 - R_VTYPE_ALTFMT_SHIFT= ); + } + + return reserved; +} + target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, target_ulong s2, target_ulong x0) { @@ -41,12 +57,9 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_u= long s1, uint64_t vlmul =3D FIELD_EX64(s2, VTYPE, VLMUL); uint8_t vsew =3D FIELD_EX64(s2, VTYPE, VSEW); uint16_t sew =3D 8 << vsew; - uint8_t ediv =3D FIELD_EX64(s2, VTYPE, VEDIV); + uint8_t altfmt =3D FIELD_EX64(s2, VTYPE, ALTFMT); int xlen =3D riscv_cpu_xlen(env); bool vill =3D (s2 >> (xlen - 1)) & 0x1; - target_ulong reserved =3D s2 & - MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, - xlen - 1 - R_VTYPE_RESERVED_SH= IFT); uint16_t vlen =3D cpu->cfg.vlenb << 3; int8_t lmul; =20 @@ -63,7 +76,13 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_u= long s1, } } =20 - if ((sew > cpu->cfg.elen) || vill || (ediv !=3D 0) || (reserved !=3D 0= )) { + if (cpu->cfg.ext_zvfbfa) { + if (altfmt =3D=3D 1 && vsew >=3D MO_32) { + vill =3D true; + } + } + + if ((sew > cpu->cfg.elen) || vill || (vtype_reserved(env, s2) !=3D 0))= { /* only set vill bit. */ env->vill =3D 1; env->vtype =3D 0; --=20 2.52.0