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Iglesias" , Ruslan_Ruslichenko@epam.com Subject: [PATCH 22/27] target/arm/cpu: add fdt support for armv8-timer Date: Mon, 26 Jan 2026 18:43:08 +0100 Message-ID: <20260126174313.1418150-23-ruslichenko.r@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260126174313.1418150-1-ruslichenko.r@gmail.com> References: <20260126174313.1418150-1-ruslichenko.r@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=ruslichenko.r@gmail.com; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769449591288154100 Content-Type: text/plain; charset="utf-8" From: Ruslan Ruslichenko Implement FDT compatibility, so that timer can initilize and wire irqs based on device tree information. Signed-off-by: Ruslan Ruslichenko --- target/arm/cpu.c | 115 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6e1cbf3d61..96696ed4f1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -53,6 +53,8 @@ #include "target/arm/gtimer.h" =20 #include "trace.h" +#include "hw/core/fdt_generic_util.h" + =20 static void arm_cpu_set_pc(CPUState *cs, vaddr value) { @@ -2446,3 +2448,116 @@ static void arm_cpu_register_types(void) } =20 type_init(arm_cpu_register_types) + +#ifndef CONFIG_USER_ONLY + +static Object *fdt_armv8_timer_get_intc(FDTMachineInfo *fdti, char *node_p= ath) +{ + char intc_node_path[DT_PATH_LENGTH]; + uint32_t intc_phandle; + Error *errp =3D NULL; + DeviceState *intc; + + intc_phandle =3D qemu_fdt_getprop_cell(fdti->fdt, node_path, + "interrupt-parent", + 0, true, &errp); + + /* There must be an interrupt-parent */ + if (errp || + qemu_devtree_get_node_by_phandle(fdti->fdt, + intc_node_path, intc_phandle)) { + g_assert_not_reached(); + } + + while (!fdt_init_has_opaque(fdti, intc_node_path)) { + fdt_init_yield(fdti); + } + + intc =3D DEVICE(fdt_init_get_opaque(fdti, intc_node_path)); + + while (!intc->realized) { + fdt_init_yield(fdti); + } + + return OBJECT(intc); +} + +static int armv8_timer_fdt_init(char *node_path, FDTMachineInfo *fdti, + void *priv) +{ + Object *intc =3D fdt_armv8_timer_get_intc(fdti, node_path); + CPUState *cpu; + bool map_mode =3D false; + qemu_irq *sec_irqs =3D NULL; + qemu_irq *ns_irqs; + qemu_irq *v_irqs; + qemu_irq *h_irqs; + uint32_t first_cpu_idx; + uint32_t num_cpu; + bool has_sec_ext; + Error *err =3D NULL; + + first_cpu_idx =3D object_property_get_uint(intc, "first-cpu-idx", &err= ); + if (!err) { + num_cpu =3D object_property_get_uint(intc, "num-cpu", &err); + assert(!err); + has_sec_ext =3D object_property_get_bool(intc, "has-security-exten= sions", + &err); + assert(!err); + } else { + /* + * Connect all CPUs with the ARM_FEATURE_GENERIC_TIMER set for + * backwards compatibility when the 'first-cpu-idx' property does = not + * exist. + */ + num_cpu =3D 0; + has_sec_ext =3D true; + } + + if (has_sec_ext) { + sec_irqs =3D fdt_get_irq(fdti, node_path, 0, &map_mode); + ns_irqs =3D fdt_get_irq(fdti, node_path, 1, &map_mode); + v_irqs =3D fdt_get_irq(fdti, node_path, 2, &map_mode); + h_irqs =3D fdt_get_irq(fdti, node_path, 3, &map_mode); + } else { + ns_irqs =3D fdt_get_irq(fdti, node_path, 0, &map_mode); + v_irqs =3D fdt_get_irq(fdti, node_path, 1, &map_mode); + h_irqs =3D fdt_get_irq(fdti, node_path, 2, &map_mode); + } + + assert(!map_mode); /* not supported for PPI */ + + for (cpu =3D first_cpu; cpu; cpu =3D CPU_NEXT(cpu)) { + ARMCPU *acpu =3D ARM_CPU(cpu); + bool is_gic_cpu; + + if (!arm_feature(&acpu->env, ARM_FEATURE_GENERIC_TIMER)) { + continue; + } + + is_gic_cpu =3D cpu->cpu_index >=3D first_cpu_idx && + cpu->cpu_index < (first_cpu_idx + num_cpu); + + if (!num_cpu || is_gic_cpu) { + + assert(*ns_irqs); + assert(*v_irqs); + assert(*h_irqs); + qdev_connect_gpio_out(DEVICE(acpu), 0, *ns_irqs++); + qdev_connect_gpio_out(DEVICE(acpu), 1, *v_irqs++); + qdev_connect_gpio_out(DEVICE(acpu), 2, *h_irqs++); + + if (has_sec_ext) { + assert(*sec_irqs); + qdev_connect_gpio_out(DEVICE(acpu), 3, *sec_irqs++); + } + } + } + + return 0; +} + +fdt_register_compatibility(armv8_timer_fdt_init, + "compatible:arm,armv8-timer"); + +#endif --=20 2.43.0