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Iglesias" , Ruslan_Ruslichenko@epam.com Subject: [PATCH 21/27] hw/intc/arm_gic: implement FDT_GENERIC_INTC and fdt support Date: Mon, 26 Jan 2026 18:43:07 +0100 Message-ID: <20260126174313.1418150-22-ruslichenko.r@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260126174313.1418150-1-ruslichenko.r@gmail.com> References: <20260126174313.1418150-1-ruslichenko.r@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=ruslichenko.r@gmail.com; helo=mail-lf1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769449863011154100 Content-Type: text/plain; charset="utf-8" From: Ruslan Ruslichenko The patch implements TYPE_FDT_GENERIC_INTC interface, which enables GIC to be instantiated and wired via the device tree description. The implemented interface method are following: 1. 'get_irq': Parses device tree interrupt specifiers and return correct qemu_irq for devices which has IRQ's wired to GIC. 2. 'auto_parent': Automatically connect the GIC's output signals to the CPU's found in current machine configuration. Signed-off-by: Ruslan Ruslichenko --- hw/intc/arm_gic.c | 32 +++++++++++++++++++++++++ hw/intc/arm_gic_common.c | 50 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 4d4b79e6f3..2be44d8e5b 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -24,12 +24,15 @@ #include "gic_internal.h" #include "qapi/error.h" #include "hw/core/cpu.h" +#include "hw/core/boards.h" #include "qemu/log.h" #include "qemu/module.h" #include "trace.h" #include "system/kvm.h" #include "system/qtest.h" =20 +#include "hw/core/fdt_generic_util.h" + /* #define DEBUG_GIC */ =20 #ifdef DEBUG_GIC @@ -2162,12 +2165,41 @@ static void arm_gic_realize(DeviceState *dev, Error= **errp) =20 } =20 +static void arm_gic_fdt_auto_parent(FDTGenericIntc *obj, Error **errp) +{ + GICState *s =3D ARM_GIC(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + int num_cpus =3D current_machine->smp.cpus; + CPUState *cs; + int i =3D 0; + + for (cs =3D first_cpu; cs; cs =3D CPU_NEXT(cs)) { + if (i >=3D s->num_cpu) { + break; + } + + sysbus_connect_irq(sbd, i, + qdev_get_gpio_in(DEVICE(cs), 0)); + sysbus_connect_irq(sbd, i + num_cpus, + qdev_get_gpio_in(DEVICE(cs), 1)); + sysbus_connect_irq(sbd, i + 2 * num_cpus, + qdev_get_gpio_in(DEVICE(cs), 2)); + sysbus_connect_irq(sbd, i + 3 * num_cpus, + qdev_get_gpio_in(DEVICE(cs), 3)); + i++; + } + + /* FIXME: Add some error checking */ +} + static void arm_gic_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); ARMGICClass *agc =3D ARM_GIC_CLASS(klass); + FDTGenericIntcClass *fgic =3D FDT_GENERIC_INTC_CLASS(klass); =20 device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_real= ize); + fgic->auto_parent =3D arm_gic_fdt_auto_parent; } =20 static const TypeInfo arm_gic_info =3D { diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 304d89cf56..04787cff79 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -28,6 +28,8 @@ #include "migration/vmstate.h" #include "system/kvm.h" =20 +#include "hw/core/fdt_generic_util.h" + static int gic_pre_save(void *opaque) { GICState *s =3D (GICState *)opaque; @@ -348,6 +350,51 @@ static void arm_gic_common_linux_init(ARMLinuxBootIf *= obj, } } =20 +static int arm_gic_common_fdt_get_irq(FDTGenericIntc *obj, qemu_irq *irqs, + uint32_t *cells, int ncells, int max, + Error **errp) +{ + GICState *gs =3D ARM_GIC_COMMON(obj); + int cpu =3D 0; + uint32_t idx; + + if (ncells !=3D 3) { + error_setg(errp, "ARM GIC requires 3 interrupt cells, %d cells giv= en", + ncells); + return 0; + } + idx =3D cells[1]; + + switch (cells[0]) { + case 0: + if (idx >=3D gs->num_irq) { + error_setg(errp, "ARM GIC SPI has maximum index of %" PRId32 "= , " + "index %" PRId32 " given", gs->num_irq - 1, idx); + return 0; + } + (*irqs) =3D qdev_get_gpio_in(DEVICE(obj), cells[1]); + return 1; + case 1: /* PPI */ + if (idx >=3D 16) { + error_setg(errp, "ARM GIC PPI has maximum index of 15, " + "index %" PRId32 " given", idx); + return 0; + } + for (cpu =3D 0; cpu < max && cpu < gs->num_cpu; cpu++) { + if (cells[2] & 1 << (cpu + 8)) { + *irqs =3D qdev_get_gpio_in(DEVICE(obj), + gs->num_irq - 16 + idx + cpu * 32= ); + } + irqs++; + } + return cpu; + default: + error_setg(errp, "Invalid cell 0 value in interrupt binding: %d", + cells[0]); + return 0; + } +} + static const Property arm_gic_common_properties[] =3D { DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1), DEFINE_PROP_UINT32("first-cpu-index", GICState, first_cpu_index, 0), @@ -368,12 +415,14 @@ static void arm_gic_common_class_init(ObjectClass *kl= ass, const void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); ResettableClass *rc =3D RESETTABLE_CLASS(klass); ARMLinuxBootIfClass *albifc =3D ARM_LINUX_BOOT_IF_CLASS(klass); + FDTGenericIntcClass *fgic =3D FDT_GENERIC_INTC_CLASS(klass); =20 rc->phases.hold =3D arm_gic_common_reset_hold; dc->realize =3D arm_gic_common_realize; device_class_set_props(dc, arm_gic_common_properties); dc->vmsd =3D &vmstate_gic; albifc->arm_linux_init =3D arm_gic_common_linux_init; + fgic->get_irq =3D arm_gic_common_fdt_get_irq; } =20 static const TypeInfo arm_gic_common_type =3D { @@ -385,6 +434,7 @@ static const TypeInfo arm_gic_common_type =3D { .abstract =3D true, .interfaces =3D (const InterfaceInfo[]) { { TYPE_ARM_LINUX_BOOT_IF }, + { TYPE_FDT_GENERIC_INTC }, { }, }, }; --=20 2.43.0