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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1769446546; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=l457qV4i+POufgV6lrAfjlUcU2aOiTP2P7cDT3UPHb4=; b=A/qTuJObdJk+2uxur0MXgFrq2EaQhV4DdTMaUXEFrgQ7iE1eO4vWwn/PQSnsSUCla69V7C f6iw8Fyz1VDYtsq4eoqAQ1rHO78JwOTes3fxyt7FoyLrkoOF6EelpIGBz2WydVAoxsTPdI dPZOgAdx8X1umHHVnPeHHv10IJk21Dw= X-MC-Unique: aASa5VGnM1upXcZYF5hXgA-1 X-Mimecast-MFC-AGG-ID: aASa5VGnM1upXcZYF5hXgA_1769446541 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, cohuck@redhat.com, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, gshan@redhat.com, ddutile@redhat.com, peterx@redhat.com, philmd@linaro.org, pbonzini@redhat.com Subject: [PATCH v6 10/11] hw/arm/virt: Introduce framework to aggregate hidden-regs and safe-missing-regs Date: Mon, 26 Jan 2026 17:53:09 +0100 Message-ID: <20260126165445.3033335-11-eric.auger@redhat.com> In-Reply-To: <20260126165445.3033335-1-eric.auger@redhat.com> References: <20260126165445.3033335-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1769446583821154100 Content-Type: text/plain; charset="utf-8" Currently if a virt_machine__options() sets a TYPE_ARM_CPU x-mig-hidden-regs or x-mig-safe-missing-regs array property, another one cannot overwrite it or extend it. We end up with a core dump: qemu-system-aarch64: can't apply global arm-cpu.x-mig-safe-missing-regs=3D0= x603000000013c103, 0x603000000013c512, 0x603000000013c513: array size prope= rty x-mig-safe-missing-regs may not be set more than once Aborted (core dumped) In practice we would like an easy way to register regs that belong to either of those categories and allow aggregation of those. We introduce arm_virt_compat_register_safe_missing_reg() and arm_virt_compat_register_hidden_reg() which populate GLists of int64_t. After all virt_machine__options have been called and have registered their regs, the GList are converted into the associated array property value and the GlobalProperties are set. Signed-off-by: Eric Auger Reviewed-by: Sebastian Ott --- v5 -> v6: - move g_string_new after list length check - collected Sebastian's R-b v5: - new patch --- include/hw/arm/virt.h | 23 ++++++++++++++ hw/arm/virt.c | 73 ++++++++++++++++++++++++++++++++++++++----- 2 files changed, 89 insertions(+), 7 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 5907d41dbb2..d83e6f00068 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -41,6 +41,7 @@ #include "system/kvm.h" #include "hw/intc/arm_gicv3_common.h" #include "qom/object.h" +#include "qobject/qlist.h" =20 #define NUM_GICV2M_SPIS 64 #define NUM_VIRTIO_TRANSPORTS 32 @@ -131,6 +132,8 @@ struct VirtMachineClass { bool no_tcg_lpa2; bool no_ns_el2_virt_timer_irq; bool no_nested_smmu; + QList *safe_missing_regs; + QList *hidden_regs; }; =20 struct VirtMachineState { @@ -216,4 +219,24 @@ static inline int virt_gicv3_redist_region_count(VirtM= achineState *vms) vms->highmem_redists) ? 2 : 1; } =20 +static inline void arm_virt_class_init(MachineClass *mc) +{ + VirtMachineClass *vmc =3D VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + + vmc->safe_missing_regs =3D qlist_new(); + vmc->hidden_regs =3D qlist_new(); +} + +static inline void +arm_virt_compat_register_safe_missing_reg(VirtMachineClass *vmc, int64_t r= egidx) +{ + qlist_append_int(vmc->safe_missing_regs, regidx); +} + +static inline void +arm_virt_compat_register_hidden_reg(VirtMachineClass *vmc, int64_t regidx) +{ + qlist_append_int(vmc->hidden_regs, regidx); +} + #endif /* QEMU_ARM_VIRT_H */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 03d5af18f26..a01dfb7fb79 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -93,6 +93,7 @@ #include "hw/cxl/cxl.h" #include "hw/cxl/cxl_host.h" #include "qemu/guest-random.h" +#include "qobject/qnum.h" =20 static GlobalProperty arm_virt_compat_defaults[] =3D { { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "48" }, @@ -100,15 +101,18 @@ static GlobalProperty arm_virt_compat_defaults[] =3D { static const size_t arm_virt_compat_defaults_len =3D G_N_ELEMENTS(arm_virt_compat_defaults); =20 +/* + * Array made of x-mig-safe-missing-regs and x-mig-hidden-regs global + * properties. It is populated by arm_virt_aggregate_x_mig_props() that + * aggregates registrations respectively made with: + * - arm_virt_compat_register_safe_missing_reg() and + * - arm_virt_compat_register_hidden_reg() + */ +static GlobalProperty aggregated_x_mig_array_props[2]; + /* Register erronously exposed on 10.2 and earlier */ #define DBGDTRTX 0x40200000200e0298 =20 -static GlobalProperty arm_virt_compat_10_2[] =3D { - { TYPE_ARM_CPU, "x-mig-safe-missing-regs", stringify(DBGDTRTX)}, -}; -static const size_t arm_virt_compat_10_2_len =3D - G_N_ELEMENTS(arm_virt_compat_10_2); - /* * This cannot be called from the virt_machine_class_init() because * TYPE_VIRT_MACHINE is abstract and mc->compat_props g_ptr_array_new() @@ -120,14 +124,67 @@ static void arm_virt_compat_default_set(MachineClass = *mc) arm_virt_compat_defaults_len); } =20 +static char *get_prop_value_from_reg_qlist(QList *l) +{ + size_t size =3D qlist_size(l); + QListEntry *item; + GString *s; + int i =3D 0; + QNum *qi; + + if (!size) { + return NULL; + } + + s =3D g_string_new(""); + + QLIST_FOREACH_ENTRY(l, item) { + qi =3D qobject_to(QNum, qlist_entry_obj(item)); + int64_t regidx; + + qnum_get_try_int(qi, ®idx); + if (i++ > 0) { + g_string_append(s, ", "); + } + g_string_append_printf(s, "%" G_GINT64_FORMAT, regidx); + } + return g_string_free(s, false); +} + +static void arm_virt_aggregate_x_mig_props(MachineClass *mc) +{ + VirtMachineClass *vmc =3D VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + const char *safe_missing_regs_prop_value =3D + get_prop_value_from_reg_qlist(vmc->safe_missing_regs); + const char *hidden_regs_prop_value =3D + get_prop_value_from_reg_qlist(vmc->hidden_regs); + int i =3D 0; + + if (safe_missing_regs_prop_value) { + aggregated_x_mig_array_props[i].driver =3D TYPE_ARM_CPU; + aggregated_x_mig_array_props[i].property =3D "x-mig-safe-missing-r= egs"; + aggregated_x_mig_array_props[i++].value =3D safe_missing_regs_prop= _value; + } + + if (hidden_regs_prop_value) { + aggregated_x_mig_array_props[i].driver =3D TYPE_ARM_CPU; + aggregated_x_mig_array_props[i].property =3D "x-mig-hidden-regs"; + aggregated_x_mig_array_props[i++].value =3D hidden_regs_prop_value; + } + + compat_props_add(mc->compat_props, aggregated_x_mig_array_props, i); +} + #define DEFINE_VIRT_MACHINE_IMPL(latest, ...) \ static void MACHINE_VER_SYM(class_init, virt, __VA_ARGS__)( \ ObjectClass *oc, \ const void *data) \ { \ MachineClass *mc =3D MACHINE_CLASS(oc); \ + arm_virt_class_init(mc); \ arm_virt_compat_default_set(mc); \ MACHINE_VER_SYM(options, virt, __VA_ARGS__)(mc); \ + arm_virt_aggregate_x_mig_props(mc); \ mc->desc =3D "QEMU " MACHINE_VER_STR(__VA_ARGS__) " ARM Virtual Ma= chine"; \ MACHINE_VER_DEPRECATION(__VA_ARGS__); \ if (latest) { \ @@ -3559,9 +3616,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(11, 0) =20 static void virt_machine_10_2_options(MachineClass *mc) { + VirtMachineClass *vmc =3D VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_11_0_options(mc); compat_props_add(mc->compat_props, hw_compat_10_2, hw_compat_10_2_len); - compat_props_add(mc->compat_props, arm_virt_compat_10_2, arm_virt_comp= at_10_2_len); + arm_virt_compat_register_safe_missing_reg(vmc, DBGDTRTX); } DEFINE_VIRT_MACHINE(10, 2) =20 --=20 2.52.0