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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1769446541; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7/G678DDbXCgNGkigZdO6LX+E2evVF+SLkVbTYB/0S4=; b=TxeQyFcyFpvuIZokk8cWxM1JWXiKrCvXXObunS4OMgweanL5+ulCI6bRpKksL++ZATqFMa 92uIcb7GtW+jowUIMAJYj3MHIg2C9/scA4pU0utB/ifenrof1sbJWVFXCDFgHiZ/abDmwu XDGDHM4LzozRknDqi8LoxrTsbd8gPRY= X-MC-Unique: KFjAmmDnO5upRt2vF5DzSQ-1 X-Mimecast-MFC-AGG-ID: KFjAmmDnO5upRt2vF5DzSQ_1769446536 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, cohuck@redhat.com, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, gshan@redhat.com, ddutile@redhat.com, peterx@redhat.com, philmd@linaro.org, pbonzini@redhat.com Subject: [PATCH v6 09/11] Revert "target/arm: Reinstate bogus AArch32 DBGDTRTX register for migration compat" Date: Mon, 26 Jan 2026 17:53:08 +0100 Message-ID: <20260126165445.3033335-10-eric.auger@redhat.com> In-Reply-To: <20260126165445.3033335-1-eric.auger@redhat.com> References: <20260126165445.3033335-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" This reverts commit 4f2b82f60431e4792ecfd86a4d6b824248ee4c21. We don't need that commit anymore as the AArch32 DBGDTRTX register is declared to be safe to ignore in the incoming migration stream using a compat in arm virt machine. Signed-off-by: Eric Auger --- target/arm/debug_helper.c | 29 ----------------------------- 1 file changed, 29 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 579516e1541..aee06d4d426 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -940,13 +940,6 @@ static void dbgclaimclr_write(CPUARMState *env, const = ARMCPRegInfo *ri, env->cp15.dbgclaim &=3D ~(value & 0xFF); } =20 -static CPAccessResult access_bogus(CPUARMState *env, const ARMCPRegInfo *r= i, - bool isread) -{ - /* Always UNDEF, as if this cpreg didn't exist */ - return CP_ACCESS_UNDEFINED; -} - static const ARMCPRegInfo debug_cp_reginfo[] =3D { /* * DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped @@ -1009,28 +1002,6 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .opc0 =3D 2, .opc1 =3D 3, .crn =3D 0, .crm =3D 4, .opc2 =3D 0, .access =3D PL0_RW, .accessfn =3D access_tdcc, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* - * This is not a real AArch32 register. We used to incorrectly expose - * this due to a QEMU bug; to avoid breaking migration compatibility we - * need to continue to provide it so that we don't fail the inbound - * migration when it tells us about a sysreg that we don't have. - * We set an always-fails .accessfn, which means that the guest doesn't - * actually see this register (it will always UNDEF, identically to if - * there were no cpreg definition for it other than that we won't print - * a LOG_UNIMP message about it), and we set the ARM_CP_NO_GDB flag so= the - * gdbstub won't see it either. - * (We can't just set .access =3D 0, because add_cpreg_to_hashtable() - * helpfully ignores cpregs which aren't accessible to the highest - * implemented EL.) - * - * TODO: implement a system for being able to describe "this register - * can be ignored if it appears in the inbound stream"; then we can - * remove this temporary hack. - */ - { .name =3D "BOGUS_DBGDTR_EL0", .state =3D ARM_CP_STATE_AA32, - .cp =3D 14, .opc1 =3D 3, .crn =3D 0, .crm =3D 5, .opc2 =3D 0, - .access =3D PL0_RW, .accessfn =3D access_bogus, - .type =3D ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue =3D 0 }, /* * OSECCR_EL1 provides a mechanism for an operating system * to access the contents of EDECCR. EDECCR is not implemented though, --=20 2.52.0