From nobody Sun Jan 25 11:58:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1769072110; cv=none; d=zohomail.com; s=zohoarc; b=B3YuJilZU2a5WIY0feYpudcKBtWNiCDq9FUhViCjsoi3+30U5aSm4sVKB9ifx1xd+LaHsBYULkrydJOrv2cV5wDrKGZnz4spCLjjcQP1rXbCZq8EjBYtFdlg9Y6uHH6zCkuyNGFMZdF7w21YFFldRBxZBPlL9pFEWLfRKncRh44= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769072110; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=7A7ThAd+PQaR/LhX/5YgclGW2q/qeUOC4O30RF1K0TM=; b=ClaOCHUhOVlQFTI6pg36w4Xz3xGVdJITQVVnNgJMCiOco92JpCpssPyLE/i3afMkFj+LDgTOdgaB1FWblgzt9ztz/kl4YZNhpgD4REz+gGJrDy6bEQCZUsDv1A7YOH3AL6Vdcdm3fOQ3gpTNrtIYnlASKAluejF512pQCc2V6LY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769072110540437.1047616090061; Thu, 22 Jan 2026 00:55:10 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1viqSy-0006HS-PZ; Thu, 22 Jan 2026 03:55:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1viqRt-0005EM-Vg for qemu-devel@nongnu.org; Thu, 22 Jan 2026 03:53:53 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1viqRr-0005th-OZ for qemu-devel@nongnu.org; Thu, 22 Jan 2026 03:53:53 -0500 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-432d28870ddso396048f8f.3 for ; Thu, 22 Jan 2026 00:53:51 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4356992201csm44286403f8f.2.2026.01.22.00.53.49 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 22 Jan 2026 00:53:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769072030; x=1769676830; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7A7ThAd+PQaR/LhX/5YgclGW2q/qeUOC4O30RF1K0TM=; b=siiNd1AeAW+lQZN8ErvDoNOXRap/5p1ad6pDOrFHJIgkJ9/J0UiO2vU+eLF2gToQLz TRgArVC6rUYUs+9a8WlA9g/vcmWyG7MbCC2IwN/hKJyoUOA+D/cE6TodXK2Q+B519KOj cVmELHkp6hTc0/EtBnb0TSmA2tCjaBaOpA7QbK6tYVBiN8fhY7zWEOQB21ul6FVkks1S 0DmFS023UShxzPa3ZJqh3p7lIC8Fqf+nsNHgAx5aISPjBY7w4X0km59Plw0O6MAHVknt wfJe1rIW8h4Jl19MCBi4CLui2nUR0venQ0h+H2414FPbWS9S6yOJ8/xhnL5tCWdHJT4t 9ruw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769072030; x=1769676830; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=7A7ThAd+PQaR/LhX/5YgclGW2q/qeUOC4O30RF1K0TM=; b=dTDxAPBDsWoLK/Gu5Ql07L2nLK52QJQcc/lYJM1cPY+M4VL3D1/Fu6QwLnOOUWIlXz +fWM4YBJx6D2XH79YMIW3qZOZtZn+ccEOuBszi/WXUbYyVJrQTUwBR6d7LOXBWIVBncK zYEpz4U6KK6VmcPqHLmg8/PJP5zyRIi227ybvAdUgoxvjPIrPOFMlUohKybBKXzxYbMw GKHz5Tk3AfUbP9T8UYihYWozpUkfnSK8sdyjM9Ss4zaLhKXqmB+Desihbram5tBD8W4M 1RR6CBFrR81SEOvmxuUTgSn9UtaEIzuJPQIGFjSJUWeDdRHo/C0qlAQvKrsHo6lJ1k17 RKSA== X-Gm-Message-State: AOJu0YxBjMtDcVE+z35L85mOCbbRODUiYAirKUsITFG5dG6FOBkBomZZ NYoknfwA3l+RUFauqCZV57s1MmRq0X55KH/hLLhNdLUMaeC/LtQJlWna4PRLidzP3+QUAJLI1KP SYdyd59E= X-Gm-Gg: AZuq6aJLPHkoanq1BnxGM9kL1tIjY2RKacMhx8sapXOwfXZO8Fu+qlDBj7Ud0Bi/N27 xQ8S6/YrYVKkfW/tBYY0dD0p3b4uo8pE83d0cvyXY8HGwzLWLpMzydI7tS0/dDkBeQW2oU7HNZI mb8RBj5zHrNTvhlJnSBcW5Y2/Wtn99QlSwFkObEhcEvfKWp6CA3m/8yFjZ5tM9AnUk7dTHxM9k4 ajjVeba6nMoxFE/OcTJ/4+/Foa4q5p8rgyZy82TFkZO1kbYmXK1DdfNRq/yhRb0vfudP/ycWM1C o+T6d73W4Blpu6r98kVLR1ikZVAmBcYpLI6FiEbvVRWfMhABwwos4cO8G8CpoJVctwPnHY3CtUS tb5DbmzMHBYg4X6a7jPwZOm0M8HP9dZJST0zuRyYgPzGU2SDH7JeGqqEJ2Hzj0IWf7R0xj5hDXs LPlCMlAGGLfP3RHj2uKTaP/I4exsdAlRahvVhUlbYr8Zq6IEPk93YQ6qEA65nj X-Received: by 2002:a05:6000:1883:b0:430:fd84:3171 with SMTP id ffacd0b85a97d-4356999452amr29809916f8f.22.1769072029773; Thu, 22 Jan 2026 00:53:49 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 08/31] system/memory: Factor address_space_ldst[M]_internal() helper out Date: Thu, 22 Jan 2026 09:52:31 +0100 Message-ID: <20260122085255.95035-9-philmd@linaro.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260122085255.95035-1-philmd@linaro.org> References: <20260122085255.95035-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769072111958158500 All the LD/ST[W,L,Q] variants use the same template, only modifying the access size used. Unify as a single pair of LD/ST methods taking a MemOp argument. Thus use the 'm' suffix for MemOp. Keep the pre-existing "warning: addr must be aligned" comment. We leave the wonder about why we aren't asserting alignment for later. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-ID: <20260109165058.59144-11-philmd@linaro.org> --- system/memory_ldst.c.inc | 298 +++++++++------------------------------ 1 file changed, 63 insertions(+), 235 deletions(-) diff --git a/system/memory_ldst.c.inc b/system/memory_ldst.c.inc index 823fc3a7561..39b3930bf50 100644 --- a/system/memory_ldst.c.inc +++ b/system/memory_ldst.c.inc @@ -20,39 +20,43 @@ */ =20 /* warning: addr must be aligned */ -static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result, - enum device_endian endian) +static inline +uint64_t glue(address_space_ldm_internal, SUFFIX)(ARG1_DECL, MemOp mop, + hwaddr addr, + MemTxAttrs attrs, + MemTxResult *result, + enum device_endian endia= n) { + const unsigned size =3D memop_size(mop); uint8_t *ptr; uint64_t val; MemoryRegion *mr; - hwaddr l =3D 4; + hwaddr l =3D size; hwaddr addr1; MemTxResult r; bool release_lock =3D false; =20 RCU_READ_LOCK(); mr =3D TRANSLATE(addr, &addr1, &l, false, attrs); - if (l < 4 || !memory_access_is_direct(mr, false, attrs)) { + if (l < size || !memory_access_is_direct(mr, false, attrs)) { release_lock |=3D prepare_mmio_access(mr); =20 /* I/O case */ r =3D memory_region_dispatch_read(mr, addr1, &val, - MO_32 | devend_memop(endian), attr= s); + mop | devend_memop(endian), attrs); } else { /* RAM case */ - fuzz_dma_read_cb(addr, 4, mr); + fuzz_dma_read_cb(addr, size, mr); ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); switch (endian) { case DEVICE_LITTLE_ENDIAN: - val =3D ldl_le_p(ptr); + val =3D ldn_le_p(ptr, size); break; case DEVICE_BIG_ENDIAN: - val =3D ldl_be_p(ptr); + val =3D ldn_be_p(ptr, size); break; default: - val =3D ldl_p(ptr); + val =3D ldn_p(ptr, size); break; } r =3D MEMTX_OK; @@ -67,87 +71,30 @@ static inline uint32_t glue(address_space_ldl_internal,= SUFFIX)(ARG1_DECL, return val; } =20 +/* warning: addr must be aligned */ +static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result, + enum device_endian endian) +{ + return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_32, addr, + attrs, result, endian); +} + /* warning: addr must be aligned */ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result, enum device_endian endian) { - uint8_t *ptr; - uint64_t val; - MemoryRegion *mr; - hwaddr l =3D 8; - hwaddr addr1; - MemTxResult r; - bool release_lock =3D false; - - RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, false, attrs); - if (l < 8 || !memory_access_is_direct(mr, false, attrs)) { - release_lock |=3D prepare_mmio_access(mr); - - /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, - MO_64 | devend_memop(endian), attr= s); - } else { - /* RAM case */ - fuzz_dma_read_cb(addr, 8, mr); - ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); - switch (endian) { - case DEVICE_LITTLE_ENDIAN: - val =3D ldq_le_p(ptr); - break; - case DEVICE_BIG_ENDIAN: - val =3D ldq_be_p(ptr); - break; - default: - val =3D ldq_p(ptr); - break; - } - r =3D MEMTX_OK; - } - if (result) { - *result =3D r; - } - if (release_lock) { - bql_unlock(); - } - RCU_READ_UNLOCK(); - return val; + return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_64, addr, + attrs, result, endian); } =20 -uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result) +uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, hwaddr addr, + MemTxAttrs attrs, MemTxResult *re= sult) { - uint8_t *ptr; - uint64_t val; - MemoryRegion *mr; - hwaddr l =3D 1; - hwaddr addr1; - MemTxResult r; - bool release_lock =3D false; - - RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, false, attrs); - if (!memory_access_is_direct(mr, false, attrs)) { - release_lock |=3D prepare_mmio_access(mr); - - /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_8, attrs); - } else { - /* RAM case */ - fuzz_dma_read_cb(addr, 1, mr); - ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); - val =3D ldub_p(ptr); - r =3D MEMTX_OK; - } - if (result) { - *result =3D r; - } - if (release_lock) { - bql_unlock(); - } - RCU_READ_UNLOCK(); - return val; + return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_8, addr, + attrs, result, + DEVICE_NATIVE_ENDIAN); } =20 /* warning: addr must be aligned */ @@ -155,37 +102,47 @@ static inline uint16_t glue(address_space_lduw_intern= al, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result, enum device_endian endian) { + return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_16, addr, + attrs, result, endian); +} + +/* warning: addr must be aligned */ +static inline +void glue(address_space_stm_internal, SUFFIX)(ARG1_DECL, MemOp mop, + hwaddr addr, uint64_t val, + MemTxAttrs attrs, + MemTxResult *result, + enum device_endian endian) +{ + const unsigned size =3D memop_size(mop); uint8_t *ptr; - uint64_t val; MemoryRegion *mr; - hwaddr l =3D 2; + hwaddr l =3D size; hwaddr addr1; MemTxResult r; bool release_lock =3D false; =20 RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, false, attrs); - if (l < 2 || !memory_access_is_direct(mr, false, attrs)) { + mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); + if (l < size || !memory_access_is_direct(mr, true, attrs)) { release_lock |=3D prepare_mmio_access(mr); - - /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, - MO_16 | devend_memop(endian), attr= s); + r =3D memory_region_dispatch_write(mr, addr1, val, + mop | devend_memop(endian), attrs= ); } else { /* RAM case */ - fuzz_dma_read_cb(addr, 2, mr); ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); switch (endian) { case DEVICE_LITTLE_ENDIAN: - val =3D lduw_le_p(ptr); + stn_le_p(ptr, size, val); break; case DEVICE_BIG_ENDIAN: - val =3D lduw_be_p(ptr); + stn_be_p(ptr, size, val); break; default: - val =3D lduw_p(ptr); + stn_p(ptr, size, val); break; } + invalidate_and_set_dirty(mr, addr1, size); r =3D MEMTX_OK; } if (result) { @@ -195,7 +152,6 @@ static inline uint16_t glue(address_space_lduw_internal= , SUFFIX)(ARG1_DECL, bql_unlock(); } RCU_READ_UNLOCK(); - return val; } =20 /* warning: addr must be aligned */ @@ -203,74 +159,16 @@ static inline void glue(address_space_stl_internal, S= UFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result, enum device_endian endian) { - uint8_t *ptr; - MemoryRegion *mr; - hwaddr l =3D 4; - hwaddr addr1; - MemTxResult r; - bool release_lock =3D false; - - RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); - if (l < 4 || !memory_access_is_direct(mr, true, attrs)) { - release_lock |=3D prepare_mmio_access(mr); - r =3D memory_region_dispatch_write(mr, addr1, val, - MO_32 | devend_memop(endian), att= rs); - } else { - /* RAM case */ - ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); - switch (endian) { - case DEVICE_LITTLE_ENDIAN: - stl_le_p(ptr, val); - break; - case DEVICE_BIG_ENDIAN: - stl_be_p(ptr, val); - break; - default: - stl_p(ptr, val); - break; - } - invalidate_and_set_dirty(mr, addr1, 4); - r =3D MEMTX_OK; - } - if (result) { - *result =3D r; - } - if (release_lock) { - bql_unlock(); - } - RCU_READ_UNLOCK(); + glue(address_space_stm_internal, SUFFIX)(ARG1, MO_32, addr, val, + attrs, result, endian); } =20 -void glue(address_space_stb, SUFFIX)(ARG1_DECL, - hwaddr addr, uint8_t val, MemTxAttrs attrs, MemTxResult *result) +void glue(address_space_stb, SUFFIX)(ARG1_DECL, hwaddr addr, uint8_t val, + MemTxAttrs attrs, MemTxResult *result) { - uint8_t *ptr; - MemoryRegion *mr; - hwaddr l =3D 1; - hwaddr addr1; - MemTxResult r; - bool release_lock =3D false; - - RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); - if (!memory_access_is_direct(mr, true, attrs)) { - release_lock |=3D prepare_mmio_access(mr); - r =3D memory_region_dispatch_write(mr, addr1, val, MO_8, attrs); - } else { - /* RAM case */ - ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); - stb_p(ptr, val); - invalidate_and_set_dirty(mr, addr1, 1); - r =3D MEMTX_OK; - } - if (result) { - *result =3D r; - } - if (release_lock) { - bql_unlock(); - } - RCU_READ_UNLOCK(); + glue(address_space_stm_internal, SUFFIX)(ARG1, MO_8, addr, val, + attrs, result, + DEVICE_NATIVE_ENDIAN); } =20 /* warning: addr must be aligned */ @@ -278,86 +176,16 @@ static inline void glue(address_space_stw_internal, S= UFFIX)(ARG1_DECL, hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result, enum device_endian endian) { - uint8_t *ptr; - MemoryRegion *mr; - hwaddr l =3D 2; - hwaddr addr1; - MemTxResult r; - bool release_lock =3D false; - - RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); - if (l < 2 || !memory_access_is_direct(mr, true, attrs)) { - release_lock |=3D prepare_mmio_access(mr); - r =3D memory_region_dispatch_write(mr, addr1, val, - MO_16 | devend_memop(endian), att= rs); - } else { - /* RAM case */ - ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); - switch (endian) { - case DEVICE_LITTLE_ENDIAN: - stw_le_p(ptr, val); - break; - case DEVICE_BIG_ENDIAN: - stw_be_p(ptr, val); - break; - default: - stw_p(ptr, val); - break; - } - invalidate_and_set_dirty(mr, addr1, 2); - r =3D MEMTX_OK; - } - if (result) { - *result =3D r; - } - if (release_lock) { - bql_unlock(); - } - RCU_READ_UNLOCK(); + glue(address_space_stm_internal, SUFFIX)(ARG1, MO_16, addr, val, + attrs, result, endian); } =20 static inline void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result, enum device_endian endian) { - uint8_t *ptr; - MemoryRegion *mr; - hwaddr l =3D 8; - hwaddr addr1; - MemTxResult r; - bool release_lock =3D false; - - RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); - if (l < 8 || !memory_access_is_direct(mr, true, attrs)) { - release_lock |=3D prepare_mmio_access(mr); - r =3D memory_region_dispatch_write(mr, addr1, val, - MO_64 | devend_memop(endian), att= rs); - } else { - /* RAM case */ - ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); - switch (endian) { - case DEVICE_LITTLE_ENDIAN: - stq_le_p(ptr, val); - break; - case DEVICE_BIG_ENDIAN: - stq_be_p(ptr, val); - break; - default: - stq_p(ptr, val); - break; - } - invalidate_and_set_dirty(mr, addr1, 8); - r =3D MEMTX_OK; - } - if (result) { - *result =3D r; - } - if (release_lock) { - bql_unlock(); - } - RCU_READ_UNLOCK(); + glue(address_space_stm_internal, SUFFIX)(ARG1, MO_64, addr, val, + attrs, result, endian); } =20 #define ENDIANNESS --=20 2.52.0