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charset="utf-8" smmuv3_cmdq_consume() is updated to return detailed errors via errp. Although this is currently a no-op, it prepares the ground for accel SMMUv3 specific command handling where proper error reporting will be useful. Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron --- hw/arm/smmuv3.c | 67 +++++++++++++++++++++++++++---------------------- 1 file changed, 37 insertions(+), 30 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 95d44f81ed..ade2b43ab8 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1279,7 +1279,7 @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd= , SMMUStage stage) } } =20 -static int smmuv3_cmdq_consume(SMMUv3State *s) +static int smmuv3_cmdq_consume(SMMUv3State *s, Error **errp) { SMMUState *bs =3D ARM_SMMU(s); SMMUCmdError cmd_error =3D SMMU_CERROR_NONE; @@ -1547,42 +1547,44 @@ static MemTxResult smmu_writell(SMMUv3State *s, hwa= ddr offset, static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset, uint64_t data, MemTxAttrs attrs) { + Error *local_err =3D NULL; + switch (offset) { case A_CR0: s->cr[0] =3D data; s->cr0ack =3D data & ~SMMU_CR0_RESERVED; /* in case the command queue has been enabled */ - smmuv3_cmdq_consume(s); - return MEMTX_OK; + smmuv3_cmdq_consume(s, &local_err); + break; case A_CR1: s->cr[1] =3D data; - return MEMTX_OK; + break; case A_CR2: s->cr[2] =3D data; - return MEMTX_OK; + break; case A_IRQ_CTRL: s->irq_ctrl =3D data; - return MEMTX_OK; + break; case A_GERRORN: smmuv3_write_gerrorn(s, data); /* * By acknowledging the CMDQ_ERR, SW may notify cmds can * be processed again */ - smmuv3_cmdq_consume(s); - return MEMTX_OK; + smmuv3_cmdq_consume(s, &local_err); + break; case A_GERROR_IRQ_CFG0: /* 64b */ s->gerror_irq_cfg0 =3D deposit64(s->gerror_irq_cfg0, 0, 32, data); - return MEMTX_OK; + break; case A_GERROR_IRQ_CFG0 + 4: s->gerror_irq_cfg0 =3D deposit64(s->gerror_irq_cfg0, 32, 32, data); - return MEMTX_OK; + break; case A_GERROR_IRQ_CFG1: s->gerror_irq_cfg1 =3D data; - return MEMTX_OK; + break; case A_GERROR_IRQ_CFG2: s->gerror_irq_cfg2 =3D data; - return MEMTX_OK; + break; case A_GBPA: /* * If UPDATE is not set, the write is ignored. This is the only @@ -1592,71 +1594,76 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwad= dr offset, /* Ignore update bit as write is synchronous. */ s->gbpa =3D data & ~R_GBPA_UPDATE_MASK; } - return MEMTX_OK; + break; case A_STRTAB_BASE: /* 64b */ s->strtab_base =3D deposit64(s->strtab_base, 0, 32, data); - return MEMTX_OK; + break; case A_STRTAB_BASE + 4: s->strtab_base =3D deposit64(s->strtab_base, 32, 32, data); - return MEMTX_OK; + break; case A_STRTAB_BASE_CFG: s->strtab_base_cfg =3D data; if (FIELD_EX32(data, STRTAB_BASE_CFG, FMT) =3D=3D 1) { s->sid_split =3D FIELD_EX32(data, STRTAB_BASE_CFG, SPLIT); s->features |=3D SMMU_FEATURE_2LVL_STE; } - return MEMTX_OK; + break; case A_CMDQ_BASE: /* 64b */ s->cmdq.base =3D deposit64(s->cmdq.base, 0, 32, data); s->cmdq.log2size =3D extract64(s->cmdq.base, 0, 5); if (s->cmdq.log2size > SMMU_CMDQS) { s->cmdq.log2size =3D SMMU_CMDQS; } - return MEMTX_OK; + break; case A_CMDQ_BASE + 4: /* 64b */ s->cmdq.base =3D deposit64(s->cmdq.base, 32, 32, data); - return MEMTX_OK; + break; case A_CMDQ_PROD: s->cmdq.prod =3D data; - smmuv3_cmdq_consume(s); - return MEMTX_OK; + smmuv3_cmdq_consume(s, &local_err); + break; case A_CMDQ_CONS: s->cmdq.cons =3D data; - return MEMTX_OK; + break; case A_EVENTQ_BASE: /* 64b */ s->eventq.base =3D deposit64(s->eventq.base, 0, 32, data); s->eventq.log2size =3D extract64(s->eventq.base, 0, 5); if (s->eventq.log2size > SMMU_EVENTQS) { s->eventq.log2size =3D SMMU_EVENTQS; } - return MEMTX_OK; + break; case A_EVENTQ_BASE + 4: s->eventq.base =3D deposit64(s->eventq.base, 32, 32, data); - return MEMTX_OK; + break; case A_EVENTQ_PROD: s->eventq.prod =3D data; - return MEMTX_OK; + break; case A_EVENTQ_CONS: s->eventq.cons =3D data; - return MEMTX_OK; + break; case A_EVENTQ_IRQ_CFG0: /* 64b */ s->eventq_irq_cfg0 =3D deposit64(s->eventq_irq_cfg0, 0, 32, data); - return MEMTX_OK; + break; case A_EVENTQ_IRQ_CFG0 + 4: s->eventq_irq_cfg0 =3D deposit64(s->eventq_irq_cfg0, 32, 32, data); - return MEMTX_OK; + break; case A_EVENTQ_IRQ_CFG1: s->eventq_irq_cfg1 =3D data; - return MEMTX_OK; + break; case A_EVENTQ_IRQ_CFG2: s->eventq_irq_cfg2 =3D data; - return MEMTX_OK; + break; default: qemu_log_mask(LOG_UNIMP, "%s Unexpected 32-bit access to 0x%"PRIx64" (WI)\n", __func__, offset); - return MEMTX_OK; + break; } + + if (local_err) { + error_report_err(local_err); + } + return MEMTX_OK; } =20 static MemTxResult smmu_write_mmio(void *opaque, hwaddr offset, uint64_t d= ata, --=20 2.43.0