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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(7416014)(1800799024)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jan 2026 17:56:11.7757 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c12db85-571d-41ef-502c-08de59165d1d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8105 Received-SPF: permerror client-ip=2a01:111:f403:c107::9; envelope-from=skolothumtho@nvidia.com; helo=PH7PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.069, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1769018241403158500 Accelerated SMMUv3 is only meaningful when a device can leverage the host SMMUv3 in nested mode (S1+S2 translation). To keep the model consistent and correct, this mode is restricted to vfio-pci endpoint devices using the iommufd backend. Non-endpoint emulated devices such as PCIe root ports and bridges are also permitted so that vfio-pci devices can be attached downstream. All other device types are unsupported in accelerated mode. Implement supports_address_space() callback to reject all such unsupported devices. This restriction also avoids complications with IOTLB invalidations. Some TLBI commands (e.g. CMD_TLBI_NH_ASID) lack an associated SID, making it difficult to trace the originating device. Allowing emulated endpoints would require invalidating both QEMU=E2=80=99s software IOTLB and the host= =E2=80=99s hardware IOTLB, which can significantly degrade performance. A key design choice is the address space returned for accelerated vfio-pci endpoints. VFIO core has a container that manages an HWPT. By default, it allocates a stage-1 normal HWPT, unless vIOMMU requests for a nesting parent HWPT for accelerated cases. VFIO core adds a listener for that HWPT and sets up a handler vfio_container_region_add() where it checks the memory region. -If the region is a non-IOMMU translated one (system address space), VFIO treats it as RAM and handles all stage-2 mappings for the core allocated nesting parent HWPT. -If the region is an IOMMU address space, VFIO instead enables IOTLB notifier handling and translation replay, skipping the RAM listener and therefore not installing stage-2 mappings. For accelerated SMMUv3, correct operation requires the S1+S2 nesting model, and therefore VFIO must take the "system address space" path so that stage-2 mappings are properly built. Returning an alias of the system address space ensures this happens. Returning the IOMMU address space would omit stage-2 mapping and break nested translation. Another option considered was forcing a pre-registration path using vfio_prereg_listener() to set up stage-2 mappings, but this requires changes in VFIO core and was not adopted. Returning an alias of the system address space keeps the design aligned with existing VFIO/iommufd nesting flows and avoids the need for cross-subsystem changes. In summary: - vfio-pci devices(with iommufd as backend) return an address space aliased to system address space. - bridges and root ports return the IOMMU address space. Reviewed-by: Jonathan Cameron Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 77 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 76 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index b2eded743e..2fcd301322 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -7,8 +7,13 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/error-report.h" =20 #include "hw/arm/smmuv3.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci-host/gpex.h" +#include "hw/vfio/pci.h" + #include "smmuv3-accel.h" =20 /* @@ -37,6 +42,48 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState= *bs, SMMUPciBus *sbus, return accel_dev; } =20 +/* + * Only allow PCIe bridges, pxb-pcie roots, and GPEX roots so vfio-pci + * endpoints can sit downstream. Accelerated SMMUv3 requires a vfio-pci + * endpoint using the iommufd backend; all other device types are rejected. + * This avoids supporting emulated endpoints, which would complicate IOTLB + * invalidation and hurt performance. + */ +static bool smmuv3_accel_pdev_allowed(PCIDevice *pdev, bool *vfio_pci) +{ + + if (object_dynamic_cast(OBJECT(pdev), TYPE_PCI_BRIDGE) || + object_dynamic_cast(OBJECT(pdev), TYPE_PXB_PCIE_DEV) || + object_dynamic_cast(OBJECT(pdev), TYPE_GPEX_ROOT_DEVICE)) { + return true; + } else if ((object_dynamic_cast(OBJECT(pdev), TYPE_VFIO_PCI))) { + *vfio_pci =3D true; + if (object_property_get_link(OBJECT(pdev), "iommufd", NULL)) { + return true; + } + } + return false; +} + +static bool smmuv3_accel_supports_as(PCIBus *bus, void *opaque, int devfn, + Error **errp) +{ + PCIDevice *pdev =3D pci_find_device(bus, pci_bus_num(bus), devfn); + bool vfio_pci =3D false; + + if (pdev && !smmuv3_accel_pdev_allowed(pdev, &vfio_pci)) { + if (vfio_pci) { + error_setg(errp, "vfio-pci endpoint devices without an iommufd= " + "backend not allowed when using arm-smmuv3,accel=3D= on"); + + } else { + error_setg(errp, "Emulated endpoint devices are not allowed wh= en " + "using arm-smmuv3,accel=3Don"); + } + return false; + } + return true; +} /* * Find or add an address space for the given PCI device. * @@ -47,15 +94,43 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUStat= e *bs, SMMUPciBus *sbus, static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void *opaque, int devfn) { + PCIDevice *pdev =3D pci_find_device(bus, pci_bus_num(bus), devfn); SMMUState *bs =3D opaque; SMMUPciBus *sbus =3D smmu_get_sbus(bs, bus); SMMUv3AccelDevice *accel_dev =3D smmuv3_accel_get_dev(bs, sbus, bus, d= evfn); SMMUDevice *sdev =3D &accel_dev->sdev; + bool vfio_pci =3D false; =20 - return &sdev->as; + if (pdev && !smmuv3_accel_pdev_allowed(pdev, &vfio_pci)) { + /* Should never be here: supports_address_space() filters these ou= t */ + g_assert_not_reached(); + } + + /* + * In the accelerated mode, a vfio-pci device attached via the iommufd + * backend must remain in the system address space. Such a device is + * always translated by its physical SMMU (using either a stage-2-only + * STE or a nested STE), where the parent stage-2 page table is alloca= ted + * by the VFIO core to back the system address space. + * + * Return the shared_as_sysmem aliased to the global system memory in = this + * case. Sharing address_space_memory also allows devices under differ= ent + * vSMMU instances in the same VM to reuse a single nesting parent HWP= T in + * the VFIO core. + * + * For non-endpoint emulated devices such as PCIe root ports and bridg= es, + * which may use the normal emulated translation path and software IOT= LBs, + * return the SMMU's IOMMU address space. + */ + if (vfio_pci) { + return shared_as_sysmem; + } else { + return &sdev->as; + } } =20 static const PCIIOMMUOps smmuv3_accel_ops =3D { + .supports_address_space =3D smmuv3_accel_supports_as, .get_address_space =3D smmuv3_accel_find_add_as, }; =20 --=20 2.43.0