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Wed, 21 Jan 2026 02:59:34 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH 1/4] hw/intc: declare NVIC regions as little endian Date: Wed, 21 Jan 2026 10:59:29 +0000 Message-ID: <20260121105932.135676-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260121105932.135676-1-alex.bennee@linaro.org> References: <20260121105932.135676-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768993272137154101 The NVIC should always be a little-endian device as big-endian behaviour is a function of the current CPU configuration not the system as a whole. Indeed the Armv8-M architecture reference manual declares: All accesses to the Private Peripheral Bus (PPB) are always little-endian, which means that the PE assumes a little-endian arrangement of the PPB registers. This should have no functional effect as the NVIC cannot be instantiated on a BE system but will help the single binary efforts. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/armv7m_nvic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 3a31eb56f36..28b34e99446 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2467,7 +2467,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hw= addr addr, static const MemoryRegionOps nvic_sysreg_ops =3D { .read_with_attrs =3D nvic_sysreg_read, .write_with_attrs =3D nvic_sysreg_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 static int nvic_post_load(void *opaque, int version_id) --=20 2.47.3 From nobody Mon Feb 9 12:57:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Wed, 21 Jan 2026 02:59:34 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH 2/4] hw/intc: declare GIC regions as little endian Date: Wed, 21 Jan 2026 10:59:30 +0000 Message-ID: <20260121105932.135676-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260121105932.135676-1-alex.bennee@linaro.org> References: <20260121105932.135676-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768993272133154100 The GIC should always be a little-endian device as big-endian behaviour is a function of the current CPU configuration not the system as a whole. This should have no functional effect as the GIC cannot be instantiated on a BE system but will help the single binary efforts. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/arm_gic.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 4d0cb125a61..4d4b79e6f34 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -2062,38 +2062,38 @@ static const MemoryRegionOps gic_ops[2] =3D { { .read_with_attrs =3D gic_dist_read, .write_with_attrs =3D gic_dist_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, }, { .read_with_attrs =3D gic_thiscpu_read, .write_with_attrs =3D gic_thiscpu_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, } }; =20 static const MemoryRegionOps gic_cpu_ops =3D { .read_with_attrs =3D gic_do_cpu_read, .write_with_attrs =3D gic_do_cpu_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 static const MemoryRegionOps gic_virt_ops[2] =3D { { .read_with_attrs =3D gic_thiscpu_hyp_read, .write_with_attrs =3D gic_thiscpu_hyp_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, }, { .read_with_attrs =3D gic_thisvcpu_read, .write_with_attrs =3D gic_thisvcpu_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, } }; =20 static const MemoryRegionOps gic_viface_ops =3D { .read_with_attrs =3D gic_do_hyp_read, .write_with_attrs =3D gic_do_hyp_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 static void arm_gic_realize(DeviceState *dev, Error **errp) --=20 2.47.3 From nobody Mon Feb 9 12:57:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768993316; cv=none; d=zohomail.com; s=zohoarc; b=BArSc3slA1hZeQAC1l84IRUoAeU76u7M9rnekFTGff/XJR/6MNRQO1RU99xwaga42Un8n6U66pecKBQd1S9G8jRgJxlc94ADPS7vLUN0hb2bjUsvNxVkD9R80qqqNLc3ChUfYJvE4Nnv2C+q8vhWYUow7bBb/tjrSYCiOocoFrY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768993316; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 21 Jan 2026 02:59:36 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH 3/4] hw/intc: declare GICv3 regions as little endian Date: Wed, 21 Jan 2026 10:59:31 +0000 Message-ID: <20260121105932.135676-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260121105932.135676-1-alex.bennee@linaro.org> References: <20260121105932.135676-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768993317149158500 The GIC should always be a little-endian device as big-endian behaviour is a function of the current CPU configuration not the system as a whole. This should have no functional effect as the GIC cannot be instantiated on a BE system but will help the single binary efforts. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/arm_gicv3.c | 4 ++-- hw/intc/arm_gicv3_its.c | 4 ++-- hw/intc/arm_gicv3_its_common.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 6059ce926a6..542f81ea49a 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -417,7 +417,7 @@ static const MemoryRegionOps gic_ops[] =3D { { .read_with_attrs =3D gicv3_dist_read, .write_with_attrs =3D gicv3_dist_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, .valid.min_access_size =3D 1, .valid.max_access_size =3D 8, .impl.min_access_size =3D 1, @@ -426,7 +426,7 @@ static const MemoryRegionOps gic_ops[] =3D { { .read_with_attrs =3D gicv3_redist_read, .write_with_attrs =3D gicv3_redist_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, .valid.min_access_size =3D 1, .valid.max_access_size =3D 8, .impl.min_access_size =3D 1, diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index cce3486d74c..b639c03b67c 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -1906,7 +1906,7 @@ static const MemoryRegionOps gicv3_its_control_ops = =3D { .valid.max_access_size =3D 8, .impl.min_access_size =3D 4, .impl.max_access_size =3D 8, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 static const MemoryRegionOps gicv3_its_translation_ops =3D { @@ -1916,7 +1916,7 @@ static const MemoryRegionOps gicv3_its_translation_op= s =3D { .valid.max_access_size =3D 4, .impl.min_access_size =3D 2, .impl.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 static void gicv3_arm_its_realize(DeviceState *dev, Error **errp) diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c index e946e3fb87b..9fc51ad1e0b 100644 --- a/hw/intc/arm_gicv3_its_common.c +++ b/hw/intc/arm_gicv3_its_common.c @@ -97,7 +97,7 @@ static MemTxResult gicv3_its_trans_write(void *opaque, hw= addr offset, static const MemoryRegionOps gicv3_its_trans_ops =3D { .read_with_attrs =3D gicv3_its_trans_read, .write_with_attrs =3D gicv3_its_trans_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops, --=20 2.47.3 From nobody Mon Feb 9 12:57:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Jan 2026 02:59:36 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-stable@nongnu.org Subject: [PATCH 4/4] hw/intc: avoid byte swap fiddling in gicv3 its path Date: Wed, 21 Jan 2026 10:59:32 +0000 Message-ID: <20260121105932.135676-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260121105932.135676-1-alex.bennee@linaro.org> References: <20260121105932.135676-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768993302290154100 This allows us to keep the MSI data in plain host order all the way from the MemoryRegionOps write method to the final KVM_SIGNAL_MSI ioctl. This fixes a theoretical bug on big-endian hosts because we were using different size byte swaps which would have truncated the data. Signed-off-by: Alex Benn=C3=A9e Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell --- v2 - split from DEVICE_LITTLE_ENDIAN changes - expanded the commit message - cc stable --- hw/intc/arm_gicv3_its_common.c | 2 +- hw/intc/arm_gicv3_its_kvm.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c index 9fc51ad1e0b..60a5abd8d3e 100644 --- a/hw/intc/arm_gicv3_its_common.c +++ b/hw/intc/arm_gicv3_its_common.c @@ -81,7 +81,7 @@ static MemTxResult gicv3_its_trans_write(void *opaque, hw= addr offset, if (offset =3D=3D 0x0040 && ((size =3D=3D 2) || (size =3D=3D 4))) { GICv3ITSState *s =3D ARM_GICV3_ITS_COMMON(opaque); GICv3ITSCommonClass *c =3D ARM_GICV3_ITS_COMMON_GET_CLASS(s); - int ret =3D c->send_msi(s, le64_to_cpu(value), attrs.requester_id); + int ret =3D c->send_msi(s, value, attrs.requester_id); =20 if (ret <=3D 0) { qemu_log_mask(LOG_GUEST_ERROR, diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index ae12d41eee1..a8d6d4fb540 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -58,7 +58,7 @@ static int kvm_its_send_msi(GICv3ITSState *s, uint32_t va= lue, uint16_t devid) =20 msi.address_lo =3D extract64(s->gits_translater_gpa, 0, 32); msi.address_hi =3D extract64(s->gits_translater_gpa, 32, 32); - msi.data =3D le32_to_cpu(value); + msi.data =3D value; msi.flags =3D KVM_MSI_VALID_DEVID; msi.devid =3D devid; memset(msi.pad, 0, sizeof(msi.pad)); --=20 2.47.3