From nobody Sun Feb 8 20:53:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768901525; cv=none; d=zohomail.com; s=zohoarc; b=O9YyccOMR3Dp6vu0mPXnbw5euEabr2iKiNf/LfMCgjLkfV8NDVXePz7T4CcDZZVekSsHkTcbESLTS6W5YCAyLa7kPlyEVnAF2J/P5S7LT3WDAreeAcbADURfikHxjp2qXVFysTKMaUmIQvwL0k757HjRxSO/jKnjxns44E8NDaI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768901525; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=3M7+ZMvLsEc7XF/WTJQEjiPeefWNMndDpf08j0sjeiE=; b=Iw3+ARxLqNoe2WiExeLrD3pY1v0Hp2JwNOF+IlyqcPUGmpwomeHhStiRdBsshhp820FoD/CP+OqfzGnwG1wMMmmiOB6KVdISQVc3pZV/f3hy6Uxa9Jq1Cky7uuTPX3Si7dAwjv0h71f4YQyJWiMv2LOmOKDCFMLkiSdL+brWQoY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176890152594988.1998257641759; Tue, 20 Jan 2026 01:32:05 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vi83d-0003MM-HK; Tue, 20 Jan 2026 04:29:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi83b-0003Ja-Ve; Tue, 20 Jan 2026 04:29:52 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi83a-0005eG-Fs; Tue, 20 Jan 2026 04:29:51 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 17:29:39 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 17:29:39 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 01/11] hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support memory aliasing Date: Tue, 20 Jan 2026 17:29:26 +0800 Message-ID: <20260120092939.2708302-2-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120092939.2708302-1-jamin_lin@aspeedtech.com> References: <20260120092939.2708302-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768901528352154100 To support DRAM aliasing for coprocessors (SSP/TSP), this commit moves the initialization of the SDMC (SDRAM controller) and DRAM models earlier in the device realization order. In the upcoming changes, the PSP will expose a portion of its DRAM as shared memory by creating a memory region alias at a specific offset. This alias is mapped into the coprocessor's SDRAM address space, allowing both PSP and the coprocessor (SSP/TSP) to access the same physical memory through their resp= ective views =E2=80=94 PSP via its DRAM, and the coprocessor via its SDRAM. The remapping is configured through SCU registers and enables shared memory communication between PSP and the coprocessors. Therefore, the DRAM and SDMC devices must be realized before: - the SCU, which configures the alias offset and size - the coprocessors, which access the alias through their SDRAM window No functional change. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index d17f446661..74a004adca 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -702,6 +702,26 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0])= , i)); } =20 + /* + * SDMC - SDRAM Memory Controller + * The SDMC controller is unlocked at SPL stage. + * At present, only supports to emulate booting + * start from u-boot stage. Set SDMC controller + * unlocked by default. It is a temporarily solution. + */ + object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { + return; + } + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdmc), 0, + sc->memmap[ASPEED_DEV_SDMC]); + + /* RAM */ + if (!aspeed_soc_ast2700_dram_init(dev, errp)) { + return; + } + /* SRAM */ name =3D g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); if (!memory_region_init_ram(&s->sram, OBJECT(s), name, sc->sram_size, @@ -792,26 +812,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) ASPEED_DEV_EHCI1 + i= )); } =20 - /* - * SDMC - SDRAM Memory Controller - * The SDMC controller is unlocked at SPL stage. - * At present, only supports to emulate booting - * start from u-boot stage. Set SDMC controller - * unlocked by default. It is a temporarily solution. - */ - object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, - &error_abort); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { - return; - } - aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdmc), 0, - sc->memmap[ASPEED_DEV_SDMC]); - - /* RAM */ - if (!aspeed_soc_ast2700_dram_init(dev, errp)) { - return; - } - /* Net */ for (i =3D 0; i < sc->macs_num; i++) { object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, --=20 2.43.0 From nobody Sun Feb 8 20:53:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768901582; cv=none; d=zohomail.com; s=zohoarc; b=hPmxsMUJZiyTZ199M4w18OlWucS1zi0Fy4SGNlKhcNfHbRfruNUvCVE6I5hhZktM1dRYJx487w5ic7sNiXeotrEKj4+RG+15m8N6vnV2BUbEGqCNXhGPp5QGH9m3TmCdYDpqYYURbbvrf8u2kKmmqv9QsNrrrh/u2E2O9IcUO9Q= ARC-Message-Signature: i=1; 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Tue, 20 Jan 2026 04:29:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi83e-0003N0-8R; Tue, 20 Jan 2026 04:29:54 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi83c-0005eG-VO; Tue, 20 Jan 2026 04:29:54 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 17:29:40 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 17:29:40 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 02/11] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior Date: Tue, 20 Jan 2026 17:29:27 +0800 Message-ID: <20260120092939.2708302-3-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120092939.2708302-1-jamin_lin@aspeedtech.com> References: <20260120092939.2708302-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768901584873154100 Content-Type: text/plain; charset="utf-8" In the previous design, both the PSP and SSP were started together during SoC initialization. However, on real hardware, the SSP begins in a powered-= off state. The typical boot sequence involves the PSP powering up first, loading the SSP firmware binary into shared memory via DRAM remap, and then releasi= ng the SSP reset and enabling it through SCU control registers. To more accurately model this behavior in QEMU, this commit sets the "start-powered-off" property for the SSP's ARMv7M core. This change ensures the SSP remains off until explicitly enabled via the SCU, simulating the real-world flow where the PSP controls SSP boot through SCU interaction. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0-ssp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index cee937b37e..cba59ae11a 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -165,6 +165,13 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState = *dev_soc, Error **errp) qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); object_property_set_link(OBJECT(&a->armv7m), "memory", OBJECT(s->memory), &error_abort); + /* + * The SSP starts in a powered-down state and can be powered up + * by setting the SSP Control Register through the SCU + * (System Control Unit) + */ + object_property_set_bool(OBJECT(&a->armv7m), "start-powered-off", true, + &error_abort); sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort); =20 /* SDRAM */ --=20 2.43.0 From nobody Sun Feb 8 20:53:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768901467408154100 Content-Type: text/plain; charset="utf-8" In the previous design, both the PSP and TSP were started together during SoC initialization. However, on real hardware, the TSP begins in a powered-= off state. The typical boot sequence involves the PSP powering up first, loading the TSP firmware binary into shared memory via DRAM remap, and then releasi= ng the TSP reset and enabling it through SCU control registers. To more accurately model this behavior in QEMU, this commit sets the "start-powered-off" property for the TSP's ARMv7M core. This change ensures the TSP remains off until explicitly enabled via the SCU, simulating the real-world flow where the PSP controls TSP boot through SCU interaction. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0-tsp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index 9c11c016ca..46691080d1 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -165,6 +165,13 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState = *dev_soc, Error **errp) qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); object_property_set_link(OBJECT(&a->armv7m), "memory", OBJECT(s->memory), &error_abort); + /* + * The TSP starts in a powered-down state and can be powered up + * by setting the TSP Control Register through the SCU + * (System Control Unit) + */ + object_property_set_bool(OBJECT(&a->armv7m), "start-powered-off", true, + &error_abort); sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort); =20 /* SDRAM */ --=20 2.43.0 From nobody Sun Feb 8 20:53:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768901604780158500 Content-Type: text/plain; charset="utf-8" This commit adds two MemoryRegion aliases to support PSP access to SSP SDRAM through shared memory remapping, as defined by the default SCU configuration. The SSP exposes two DRAM aliases: - remap1 maps PSP DRAM at 0x400000000 (32MB) to SSP SDRAM offset 0x2000000 - remap2 maps PSP DRAM at 0x42c000000 (32MB) to SSP SDRAM offset 0x0 These regions correspond to the default SCU register values, which control the mapping between PSP and coprocessor memory windows. Set SSP CPUID 4 and bumps the SCU VMState version to 3. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_scu.h | 5 +++++ hw/arm/aspeed_ast27x0-fc.c | 2 ++ hw/arm/aspeed_ast27x0-ssp.c | 6 ++++++ hw/arm/aspeed_ast27x0.c | 4 ++++ hw/misc/aspeed_scu.c | 38 ++++++++++++++++++++++++++++++++++-- 5 files changed, 53 insertions(+), 2 deletions(-) diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index 9e28bd4d2e..6f7f7d2766 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -39,6 +39,10 @@ struct AspeedSCUState { uint32_t hw_strap1; uint32_t hw_strap2; uint32_t hw_prot_key; + + MemoryRegion dram_remap_alias[3]; + MemoryRegion *dram; + int ssp_cpuid; }; =20 #define AST2400_A0_SILICON_REV 0x02000303U @@ -73,6 +77,7 @@ struct AspeedSCUClass { uint32_t nr_regs; bool clkin_25Mhz; const MemoryRegionOps *ops; + void (*dram_remap)(AspeedSCUState *s); }; =20 #define ASPEED_SCU_PROT_KEY 0x1688A8A8 diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index 0502a137f3..b788e6ca2a 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -101,6 +101,8 @@ static bool ast2700fc_ca35_init(MachineState *machine, = Error **errp) sc->uarts_num, serial_hd(1)); aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base, sc->uarts_num, serial_hd(2)); + object_property_set_int(OBJECT(&s->ca35), "ssp-cpuid", 4, + &error_abort); if (!qdev_realize(DEVICE(&s->ca35), NULL, errp)) { return false; } diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index cba59ae11a..cf1339e2c7 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -198,6 +198,12 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState = *dev_soc, Error **errp) memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU], &s->scu_alias); =20 + /* SDRAM remap alias used by PSP to access SSP SDRAM */ + memory_region_add_subregion(&s->sdram, 0, &s->scu->dram_remap_alias[1]= ); + memory_region_add_subregion(&s->sdram, + memory_region_size(&s->scu->dram_remap_alias[1]), + &s->scu->dram_remap_alias[0]); + /* INTC */ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { return; diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 74a004adca..ae8b22fc1c 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -389,6 +389,8 @@ static void aspeed_soc_ast2700_init(Object *obj) "hw-strap1"); object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), "hw-prot-key"); + object_property_add_alias(obj, "ssp-cpuid", OBJECT(&s->scu), + "ssp-cpuid"); =20 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUI= O); qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", @@ -740,6 +742,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) sc->memmap[ASPEED_DEV_VBOOTROM], &s->vboot= rom); =20 /* SCU */ + object_property_set_link(OBJECT(&s->scu), "dram", OBJECT(s->dram_mr), + &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { return; } diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 6829efa2dc..4b74e5adcb 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -20,6 +20,7 @@ #include "qemu/guest-random.h" #include "qemu/module.h" #include "trace.h" +#include "qemu/units.h" =20 #define TO_REG(offset) ((offset) >> 2) =20 @@ -602,12 +603,20 @@ static void aspeed_scu_realize(DeviceState *dev, Erro= r **errp) TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE); =20 sysbus_init_mmio(sbd, &s->iomem); + + if (asc->dram_remap) { + if (!s->dram) { + error_setg(errp, TYPE_ASPEED_SCU ": 'dram' link not set"); + return; + } + asc->dram_remap(s); + } } =20 static const VMStateDescription vmstate_aspeed_scu =3D { .name =3D "aspeed.scu", - .version_id =3D 2, - .minimum_version_id =3D 2, + .version_id =3D 3, + .minimum_version_id =3D 3, .fields =3D (const VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_AST2600_SCU_NR_R= EGS), VMSTATE_END_OF_LIST() @@ -619,6 +628,9 @@ static const Property aspeed_scu_properties[] =3D { DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0), DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0), DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0), + DEFINE_PROP_INT32("ssp-cpuid", AspeedSCUState, ssp_cpuid, -1), + DEFINE_PROP_LINK("dram", AspeedSCUState, dram, TYPE_MEMORY_REGION, + MemoryRegion *), }; =20 static void aspeed_scu_class_init(ObjectClass *klass, const void *data) @@ -872,6 +884,27 @@ static const TypeInfo aspeed_2600_scu_info =3D { .class_init =3D aspeed_2600_scu_class_init, }; =20 +static void aspeed_2700_scu_dram_remap_alias_init(AspeedSCUState *s) +{ + if (s->ssp_cpuid > 0) { + /* + * The SSP coprocessor uses two memory aliases (remap1 and remap2) + * to access shared memory regions in the PSP DRAM: + * + * - remap1 maps PSP DRAM at 0x400000000 (size: 32MB) to SSP SDRAM + * offset 0x2000000 + * - remap2 maps PSP DRAM at 0x42c000000 (size: 32MB) to SSP SDRAM + * offset 0x0 + */ + memory_region_init_alias(&s->dram_remap_alias[0], OBJECT(s), + "ssp.dram.remap1", s->dram, + 0, 32 * MiB); + memory_region_init_alias(&s->dram_remap_alias[1], OBJECT(s), + "ssp.dram.remap2", s->dram, + 0x2c000000, 32 * MiB); + } +} + static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset, unsigned size) { @@ -982,6 +1015,7 @@ static void aspeed_2700_scu_class_init(ObjectClass *kl= ass, const void *data) asc->nr_regs =3D ASPEED_AST2700_SCU_NR_REGS; asc->clkin_25Mhz =3D true; asc->ops =3D &aspeed_ast2700_scu_ops; + asc->dram_remap =3D aspeed_2700_scu_dram_remap_alias_init; } =20 static uint64_t aspeed_ast2700_scuio_read(void *opaque, hwaddr offset, --=20 2.43.0 From nobody Sun Feb 8 20:53:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768901457; cv=none; d=zohomail.com; s=zohoarc; b=Vdk7QUi3vHgnj+oM2/DcQRyluyDAJU2FmYcF0ocMuvr95ipVrV+gHiZCFTL6E19m7m+0LXxVib8ky10hKfClf5WfY618v/lI/tgmdoGgJqeU36BYEsgiiDjmQDnAkYtf+WyCEvEhKG46c8d5GpylK2uTbZ/FlvrID6OMhrFz8xU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768901457; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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charset="utf-8" This commit adds a MemoryRegion alias to support PSP access to TSP SDRAM through shared memory remapping, as defined by the default SCU configuration. The TSP coprocessor exposes one DRAM alias: - remap maps PSP DRAM at 0x42e000000 (32MB) to TSP SDRAM offset 0x0 This region corresponds to the default SCU register value, which controls the mapping between PSP and coprocessor memory windows. Set TSP CPUID 5. SCU VMState version remains at 3, as it was already bumped= in a previous commit. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_scu.h | 1 + hw/arm/aspeed_ast27x0-fc.c | 2 ++ hw/arm/aspeed_ast27x0-tsp.c | 3 +++ hw/arm/aspeed_ast27x0.c | 2 ++ hw/misc/aspeed_scu.c | 15 +++++++++++++++ 5 files changed, 23 insertions(+) diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index 6f7f7d2766..1e18dcd4a5 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -43,6 +43,7 @@ struct AspeedSCUState { MemoryRegion dram_remap_alias[3]; MemoryRegion *dram; int ssp_cpuid; + int tsp_cpuid; }; =20 #define AST2400_A0_SILICON_REV 0x02000303U diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index b788e6ca2a..e03f6870e7 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -103,6 +103,8 @@ static bool ast2700fc_ca35_init(MachineState *machine, = Error **errp) sc->uarts_num, serial_hd(2)); object_property_set_int(OBJECT(&s->ca35), "ssp-cpuid", 4, &error_abort); + object_property_set_int(OBJECT(&s->ca35), "tsp-cpuid", 5, + &error_abort); if (!qdev_realize(DEVICE(&s->ca35), NULL, errp)) { return false; } diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index 46691080d1..5d2977b45c 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -198,6 +198,9 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *= dev_soc, Error **errp) memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU], &s->scu_alias); =20 + /* SDRAM remap alias used by PSP to access TSP SDRAM */ + memory_region_add_subregion(&s->sdram, 0, &s->scu->dram_remap_alias[2]= ); + /* INTC */ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { return; diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index ae8b22fc1c..6e4b456b8c 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -391,6 +391,8 @@ static void aspeed_soc_ast2700_init(Object *obj) "hw-prot-key"); object_property_add_alias(obj, "ssp-cpuid", OBJECT(&s->scu), "ssp-cpuid"); + object_property_add_alias(obj, "tsp-cpuid", OBJECT(&s->scu), + "tsp-cpuid"); =20 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUI= O); qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 4b74e5adcb..ec373147ab 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -629,6 +629,7 @@ static const Property aspeed_scu_properties[] =3D { DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0), DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0), DEFINE_PROP_INT32("ssp-cpuid", AspeedSCUState, ssp_cpuid, -1), + DEFINE_PROP_INT32("tsp-cpuid", AspeedSCUState, tsp_cpuid, -1), DEFINE_PROP_LINK("dram", AspeedSCUState, dram, TYPE_MEMORY_REGION, MemoryRegion *), }; @@ -903,6 +904,20 @@ static void aspeed_2700_scu_dram_remap_alias_init(Aspe= edSCUState *s) "ssp.dram.remap2", s->dram, 0x2c000000, 32 * MiB); } + + if (s->tsp_cpuid > 0) { + /* + * The TSP coprocessor uses one memory alias (remap) to access a s= hared + * region in the PSP DRAM: + * + * - remap maps PSP DRAM at 0x42e000000 (size: 32MB) to TSP SDRAM + * offset 0x0 + * + */ + memory_region_init_alias(&s->dram_remap_alias[2], OBJECT(s), + "tsp.dram.remap", s->dram, + 0x2e000000, 32 * MiB); + } } =20 static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset, --=20 2.43.0 From nobody Sun Feb 8 20:53:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768901561; cv=none; d=zohomail.com; s=zohoarc; b=K127cOI+FvvADCOA+0d6gEVWs0oORbGh7TKLItZEi3GoxnVR2oQnbU3kcrOt0qCs7PdO/RgjGORPa5jvyEZgUVHorRY7UFqEjLdqWTGLHrscYY5dIZ2rmJo0f8DLV6Ld9v6JyYg2eoiysR+myz5RtG74/uVSXIP8d5j4tpnlYEI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768901561; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768901562643158500 Content-Type: text/plain; charset="utf-8" This patch implements SSP reset and power control logic in the SCU for AST2= 700. It introduces support for the following behavior: 1. SSP Reset Trigger (via SCU 0x200): - SSP reset is triggered by writing 1 to bit 30 (RW1S) of SYS_RESET_CTRL= _1. 2. SSP Reset State and Source Hold (via SCU 0x120): - Upon reset, bit 8 (RST_RB) is set to indicate the SSP is in reset. - Bit 10 (RST_SRC_RB) is set to indicate the reset was triggered by an e= xternal source. - Bit 1 (RST) is a software-controlled bit used to request holding SSP i= n reset. - If an external reset source is present and bit 1 is set, bit 9 (RST_HO= LD_RB) will also be asserted to indicate the SSP is being held in reset. - If bit 1 is cleared, RST_HOLD_RB will be deasserted accordingly. 3. Hold Release and Power-on: - If RST_HOLD_RB is clear (0), SSP is powered on immediately after reset= is deasserted. - If RST_HOLD_RB is set (1), the user must write ENABLE (bit 0) to SSP_C= TRL_0 to release the hold and power on SSP explicitly. - Writing ENABLE (bit 0) is a one-shot operation and will auto-clear aft= er execution. 4. Reset Status Clear (via SCU 0x204): - The reset status can be cleared by writing 1 to bit 30 (RW1C) of SYS_R= ST_CLR_1, which will deassert RST_SRC_RB and potentially trigger power-on if no = hold is active. 5. SSP Power Control Logic: - `handle_ssp_tsp_on()` clears RST_SRC_RB and RST_RB (if not held), and = invokes `arm_set_cpu_on_and_reset(cpuid)` to power on the SSP core (CPUID 4). - `handle_ssp_tsp_off()` sets RST_RB and RST_SRC_RB; if RST is active, a= lso asserts RST_HOLD_RB and invokes `arm_set_cpu_off(cpuid)`. 6. Register Initialization and Definitions: - Adds SCU register definitions for SSP_CTRL_0 (0x120), SYS_RST_CTRL_1 (= 0x200), and SYS_RST_CLR_1 (0x204). - Updates the reset values for these registers during SCU initialization. The default values are based on EVB (evaluation board) register dump observ= ations. This patch enables proper modeling of SSP lifecycle management across reset, hold, and power-on states for the AST2700 SoC. Signed-off-by: Jamin Lin --- hw/misc/aspeed_scu.c | 107 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index ec373147ab..506a4fa73f 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -21,6 +21,7 @@ #include "qemu/module.h" #include "trace.h" #include "qemu/units.h" +#include "target/arm/arm-powerctl.h" =20 #define TO_REG(offset) ((offset) >> 2) =20 @@ -144,6 +145,17 @@ #define AST2700_HW_STRAP1_SEC2 TO_REG(0x28) #define AST2700_HW_STRAP1_SEC3 TO_REG(0x2C) =20 +/* SSP TSP */ +#define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120) +#define AST2700_SSP_TSP_ENABLE BIT(0) +#define AST2700_SSP_TSP_RST BIT(1) +#define AST2700_SSP_TSP_RST_RB BIT(8) +#define AST2700_SSP_TSP_RST_HOLD_RB BIT(9) +#define AST2700_SSP_TSP_RST_SRC_RB BIT(10) +#define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200) +#define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204) +#define AST2700_SCU_SYS_RST_SSP BIT(30) + #define AST2700_SCU_CLK_SEL_1 TO_REG(0x280) #define AST2700_SCU_HPLL_PARAM TO_REG(0x300) #define AST2700_SCU_HPLL_EXT_PARAM TO_REG(0x304) @@ -920,6 +932,35 @@ static void aspeed_2700_scu_dram_remap_alias_init(Aspe= edSCUState *s) } } =20 +static void handle_2700_ssp_tsp_on(struct AspeedSCUState *s, int cpuid, + int reg) +{ + uint32_t val =3D s->regs[reg]; + + val &=3D ~AST2700_SSP_TSP_RST_SRC_RB; + if (!(val & AST2700_SSP_TSP_RST_HOLD_RB)) { + val &=3D ~AST2700_SSP_TSP_RST_RB; + arm_set_cpu_on_and_reset(cpuid); + } + + s->regs[reg] =3D val; +} + +static void handle_2700_ssp_tsp_off(struct AspeedSCUState *s, int cpuid, + int reg) +{ + uint32_t val =3D s->regs[reg]; + + val |=3D AST2700_SSP_TSP_RST_RB; + val |=3D AST2700_SSP_TSP_RST_SRC_RB; + if (val & AST2700_SSP_TSP_RST) { + val |=3D AST2700_SSP_TSP_RST_HOLD_RB; + } + arm_set_cpu_off(cpuid); + + s->regs[reg] =3D val; +} + static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset, unsigned size) { @@ -951,6 +992,9 @@ static void aspeed_ast2700_scu_write(void *opaque, hwad= dr offset, int reg =3D TO_REG(offset); /* Truncate here so bitwise operations below behave as expected */ uint32_t data =3D data64; + uint32_t active; + uint32_t oldval; + int cpuid; =20 if (reg >=3D ASPEED_AST2700_SCU_NR_REGS) { qemu_log_mask(LOG_GUEST_ERROR, @@ -962,6 +1006,63 @@ static void aspeed_ast2700_scu_write(void *opaque, hw= addr offset, trace_aspeed_ast2700_scu_write(offset, size, data); =20 switch (reg) { + case AST2700_SCU_SSP_CTRL_0: + cpuid =3D s->ssp_cpuid; + if (cpuid < 0) { + return; + } + oldval =3D s->regs[reg]; + data &=3D 0xff; + active =3D oldval ^ data; + + /* + * If reset bit is being released (1 -> 0) and no other reset sour= ce + * is active, clear HOLD_RB and power on the corresponding CPU. + */ + if ((active & AST2700_SSP_TSP_RST) && !(data & AST2700_SSP_TSP_RST= )) { + s->regs[reg] &=3D ~AST2700_SSP_TSP_RST_HOLD_RB; + if ((oldval & AST2700_SSP_TSP_RST_RB) && + !(oldval & AST2700_SSP_TSP_RST_SRC_RB)) { + handle_2700_ssp_tsp_on(s, cpuid, reg); + } + } + + /* + * If ENABLE bit is newly set and reset state is ready, + * clear HOLD_RB and power on the corresponding CPU. + */ + if ((active & AST2700_SSP_TSP_ENABLE) && + (oldval & AST2700_SSP_TSP_RST_RB) && + (oldval & AST2700_SSP_TSP_RST_HOLD_RB) && + !(oldval & AST2700_SSP_TSP_RST_SRC_RB)) { + s->regs[reg] &=3D ~AST2700_SSP_TSP_RST_HOLD_RB; + handle_2700_ssp_tsp_on(s, cpuid, reg); + } + + /* Auto-clear the ENABLE bit (one-shot behavior) */ + data &=3D ~AST2700_SSP_TSP_ENABLE; + s->regs[reg] =3D (s->regs[reg] & ~0xff) | (data & 0xff); + return; + case AST2700_SCU_SYS_RST_CTRL_1: + if (s->ssp_cpuid < 0) { + return; + } + if (data & AST2700_SCU_SYS_RST_SSP) { + handle_2700_ssp_tsp_off(s, s->ssp_cpuid, AST2700_SCU_SSP_CTRL_= 0); + } + s->regs[reg] |=3D data; + return; + case AST2700_SCU_SYS_RST_CLR_1: + if (s->ssp_cpuid < 0) { + return; + } + oldval =3D s->regs[AST2700_SCU_SYS_RST_CTRL_1]; + active =3D data & oldval; + if (active & AST2700_SCU_SYS_RST_SSP) { + handle_2700_ssp_tsp_on(s, s->ssp_cpuid, AST2700_SCU_SSP_CTRL_0= ); + } + s->regs[AST2700_SCU_SYS_RST_CTRL_1] &=3D ~active; + return; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n", @@ -989,6 +1090,8 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700= _SCU_NR_REGS] =3D { [AST2700_HW_STRAP1_SEC1] =3D 0x000000FF, [AST2700_HW_STRAP1_SEC2] =3D 0x00000000, [AST2700_HW_STRAP1_SEC3] =3D 0x1000408F, + [AST2700_SCU_SSP_CTRL_0] =3D 0x000007FE, + [AST2700_SCU_SYS_RST_CTRL_1] =3D 0xFFC37FDC, [AST2700_SCU_HPLL_PARAM] =3D 0x0000009f, [AST2700_SCU_HPLL_EXT_PARAM] =3D 0x8000004f, [AST2700_SCU_DPLL_PARAM] =3D 0x0080009f, @@ -1014,6 +1117,10 @@ static void aspeed_ast2700_scu_reset(DeviceState *de= v) memcpy(s->regs, asc->resets, asc->nr_regs * 4); s->regs[AST2700_SILICON_REV] =3D s->silicon_rev; s->regs[AST2700_HW_STRAP1] =3D s->hw_strap1; + + if (s->ssp_cpuid > 0) { + arm_set_cpu_off(s->ssp_cpuid); + } } =20 static void aspeed_2700_scu_class_init(ObjectClass *klass, const void *dat= a) --=20 2.43.0 From nobody Sun Feb 8 20:53:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768901604; cv=none; d=zohomail.com; s=zohoarc; b=M/FJ20btROoojcXI6rCeqlapwpzB0V29kXm2DtvkQCAKxpDNRhFN/P22EQ3CTMHRSe+zdwBj2AVwdPRByg624mshw/gJYMxUZ5gEutBnWlKZ/1FwU5uDzEqLWw6MXRlknrtGbc5rMRlUmXUnEDXjLYvhAVwhKYdkNql/OKF7gAM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768901604; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768901604967154100 Content-Type: text/plain; charset="utf-8" This patch implements TSP reset and power control logic in the SCU module for AST2700. It introduces support for the following behavior: 1. TSP Reset Trigger (via SCU 0x220): - TSP reset is triggered by writing 1 to bit 9 (RW1S) of SYS_RESET_CTRL_= 2. 2. TSP Reset State and Source Hold (via SCU 0x160): - Upon reset, bit 8 (RST_RB) is set to indicate the TSP is in reset. - Bit 10 (RST_SRC_RB) is set to indicate the reset was triggered by an e= xternal source. - Bit 1 (RST) is a software-controlled bit used to request holding TSP i= n reset. - If an external reset source is present and bit 1 is set, bit 9 (RST_HO= LD_RB) will also be asserted to indicate the TSP is being held in reset. - If bit 1 is cleared, RST_HOLD_RB will be deasserted accordingly. 3. Hold Release and Power-on: - If RST_HOLD_RB is clear (0), TSP is powered on immediately after reset= is deasserted. - If RST_HOLD_RB is set (1), the user must write ENABLE (bit 0) to TSP_C= TRL_0 to release the hold and power on TSP explicitly. - Writing ENABLE (bit 0) is a one-shot operation and will auto-clear aft= er execution. 4. Reset Status Clear (via SCU 0x224): - The reset status can be cleared by writing 1 to bit 9 (RW1C) of SYS_RS= T_CLR_2, which will deassert RST_SRC_RB and potentially trigger power-on if no = hold is active. 5. TSP Power Control Logic: - handle_ssp_tsp_on() clears RST_SRC_RB and RST_RB (if not held), and in= vokes arm_set_cpu_on_and_reset(cpuid) to power on the TSP core (CPUID 5). - handle_ssp_tsp_off() sets RST_RB and RST_SRC_RB; if RST is active, als= o asserts RST_HOLD_RB and invokes arm_set_cpu_off(cpuid). The default values are based on EVB (evaluation board) register dump observ= ations. TSP reset control shares the same helper functions and register bit layout = as SSP, with logic selected by cpuid and distinct external reset sources. Signed-off-by: Jamin Lin --- hw/misc/aspeed_scu.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 506a4fa73f..6aebdd630f 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -147,6 +147,7 @@ =20 /* SSP TSP */ #define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120) +#define AST2700_SCU_TSP_CTRL_0 TO_REG(0x160) #define AST2700_SSP_TSP_ENABLE BIT(0) #define AST2700_SSP_TSP_RST BIT(1) #define AST2700_SSP_TSP_RST_RB BIT(8) @@ -155,6 +156,9 @@ #define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200) #define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204) #define AST2700_SCU_SYS_RST_SSP BIT(30) +#define AST2700_SCU_SYS_RST_CTRL_2 TO_REG(0x220) +#define AST2700_SCU_SYS_RST_CLR_2 TO_REG(0x224) +#define AST2700_SCU_SYS_RST_TSP BIT(9) =20 #define AST2700_SCU_CLK_SEL_1 TO_REG(0x280) #define AST2700_SCU_HPLL_PARAM TO_REG(0x300) @@ -1007,7 +1011,10 @@ static void aspeed_ast2700_scu_write(void *opaque, h= waddr offset, =20 switch (reg) { case AST2700_SCU_SSP_CTRL_0: - cpuid =3D s->ssp_cpuid; + case AST2700_SCU_TSP_CTRL_0: + cpuid =3D (reg =3D=3D AST2700_SCU_SSP_CTRL_0) ? + s->ssp_cpuid : s->tsp_cpuid; + if (cpuid < 0) { return; } @@ -1063,6 +1070,28 @@ static void aspeed_ast2700_scu_write(void *opaque, h= waddr offset, } s->regs[AST2700_SCU_SYS_RST_CTRL_1] &=3D ~active; return; + case AST2700_SCU_SYS_RST_CTRL_2: + if (s->tsp_cpuid < 0) { + return; + } + data &=3D 0x00001fff; + if (data & AST2700_SCU_SYS_RST_TSP) { + handle_2700_ssp_tsp_off(s, s->tsp_cpuid, AST2700_SCU_TSP_CTRL_= 0); + } + s->regs[reg] |=3D data; + return; + case AST2700_SCU_SYS_RST_CLR_2: + if (s->tsp_cpuid < 0) { + return; + } + data &=3D 0x00001fff; + oldval =3D s->regs[AST2700_SCU_SYS_RST_CTRL_2]; + active =3D data & oldval; + if (active & AST2700_SCU_SYS_RST_TSP) { + handle_2700_ssp_tsp_on(s, s->tsp_cpuid, AST2700_SCU_TSP_CTRL_0= ); + } + s->regs[AST2700_SCU_SYS_RST_CTRL_2] &=3D ~active; + return; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n", @@ -1091,7 +1120,9 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST270= 0_SCU_NR_REGS] =3D { [AST2700_HW_STRAP1_SEC2] =3D 0x00000000, [AST2700_HW_STRAP1_SEC3] =3D 0x1000408F, [AST2700_SCU_SSP_CTRL_0] =3D 0x000007FE, + [AST2700_SCU_TSP_CTRL_0] =3D 0x000007FE, [AST2700_SCU_SYS_RST_CTRL_1] =3D 0xFFC37FDC, + [AST2700_SCU_SYS_RST_CTRL_2] =3D 0x00001FFF, [AST2700_SCU_HPLL_PARAM] =3D 0x0000009f, [AST2700_SCU_HPLL_EXT_PARAM] =3D 0x8000004f, [AST2700_SCU_DPLL_PARAM] =3D 0x0080009f, @@ -1121,6 +1152,10 @@ static void aspeed_ast2700_scu_reset(DeviceState *de= v) if (s->ssp_cpuid > 0) { arm_set_cpu_off(s->ssp_cpuid); } + + if (s->tsp_cpuid > 0) { + arm_set_cpu_off(s->tsp_cpuid); + } } =20 static void aspeed_2700_scu_class_init(ObjectClass *klass, const void *dat= a) --=20 2.43.0 From nobody Sun Feb 8 20:53:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768901608; cv=none; d=zohomail.com; s=zohoarc; b=Jn1ohYZNfsNQRatW537wiJlwUUQedNKlDsXT30rQJKDAvaldLt1w64eiFWyGdjHQDsnshFWj+Z/gAvTDnZOrlBGRFOHUhGGss0QVOGpoihNiUvwumI71UsxDjJ9GGkSlC0t/vd8R9IXl515x+qcZ70ZFXYlQbdOJRb8IVyIF8ko= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768901608; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 20 Jan 2026 04:30:09 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 17:29:41 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 17:29:41 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 08/11] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap Date: Tue, 20 Jan 2026 17:29:33 +0800 Message-ID: <20260120092939.2708302-9-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120092939.2708302-1-jamin_lin@aspeedtech.com> References: <20260120092939.2708302-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768901610992154100 Content-Type: text/plain; charset="utf-8" This commit adds SCU register support for SSP SDRAM remap control and runti= me activation. It introduces logic for the PSP to dynamically configure the ma= pping of its own DRAM windows into SSP-visible SDRAM space, enabling shared memory communication via memory region aliases. - coprocessor_sdram_remap[0]: maps PSP DRAM offset 0x400000000 (size: 32MB)= to SSP SDRAM offset 0x2000000 - coprocessor_sdram_remap[0]: maps PSP DRAM offset 0x42c000000 (size: 32MB)= to SSP SDRAM offset 0x0 The SCU registers AST2700_SCU_SSP_CTRL_1/2 and AST2700_SCU_SSP_REMAP_ADDR_{1,2} / REMAP_SIZE_{1,2} allow runtime reconfigu= ration of alias offset, base, and size. |------------------------------------------| |---------------------= -------| | PSP DRAM | | SSP SDRAM = | |------------------------------------------| |---------------------= -------| | 0x4_0000_0000 (SCU_124 << 4) | --> | 0x0000_0000 = | | remap1 base |---| | | - SCU_150: target a= ddr | | size: 32MB (SCU_14C) | | | | remap2 = | |------------------------------------------| | | |---------------------= -------| | | | | | = | | 0x4_2C00_0000 (SCU_128 << 4) |-----| | 0x0200_0000 = | | remap2 base | | | - SCU_148: target a= ddr | | size: 32MB (SCU_154) | |---> | remap1 = | |------------------------------------------| |---------------------= -------| Signed-off-by: Jamin Lin --- hw/misc/aspeed_scu.c | 50 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 6aebdd630f..27591f53c4 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -147,6 +147,12 @@ =20 /* SSP TSP */ #define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120) +#define AST2700_SCU_SSP_CTRL_1 TO_REG(0x124) +#define AST2700_SCU_SSP_CTRL_2 TO_REG(0x128) +#define AST2700_SCU_SSP_REMAP_ADDR_1 TO_REG(0x148) +#define AST2700_SCU_SSP_REMAP_SIZE_1 TO_REG(0x14C) +#define AST2700_SCU_SSP_REMAP_ADDR_2 TO_REG(0x150) +#define AST2700_SCU_SSP_REMAP_SIZE_2 TO_REG(0x154) #define AST2700_SCU_TSP_CTRL_0 TO_REG(0x160) #define AST2700_SSP_TSP_ENABLE BIT(0) #define AST2700_SSP_TSP_RST BIT(1) @@ -993,6 +999,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwad= dr offset, uint64_t data64, unsigned size) { AspeedSCUState *s =3D ASPEED_SCU(opaque); + MemoryRegion *mr =3D NULL; int reg =3D TO_REG(offset); /* Truncate here so bitwise operations below behave as expected */ uint32_t data =3D data64; @@ -1050,6 +1057,37 @@ static void aspeed_ast2700_scu_write(void *opaque, h= waddr offset, data &=3D ~AST2700_SSP_TSP_ENABLE; s->regs[reg] =3D (s->regs[reg] & ~0xff) | (data & 0xff); return; + case AST2700_SCU_SSP_CTRL_1: + case AST2700_SCU_SSP_CTRL_2: + mr =3D (reg =3D=3D AST2700_SCU_SSP_CTRL_1) ? + &s->dram_remap_alias[0] : &s->dram_remap_alias[1]; + if (s->ssp_cpuid < 0 || mr =3D=3D NULL) { + return; + } + data &=3D 0x7fffffff; + memory_region_set_alias_offset(mr, + ((uint64_t) data << 4) & 0x3fffffff= f); + break; + case AST2700_SCU_SSP_REMAP_ADDR_1: + case AST2700_SCU_SSP_REMAP_ADDR_2: + mr =3D (reg =3D=3D AST2700_SCU_SSP_REMAP_ADDR_1) ? + &s->dram_remap_alias[0] : &s->dram_remap_alias[1]; + if (s->ssp_cpuid < 0 || mr =3D=3D NULL) { + return; + } + data &=3D 0x3fffffff; + memory_region_set_address(mr, data); + break; + case AST2700_SCU_SSP_REMAP_SIZE_1: + case AST2700_SCU_SSP_REMAP_SIZE_2: + mr =3D (reg =3D=3D AST2700_SCU_SSP_REMAP_SIZE_1) ? + &s->dram_remap_alias[0] : &s->dram_remap_alias[1]; + if (s->ssp_cpuid < 0 || mr =3D=3D NULL) { + return; + } + data &=3D 0x3fffffff; + memory_region_set_size(mr, data); + break; case AST2700_SCU_SYS_RST_CTRL_1: if (s->ssp_cpuid < 0) { return; @@ -1120,6 +1158,12 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST27= 00_SCU_NR_REGS] =3D { [AST2700_HW_STRAP1_SEC2] =3D 0x00000000, [AST2700_HW_STRAP1_SEC3] =3D 0x1000408F, [AST2700_SCU_SSP_CTRL_0] =3D 0x000007FE, + [AST2700_SCU_SSP_CTRL_1] =3D 0x40000000, + [AST2700_SCU_SSP_CTRL_2] =3D 0x42C00000, + [AST2700_SCU_SSP_REMAP_ADDR_1] =3D 0x02000000, + [AST2700_SCU_SSP_REMAP_SIZE_1] =3D 0x02000000, + [AST2700_SCU_SSP_REMAP_ADDR_2] =3D 0x00000000, + [AST2700_SCU_SSP_REMAP_SIZE_2] =3D 0x02000000, [AST2700_SCU_TSP_CTRL_0] =3D 0x000007FE, [AST2700_SCU_SYS_RST_CTRL_1] =3D 0xFFC37FDC, [AST2700_SCU_SYS_RST_CTRL_2] =3D 0x00001FFF, @@ -1151,6 +1195,12 @@ static void aspeed_ast2700_scu_reset(DeviceState *de= v) =20 if (s->ssp_cpuid > 0) { arm_set_cpu_off(s->ssp_cpuid); + memory_region_set_address(&s->dram_remap_alias[0], 32 * MiB); + memory_region_set_alias_offset(&s->dram_remap_alias[0], 0); + memory_region_set_size(&s->dram_remap_alias[0], 32 * MiB); + memory_region_set_address(&s->dram_remap_alias[1], 0); + memory_region_set_alias_offset(&s->dram_remap_alias[1], 0x2c000000= ); + memory_region_set_size(&s->dram_remap_alias[1], 32 * MiB); } =20 if (s->tsp_cpuid > 0) { --=20 2.43.0 From nobody Sun Feb 8 20:53:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768901503; cv=none; d=zohomail.com; s=zohoarc; b=aiXXvo2ye5x+p5ZFnopK4uR0310K6/pUszTeAEso1wtny7ispKJz392rNjgiSN7/bRnPMsJOITqgAROdnu0idY3WFu8T0FU0zDGidY3g/4Rz2jQf5DNLgeqLeyEpZLdixo2KrMX873ZxWQTbbFl41D6EgaTz12vIfIu2LKyqj0s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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charset="utf-8" This commit adds SCU register support for TSP SDRAM remap control and runti= me activation. Unlike SSP, the TSP does not support configurable target addres= s remapping through SCU registers. It only supports setting the PSP DRAM base and size,= which are then aliased into the TSP-visible SDRAM window. coprocessor_sdram_remap[2]: maps PSP DRAM offset 0x42E000000 (size: 32MB) t= o TSP SDRAM offset 0x0 The SCU registers AST2700_SCU_TSP_CTRL_1 and AST2700_SCU_TSP_REMAP_SIZE_2 allow runtime reconfiguration of the DRAM base= (alias offset) and mapping size. |------------------------------------------| |---------------------= -------| | PSP DRAM | | TSP SDRAM = | |------------------------------------------| |---------------------= -------| | 0x42E0_0000_0 (SCU_168 << 4) | | 0x0000_0000 = | | remap base |------> | - fixed target addr= | | size: 32MB (SCU_194) | | = | |------------------------------------------| |---------------------= -------| Signed-off-by: Jamin Lin --- hw/misc/aspeed_scu.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 27591f53c4..69d26df818 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -159,6 +159,8 @@ #define AST2700_SSP_TSP_RST_RB BIT(8) #define AST2700_SSP_TSP_RST_HOLD_RB BIT(9) #define AST2700_SSP_TSP_RST_SRC_RB BIT(10) +#define AST2700_SCU_TSP_CTRL_1 TO_REG(0x168) +#define AST2700_SCU_TSP_REMAP_SIZE_2 TO_REG(0x194) #define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200) #define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204) #define AST2700_SCU_SYS_RST_SSP BIT(30) @@ -1088,6 +1090,23 @@ static void aspeed_ast2700_scu_write(void *opaque, h= waddr offset, data &=3D 0x3fffffff; memory_region_set_size(mr, data); break; + case AST2700_SCU_TSP_CTRL_1: + mr =3D &s->dram_remap_alias[2]; + if (s->tsp_cpuid < 0 || mr =3D=3D NULL) { + return; + } + data &=3D 0x7fffffff; + memory_region_set_alias_offset(mr, + ((uint64_t) data << 4) & 0x3fffffff= f); + break; + case AST2700_SCU_TSP_REMAP_SIZE_2: + mr =3D &s->dram_remap_alias[2]; + if (s->tsp_cpuid < 0 || mr =3D=3D NULL) { + return; + } + data &=3D 0x3fffffff; + memory_region_set_size(mr, data); + break; case AST2700_SCU_SYS_RST_CTRL_1: if (s->ssp_cpuid < 0) { return; @@ -1165,6 +1184,8 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST270= 0_SCU_NR_REGS] =3D { [AST2700_SCU_SSP_REMAP_ADDR_2] =3D 0x00000000, [AST2700_SCU_SSP_REMAP_SIZE_2] =3D 0x02000000, [AST2700_SCU_TSP_CTRL_0] =3D 0x000007FE, + [AST2700_SCU_TSP_CTRL_1] =3D 0x42E00000, + [AST2700_SCU_TSP_REMAP_SIZE_2] =3D 0x02000000, [AST2700_SCU_SYS_RST_CTRL_1] =3D 0xFFC37FDC, [AST2700_SCU_SYS_RST_CTRL_2] =3D 0x00001FFF, [AST2700_SCU_HPLL_PARAM] =3D 0x0000009f, @@ -1205,6 +1226,8 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev) =20 if (s->tsp_cpuid > 0) { arm_set_cpu_off(s->tsp_cpuid); + memory_region_set_alias_offset(&s->dram_remap_alias[2], 0x2e000000= ); + memory_region_set_size(&s->dram_remap_alias[2], 32 * MiB); } } =20 --=20 2.43.0 From nobody Sun Feb 8 20:53:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768901502; cv=none; d=zohomail.com; s=zohoarc; b=Q17nZPhxGLHexJcvxRkuY3qjGEp5lxFZg6iOkfKns67je0nrPCqFAxn15QW4iIpM2o1THQG89wN198jayZPSnQzWB4bSTO1XaN+fwuUqk7QvjjkfO+S3uwHH+h+LgIER2HuoLGs7S64LVEdjLOjbVT0Xp9Lx/dWnljwmu2VFjMw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768901502; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 20 Jan 2026 04:30:15 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 17:29:42 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 17:29:42 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 10/11] tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP and load binaries from DRAM Date: Tue, 20 Jan 2026 17:29:35 +0800 Message-ID: <20260120092939.2708302-11-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120092939.2708302-1-jamin_lin@aspeedtech.com> References: <20260120092939.2708302-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" SSP and TSP now boot in a powered-off state by default. Enabling them requi= res the PSP (Cortex-A35) to explicitly set SCU control registers at runtime. Th= is behavior aligns with real hardware. Update the AST2700 FC functional test to reflect this behavior by enabling SSP and TSP from the U-Boot shell before booting OpenBMC. The test now programs the required SCU registers, saves the environment, and boots the system so that SSP and TSP are powered on when the PSP starts. For the vbootrom test case, these steps are not required because vbootrom already performs the necessary initialization. Therefore, the U-Boot shell configuration is only applied to the manual loader test flow. Additionally, switch SSP and TSP loading from ELF-based CPU loaders to binary images loaded into PSP DRAM at fixed addresses, and remove the use of snapshot mode. Changes include: - Add enable_ssp_tsp() to configure SCU registers via U-Boot - Remove snapshot option from QEMU command line - Load SSP binary at DRAM address 0x42C000000 - Load TSP binary at DRAM address 0x42E000000 Signed-off-by: Jamin Lin --- .../aarch64/test_aspeed_ast2700fc.py | 35 +++++++++++-------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/func= tional/aarch64/test_aspeed_ast2700fc.py index 8dbc8f234f..e0fb4890be 100755 --- a/tests/functional/aarch64/test_aspeed_ast2700fc.py +++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py @@ -9,7 +9,7 @@ import os =20 from qemu_test import QemuSystemTest, Asset -from qemu_test import wait_for_console_pattern +from qemu_test import wait_for_console_pattern, exec_command from qemu_test import exec_command_and_wait_for_pattern =20 =20 @@ -23,12 +23,22 @@ def do_test_aarch64_aspeed_sdk_start(self, image): self.vm.add_args('-device', 'e1000e,netdev=3Dnet1,bus=3Dpcie.2') self.vm.add_args('-netdev', 'user,id=3Dnet1') self.vm.add_args('-drive', 'file=3D' + image + ',if=3Dmtd,format= =3Draw', - '-net', 'nic', '-net', 'user', '-snapshot') + '-net', 'nic', '-net', 'user') =20 self.vm.launch() =20 + def enable_ssp_tsp(self): + wait_for_console_pattern(self, 'Hit any key to stop autoboot') + exec_command_and_wait_for_pattern(self, '\012', '=3D>') + exec_command_and_wait_for_pattern(self, + 'setenv bootcmd "mw 12c02204 40000000; mw 12c02120 1;' + 'mw 12c02224 00000200; mw 12c02160 1; run bootspi"', '=3D>') + exec_command_and_wait_for_pattern(self, 'saveenv', 'OK') + exec_command(self, 'boot') + def verify_openbmc_boot_and_login(self, name): wait_for_console_pattern(self, 'U-Boot 2023.10') + self.enable_ssp_tsp(); wait_for_console_pattern(self, '## Loading kernel from FIT Image') wait_for_console_pattern(self, 'Starting kernel ...') =20 @@ -36,17 +46,6 @@ def verify_openbmc_boot_and_login(self, name): exec_command_and_wait_for_pattern(self, 'root', 'Password:') exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~= #') =20 - def load_ast2700fc_coprocessor(self, name): - load_elf_list =3D { - 'ssp': self.scratch_file(name, 'zephyr-aspeed-ssp.elf'), - 'tsp': self.scratch_file(name, 'zephyr-aspeed-tsp.elf') - } - - for cpu_num, key in enumerate(load_elf_list, start=3D4): - file =3D load_elf_list[key] - self.vm.add_args('-device', - f'loader,file=3D{file},cpu-num=3D{cpu_num}') - ASSET_SDK_V908_AST2700 =3D Asset( 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v= 09.08/ast2700-default-obmc.tar.gz', 'eac3dc409b7ea3cd4b03d4792d3cebd469792ad893cb51e1d15f0fc20bd1e= 2cd') @@ -121,6 +120,14 @@ def start_ast2700fc_test(self, name): 'addr': '0x430080000', 'file': self.scratch_file(name, 'optee', 'tee-raw.bin') + }, + { + 'addr': '0x42C000000', + 'file': self.scratch_file(name, 'zephyr-aspeed-ssp.bin') + }, + { + 'addr': '0x42E000000', + 'file': self.scratch_file(name, 'zephyr-aspeed-tsp.bin') } ] =20 @@ -134,13 +141,11 @@ def start_ast2700fc_test(self, name): self.vm.add_args('-device', f'loader,addr=3D0x430000000,cpu-num=3D{i}') =20 - self.load_ast2700fc_coprocessor(name) self.do_test_aarch64_aspeed_sdk_start( self.scratch_file(name, 'image-bmc')) =20 def start_ast2700fc_test_vbootrom(self, name): self.vm.add_args('-bios', 'ast27x0_bootrom.bin') - self.load_ast2700fc_coprocessor(name) self.do_test_aarch64_aspeed_sdk_start( self.scratch_file(name, 'image-bmc')) =20 --=20 2.43.0 From nobody Sun Feb 8 20:53:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Signed-off-by: Jamin Lin --- docs/system/arm/aspeed.rst | 37 +++++++++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 4fa1739cb5..a1f4366f87 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -391,6 +391,14 @@ Booting the ast2700fc machine AST2700 features four Cortex-A35 primary processors and two Cortex-M4 copr= ocessors. **ast2700-evb** machine focuses on emulating the four Cortex-A35 primary p= rocessors, **ast2700fc** machine extends **ast2700-evb** by adding support for the tw= o Cortex-M4 coprocessors. +There are two methods to boot the ast2700fc machine. + +Manual boot using ``-device loader``: + +In this approach, users manually load firmware and assign entry points via= QEMU loader devices. +By default, the PSP begins execution at address ``0x430000000``, the load = address of the bl31 +firmware. The SSP and TSP start in the powered-off state and must be expli= citly enabled by the +PSP through writes to SCU registers. =20 Steps to boot the AST2700fc machine: =20 @@ -401,8 +409,8 @@ Steps to boot the AST2700fc machine: * bl31.bin * optee/tee-raw.bin * image-bmc - * zephyr-aspeed-ssp.elf (for SSP firmware, CPU 5) - * zephyr-aspeed-tsp.elf (for TSP firmware, CPU 6) + * zephyr-aspeed-ssp.bin (for SSP firmware, CPU 5) + * zephyr-aspeed-tsp.bin (for TSP firmware, CPU 6) =20 2. Execute the following command to start ``ast2700fc`` machine: =20 @@ -416,17 +424,38 @@ Steps to boot the AST2700fc machine: -device loader,force-raw=3Don,addr=3D$((0x400000000 + ${UBOOT_SIZE}= )),file=3D${IMGDIR}/u-boot.dtb \ -device loader,force-raw=3Don,addr=3D0x430000000,file=3D${IMGDIR}/b= l31.bin \ -device loader,force-raw=3Don,addr=3D0x430080000,file=3D${IMGDIR}/o= ptee/tee-raw.bin \ + -device loader,addr=3D0x42C000000,file=3D${IMGDIR}/zephyr-aspeed-ss= p.bin,force-raw=3Don \ + -device loader,addr=3D0x42E000000,file=3D${IMGDIR}/zephyr-aspeed-ts= p.bin,force-raw=3Don \ -device loader,cpu-num=3D0,addr=3D0x430000000 \ -device loader,cpu-num=3D1,addr=3D0x430000000 \ -device loader,cpu-num=3D2,addr=3D0x430000000 \ -device loader,cpu-num=3D3,addr=3D0x430000000 \ -drive file=3D${IMGDIR}/image-bmc,if=3Dmtd,format=3Draw \ - -device loader,file=3D${IMGDIR}/zephyr-aspeed-ssp.elf,cpu-num=3D4 \ - -device loader,file=3D${IMGDIR}/zephyr-aspeed-tsp.elf,cpu-num=3D5 \ -serial pty -serial pty -serial pty \ -snapshot \ -S -nographic =20 +Boot using a virtual boot ROM (-bios): + +In this method, the virtual boot ROM (vbootrom) handles the full initializ= ation sequence. +It starts the PSP, which then enables the SSP and TSP by programming the a= ppropriate SCU +registers, following the hardware behavior. + +Execute the following command to start ``ast2700fc`` machine: + +.. code-block:: bash + + IMGDIR=3Dast2700-default + + $ qemu-system-aarch64 -M ast2700fc \ + -bios ast27x0_bootrom.bin \ + -drive file=3D${IMGDIR}/image-bmc,if=3Dmtd,format=3Draw \ + -serial pty -serial pty -serial pty \ + -snapshot \ + -S -nographic + +Serial Console Redirection: + After launching QEMU, serial devices will be automatically redirected. Example output: =20 --=20 2.43.0