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([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7190ab921sm73298205ad.8.2026.01.18.14.08.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:08:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768774139; x=1769378939; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rE9SCEsfxqLkJO7HvWLWosr5Ikr+Oai+wZCJ1H9Hel0=; b=RsCQl6zEmNfGfNQqVOrWwsJ0Vg/mVXYxoWunHzf2Mkw19fL+nFMOXsLjJOaAxwMJLh EZu5KHecYFd/ZwbCpLqq16oa5XMB3h4okC0B9YfbO+en8Fh4DhSGnlBpT2pZZ9vo09tB WqySoiBp4Ikg+knsvjR68Di+DHW774VpoDttbaAXE2W7ZmdIPm5JqytBQvRKfDaHgnsK 5dagACOx36x7dPWe5z7gCJKb9PZQZn/R1+3/MQLaLdTbmEwVYUgkrOLuv+NPjhWeUfo0 H0Dn8d3FVuaoU+Xw8z4C7hlvd+E0JGelMRF6ZSDdoKI/WY9JetdAIJqKuhw12R+xC5ze 0etw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768774139; x=1769378939; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=rE9SCEsfxqLkJO7HvWLWosr5Ikr+Oai+wZCJ1H9Hel0=; b=pXN5m6nh5xRebVUy9bOt6Q1gkkcrR168QA1O2kSiWaK8erox13aKR3aG+dSvxi39ut qdKUkZ59CZfRIoI/GJlTWS6YrI3dh8jgVgxuiL0a+SnSiqgzsDmEU5WOVWR/SzJrn3pf 49SroRaV/NSGXv6aemSO9sUcmF7Bwo4uZAzalUXXMFCZBo0QwiBKY/aVpAxazRP+3LIW 00hB5KYighue1PVPJe5YlYIYE2ySdd8sJux9GuWhcdZnVUD3XHe+4IBvzLxqbQW70aI0 kGH0VgpMqgoznWM32rtdu29XJbv3NSrmFv+bjGImNWs+CbxMo8rrFJdIZ6iPTUn+JMeN gznA== X-Gm-Message-State: AOJu0Yz3Y+j6RwQQSTmSUqthy0lD4SVpDHe2bayJnd3L3LwpzRH1LE7R gorqiSFdvdu6L44VoH8MLLCeGep32pypYtikhY+7LPWw7Kg49CzSR+8fiHakLJ/hcnKMq/O8rW2 beFfdOrBxkg== X-Gm-Gg: AY/fxX5spX38ZtdKDzAYCPwfLLic48WTEAAd28iIPP16kK3/j64Pl748/+DDikbxJar 1OoZdro1FGys4ZxS9dW42lBRP9xm+iU6WGof1SNmVpMpvGJEXFk/fkK7fXDLaAbHT8c4ga9wSKX HdHakJME9Mk3l8wUl5cJq2qt0nEo9VvR3bJDN8qnefXxL+er5EjcecR8mbnJRTXHjzbOT8s43nD 6qHseSeDBgPZo+tVyBuwOf1j/DyvAZ0ncX9vdmthDl2NBKHm5/r5XrKDI2YM0kfUjPSOt4N6KXl FbpPUPQ7KMe43HScg+0SM1hBwTOjvb59d9+kM2gNY/8j3K0XusidotoUPd7/mTFIOUhNpfYvBBJ CSojANeXVU3D/EbaaicnbNbbrSQpBOKOzNnJg9nHrISRf4HWjTyA0Itos/ba51xXYTIH8vG9RIV s/0oSsnnErvyg1jGA5ikIfzsyscmXy X-Received: by 2002:a17:902:c951:b0:2a0:de4f:ca7 with SMTP id d9443c01a7336-2a7174efc8amr92610895ad.1.1768774138699; Sun, 18 Jan 2026 14:08:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 40/54] accel/tcg: Drop CONFIG_ATOMIC64 checks from ldst_atomicicy.c.inc Date: Mon, 19 Jan 2026 09:04:00 +1100 Message-ID: <20260118220414.8177-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774174866158500 Content-Type: text/plain; charset="utf-8" CONFIG_ATOMIC64 is a configuration knob for 32-bit hosts. This allows removal of functions like load_atomic8_or_exit and simplification of load_atom_extract_al8_or_exit to load_atom_extract_al8. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 35 +------- accel/tcg/ldst_atomicity.c.inc | 149 +++++---------------------------- 2 files changed, 24 insertions(+), 160 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a6774083b0..6900a12682 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2080,25 +2080,6 @@ static uint64_t do_ld_parts_beN(MMULookupPageData *p= , uint64_t ret_be) return ret_be; } =20 -/** - * do_ld_parts_be4 - * @p: translation parameters - * @ret_be: accumulated data - * - * As do_ld_bytes_beN, but with one atomic load. - * Four aligned bytes are guaranteed to cover the load. - */ -static uint64_t do_ld_whole_be4(MMULookupPageData *p, uint64_t ret_be) -{ - int o =3D p->addr & 3; - uint32_t x =3D load_atomic4(p->haddr - o); - - x =3D cpu_to_be32(x); - x <<=3D o * 8; - x >>=3D (4 - p->size) * 8; - return (ret_be << (p->size * 8)) | x; -} - /** * do_ld_parts_be8 * @p: translation parameters @@ -2111,7 +2092,7 @@ static uint64_t do_ld_whole_be8(CPUState *cpu, uintpt= r_t ra, MMULookupPageData *p, uint64_t ret_be) { int o =3D p->addr & 7; - uint64_t x =3D load_atomic8_or_exit(cpu, ra, p->haddr - o); + uint64_t x =3D load_atomic8(p->haddr - o); =20 x =3D cpu_to_be64(x); x <<=3D o * 8; @@ -2176,11 +2157,7 @@ static uint64_t do_ld_beN(CPUState *cpu, MMULookupPa= geData *p, if (atom =3D=3D MO_ATOM_IFALIGN_PAIR ? p->size =3D=3D half_size : p->size >=3D half_size) { - if (!HAVE_al8_fast && p->size < 4) { - return do_ld_whole_be4(p, ret_be); - } else { - return do_ld_whole_be8(cpu, ra, p, ret_be); - } + return do_ld_whole_be8(cpu, ra, p, ret_be); } /* fall through */ =20 @@ -2586,13 +2563,7 @@ static uint64_t do_st_leN(CPUState *cpu, MMULookupPa= geData *p, if (atom =3D=3D MO_ATOM_IFALIGN_PAIR ? p->size =3D=3D half_size : p->size >=3D half_size) { - if (!HAVE_al8_fast && p->size <=3D 4) { - return store_whole_le4(p->haddr, p->size, val_le); - } else if (HAVE_al8) { - return store_whole_le8(p->haddr, p->size, val_le); - } else { - cpu_loop_exit_atomic(cpu, ra); - } + return store_whole_le8(p->haddr, p->size, val_le); } /* fall through */ =20 diff --git a/accel/tcg/ldst_atomicity.c.inc b/accel/tcg/ldst_atomicity.c.inc index c735add261..f5b8289009 100644 --- a/accel/tcg/ldst_atomicity.c.inc +++ b/accel/tcg/ldst_atomicity.c.inc @@ -12,13 +12,6 @@ #include "host/load-extract-al16-al8.h.inc" #include "host/store-insert-al16.h.inc" =20 -#ifdef CONFIG_ATOMIC64 -# define HAVE_al8 true -#else -# define HAVE_al8 false -#endif -#define HAVE_al8_fast (ATOMIC_REG_SIZE >=3D 8) - /** * required_atomicity: * @@ -132,44 +125,7 @@ static inline uint32_t load_atomic4(void *pv) static inline uint64_t load_atomic8(void *pv) { uint64_t *p =3D __builtin_assume_aligned(pv, 8); - - qemu_build_assert(HAVE_al8); - return qatomic_read__nocheck(p); -} - -/** - * load_atomic8_or_exit: - * @cpu: generic cpu state - * @ra: host unwind address - * @pv: host address - * - * Atomically load 8 aligned bytes from @pv. - * If this is not possible, longjmp out to restart serially. - */ -static uint64_t load_atomic8_or_exit(CPUState *cpu, uintptr_t ra, void *pv) -{ - if (HAVE_al8) { - return load_atomic8(pv); - } - -#ifdef CONFIG_USER_ONLY - /* - * If the page is not writable, then assume the value is immutable - * and requires no locking. This ignores the case of MAP_SHARED with - * another process, because the fallback start_exclusive solution - * provides no protection across processes. - */ - WITH_MMAP_LOCK_GUARD() { - if (!page_check_range(h2g(pv), 8, PAGE_WRITE_ORG)) { - uint64_t *p =3D __builtin_assume_aligned(pv, 8); - return *p; - } - } -#endif - - /* Ultimate fallback: re-execute in serial context. */ - trace_load_atom8_or_exit_fallback(ra); - cpu_loop_exit_atomic(cpu, ra); + return qatomic_read(p); } =20 /** @@ -264,9 +220,7 @@ static uint64_t load_atom_extract_al8x2(void *pv) } =20 /** - * load_atom_extract_al8_or_exit: - * @cpu: generic cpu state - * @ra: host unwind address + * load_atom_extract_al8 * @pv: host address * @s: object size in bytes, @s <=3D 4. * @@ -275,15 +229,14 @@ static uint64_t load_atom_extract_al8x2(void *pv) * 8-byte load and extract. * The value is returned in the low bits of a uint32_t. */ -static uint32_t load_atom_extract_al8_or_exit(CPUState *cpu, uintptr_t ra, - void *pv, int s) +static uint32_t load_atom_extract_al8(void *pv, int s) { uintptr_t pi =3D (uintptr_t)pv; int o =3D pi & 7; int shr =3D (HOST_BIG_ENDIAN ? 8 - s - o : o) * 8; =20 pv =3D (void *)(pi & ~7); - return load_atomic8_or_exit(cpu, ra, pv) >> shr; + return load_atomic8(pv) >> shr; } =20 /** @@ -297,7 +250,7 @@ static uint32_t load_atom_extract_al8_or_exit(CPUState = *cpu, uintptr_t ra, * and p % 16 + s > 8. I.e. does not cross a 16-byte * boundary, but *does* cross an 8-byte boundary. * This is the slow version, so we must have eliminated - * any faster load_atom_extract_al8_or_exit case. + * any faster load_atom_extract_al8 case. * * If this is not possible, longjmp out to restart serially. */ @@ -374,21 +327,6 @@ static inline uint64_t load_atom_8_by_4(void *pv) } } =20 -/** - * load_atom_8_by_8_or_4: - * @pv: host address - * - * Load 8 bytes from aligned @pv, with at least 4-byte atomicity. - */ -static inline uint64_t load_atom_8_by_8_or_4(void *pv) -{ - if (HAVE_al8_fast) { - return load_atomic8(pv); - } else { - return load_atom_8_by_4(pv); - } -} - /** * load_atom_2: * @p: host address @@ -418,12 +356,8 @@ static uint16_t load_atom_2(CPUState *cpu, uintptr_t r= a, return lduw_he_p(pv); case MO_16: /* The only case remaining is MO_ATOM_WITHIN16. */ - if (!HAVE_al8_fast && (pi & 3) =3D=3D 1) { - /* Big or little endian, we want the middle two bytes. */ - return load_atomic4(pv - 1) >> 8; - } if ((pi & 15) !=3D 7) { - return load_atom_extract_al8_or_exit(cpu, ra, pv, 2); + return load_atom_extract_al8(pv, 2); } return load_atom_extract_al16_or_exit(cpu, ra, pv, 2); default: @@ -468,7 +402,7 @@ static uint32_t load_atom_4(CPUState *cpu, uintptr_t ra, return load_atom_extract_al4x2(pv); case MO_32: if (!(pi & 4)) { - return load_atom_extract_al8_or_exit(cpu, ra, pv, 4); + return load_atom_extract_al8(pv, 4); } return load_atom_extract_al16_or_exit(cpu, ra, pv, 4); default: @@ -493,7 +427,7 @@ static uint64_t load_atom_8(CPUState *cpu, uintptr_t ra, * If the host does not support 8-byte atomics, wait until we have * examined the atomicity parameters below. */ - if (HAVE_al8 && likely((pi & 7) =3D=3D 0)) { + if (likely((pi & 7) =3D=3D 0)) { return load_atomic8(pv); } if (HAVE_ATOMIC128_RO) { @@ -502,30 +436,9 @@ static uint64_t load_atom_8(CPUState *cpu, uintptr_t r= a, =20 atmax =3D required_atomicity(cpu, pi, memop); if (atmax =3D=3D MO_64) { - if (!HAVE_al8 && (pi & 7) =3D=3D 0) { - load_atomic8_or_exit(cpu, ra, pv); - } return load_atom_extract_al16_or_exit(cpu, ra, pv, 8); } - if (HAVE_al8_fast) { - return load_atom_extract_al8x2(pv); - } - switch (atmax) { - case MO_8: - return ldq_he_p(pv); - case MO_16: - return load_atom_8_by_2(pv); - case MO_32: - return load_atom_8_by_4(pv); - case -MO_32: - if (HAVE_al8) { - return load_atom_extract_al8x2(pv); - } - trace_load_atom8_fallback(memop, ra); - cpu_loop_exit_atomic(cpu, ra); - default: - g_assert_not_reached(); - } + return load_atom_extract_al8x2(pv); } =20 /** @@ -565,18 +478,10 @@ static Int128 load_atom_16(CPUState *cpu, uintptr_t r= a, b =3D load_atom_8_by_4(pv + 8); break; case MO_64: - if (!HAVE_al8) { - trace_load_atom16_fallback(memop, ra); - cpu_loop_exit_atomic(cpu, ra); - } a =3D load_atomic8(pv); b =3D load_atomic8(pv + 8); break; case -MO_64: - if (!HAVE_al8) { - trace_load_atom16_fallback(memop, ra); - cpu_loop_exit_atomic(cpu, ra); - } a =3D load_atom_extract_al8x2(pv); b =3D load_atom_extract_al8x2(pv + 8); break; @@ -624,9 +529,7 @@ static inline void store_atomic4(void *pv, uint32_t val) static inline void store_atomic8(void *pv, uint64_t val) { uint64_t *p =3D __builtin_assume_aligned(pv, 8); - - qemu_build_assert(HAVE_al8); - qatomic_set__nocheck(p, val); + qatomic_set(p, val); } =20 /** @@ -688,9 +591,8 @@ static void store_atom_insert_al8(uint64_t *p, uint64_t= val, uint64_t msk) { uint64_t old, new; =20 - qemu_build_assert(HAVE_al8); p =3D __builtin_assume_aligned(p, 8); - old =3D qatomic_read__nocheck(p); + old =3D qatomic_read(p); do { new =3D (old & ~msk) | val; } while (!__atomic_compare_exchange_n(p, &old, new, true, @@ -802,7 +704,6 @@ static uint64_t store_whole_le8(void *pv, int size, uin= t64_t val_le) uint64_t m =3D MAKE_64BIT_MASK(0, sz); uint64_t v; =20 - qemu_build_assert(HAVE_al8); if (HOST_BIG_ENDIAN) { v =3D bswap64(val_le) >> sh; m =3D bswap64(m) >> sh; @@ -887,10 +788,8 @@ static void store_atom_2(CPUState *cpu, uintptr_t ra, store_atom_insert_al4(pv - 1, (uint32_t)val << 8, MAKE_64BIT_MASK(= 8, 16)); return; } else if ((pi & 7) =3D=3D 3) { - if (HAVE_al8) { - store_atom_insert_al8(pv - 3, (uint64_t)val << 24, MAKE_64BIT_= MASK(24, 16)); - return; - } + store_atom_insert_al8(pv - 3, (uint64_t)val << 24, MAKE_64BIT_MASK= (24, 16)); + return; } else if ((pi & 15) =3D=3D 7) { if (HAVE_CMPXCHG128) { Int128 v =3D int128_lshift(int128_make64(val), 56); @@ -957,10 +856,8 @@ static void store_atom_4(CPUState *cpu, uintptr_t ra, return; case MO_32: if ((pi & 7) < 4) { - if (HAVE_al8) { - store_whole_le8(pv, 4, cpu_to_le32(val)); - return; - } + store_whole_le8(pv, 4, cpu_to_le32(val)); + return; } else { if (HAVE_CMPXCHG128) { store_whole_le16(pv, 4, int128_make64(cpu_to_le32(val))); @@ -988,7 +885,7 @@ static void store_atom_8(CPUState *cpu, uintptr_t ra, uintptr_t pi =3D (uintptr_t)pv; int atmax; =20 - if (HAVE_al8 && likely((pi & 7) =3D=3D 0)) { + if (likely((pi & 7) =3D=3D 0)) { store_atomic8(pv, val); return; } @@ -1005,7 +902,7 @@ static void store_atom_8(CPUState *cpu, uintptr_t ra, store_atom_8_by_4(pv, val); return; case -MO_32: - if (HAVE_al8) { + { uint64_t val_le =3D cpu_to_le64(val); int s2 =3D pi & 7; int s1 =3D 8 - s2; @@ -1024,9 +921,8 @@ static void store_atom_8(CPUState *cpu, uintptr_t ra, default: g_assert_not_reached(); } - return; } - break; + return; case MO_64: if (HAVE_CMPXCHG128) { store_whole_le16(pv, 8, int128_make64(cpu_to_le64(val))); @@ -1077,12 +973,9 @@ static void store_atom_16(CPUState *cpu, uintptr_t ra, store_atom_8_by_4(pv + 8, b); return; case MO_64: - if (HAVE_al8) { - store_atomic8(pv, a); - store_atomic8(pv + 8, b); - return; - } - break; + store_atomic8(pv, a); + store_atomic8(pv + 8, b); + return; case -MO_64: if (HAVE_CMPXCHG128) { uint64_t val_le; --=20 2.43.0