From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768773888; cv=none; d=zohomail.com; s=zohoarc; b=SsuzbQ2aJNRjQg36SCcmmQxvARBbIQQIPISdt3J9Q89Clef4OC3+PHUxtT/B1WZrEcUn/OappqlHozBSVVTf0YHNrEJHi1L+hv+mYnIdetATnZGgZOd6I4vHqvXW1ZYRE932bEXbFByuQpR+5D3Wswi2TJEvrxvmC1ezbtssprM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768773888; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=F4ISOpBxA1JivydnewaJ3ZoQ2prH+2Mfh7IWpc8xPQc=; b=Fdu6dZhso/Ql5yzUAEGQiQbtnbJnADIQq1YWyC4QeNiG41M0SyMEBCwc9GhlarLgSAHnPLOTBYfzD5T2hModd+neU5pRVSnh5tD8AgTmnGcDTguzhCi55wQ7mx4onlkkaG71U+oEfkYIQvaEYlQ16OmJWQP/3QtdFJ6mHG4o5mQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768773888883948.6955426338055; Sun, 18 Jan 2026 14:04:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhat2-0000hs-Q5; Sun, 18 Jan 2026 17:04:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhasj-0000Mj-B9 for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:25 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhash-0000Ru-1U for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:24 -0500 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-2a07f8dd9cdso23000755ad.1 for ; Sun, 18 Jan 2026 14:04:22 -0800 (PST) Received: from stoup.. ([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7193dbb74sm74402865ad.56.2026.01.18.14.04.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:04:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768773862; x=1769378662; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F4ISOpBxA1JivydnewaJ3ZoQ2prH+2Mfh7IWpc8xPQc=; b=QOZjJCV3Hth1Rg3Ya9uBpSA39L0mujSMUrEi5srrODt/xfwbDYrUMd6Ibl9H6sReju X8TX1BBv5YxA9MktrekQVu3Po6CIsn5D4mBLug879+Bi5x+nJn9KedVKVmc3rDMXrGc1 TFd4HJ96v33bVMLfTgvBwaKk4qYnIY5Dqu4DHDHE7fgvEg2nQ64h8uUYIHp+l5ygiUlt /V4ZVACv5qPBAOY45fhsTIsvDLdRteT6XYM7aM+AzC09sP8OBmEmTMbHYuL+e/hsXBYV la5os5Vsxg6+VS6O1r6/03D2yEEeeBROqKAwRQlXxvYsQgG1sUwjFOXBnIfkCR5EwUBA sk1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768773862; x=1769378662; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=F4ISOpBxA1JivydnewaJ3ZoQ2prH+2Mfh7IWpc8xPQc=; b=nKKftYz1kaImy/kNXpRIJalU6uUgXqCctvR1ZA3pol/PiqOGzdegANv/YQlrmZD/gC lMZK+EL9K7mZLLBfOZzoAUi5UIe0bn1msRcx7OQkNoryETJGpitVrq6ipWorwJr1gqQ4 j+mbrNZ7J7EbppI/s9X5CNM4O6XJWiFISFVaOqjTdxmyLQN14ivG1hnAgLwPEuMOVsoy cYEjw31x1aQilVNCk4fx4sFi+Ed1TZLCFYtln4bZgdPknTvfqjSHsQMiLipvLUSqxes8 lwaWEVYcZKQh/GhI+YDXEWom7ofGvVEtdgFqJ3KxX1bMpoN8KrbOpqpqGYUnl3HgT0Eo uR5Q== X-Gm-Message-State: AOJu0YwWOkCd3ici+bbPcFHY1UFTZKJ/0rvAIK3bQ5bkxjl76s+muS3Y GejXzVXUBIJjfPFJ6XuZ5e3kFDYJjprM/sNc5Hp1P9y2pGZkTQ20y08OUBn2St2pA5TKVkii7cU yhHtGFsMfZQ== X-Gm-Gg: AY/fxX6A4ud+RpW57yxynJSGzYSW+w5ioMCcJ+99JA+PHtD0/FeCa0T/Vms+dXQJ72r fo34jfT7HBM75MnG+4r0xJzZqCHybEg76JGlXzhNIbo8GgFtVVthT1mpXzJ8lc1NxXNl5pvI1Pl q6MTkBZhxzfHzj6KKPsNy3fu1reRSX9h3GnyL0yZKo/useaRFfyVttI1XkPFrp7GPeuaasOJXT7 OENLHpLCgIFXXLrlk5lkTuMb+edWBXx0rcp7YlVAAoDf8fjODDBAdtlmR12OHvM6dAMUjQuZbFJ 0foVbGJJhyCd03TonTTYfxtQBodcaGIWWBeZC4GN6oE+pfXbjK+h+8Kby7CzioJ+j/+c39EG288 Un9uO3MjEn03fkZpIddF3VotCugDIcIuhNYx/BDUUQJJ1DT4VG6qgHWR84GmoMfNy6OaAYkmp7p yKDunu3OvLfqcn9Al6z8c6Q4K6Tjb7 X-Received: by 2002:a17:903:fa4:b0:2a2:dc3f:be4c with SMTP id d9443c01a7336-2a71752aff6mr70695005ad.10.1768773861586; Sun, 18 Jan 2026 14:04:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Kohei Tokunaga , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 01/54] gitlab-ci: Drop build-wasm32-32bit Date: Mon, 19 Jan 2026 09:03:21 +1100 Message-ID: <20260118220414.8177-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768773889827158500 Drop the wasm32 build and container jobs. Reviewed-by: Kohei Tokunaga Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- .gitlab-ci.d/buildtest.yml | 9 --------- .gitlab-ci.d/container-cross.yml | 7 ------- .gitlab-ci.d/containers.yml | 1 - 3 files changed, 17 deletions(-) diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml index ea0f5bb057..e9b5b05e6e 100644 --- a/.gitlab-ci.d/buildtest.yml +++ b/.gitlab-ci.d/buildtest.yml @@ -785,15 +785,6 @@ coverity: # Always manual on forks even if $QEMU_CI =3D=3D "2" - when: manual =20 -build-wasm32-32bit: - extends: .wasm_build_job_template - timeout: 2h - needs: - - job: wasm32-emsdk-cross-container - variables: - IMAGE: emsdk-wasm32-cross - CONFIGURE_ARGS: --static --cpu=3Dwasm32 --disable-tools --enable-debug= --enable-tcg-interpreter - build-wasm64-64bit: extends: .wasm_build_job_template timeout: 2h diff --git a/.gitlab-ci.d/container-cross.yml b/.gitlab-ci.d/container-cros= s.yml index 7022015e95..6bdd482b80 100644 --- a/.gitlab-ci.d/container-cross.yml +++ b/.gitlab-ci.d/container-cross.yml @@ -86,13 +86,6 @@ win64-fedora-cross-container: variables: NAME: fedora-win64-cross =20 -wasm32-emsdk-cross-container: - extends: .container_job_template - variables: - NAME: emsdk-wasm32-cross - BUILD_ARGS: --build-arg TARGET_CPU=3Dwasm32 - DOCKERFILE: emsdk-wasm-cross - wasm64-emsdk-cross-container: extends: .container_job_template variables: diff --git a/.gitlab-ci.d/containers.yml b/.gitlab-ci.d/containers.yml index dde9a3f840..9b6d33ac13 100644 --- a/.gitlab-ci.d/containers.yml +++ b/.gitlab-ci.d/containers.yml @@ -58,7 +58,6 @@ weekly-container-builds: - tricore-debian-cross-container - xtensa-debian-cross-container - win64-fedora-cross-container - - wasm32-emsdk-cross-container - wasm64-emsdk-cross-container # containers - amd64-alpine-container --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774005; cv=none; d=zohomail.com; s=zohoarc; b=KqUaXCfTJTY0PZirHEAa98U8UqlXsbpfNfXbYSe5vJ4AU35Te3gLBqf7Wfvsy5mRYt5SVBf0+zGzrV3SFOC0YjAsO5Z+1u2mQPOsx+Ve1pRhR0gKPi50JuPidLqhkNGp7v23rBDqXVIILjqfDUShflsTxxMW5yNsndxgTF4Z0KY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768774005; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=wxgl+NvwjE6afUEeClSmXGywb0xq3jmuZXqbn2txRNc=; b=BMX+0CPUNQ8/GwUwMADNi3dS76QiLH6jezYsIP1oakcT9+gnATKvAGe+yt2ZdH5yn+yP7cwqJIUh7dXIXuXQJUWkCFhaPztPKjSHhqSdxL+XfiLJ4q6r/ra3i43nwoIiuDu1GHhhVVDgT7IspTZSqvBwFujYbAz0ggtKn2esahQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768774005561833.0704405402512; Sun, 18 Jan 2026 14:06:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhat3-0000tA-Ut; Sun, 18 Jan 2026 17:04:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhasm-0000UP-0w for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:30 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhasj-0000SI-Bn for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:27 -0500 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-2a3e76d0f64so23698025ad.1 for ; Sun, 18 Jan 2026 14:04:24 -0800 (PST) Received: from stoup.. ([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7193dbb74sm74402865ad.56.2026.01.18.14.04.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:04:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768773864; x=1769378664; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wxgl+NvwjE6afUEeClSmXGywb0xq3jmuZXqbn2txRNc=; b=iAMN3JR+EYRKV2pFyTbb3uelOx6rqIHG2Nuan8giu/sUnRmahNPC669SaRW40PFseb oaG35tEBmZXX1jnX3jutvGVX9NLo1u3920c4lEc7XEvJGe3bKCMSnunoAnGrhjN31skk q0I1oh0noDYwjYrP/3gCCzzCiDvXqJA8Mvxy1EwqN6PiTe1UVkjxd1IwtXX0j2pd34DY 4Q8jTgfdD1FxeD9+Guoov+FNI0PuHFGn5ledNL9CWWGUaB5/8qYHpF73ICeazUQVXlVp /RFTrsvOZ0znhmp0XoBFk0GE4aAvyeI6cebAmC+N4OC0+0184Ka7mAFSbz+MAyqNnvc+ kaig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768773864; x=1769378664; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=wxgl+NvwjE6afUEeClSmXGywb0xq3jmuZXqbn2txRNc=; b=OHQ50i50Lnh6+tAClyDi3dS/nDeT7n+BsZmgbiDHKS1klMeyoPcdzvOV6FWjTeM6V3 01Qd4Oi+6Ay1kfJ/8j4MsJnFudaF1gF2qvqlanCnMjekilDxQDrVEioCSQxo5a7FTMoH R9h8i842niBsIO5nlleh2T5QyP7Rw6T2MBorYHecqK5wU6zENY0Ta4X9YinUt8FPjlu3 MBSUXLNEFRXFXt7WbKjt0ht+dwngUrJh5DsiunwBNyomdc9FG4X+7tadEQpNDqFzDgif s0DeyHBEHdgnIBnnUlPi4s+M0nratlUiYo9ie1pir7hUqDsaEsvwIwgSnQA9kzMwLqG4 QRJQ== X-Gm-Message-State: AOJu0Yy7o0HjXBdCUJ2JKBLcXPwS1S/HN9P9rVbDSziPVKCtmwVVgg+w QmOPp/qyD7l7DWd7k6yd0OikwE1CMxUy2M/tCmwAu0Y/lHBiR8muBJP2qxGEHEi0o17ZQ1v1rDA +DysikK2gMw== X-Gm-Gg: AY/fxX7EGP+i5nCtHp12iNtlruhwIU88f7IX/m5WIC9A5nR67V6AneXjec/vxHo5Ksc h4jLjIuNGF/WSOOnzjnxL6LFCc52F6x0mdF2hD+XbmGjmd2GdQCGZy1ziFfxGR/2526K4ZaSbph NDTNQHDpu0njMUgDaxsbKfKRfllgWUAyKFhW1WrhjxCpqeOgFYmFQp0KNhB8umqD39Usa/Uq5Ic TA7F91OQFlmzY23HXoWVv9bSh+rOdJdz3R4LsCIVq8hC4mg3AXXHsE+QTrfVgLiDtRmuIGX5Pev MDgJPqy8RMdSJDLHdbMHbXir22Rn4KieMk1qC4zAXa5DtRDeQOgILKusaAsXuM3HGs3q7OdBChQ LXauO266+JpMh5BsfXiNUOB4lnPswPMyFIwV4tXwHGg25lJGzcmE6OtiUKj07tI3dsy1/vVoKhe y+LcF02GFc50t52RxogLGpPJ602fR9c8tTGX/UpnA= X-Received: by 2002:a17:903:1108:b0:294:f6e5:b91a with SMTP id d9443c01a7336-2a7009ba1a2mr111512495ad.13.1768773863727; Sun, 18 Jan 2026 14:04:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Kohei Tokunaga Subject: [PULL 02/54] tests/docker/dockerfiles: Drop wasm32 from emsdk-wasm-cross.docker Date: Mon, 19 Jan 2026 09:03:22 +1100 Message-ID: <20260118220414.8177-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774006249158500 Content-Type: text/plain; charset="utf-8" We will no longer build wasm32, so drop the docker config. Streamline the dockerfile to hardcode TARGET_CPU as wasm64. Reviewed-by: Kohei Tokunaga Signed-off-by: Richard Henderson --- .gitlab-ci.d/container-cross.yml | 1 - tests/docker/dockerfiles/emsdk-wasm-cross.docker | 15 ++++----------- 2 files changed, 4 insertions(+), 12 deletions(-) diff --git a/.gitlab-ci.d/container-cross.yml b/.gitlab-ci.d/container-cros= s.yml index 6bdd482b80..b376c837dc 100644 --- a/.gitlab-ci.d/container-cross.yml +++ b/.gitlab-ci.d/container-cross.yml @@ -90,5 +90,4 @@ wasm64-emsdk-cross-container: extends: .container_job_template variables: NAME: emsdk-wasm64-cross - BUILD_ARGS: --build-arg TARGET_CPU=3Dwasm64 DOCKERFILE: emsdk-wasm-cross diff --git a/tests/docker/dockerfiles/emsdk-wasm-cross.docker b/tests/docke= r/dockerfiles/emsdk-wasm-cross.docker index ecd5a02903..8a924816f9 100644 --- a/tests/docker/dockerfiles/emsdk-wasm-cross.docker +++ b/tests/docker/dockerfiles/emsdk-wasm-cross.docker @@ -7,7 +7,6 @@ ARG GLIB_VERSION=3D${GLIB_MINOR_VERSION}.0 ARG PIXMAN_VERSION=3D0.44.2 ARG FFI_VERSION=3Dv3.5.2 ARG MESON_VERSION=3D1.5.0 -ARG TARGET_CPU=3Dwasm32 =20 FROM docker.io/emscripten/emsdk:$EMSDK_VERSION_QEMU AS build-base-common ARG MESON_VERSION @@ -31,21 +30,16 @@ RUN mkdir /build WORKDIR /build RUN mkdir -p $TARGET =20 -FROM build-base-common AS build-base-wasm32 - -FROM build-base-common AS build-base-wasm64 +FROM build-base-common AS build-base ENV CFLAGS=3D"$CFLAGS -sMEMORY64=3D1" ENV CXXFLAGS=3D"$CXXFLAGS -sMEMORY64=3D1" ENV LDFLAGS=3D"$LDFLAGS -sMEMORY64=3D1" - -FROM build-base-${TARGET_CPU} AS build-base -ARG TARGET_CPU RUN < /cross.meson [host_machine] system =3D 'emscripten' -cpu_family =3D '${TARGET_CPU}' -cpu =3D '${TARGET_CPU}' +cpu_family =3D 'wasm64' +cpu =3D 'wasm64' endian =3D 'little' =20 [binaries] @@ -67,14 +61,13 @@ RUN emconfigure ./configure --prefix=3D$TARGET --static RUN emmake make install -j$(nproc) =20 FROM build-base AS libffi-dev -ARG TARGET_CPU ARG FFI_VERSION RUN mkdir -p /libffi RUN git clone https://github.com/libffi/libffi /libffi WORKDIR /libffi RUN git checkout $FFI_VERSION RUN autoreconf -fiv -RUN emconfigure ./configure --host=3D${TARGET_CPU}-unknown-linux \ +RUN emconfigure ./configure --host=3Dwasm64-unknown-linux \ --prefix=3D$TARGET --enable-static \ --disable-shared --disable-dependency-tracking \ --disable-builddir --disable-multi-os-directory \ --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768773886; cv=none; d=zohomail.com; s=zohoarc; b=BWHGs22+eHu9AAXtiiOyCgsLHGyXzpD/j6IHEgEtQWTcMpVjuKa21C+ugJyO9zpKGl1nN01CHWdTXXl22TSa0MrgUDQS1jw8W38U27wxLiVf4KXYQX680IfKJQ/z0pYtLjEfgxhuz6DUmAWy8/OI8xRLW6dPgeJLLh6jK95NxxU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768773886; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=AEZduNYwLQr146mwdh+OzwJtbyPDzZLUuan1YMoWbuQ=; b=glR3B3nsI1NyZOzESv8JB0AiQnrh0vGptSQYGRGVTSVeJqrlaymSZN3DPxffi9mFDeEpQsqeURujcyRl5W2xp9+mc7d7SZMaYRjMmwW65VsJo3in8q4rFTqOX2IXK5yhYPSlCo/CIRLdPdms9rCbYRCFATBD4W3fx/qV1q8MJAk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768773886734678.0002938600693; Sun, 18 Jan 2026 14:04:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhat2-0000i3-Qu; Sun, 18 Jan 2026 17:04:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhasn-0000Xr-Nj for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:33 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhasl-0000Sb-QU for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:29 -0500 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-2a0d6f647e2so36932565ad.1 for ; Sun, 18 Jan 2026 14:04:27 -0800 (PST) Received: from stoup.. ([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7193dbb74sm74402865ad.56.2026.01.18.14.04.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:04:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768773866; x=1769378666; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AEZduNYwLQr146mwdh+OzwJtbyPDzZLUuan1YMoWbuQ=; b=yUI2Xum9m0CTQjAv3kSnAHElMMH0O3KIi3A3HO7d8TqaSTdhWyrs3KBEogIsGpXjs5 NoW0Qiajlv/E5kqFgWUrOQHueeNXOMBzzjDSgefgByJJvyUzdDDzxO2vcY1m49KO7eFm CO//3CpNmoDcaR/vssLaziTRx8duydqWlkFK31NzED1MSPjrB1eQ/OUWK/4dAQTQsRpx Zjir4bGEVzcFA+N0MOdlkUEzs0Il2pv1nJOzBYWfBzaePakDFO0hCsCuQHkT9L+4dLhE GuUYmylGUrpwcwWJcdjXEXZlS1wbf6c842uxpzX8rwbTlqyi5FNH14VfVWIgHo7wyv5R t/gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768773866; x=1769378666; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=AEZduNYwLQr146mwdh+OzwJtbyPDzZLUuan1YMoWbuQ=; b=grpro7FKPffKoM5veuSwt5jUoa1U/ZoiOP9qgfdZv09/1UD6KKt/DNptPgn04JDf+d ZEQ69uAqYkGJR8GRm9qxi65kjwNwPRPOWeh1ueU/RgREHuxioDIJJlj96BSxEUndH7jD c1jo+BxsvszqFp19mn5C35De5wgpgfAbAHhgmu0n14VtiV/1uoQ4RBf4lK0y95AVIxpE oUsJcLftFpxh8+gUxVjESDgeumM2xpY8G3Ja7rTcvJQrCiJW4NSyZ9A7Ebso/8ymoLas gNSdfcOC0AYrcSLVqEwNxpOhv+Oev5vv8Xp8z2oEBTHrOuin4reNWMt3Scf8Lvl5LK1d m28Q== X-Gm-Message-State: AOJu0Yyv3v4KjOUG3JOSEUOx9LodF0EH50Ufu4F/HBDGq1WiAsTj/a7o LCC0Nz5V4bjnW7/b4bPth1NYXOpVXkOxeG0Q8r3LNEZ4wg6ThtqsR/b7i7QKvYdhuQ3qWx5Dmmj IDShxIKGO6A== X-Gm-Gg: AY/fxX5tuAd+97mg19sB+wTvpTKkskxpsjqtJTKB83cn6Xk1VFWTfa2KbAyWp++uQme vJ0N1o2317l4Yxpes415Ye1mNk/nzEqsPJHZIDOnlF5ShcTRdb5Ucec4dUu+MKYuYV24+96DDfc Qm9UfTCIf+JD3kDlYogpzTE5ZfmKq313o/G9eGQJNV89+OrqqXPyOLprbDwS7dPzwt3x8Yo+ZKV SwkHPr6qF5Tfv7tH5Av4D2xQ65b7xmN9l52OptzCvPb1/tR4A6a0lPdeL8yQL2KfFOEBQEyiLiU IgCXhb90A02z7tahIchoSdpT5nFmMmfNVx7xxRKmju+gQrM7W2rAtjJhMdM4/SB9KDDwhcL/pqV jtMbXA3fDd+ZsDCrCTDEcJiJBNuvz+wSXtCHzENQ8s9t9NaNc4gxN7Oln9hQBsDN1RmoPHB/zlH dUqv24zhkkY2pt2YvH1g== X-Received: by 2002:a17:903:1ae4:b0:2a0:f828:24a3 with SMTP id d9443c01a7336-2a7175cc0f1mr88732775ad.28.1768773865930; Sun, 18 Jan 2026 14:04:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 03/54] gitlab: Remove 32-bit host testing Date: Mon, 19 Jan 2026 09:03:23 +1100 Message-ID: <20260118220414.8177-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768773887812158500 These deprecated builds will be disabled. Remove testing of armhf and i686. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- .gitlab-ci.d/container-cross.yml | 12 --------- .gitlab-ci.d/containers.yml | 2 -- .gitlab-ci.d/crossbuilds.yml | 45 -------------------------------- 3 files changed, 59 deletions(-) diff --git a/.gitlab-ci.d/container-cross.yml b/.gitlab-ci.d/container-cros= s.yml index b376c837dc..d7ae57fb1f 100644 --- a/.gitlab-ci.d/container-cross.yml +++ b/.gitlab-ci.d/container-cross.yml @@ -22,12 +22,6 @@ arm64-debian-cross-container: variables: NAME: debian-arm64-cross =20 -armhf-debian-cross-container: - extends: .container_job_template - stage: containers - variables: - NAME: debian-armhf-cross - hexagon-cross-container: extends: .container_job_template stage: containers @@ -40,12 +34,6 @@ loongarch-debian-cross-container: variables: NAME: debian-loongarch-cross =20 -i686-debian-cross-container: - extends: .container_job_template - stage: containers - variables: - NAME: debian-i686-cross - mips64el-debian-cross-container: extends: .container_job_template stage: containers diff --git a/.gitlab-ci.d/containers.yml b/.gitlab-ci.d/containers.yml index 9b6d33ac13..6aeccf8be0 100644 --- a/.gitlab-ci.d/containers.yml +++ b/.gitlab-ci.d/containers.yml @@ -47,10 +47,8 @@ weekly-container-builds: - amd64-debian-user-cross-container - amd64-debian-legacy-cross-container - arm64-debian-cross-container - - armhf-debian-cross-container - hexagon-cross-container - loongarch-debian-cross-container - - i686-debian-cross-container - mips64el-debian-cross-container - ppc64el-debian-cross-container - riscv64-debian-cross-container diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml index 99dfa7eea6..59ff8b1d87 100644 --- a/.gitlab-ci.d/crossbuilds.yml +++ b/.gitlab-ci.d/crossbuilds.yml @@ -1,13 +1,6 @@ include: - local: '/.gitlab-ci.d/crossbuild-template.yml' =20 -cross-armhf-user: - extends: .cross_user_build_job - needs: - - job: armhf-debian-cross-container - variables: - IMAGE: debian-armhf-cross - cross-arm64-system: extends: .cross_system_build_job needs: @@ -30,44 +23,6 @@ cross-arm64-kvm-only: IMAGE: debian-arm64-cross EXTRA_CONFIGURE_OPTS: --disable-tcg --without-default-features =20 -cross-i686-system: - extends: - - .cross_system_build_job - - .cross_test_artifacts - needs: - - job: i686-debian-cross-container - variables: - IMAGE: debian-i686-cross - EXTRA_CONFIGURE_OPTS: --disable-kvm - MAKE_CHECK_ARGS: check-qtest - -cross-i686-user: - extends: - - .cross_user_build_job - - .cross_test_artifacts - needs: - - job: i686-debian-cross-container - variables: - IMAGE: debian-i686-cross - MAKE_CHECK_ARGS: check - -cross-i686-tci: - extends: - - .cross_accel_build_job - - .cross_test_artifacts - timeout: 60m - needs: - - job: i686-debian-cross-container - variables: - IMAGE: debian-i686-cross - ACCEL: tcg-interpreter - EXTRA_CONFIGURE_OPTS: --target-list=3Di386-softmmu,i386-linux-user,arm= -softmmu,arm-linux-user,ppc-softmmu,ppc-linux-user --disable-plugins --disa= ble-kvm - # Force tests to run with reduced parallelism, to see whether this - # reduces the flakiness of this CI job. The CI - # environment by default shows us 8 CPUs and so we - # would otherwise be using a parallelism of 9. - MAKE_CHECK_ARGS: check check-tcg -j2 - cross-mips64el-system: extends: .cross_system_build_job needs: --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768773981; cv=none; d=zohomail.com; s=zohoarc; b=CFvDWslyPEpgI2GQySvbci+y2+qsWzfdfptwiuh5hhwbo4buq4cHR2uPeTvDSbg22qMUOtYCI53+zC89Lho1NejjIX3cxl/YlC/K+dyH2VWeOW437rVhL2hge/jP+pflJbLaewV80OJJX/18AFZ62vIekuDxuz8n6iAMmgr4chE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768773981; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8ZftrpeMp67H21abPmjnOQ3bq0oi0EoCBPPE1IUpN8c=; b=FVP5Lg+zaI7itSeCKbxPJato1Mz9sUWjwd2+KT7lz9KreQwLcNQCqVv/Uu2MH4q70bjPIRZy8tVX1qPlss953CoDMQFvvajk0JS7eQMBTD4dBzcyw1UemiH3KstdCf4Jaa4UkeLmEDKyh/ilMtzmZ6EPqArOqivMQ+LmD5fsFX4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768773981161853.774154535743; Sun, 18 Jan 2026 14:06:21 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhat3-0000jJ-17; Sun, 18 Jan 2026 17:04:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhasr-0000Yx-Ck for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:34 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhaso-0000Sl-Cc for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:31 -0500 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-2a0d67f1877so24380215ad.2 for ; Sun, 18 Jan 2026 14:04:30 -0800 (PST) Received: from stoup.. ([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7193dbb74sm74402865ad.56.2026.01.18.14.04.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:04:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768773869; x=1769378669; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8ZftrpeMp67H21abPmjnOQ3bq0oi0EoCBPPE1IUpN8c=; b=JEiyebqWWxsfYcFELjZfeFrj6Ef9zL0pkRBzsa3+9FuokQ0VJcJxpeZ6UjlJxaD59N /bVwm2t8zu9tGJF4SAPoaxM3XRkqmm3QN5HctJswEyXcqm/pAxBuAr7/keaDd13h9s87 xtiZ7t38Qzm9cLYdpPgbsRG4VJbRr2XVGq4EiPfxMOwcYsmkBXy8ejwwuSQQBlqkpMU0 gZ5BXb6gwn+DGdJSxYs2ZDyjV/cw1hdrQ6/Enwf71+r4H+9N2y/a1pCb34gr77nNK+1s C4rhnqgfyo82pZg+iNqLJxfMgA5Iz2SwDUN3xxeDbr9NfNznHvWXbefcdGWOgH4Q3spp b8qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768773869; x=1769378669; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=8ZftrpeMp67H21abPmjnOQ3bq0oi0EoCBPPE1IUpN8c=; b=iUZPstyzIwDd5WqtVHWaZsOeDTtrejJSApyNQ+wtt0yPhFhz3C13bfo/kGAKdMrH8t 8QSndt7AKv/Cvj5csHJmigtvr+e6nrZ5niVgo2sg0BJIuxbO6sRQuYqj9OPwPAoCMSeA jNVjjokqRFlTXX7+Y4eA7DpmgEA65xAm+Eepu9vIlaIdIFHdamM13OCEz0avtJp7f+zx XWXIbhDAAshubSoRlUfUqDUqYBeZBDOWwb8zncUo1O5pxGwTVJ56cQhZWvDE52dg5F9x tcU4p31dgC1JW8hM7UvjFQTrOYmvnI+9ufm4Np775MWGbdeIrVCF0VaittM/LogiOV2v ZGXA== X-Gm-Message-State: AOJu0YwUli+7IJZ4Ap1zH5QTs3mfcPGsuiUxJP7ot0wfcnWMKVriDEuP 1OfB4OS7sQ48TyctqFVjbzPSuuvsrV0Aib1t2L51PttwX3uahPdGJmaz6hMzNw9SyeLcQPbK0B4 hZICCK2xAnQ== X-Gm-Gg: AY/fxX7rpqkftRxYs3hzOfCXdbzIri/KsZtf9k/aEvxY+glHZTykQpucUD2dLVR1sGr vEqxr/baiW3J6jP9lw+a5IsI0uzje+yFr7Bo2QI0HSKw1+Alff+xgbu+FYmgoI9k2RIVNIGs9hz Lb+7W3sS551dpO3Mnxf85HsFjJQ5Z8/VGeZSPZ0WADronLp23XY7HKTwWl+k7JGDH/XXd0Dte89 kyujAMsaj1WKqoJbMju0uehSw1WXiJ+ACim35ZIZTSGdHI4OjVT0OfJzC/eVIPuPl0XN32YD/54 wt4SuXPK5NOH4xKW6yz9v54vsE0uA0FjQLkVxiojjEH0HFksED3cKcaACoSm99GYp01Mz9+2HEt 2XwptdKsOY9xxwJmgnUaBDdXxfUMQMl/6tKrtsH82090nD1ehYueJxDk9TcGkTC9pDnbR9Njw9D S/hxSIK1GyBHSZXH945eYBtljRWyMr X-Received: by 2002:a17:903:2a8f:b0:2a1:3cd9:a739 with SMTP id d9443c01a7336-2a7189479e3mr84461795ad.43.1768773868602; Sun, 18 Jan 2026 14:04:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 04/54] meson: Reject 32-bit hosts Date: Mon, 19 Jan 2026 09:03:24 +1100 Message-ID: <20260118220414.8177-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768773982135158500 32-bit hosts have been deprecated since 10.0. As the first step, disable any such at configuration time. Further patches will remove the dead code. Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- docs/about/deprecated.rst | 29 ----------------------------- docs/about/removed-features.rst | 6 ++++++ meson.build | 17 ++++------------- 3 files changed, 10 insertions(+), 42 deletions(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 7abb3dab59..88efa3aa80 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -186,28 +186,6 @@ maintain our cross-compilation CI tests of the archite= cture. As we no longer have CI coverage support may bitrot away before the deprecation process completes. =20 -System emulation on 32-bit x86 hosts (since 8.0) -'''''''''''''''''''''''''''''''''''''''''''''''' - -Support for 32-bit x86 host deployments is increasingly uncommon in mainst= ream -OS distributions given the widespread availability of 64-bit x86 hardware. -The QEMU project no longer considers 32-bit x86 support for system emulati= on to -be an effective use of its limited resources, and thus intends to disconti= nue -it. Since all recent x86 hardware from the past >10 years is capable of the -64-bit x86 extensions, a corresponding 64-bit OS should be used instead. - -TCG Plugin support not enabled by default on 32-bit hosts (since 9.2) -''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' - -While it is still possible to enable TCG plugin support for 32-bit -hosts there are a number of potential pitfalls when instrumenting -64-bit guests. The plugin APIs typically pass most addresses as -uint64_t but practices like encoding that address in a host pointer -for passing as user-data will lose data. As most software analysis -benefits from having plenty of host memory it seems reasonable to -encourage users to use 64 bit builds of QEMU for analysis work -whatever targets they are instrumenting. - TCG Plugin support not enabled by default with TCI (since 9.2) '''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' =20 @@ -216,13 +194,6 @@ is going to be so much slower it wouldn't make sense f= or any serious instrumentation. Due to implementation differences there will also be anomalies in things like memory instrumentation. =20 -32-bit host operating systems (since 10.0) -'''''''''''''''''''''''''''''''''''''''''' - -Keeping 32-bit host support alive is a substantial burden for the -QEMU project. Thus QEMU will in future drop the support for all -32-bit host systems. - System emulator CPUs -------------------- =20 diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.= rst index e81d79da47..b0d7fa8813 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -572,6 +572,12 @@ like the ``akita`` or ``terrier``; it has been depreca= ted in the kernel since 2001. None of the board types QEMU supports need ``param_struct`` support, so this option has been removed. =20 +32-bit host operating systems (removed in 11.0) +''''''''''''''''''''''''''''''''''''''''''''''' + +Keeping 32-bit host support alive was a substantial burden for the +QEMU project. Thus QEMU dropped all support for all 32-bit host systems. + =20 User-mode emulator command line arguments ----------------------------------------- diff --git a/meson.build b/meson.build index 600c50007d..28f61be675 100644 --- a/meson.build +++ b/meson.build @@ -332,6 +332,10 @@ endif # Compiler flags # ################## =20 +if cc.sizeof('void *') < 8 + error('QEMU requires a 64-bit CPU host architecture') +endif + foreach lang : all_languages compiler =3D meson.get_compiler(lang) if compiler.get_id() =3D=3D 'gcc' and compiler.version().version_compare= ('>=3D7.4') @@ -3247,9 +3251,6 @@ if host_os =3D=3D 'windows' endif endif =20 -# Detect host pointer size for the target configuration loop. -host_long_bits =3D cc.sizeof('void *') * 8 - # Detect if ConvertStringToBSTR has been defined in _com_util namespace if host_os =3D=3D 'windows' has_convert_string_to_bstr =3D cxx.links(''' @@ -3360,10 +3361,6 @@ foreach target : target_dirs =20 target_kconfig =3D [] foreach sym: accelerators - # Disallow 64-bit on 32-bit emulation and virtualization - if host_long_bits < config_target['TARGET_LONG_BITS'].to_int() - continue - endif if sym =3D=3D 'CONFIG_TCG' or target in accelerator_targets.get(sym, [= ]) config_target +=3D { sym: 'y' } config_all_accel +=3D { sym: 'y' } @@ -5036,12 +5033,6 @@ if host_arch =3D=3D 'unknown' message('configure has succeeded and you can continue to build, but') message('QEMU will use a slow interpreter to emulate the target CPU.') endif -elif host_long_bits < 64 - message() - warning('DEPRECATED HOST CPU') - message() - message('Support for 32-bit CPU host architecture ' + cpu + ' is going') - message('to be dropped in a future QEMU release.') elif host_arch =3D=3D 'mips' message() warning('DEPRECATED HOST CPU') --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768773944; cv=none; d=zohomail.com; s=zohoarc; b=KiJTHpjyM/LZYZ1xz6nO04jhq2/BYBda2Mp/KLunhUVZg+lqyRL9eSm7EmdM/b5D6kqPzWruJlMCxJV1MzVf8r7QPjAaFTL5uFiGxupUdgb6t6tgFgy03kbd+E/fJFoB5LzkY9JGg/J15ZG9OwbFiP6d46GWssshVYbSX/ZcmpY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768773944; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TGuZe54UTmVFXsSluuX4OgQx2qkxV1BUhiRTAljGAWk=; b=LqGlfg/voY38up2UPJI8ZwalyBXAvluib6NFR+4YuEZw6CojpcGapz+WstZPnJAzCIwJujW8bIcD3RtcSPEkZ/Mhkj+0LdvlYLp2Hn1xfMxT9mMzA2CVFhyCv/o+tC/BakYyHQGzEl6MPzH/gVRhfu1kpZhnXP5audeCkcuwmL4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768773944328582.1486913419146; Sun, 18 Jan 2026 14:05:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhat4-00010X-Sl; Sun, 18 Jan 2026 17:04:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhast-0000Zq-45 for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:35 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhasr-0000St-3L for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:34 -0500 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-2a0bb2f093aso23155215ad.3 for ; Sun, 18 Jan 2026 14:04:31 -0800 (PST) Received: from stoup.. ([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7193dbb74sm74402865ad.56.2026.01.18.14.04.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:04:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768773871; x=1769378671; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TGuZe54UTmVFXsSluuX4OgQx2qkxV1BUhiRTAljGAWk=; b=SLFgLfRThw40taEt1cqeR8mSEVQY0+qp+hDiECdT3y5ex+s+0TOJG19KfGfBhvt/Vs 7Gwq1UI9q31Tl82lwm0yRx1j0cmYRg2uPu+SiqBQTwtfHFUskq9bbDw4YwAHiWvVQFDo 8apym/j5iv53ShxDsVVrQWOUo2tpkAhM98goH3jZWb8lxAnUDQPvRmiejlf6O5RKIqDO EGBo+pYn1ty7kW2M0xVbT3FRk4w3gtk0hpYQqd9FvHbGqYKoxE2VWgy0lOBnRhffS7L1 pNLbcmfKoFzxvwiXn6oLPfFtm39WVFW3t5BKkVXuif9rp+O7FD9z6bDUi9BTAtrqcDPX HFvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768773871; x=1769378671; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=TGuZe54UTmVFXsSluuX4OgQx2qkxV1BUhiRTAljGAWk=; b=GoWrcRot8bBIo7di+wz1z9dIEiqcfWD+D1dtiIXvxvOVuBt/0QT4qrClkr43t6rIvd Qz3SSFPV2M9p+lMjYn2DZChiPxxbpYXfaL2e27c1/aoF9UHp6BuD7j0qmpWm3RIRBoqm Zor1BEXcTI6WP7vFin7U0AlDXaMlenQ8M6XT1DpwM6/M7KquTxW/d2yPMwmRfAKhPnsO AVKvor+mevRs1q0pHr4M1Lnsf9ENPoGlQs/2R7QrTuYOR3tjVVG294w3Mj0uDP8JE0rg 61Vf3Mjzinl98k6BqGOn1vEl2myOG/s70Sp/7i/mMapNJrKS81VFxYqNI2S5cxLWD7Jf 6ldA== X-Gm-Message-State: AOJu0YyeGiMH2gd6GuGhx+EQATplHUakidtFuN5hilpli3Ypik0DpbDq YwF28dwWjOE2R8Ypr2nh4ODVQDnGW9XQ5q9EmpuT9kQGCWUbVYokmlBp6rxFB2Slrra9JAJUZU2 6NO0eUcFjjw== X-Gm-Gg: AY/fxX6omhQzwwN680Y3oSx0sJkh1eek9Aam2pHboM89aOE/KO14GEgwQi4QEaiWotw CqWOii2NEuhVZwcW/106K2zJoSn2TXmZWwgtogFnjRjY1SuOKFwBpXs/p7gpMFXaK9ILCxzW35o ao1LilYnxT3Ic0FF7a71HNrIlrl0eh9HZ8OCcPGHzb8GdtRALZyCCOnxNpalB0rREhbUY7sfU04 o49a7XjRK6PSV/ORwws0hSQNA2EzU45NB/SG+5dDWpRiMXSz3wL4N8w/RS5k6pJAMKzg/GnEwFp qJ/I+/njjlrTqtbYB65O80TpwMH5x2w0wjk4QKpp09ZmwKyql8T/oyZld/a9EM5QP1XwYWwCagH yfZ5ear1PvawglTD/HRMU7JnG3iZwtQBGQ/4Q8cDjQA+eEzecyuSbEJ2qtlxcVtMmtSosQ6gIn/ jyxPglnJm6y1He/7KAcw== X-Received: by 2002:a17:903:41cd:b0:2a0:afeb:fbbb with SMTP id d9443c01a7336-2a7174fa86fmr90420355ad.1.1768773870642; Sun, 18 Jan 2026 14:04:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Kohei Tokunaga Subject: [PULL 05/54] meson: Drop cpu == wasm32 tests Date: Mon, 19 Jan 2026 09:03:25 +1100 Message-ID: <20260118220414.8177-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768773946048158500 Content-Type: text/plain; charset="utf-8" The 32-bit wasm32 host is no longer supported. Reviewed-by: Kohei Tokunaga Signed-off-by: Richard Henderson --- configure | 5 +---- meson.build | 6 +++--- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/configure b/configure index 326d27dab1..ba1b207b56 100755 --- a/configure +++ b/configure @@ -425,7 +425,7 @@ elif check_define __aarch64__ ; then elif check_define __loongarch64 ; then cpu=3D"loongarch64" elif check_define EMSCRIPTEN ; then - error_exit "wasm32 or wasm64 must be specified to the cpu flag" + error_exit "wasm64 must be specified to the cpu flag" else # Using uname is really broken, but it is just a fallback for architectu= res # that are going to use TCI anyway @@ -523,9 +523,6 @@ case "$cpu" in linux_arch=3Dx86 CPU_CFLAGS=3D"-m64" ;; - wasm32) - CPU_CFLAGS=3D"-m32" - ;; wasm64) CPU_CFLAGS=3D"-m64 -sMEMORY64=3D$wasm64_memory64" ;; diff --git a/meson.build b/meson.build index 28f61be675..082c7a86ca 100644 --- a/meson.build +++ b/meson.build @@ -51,7 +51,7 @@ qapi_trace_events =3D [] bsd_oses =3D ['gnu/kfreebsd', 'freebsd', 'netbsd', 'openbsd', 'dragonfly',= 'darwin'] supported_oses =3D ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', '= sunos', 'linux', 'emscripten'] supported_cpus =3D ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86', = 'x86_64', - 'arm', 'aarch64', 'loongarch64', 'mips64', 'sparc64', 'wasm32', 'wasm64'] + 'arm', 'aarch64', 'loongarch64', 'mips64', 'sparc64', 'wasm64'] =20 cpu =3D host_machine.cpu_family() =20 @@ -927,7 +927,7 @@ if have_tcg if not get_option('tcg_interpreter') error('Unsupported CPU @0@, try --enable-tcg-interpreter'.format(cpu= )) endif - elif host_arch =3D=3D 'wasm32' or host_arch =3D=3D 'wasm64' + elif host_arch =3D=3D 'wasm64' if not get_option('tcg_interpreter') error('WebAssembly host requires --enable-tcg-interpreter') endif @@ -4248,7 +4248,7 @@ if have_rust bindgen_args_common +=3D ['--merge-extern-blocks'] endif bindgen_c_args =3D [] - if host_arch =3D=3D 'wasm32' + if host_arch =3D=3D 'wasm64' bindgen_c_args +=3D ['-fvisibility=3Ddefault'] endif subdir('rust') --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768773976; cv=none; d=zohomail.com; s=zohoarc; b=G59EedWdU7SXd2tj1JZlkwMA2VZB2Ti9nDxCHUU8vIY+Dk5OAFhdvmAw4UHESuL2s4cWPmuqa/X5GMJCjl3l2jdyfkaMXHEiGS26TRIQuHqBDLWCXEQjCPxbYw3/oPzOVf/ELK5Pz9pIS5OYK4MAHJMagUQfYVqO8VBcxiKM8LY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768773976; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+W1ppk1NAX7/KovuBga7WaAI8bl5a0fhcvvYKVr3esM=; b=l/yVJv9jt6nW15igO9wgbnY5apmh/BWjp8z1LSEjXOSZG4K2CDqyqP4y+QFolBK6phihQvez/yamsiFaP5xQMs1RDD8ArjzB5KP7cXiKTUkaoVgfzsej0rbaSbQBP+5K44Y0vjCgP2pyhfkjd4AXzgPgn6rZW7GRzBhmCgF1DN8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768773976714265.4690698798803; Sun, 18 Jan 2026 14:06:16 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhat5-00019H-UL; Sun, 18 Jan 2026 17:04:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhasy-0000gq-T9 for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:42 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhasu-0000Tj-Ew for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:40 -0500 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-2a0c09bb78cso27696635ad.0 for ; Sun, 18 Jan 2026 14:04:36 -0800 (PST) Received: from stoup.. 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Remove instances of __arm__, except from tests and imported headers. Remove arm from supported_cpus. Remove linux-user/include/host/arm. Remove common-user/host/arm. Reviewed-by: Thomas Huth Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/qemu/osdep.h | 2 +- linux-user/include/host/arm/host-signal.h | 43 - tcg/arm/tcg-target-con-set.h | 47 - tcg/arm/tcg-target-con-str.h | 26 - tcg/arm/tcg-target-has.h | 73 - tcg/arm/tcg-target-mo.h | 13 - tcg/arm/tcg-target-reg-bits.h | 12 - tcg/arm/tcg-target.h | 73 - disas/disas-host.c | 3 - hw/virtio/virtio-mem.c | 2 +- linux-user/mmap.c | 2 +- MAINTAINERS | 6 - common-user/host/arm/safe-syscall.inc.S | 108 - configure | 7 - meson.build | 7 +- tcg/arm/tcg-target-opc.h.inc | 16 - tcg/arm/tcg-target.c.inc | 3489 --------------------- 17 files changed, 5 insertions(+), 3924 deletions(-) delete mode 100644 linux-user/include/host/arm/host-signal.h delete mode 100644 tcg/arm/tcg-target-con-set.h delete mode 100644 tcg/arm/tcg-target-con-str.h delete mode 100644 tcg/arm/tcg-target-has.h delete mode 100644 tcg/arm/tcg-target-mo.h delete mode 100644 tcg/arm/tcg-target-reg-bits.h delete mode 100644 tcg/arm/tcg-target.h delete mode 100644 common-user/host/arm/safe-syscall.inc.S delete mode 100644 tcg/arm/tcg-target-opc.h.inc delete mode 100644 tcg/arm/tcg-target.c.inc diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 3cb45a1467..4cdeda0b9c 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -566,7 +566,7 @@ int madvise(char *, size_t, int); #endif =20 #if defined(__linux__) && \ - (defined(__x86_64__) || defined(__arm__) || defined(__aarch64__) \ + (defined(__x86_64__) || defined(__aarch64__) \ || defined(__powerpc64__) || defined(__riscv)) /* Use 2 MiB alignment so transparent hugepages can be used by KVM. Valgrind does not support alignments larger than 1 MiB, diff --git a/linux-user/include/host/arm/host-signal.h b/linux-user/include= /host/arm/host-signal.h deleted file mode 100644 index faba496d24..0000000000 --- a/linux-user/include/host/arm/host-signal.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * host-signal.h: signal info dependent on the host architecture - * - * Copyright (c) 2003-2005 Fabrice Bellard - * Copyright (c) 2021 Linaro Limited - * - * This work is licensed under the terms of the GNU LGPL, version 2.1 or l= ater. - * See the COPYING file in the top-level directory. - */ - -#ifndef ARM_HOST_SIGNAL_H -#define ARM_HOST_SIGNAL_H - -/* The third argument to a SA_SIGINFO handler is ucontext_t. */ -typedef ucontext_t host_sigcontext; - -static inline uintptr_t host_signal_pc(host_sigcontext *uc) -{ - return uc->uc_mcontext.arm_pc; -} - -static inline void host_signal_set_pc(host_sigcontext *uc, uintptr_t pc) -{ - uc->uc_mcontext.arm_pc =3D pc; -} - -static inline void *host_signal_mask(host_sigcontext *uc) -{ - return &uc->uc_sigmask; -} - -static inline bool host_signal_write(siginfo_t *info, host_sigcontext *uc) -{ - /* - * In the FSR, bit 11 is WnR, assuming a v6 or - * later processor. On v5 we will always report - * this as a read, which will fail later. - */ - uint32_t fsr =3D uc->uc_mcontext.error_code; - return extract32(fsr, 11, 1); -} - -#endif diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h deleted file mode 100644 index 16b1193228..0000000000 --- a/tcg/arm/tcg-target-con-set.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Define Arm target-specific constraint sets. - * Copyright (c) 2021 Linaro - */ - -/* - * C_On_Im(...) defines a constraint set with outputs and inputs. - * Each operand should be a sequence of constraint letters as defined by - * tcg-target-con-str.h; the constraint combination is inclusive or. - */ -C_O0_I1(r) -C_O0_I2(r, r) -C_O0_I2(r, rIN) -C_O0_I2(q, q) -C_O0_I2(w, r) -C_O0_I3(q, q, q) -C_O0_I3(Q, p, q) -C_O0_I4(r, r, rI, rI) -C_O0_I4(Q, p, q, q) -C_O1_I1(r, q) -C_O1_I1(r, r) -C_O1_I1(w, r) -C_O1_I1(w, w) -C_O1_I1(w, wr) -C_O1_I2(r, 0, rZ) -C_O1_I2(r, q, q) -C_O1_I2(r, r, r) -C_O1_I2(r, r, rI) -C_O1_I2(r, r, rIK) -C_O1_I2(r, r, rIN) -C_O1_I2(r, r, ri) -C_O1_I2(r, rI, r) -C_O1_I2(r, rI, rIK) -C_O1_I2(r, rI, rIN) -C_O1_I2(r, rZ, rZ) -C_O1_I2(w, 0, w) -C_O1_I2(w, w, w) -C_O1_I2(w, w, wO) -C_O1_I2(w, w, wV) -C_O1_I2(w, w, wZ) -C_O1_I3(w, w, w, w) -C_O1_I4(r, r, r, rI, rI) -C_O1_I4(r, r, rIN, rIK, 0) -C_O2_I1(e, p, q) -C_O2_I2(e, p, q, q) -C_O2_I2(r, r, r, r) diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h deleted file mode 100644 index f83f1d3919..0000000000 --- a/tcg/arm/tcg-target-con-str.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Define Arm target-specific operand constraints. - * Copyright (c) 2021 Linaro - */ - -/* - * Define constraint letters for register sets: - * REGS(letter, register_mask) - */ -REGS('e', ALL_GENERAL_REGS & 0x5555) /* even regs */ -REGS('r', ALL_GENERAL_REGS) -REGS('q', ALL_QLDST_REGS) -REGS('Q', ALL_QLDST_REGS & 0x5555) /* even qldst */ -REGS('w', ALL_VECTOR_REGS) - -/* - * Define constraint letters for constants: - * CONST(letter, TCG_CT_CONST_* bit set) - */ -CONST('I', TCG_CT_CONST_ARM) -CONST('K', TCG_CT_CONST_INV) -CONST('N', TCG_CT_CONST_NEG) -CONST('O', TCG_CT_CONST_ORRI) -CONST('V', TCG_CT_CONST_ANDI) -CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/arm/tcg-target-has.h b/tcg/arm/tcg-target-has.h deleted file mode 100644 index 3bbbde5d59..0000000000 --- a/tcg/arm/tcg-target-has.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Define target-specific opcode support - * Copyright (c) 2008 Fabrice Bellard - * Copyright (c) 2008 Andrzej Zaborowski - */ - -#ifndef TCG_TARGET_HAS_H -#define TCG_TARGET_HAS_H - -extern int arm_arch; - -#define use_armv7_instructions (__ARM_ARCH >=3D 7 || arm_arch >=3D 7) - -#ifdef __ARM_ARCH_EXT_IDIV__ -#define use_idiv_instructions 1 -#else -extern bool use_idiv_instructions; -#endif -#ifdef __ARM_NEON__ -#define use_neon_instructions 1 -#else -extern bool use_neon_instructions; -#endif - -/* optional instructions */ -#define TCG_TARGET_HAS_qemu_ldst_i128 0 -#define TCG_TARGET_HAS_tst 1 - -#define TCG_TARGET_HAS_v64 use_neon_instructions -#define TCG_TARGET_HAS_v128 use_neon_instructions -#define TCG_TARGET_HAS_v256 0 - -#define TCG_TARGET_HAS_andc_vec 1 -#define TCG_TARGET_HAS_orc_vec 1 -#define TCG_TARGET_HAS_nand_vec 0 -#define TCG_TARGET_HAS_nor_vec 0 -#define TCG_TARGET_HAS_eqv_vec 0 -#define TCG_TARGET_HAS_not_vec 1 -#define TCG_TARGET_HAS_neg_vec 1 -#define TCG_TARGET_HAS_abs_vec 1 -#define TCG_TARGET_HAS_roti_vec 0 -#define TCG_TARGET_HAS_rots_vec 0 -#define TCG_TARGET_HAS_rotv_vec 0 -#define TCG_TARGET_HAS_shi_vec 1 -#define TCG_TARGET_HAS_shs_vec 0 -#define TCG_TARGET_HAS_shv_vec 0 -#define TCG_TARGET_HAS_mul_vec 1 -#define TCG_TARGET_HAS_sat_vec 1 -#define TCG_TARGET_HAS_minmax_vec 1 -#define TCG_TARGET_HAS_bitsel_vec 1 -#define TCG_TARGET_HAS_cmpsel_vec 0 -#define TCG_TARGET_HAS_tst_vec 1 - -static inline bool -tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len) -{ - if (use_armv7_instructions) { - return true; /* SBFX or UBFX */ - } - switch (len) { - case 8: /* SXTB or UXTB */ - case 16: /* SXTH or UXTH */ - return (ofs % 8) =3D=3D 0; - } - return false; -} - -#define TCG_TARGET_extract_valid tcg_target_extract_valid -#define TCG_TARGET_sextract_valid tcg_target_extract_valid -#define TCG_TARGET_deposit_valid(type, ofs, len) use_armv7_instructions - -#endif diff --git a/tcg/arm/tcg-target-mo.h b/tcg/arm/tcg-target-mo.h deleted file mode 100644 index 12542dfd1c..0000000000 --- a/tcg/arm/tcg-target-mo.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Define target-specific memory model - * Copyright (c) 2008 Fabrice Bellard - * Copyright (c) 2008 Andrzej Zaborowski - */ - -#ifndef TCG_TARGET_MO_H -#define TCG_TARGET_MO_H - -#define TCG_TARGET_DEFAULT_MO 0 - -#endif diff --git a/tcg/arm/tcg-target-reg-bits.h b/tcg/arm/tcg-target-reg-bits.h deleted file mode 100644 index 23b7730a8d..0000000000 --- a/tcg/arm/tcg-target-reg-bits.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Define target-specific register size - * Copyright (c) 2023 Linaro - */ - -#ifndef TCG_TARGET_REG_BITS_H -#define TCG_TARGET_REG_BITS_H - -#define TCG_TARGET_REG_BITS 32 - -#endif diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h deleted file mode 100644 index 4f9f877121..0000000000 --- a/tcg/arm/tcg-target.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Tiny Code Generator for QEMU - * - * Copyright (c) 2008 Fabrice Bellard - * Copyright (c) 2008 Andrzej Zaborowski - * - * Permission is hereby granted, free of charge, to any person obtaining a= copy - * of this software and associated documentation files (the "Software"), t= o deal - * in the Software without restriction, including without limitation the r= ights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included= in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN - * THE SOFTWARE. - */ - -#ifndef ARM_TCG_TARGET_H -#define ARM_TCG_TARGET_H - -#define TCG_TARGET_INSN_UNIT_SIZE 4 -#define MAX_CODE_GEN_BUFFER_SIZE UINT32_MAX - -typedef enum { - TCG_REG_R0 =3D 0, - TCG_REG_R1, - TCG_REG_R2, - TCG_REG_R3, - TCG_REG_R4, - TCG_REG_R5, - TCG_REG_R6, - TCG_REG_R7, - TCG_REG_R8, - TCG_REG_R9, - TCG_REG_R10, - TCG_REG_R11, - TCG_REG_R12, - TCG_REG_R13, - TCG_REG_R14, - TCG_REG_PC, - - TCG_REG_Q0, - TCG_REG_Q1, - TCG_REG_Q2, - TCG_REG_Q3, - TCG_REG_Q4, - TCG_REG_Q5, - TCG_REG_Q6, - TCG_REG_Q7, - TCG_REG_Q8, - TCG_REG_Q9, - TCG_REG_Q10, - TCG_REG_Q11, - TCG_REG_Q12, - TCG_REG_Q13, - TCG_REG_Q14, - TCG_REG_Q15, - - TCG_AREG0 =3D TCG_REG_R6, - TCG_REG_CALL_STACK =3D TCG_REG_R13, -} TCGReg; - -#define TCG_TARGET_NB_REGS 32 - -#endif diff --git a/disas/disas-host.c b/disas/disas-host.c index 4b06f41fa6..88e7d8800c 100644 --- a/disas/disas-host.c +++ b/disas/disas-host.c @@ -74,9 +74,6 @@ static void initialize_debug_host(CPUDebug *s) #elif defined(__sparc__) s->info.print_insn =3D print_insn_sparc; s->info.mach =3D bfd_mach_sparc_v9b; -#elif defined(__arm__) - /* TCG only generates code for arm mode. */ - s->info.cap_arch =3D CS_ARCH_ARM; #elif defined(__MIPSEB__) s->info.print_insn =3D print_insn_big_mips; #elif defined(__MIPSEL__) diff --git a/hw/virtio/virtio-mem.c b/hw/virtio/virtio-mem.c index 41de2ef5a0..c1e2defb68 100644 --- a/hw/virtio/virtio-mem.c +++ b/hw/virtio/virtio-mem.c @@ -60,7 +60,7 @@ static uint32_t virtio_mem_default_thp_size(void) { uint32_t default_thp_size =3D VIRTIO_MEM_MIN_BLOCK_SIZE; =20 -#if defined(__x86_64__) || defined(__arm__) || defined(__powerpc64__) +#if defined(__x86_64__) || defined(__powerpc64__) default_thp_size =3D 2 * MiB; #elif defined(__aarch64__) if (qemu_real_host_page_size() =3D=3D 4 * KiB) { diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 4bcfaf7894..07175e11d5 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -1296,7 +1296,7 @@ static inline abi_ulong target_shmlba(CPUArchState *c= pu_env) } #endif =20 -#if defined(__arm__) || defined(__mips__) || defined(__sparc__) +#if defined(__mips__) || defined(__sparc__) #define HOST_FORCE_SHMLBA 1 #else #define HOST_FORCE_SHMLBA 0 diff --git a/MAINTAINERS b/MAINTAINERS index de8246c3ff..1a6e5bbafe 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4057,12 +4057,6 @@ S: Maintained L: qemu-arm@nongnu.org F: tcg/aarch64/ =20 -ARM TCG target -M: Richard Henderson -S: Maintained -L: qemu-arm@nongnu.org -F: tcg/arm/ - i386 TCG target M: Richard Henderson S: Maintained diff --git a/common-user/host/arm/safe-syscall.inc.S b/common-user/host/arm= /safe-syscall.inc.S deleted file mode 100644 index bbfb89634e..0000000000 --- a/common-user/host/arm/safe-syscall.inc.S +++ /dev/null @@ -1,108 +0,0 @@ -/* - * safe-syscall.inc.S : host-specific assembly fragment - * to handle signals occurring at the same time as system calls. - * This is intended to be included by common-user/safe-syscall.S - * - * Written by Richard Henderson - * Copyright (C) 2016 Red Hat, Inc. - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - */ - - .global safe_syscall_base - .global safe_syscall_start - .global safe_syscall_end - .type safe_syscall_base, %function - - .cfi_sections .debug_frame - - .text - .syntax unified - .arm - .align 2 - - /* This is the entry point for making a system call. The calling - * convention here is that of a C varargs function with the - * first argument an 'int *' to the signal_pending flag, the - * second one the system call number (as a 'long'), and all further - * arguments being syscall arguments (also 'long'). - */ -safe_syscall_base: - .fnstart - .cfi_startproc - mov r12, sp /* save entry stack */ - push { r4, r5, r6, r7, r8, lr } - .save { r4, r5, r6, r7, r8, lr } - .cfi_adjust_cfa_offset 24 - .cfi_rel_offset r4, 0 - .cfi_rel_offset r5, 4 - .cfi_rel_offset r6, 8 - .cfi_rel_offset r7, 12 - .cfi_rel_offset r8, 16 - .cfi_rel_offset lr, 20 - - /* The syscall calling convention isn't the same as the C one: - * we enter with r0 =3D=3D &signal_pending - * r1 =3D=3D syscall number - * r2, r3, [sp+0] ... [sp+12] =3D=3D syscall argumen= ts - * and return the result in r0 - * and the syscall instruction needs - * r7 =3D=3D syscall number - * r0 ... r6 =3D=3D syscall arguments - * and returns the result in r0 - * Shuffle everything around appropriately. - * Note the 16 bytes that we pushed to save registers. - */ - mov r8, r0 /* copy signal_pending */ - mov r7, r1 /* syscall number */ - mov r0, r2 /* syscall args */ - mov r1, r3 - ldm r12, { r2, r3, r4, r5, r6 } - - /* This next sequence of code works in conjunction with the - * rewind_if_safe_syscall_function(). If a signal is taken - * and the interrupted PC is anywhere between 'safe_syscall_start' - * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start= '. - * The code sequence must therefore be able to cope with this, and - * the syscall instruction must be the final one in the sequence. - */ -safe_syscall_start: - /* if signal_pending is non-zero, don't do the call */ - ldr r12, [r8] /* signal_pending */ - tst r12, r12 - bne 2f - swi 0 -safe_syscall_end: - - /* code path for having successfully executed the syscall */ -#if defined(__linux__) - /* Linux kernel returns (small) negative errno. */ - cmp r0, #-4096 - neghi r0, r0 - bhi 1f -#elif defined(__FreeBSD__) - /* FreeBSD kernel returns positive errno and C bit set. */ - bcs 1f -#else -#error "unsupported os" -#endif - pop { r4, r5, r6, r7, r8, pc } - - /* code path when we didn't execute the syscall */ -2: mov r0, #QEMU_ERESTARTSYS - - /* code path setting errno */ -1: pop { r4, r5, r6, r7, r8, lr } - .cfi_adjust_cfa_offset -24 - .cfi_restore r4 - .cfi_restore r5 - .cfi_restore r6 - .cfi_restore r7 - .cfi_restore r8 - .cfi_restore lr - b safe_syscall_set_errno_tail - - .fnend - .cfi_endproc - .size safe_syscall_base, .-safe_syscall_base diff --git a/configure b/configure index ba1b207b56..0742f1212d 100755 --- a/configure +++ b/configure @@ -418,8 +418,6 @@ elif check_define __riscv ; then else cpu=3D"riscv32" fi -elif check_define __arm__ ; then - cpu=3D"arm" elif check_define __aarch64__ ; then cpu=3D"aarch64" elif check_define __loongarch64 ; then @@ -451,11 +449,6 @@ case "$cpu" in linux_arch=3Darm64 ;; =20 - armv*b|armv*l|arm) - cpu=3Darm - host_arch=3Darm - ;; - i386|i486|i586|i686) cpu=3D"i386" host_arch=3Di386 diff --git a/meson.build b/meson.build index 082c7a86ca..137b2dcdc7 100644 --- a/meson.build +++ b/meson.build @@ -51,7 +51,7 @@ qapi_trace_events =3D [] bsd_oses =3D ['gnu/kfreebsd', 'freebsd', 'netbsd', 'openbsd', 'dragonfly',= 'darwin'] supported_oses =3D ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', '= sunos', 'linux', 'emscripten'] supported_cpus =3D ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86', = 'x86_64', - 'arm', 'aarch64', 'loongarch64', 'mips64', 'sparc64', 'wasm64'] + 'aarch64', 'loongarch64', 'mips64', 'sparc64', 'wasm64'] =20 cpu =3D host_machine.cpu_family() =20 @@ -304,9 +304,6 @@ if cpu =3D=3D 'x86' xen_targets =3D ['i386-softmmu'] elif cpu =3D=3D 'x86_64' xen_targets =3D ['i386-softmmu', 'x86_64-softmmu'] -elif cpu =3D=3D 'arm' - # i386 emulator provides xenpv machine type for multiple architectures - xen_targets =3D ['i386-softmmu'] elif cpu =3D=3D 'aarch64' # i386 emulator provides xenpv machine type for multiple architectures xen_targets =3D ['i386-softmmu', 'x86_64-softmmu', 'aarch64-softmmu'] @@ -3156,7 +3153,7 @@ endif config_host_data.set('CONFIG_AVX2_OPT', have_avx2) config_host_data.set('CONFIG_AVX512BW_OPT', have_avx512bw) =20 -# For both AArch64 and AArch32, detect if builtins are available. +# For AArch64, detect if builtins are available. config_host_data.set('CONFIG_ARM_AES_BUILTIN', cc.compiles(''' #include #ifndef __ARM_FEATURE_AES diff --git a/tcg/arm/tcg-target-opc.h.inc b/tcg/arm/tcg-target-opc.h.inc deleted file mode 100644 index 70394e0282..0000000000 --- a/tcg/arm/tcg-target-opc.h.inc +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2019 Linaro - * - * This work is licensed under the terms of the GNU GPL, version 2 or - * (at your option) any later version. - * - * See the COPYING file in the top-level directory for details. - * - * Target-specific opcodes for host vector expansion. These will be - * emitted by tcg_expand_vec_op. For those familiar with GCC internals, - * consider these to be UNSPEC with names. - */ - -DEF(arm_sli_vec, 1, 2, 1, TCG_OPF_VECTOR) -DEF(arm_sshl_vec, 1, 2, 0, TCG_OPF_VECTOR) -DEF(arm_ushl_vec, 1, 2, 0, TCG_OPF_VECTOR) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc deleted file mode 100644 index 87ca66bb02..0000000000 --- a/tcg/arm/tcg-target.c.inc +++ /dev/null @@ -1,3489 +0,0 @@ -/* - * Tiny Code Generator for QEMU - * - * Copyright (c) 2008 Andrzej Zaborowski - * - * Permission is hereby granted, free of charge, to any person obtaining a= copy - * of this software and associated documentation files (the "Software"), t= o deal - * in the Software without restriction, including without limitation the r= ights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included= in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN - * THE SOFTWARE. - */ - -#include "elf.h" - -int arm_arch =3D __ARM_ARCH; - -#ifndef use_idiv_instructions -bool use_idiv_instructions; -#endif -#ifndef use_neon_instructions -bool use_neon_instructions; -#endif - -/* Used for function call generation. */ -#define TCG_TARGET_STACK_ALIGN 8 -#define TCG_TARGET_CALL_STACK_OFFSET 0 -#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL -#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN -#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN -#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF - -#ifdef CONFIG_DEBUG_TCG -static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { - "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", - "%r8", "%r9", "%r10", "%r11", "%r12", "%sp", "%r14", "%pc", - "%q0", "%q1", "%q2", "%q3", "%q4", "%q5", "%q6", "%q7", - "%q8", "%q9", "%q10", "%q11", "%q12", "%q13", "%q14", "%q15", -}; -#endif - -static const int tcg_target_reg_alloc_order[] =3D { - TCG_REG_R4, - TCG_REG_R5, - TCG_REG_R6, - TCG_REG_R7, - TCG_REG_R8, - TCG_REG_R9, - TCG_REG_R10, - TCG_REG_R11, - TCG_REG_R13, - TCG_REG_R0, - TCG_REG_R1, - TCG_REG_R2, - TCG_REG_R3, - TCG_REG_R12, - TCG_REG_R14, - - TCG_REG_Q0, - TCG_REG_Q1, - TCG_REG_Q2, - TCG_REG_Q3, - /* Q4 - Q7 are call-saved, and skipped. */ - TCG_REG_Q8, - TCG_REG_Q9, - TCG_REG_Q10, - TCG_REG_Q11, - TCG_REG_Q12, - TCG_REG_Q13, - TCG_REG_Q14, - TCG_REG_Q15, -}; - -static const int tcg_target_call_iarg_regs[4] =3D { - TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 -}; - -static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) -{ - tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); - tcg_debug_assert(slot >=3D 0 && slot <=3D 3); - return TCG_REG_R0 + slot; -} - -#define TCG_REG_TMP TCG_REG_R12 -#define TCG_VEC_TMP TCG_REG_Q15 -#define TCG_REG_GUEST_BASE TCG_REG_R11 - -typedef enum { - COND_EQ =3D 0x0, - COND_NE =3D 0x1, - COND_CS =3D 0x2, /* Unsigned greater or equal */ - COND_CC =3D 0x3, /* Unsigned less than */ - COND_MI =3D 0x4, /* Negative */ - COND_PL =3D 0x5, /* Zero or greater */ - COND_VS =3D 0x6, /* Overflow */ - COND_VC =3D 0x7, /* No overflow */ - COND_HI =3D 0x8, /* Unsigned greater than */ - COND_LS =3D 0x9, /* Unsigned less or equal */ - COND_GE =3D 0xa, - COND_LT =3D 0xb, - COND_GT =3D 0xc, - COND_LE =3D 0xd, - COND_AL =3D 0xe, -} ARMCond; - -#define TO_CPSR (1 << 20) - -#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) -#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) -#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) -#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) -#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) -#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) -#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) -#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) - -typedef enum { - ARITH_AND =3D 0x0 << 21, - ARITH_EOR =3D 0x1 << 21, - ARITH_SUB =3D 0x2 << 21, - ARITH_RSB =3D 0x3 << 21, - ARITH_ADD =3D 0x4 << 21, - ARITH_ADC =3D 0x5 << 21, - ARITH_SBC =3D 0x6 << 21, - ARITH_RSC =3D 0x7 << 21, - ARITH_TST =3D 0x8 << 21 | TO_CPSR, - ARITH_CMP =3D 0xa << 21 | TO_CPSR, - ARITH_CMN =3D 0xb << 21 | TO_CPSR, - ARITH_ORR =3D 0xc << 21, - ARITH_MOV =3D 0xd << 21, - ARITH_BIC =3D 0xe << 21, - ARITH_MVN =3D 0xf << 21, - - INSN_B =3D 0x0a000000, - - INSN_CLZ =3D 0x016f0f10, - INSN_RBIT =3D 0x06ff0f30, - - INSN_LDMIA =3D 0x08b00000, - INSN_STMDB =3D 0x09200000, - - INSN_LDR_IMM =3D 0x04100000, - INSN_LDR_REG =3D 0x06100000, - INSN_STR_IMM =3D 0x04000000, - INSN_STR_REG =3D 0x06000000, - - INSN_LDRH_IMM =3D 0x005000b0, - INSN_LDRH_REG =3D 0x001000b0, - INSN_LDRSH_IMM =3D 0x005000f0, - INSN_LDRSH_REG =3D 0x001000f0, - INSN_STRH_IMM =3D 0x004000b0, - INSN_STRH_REG =3D 0x000000b0, - - INSN_LDRB_IMM =3D 0x04500000, - INSN_LDRB_REG =3D 0x06500000, - INSN_LDRSB_IMM =3D 0x005000d0, - INSN_LDRSB_REG =3D 0x001000d0, - INSN_STRB_IMM =3D 0x04400000, - INSN_STRB_REG =3D 0x06400000, - - INSN_LDRD_IMM =3D 0x004000d0, - INSN_LDRD_REG =3D 0x000000d0, - INSN_STRD_IMM =3D 0x004000f0, - INSN_STRD_REG =3D 0x000000f0, - - INSN_DMB_ISH =3D 0xf57ff05b, - INSN_DMB_MCR =3D 0xee070fba, - - INSN_MSRI_CPSR =3D 0x0360f000, - - /* Architected nop introduced in v6k. */ - /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this - also Just So Happened to do nothing on pre-v6k so that we - don't need to conditionalize it? */ - INSN_NOP_v6k =3D 0xe320f000, - /* Otherwise the assembler uses mov r0,r0 */ - INSN_NOP_v4 =3D (COND_AL << 28) | ARITH_MOV, - - INSN_VADD =3D 0xf2000800, - INSN_VAND =3D 0xf2000110, - INSN_VBIC =3D 0xf2100110, - INSN_VEOR =3D 0xf3000110, - INSN_VORN =3D 0xf2300110, - INSN_VORR =3D 0xf2200110, - INSN_VSUB =3D 0xf3000800, - INSN_VMUL =3D 0xf2000910, - INSN_VQADD =3D 0xf2000010, - INSN_VQADD_U =3D 0xf3000010, - INSN_VQSUB =3D 0xf2000210, - INSN_VQSUB_U =3D 0xf3000210, - INSN_VMAX =3D 0xf2000600, - INSN_VMAX_U =3D 0xf3000600, - INSN_VMIN =3D 0xf2000610, - INSN_VMIN_U =3D 0xf3000610, - - INSN_VABS =3D 0xf3b10300, - INSN_VMVN =3D 0xf3b00580, - INSN_VNEG =3D 0xf3b10380, - - INSN_VCEQ0 =3D 0xf3b10100, - INSN_VCGT0 =3D 0xf3b10000, - INSN_VCGE0 =3D 0xf3b10080, - INSN_VCLE0 =3D 0xf3b10180, - INSN_VCLT0 =3D 0xf3b10200, - - INSN_VCEQ =3D 0xf3000810, - INSN_VCGE =3D 0xf2000310, - INSN_VCGT =3D 0xf2000300, - INSN_VCGE_U =3D 0xf3000310, - INSN_VCGT_U =3D 0xf3000300, - - INSN_VSHLI =3D 0xf2800510, /* VSHL (immediate) */ - INSN_VSARI =3D 0xf2800010, /* VSHR.S */ - INSN_VSHRI =3D 0xf3800010, /* VSHR.U */ - INSN_VSLI =3D 0xf3800510, - INSN_VSHL_S =3D 0xf2000400, /* VSHL.S (register) */ - INSN_VSHL_U =3D 0xf3000400, /* VSHL.U (register) */ - - INSN_VBSL =3D 0xf3100110, - INSN_VBIT =3D 0xf3200110, - INSN_VBIF =3D 0xf3300110, - - INSN_VTST =3D 0xf2000810, - - INSN_VDUP_G =3D 0xee800b10, /* VDUP (ARM core register) */ - INSN_VDUP_S =3D 0xf3b00c00, /* VDUP (scalar) */ - INSN_VLDR_D =3D 0xed100b00, /* VLDR.64 */ - INSN_VLD1 =3D 0xf4200000, /* VLD1 (multiple single elements) */ - INSN_VLD1R =3D 0xf4a00c00, /* VLD1 (single element to all lanes) = */ - INSN_VST1 =3D 0xf4000000, /* VST1 (multiple single elements) */ - INSN_VMOVI =3D 0xf2800010, /* VMOV (immediate) */ -} ARMInsn; - -#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) - -static const uint8_t tcg_cond_to_arm_cond[] =3D { - [TCG_COND_EQ] =3D COND_EQ, - [TCG_COND_NE] =3D COND_NE, - [TCG_COND_LT] =3D COND_LT, - [TCG_COND_GE] =3D COND_GE, - [TCG_COND_LE] =3D COND_LE, - [TCG_COND_GT] =3D COND_GT, - /* unsigned */ - [TCG_COND_LTU] =3D COND_CC, - [TCG_COND_GEU] =3D COND_CS, - [TCG_COND_LEU] =3D COND_LS, - [TCG_COND_GTU] =3D COND_HI, -}; - -static int encode_imm(uint32_t imm); - -/* TCG private relocation type: add with pc+imm8 */ -#define R_ARM_PC8 11 - -/* TCG private relocation type: vldr with imm8 << 2 */ -#define R_ARM_PC11 12 - -static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) -{ - const tcg_insn_unit *src_rx =3D tcg_splitwx_to_rx(src_rw); - ptrdiff_t offset =3D (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2; - - if (offset =3D=3D sextract32(offset, 0, 24)) { - *src_rw =3D deposit32(*src_rw, 0, 24, offset); - return true; - } - return false; -} - -static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target) -{ - const tcg_insn_unit *src_rx =3D tcg_splitwx_to_rx(src_rw); - ptrdiff_t offset =3D tcg_ptr_byte_diff(target, src_rx) - 8; - - if (offset >=3D -0xfff && offset <=3D 0xfff) { - tcg_insn_unit insn =3D *src_rw; - bool u =3D (offset >=3D 0); - if (!u) { - offset =3D -offset; - } - insn =3D deposit32(insn, 23, 1, u); - insn =3D deposit32(insn, 0, 12, offset); - *src_rw =3D insn; - return true; - } - return false; -} - -static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target) -{ - const tcg_insn_unit *src_rx =3D tcg_splitwx_to_rx(src_rw); - ptrdiff_t offset =3D (tcg_ptr_byte_diff(target, src_rx) - 8) / 4; - - if (offset >=3D -0xff && offset <=3D 0xff) { - tcg_insn_unit insn =3D *src_rw; - bool u =3D (offset >=3D 0); - if (!u) { - offset =3D -offset; - } - insn =3D deposit32(insn, 23, 1, u); - insn =3D deposit32(insn, 0, 8, offset); - *src_rw =3D insn; - return true; - } - return false; -} - -static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target) -{ - const tcg_insn_unit *src_rx =3D tcg_splitwx_to_rx(src_rw); - ptrdiff_t offset =3D tcg_ptr_byte_diff(target, src_rx) - 8; - int imm12 =3D encode_imm(offset); - - if (imm12 >=3D 0) { - *src_rw =3D deposit32(*src_rw, 0, 12, imm12); - return true; - } - return false; -} - -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, - intptr_t value, intptr_t addend) -{ - tcg_debug_assert(addend =3D=3D 0); - switch (type) { - case R_ARM_PC24: - return reloc_pc24(code_ptr, (const tcg_insn_unit *)value); - case R_ARM_PC13: - return reloc_pc13(code_ptr, (const tcg_insn_unit *)value); - case R_ARM_PC11: - return reloc_pc11(code_ptr, (const tcg_insn_unit *)value); - case R_ARM_PC8: - return reloc_pc8(code_ptr, (const tcg_insn_unit *)value); - default: - g_assert_not_reached(); - } -} - -#define TCG_CT_CONST_ARM 0x100 -#define TCG_CT_CONST_INV 0x200 -#define TCG_CT_CONST_NEG 0x400 -#define TCG_CT_CONST_ZERO 0x800 -#define TCG_CT_CONST_ORRI 0x1000 -#define TCG_CT_CONST_ANDI 0x2000 - -#define ALL_GENERAL_REGS 0xffffu -#define ALL_VECTOR_REGS 0xffff0000u - -/* - * r0-r3 will be overwritten when reading the tlb entry (system-mode only); - * r14 will be overwritten by the BLNE branching to the slow path. - */ -#define ALL_QLDST_REGS \ - (ALL_GENERAL_REGS & ~((tcg_use_softmmu ? 0xf : 0) | (1 << TCG_REG_R14)= )) - -/* - * ARM immediates for ALU instructions are made of an unsigned 8-bit - * right-rotated by an even amount between 0 and 30. - * - * Return < 0 if @imm cannot be encoded, else the entire imm12 field. - */ -static int encode_imm(uint32_t imm) -{ - uint32_t rot, imm8; - - /* Simple case, no rotation required. */ - if ((imm & ~0xff) =3D=3D 0) { - return imm; - } - - /* Next, try a simple even shift. */ - rot =3D ctz32(imm) & ~1; - imm8 =3D imm >> rot; - rot =3D 32 - rot; - if ((imm8 & ~0xff) =3D=3D 0) { - goto found; - } - - /* - * Finally, try harder with rotations. - * The ctz test above will have taken care of rotates >=3D 8. - */ - for (rot =3D 2; rot < 8; rot +=3D 2) { - imm8 =3D rol32(imm, rot); - if ((imm8 & ~0xff) =3D=3D 0) { - goto found; - } - } - /* Fail: imm cannot be encoded. */ - return -1; - - found: - /* Note that rot is even, and we discard bit 0 by shifting by 7. */ - return rot << 7 | imm8; -} - -static int encode_imm_nofail(uint32_t imm) -{ - int ret =3D encode_imm(imm); - tcg_debug_assert(ret >=3D 0); - return ret; -} - -static bool check_fit_imm(uint32_t imm) -{ - return encode_imm(imm) >=3D 0; -} - -/* Return true if v16 is a valid 16-bit shifted immediate. */ -static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) -{ - if (v16 =3D=3D (v16 & 0xff)) { - *cmode =3D 0x8; - *imm8 =3D v16 & 0xff; - return true; - } else if (v16 =3D=3D (v16 & 0xff00)) { - *cmode =3D 0xa; - *imm8 =3D v16 >> 8; - return true; - } - return false; -} - -/* Return true if v32 is a valid 32-bit shifted immediate. */ -static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) -{ - if (v32 =3D=3D (v32 & 0xff)) { - *cmode =3D 0x0; - *imm8 =3D v32 & 0xff; - return true; - } else if (v32 =3D=3D (v32 & 0xff00)) { - *cmode =3D 0x2; - *imm8 =3D (v32 >> 8) & 0xff; - return true; - } else if (v32 =3D=3D (v32 & 0xff0000)) { - *cmode =3D 0x4; - *imm8 =3D (v32 >> 16) & 0xff; - return true; - } else if (v32 =3D=3D (v32 & 0xff000000)) { - *cmode =3D 0x6; - *imm8 =3D v32 >> 24; - return true; - } - return false; -} - -/* Return true if v32 is a valid 32-bit shifting ones immediate. */ -static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) -{ - if ((v32 & 0xffff00ff) =3D=3D 0xff) { - *cmode =3D 0xc; - *imm8 =3D (v32 >> 8) & 0xff; - return true; - } else if ((v32 & 0xff00ffff) =3D=3D 0xffff) { - *cmode =3D 0xd; - *imm8 =3D (v32 >> 16) & 0xff; - return true; - } - return false; -} - -/* - * Return non-zero if v32 can be formed by MOVI+ORR. - * Place the parameters for MOVI in (cmode, imm8). - * Return the cmode for ORR; the imm8 can be had via extraction from v32. - */ -static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) -{ - int i; - - for (i =3D 6; i > 0; i -=3D 2) { - /* Mask out one byte we can add with ORR. */ - uint32_t tmp =3D v32 & ~(0xffu << (i * 4)); - if (is_shimm32(tmp, cmode, imm8) || - is_soimm32(tmp, cmode, imm8)) { - break; - } - } - return i; -} - -/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ -static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) -{ - if (v32 =3D=3D deposit32(v32, 16, 16, v32)) { - return is_shimm16(v32, cmode, imm8); - } else { - return is_shimm32(v32, cmode, imm8); - } -} - -/* Test if a constant matches the constraint. - * TODO: define constraints for: - * - * ldr/str offset: between -0xfff and 0xfff - * ldrh/strh offset: between -0xff and 0xff - * mov operand2: values represented with x << (2 * y), x < 0x100 - * add, sub, eor...: ditto - */ -static bool tcg_target_const_match(int64_t val, int ct, - TCGType type, TCGCond cond, int vece) -{ - if (ct & TCG_CT_CONST) { - return 1; - } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { - return 1; - } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) { - return 1; - } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { - return 1; - } else if ((ct & TCG_CT_CONST_ZERO) && val =3D=3D 0) { - return 1; - } - - switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { - case 0: - break; - case TCG_CT_CONST_ANDI: - val =3D ~val; - /* fallthru */ - case TCG_CT_CONST_ORRI: - if (val =3D=3D deposit64(val, 32, 32, val)) { - int cmode, imm8; - return is_shimm1632(val, &cmode, &imm8); - } - break; - default: - /* Both bits should not be set for the same insn. */ - g_assert_not_reached(); - } - - return 0; -} - -static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset) -{ - tcg_out32(s, (cond << 28) | INSN_B | - (((offset - 8) >> 2) & 0x00ffffff)); -} - -static void tcg_out_bl_imm(TCGContext *s, ARMCond cond, int32_t offset) -{ - tcg_out32(s, (cond << 28) | 0x0b000000 | - (((offset - 8) >> 2) & 0x00ffffff)); -} - -static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, TCGReg rn) -{ - tcg_out32(s, (cond << 28) | 0x012fff30 | rn); -} - -static void tcg_out_blx_imm(TCGContext *s, int32_t offset) -{ - tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | - (((offset - 8) >> 2) & 0x00ffffff)); -} - -static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, - TCGReg rd, TCGReg rn, TCGReg rm, int shift) -{ - tcg_out32(s, (cond << 28) | (0 << 25) | opc | - (rn << 16) | (rd << 12) | shift | rm); -} - -static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg= rm) -{ - /* Simple reg-reg move, optimising out the 'do nothing' case */ - if (rd !=3D rm) { - tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); - } -} - -static void tcg_out_bx_reg(TCGContext *s, ARMCond cond, TCGReg rn) -{ - tcg_out32(s, (cond << 28) | 0x012fff10 | rn); -} - -static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn) -{ - /* - * Unless the C portion of QEMU is compiled as thumb, we don't need - * true BX semantics; merely a branch to an address held in a register. - */ - tcg_out_bx_reg(s, cond, rn); -} - -static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, - TCGReg rd, TCGReg rn, int im) -{ - tcg_out32(s, (cond << 28) | (1 << 25) | opc | - (rn << 16) | (rd << 12) | im); -} - -static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc, - TCGReg rn, uint16_t mask) -{ - tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); -} - -/* Note that this routine is used for both LDR and LDRH formats, so we do - not wish to include an immediate shift at this point. */ -static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGR= eg rt, - TCGReg rn, TCGReg rm, bool u, bool p, bool w) -{ - tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) - | (w << 21) | (rn << 16) | (rt << 12) | rm); -} - -static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGR= eg rt, - TCGReg rn, int imm8, bool p, bool w) -{ - bool u =3D 1; - if (imm8 < 0) { - imm8 =3D -imm8; - u =3D 0; - } - tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | - (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf= )); -} - -static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, - TCGReg rt, TCGReg rn, int imm12, bool p, bool= w) -{ - bool u =3D 1; - if (imm12 < 0) { - imm12 =3D -imm12; - u =3D 0; - } - tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | - (rn << 16) | (rt << 12) | imm12); -} - -static void tcg_out_ld32_12(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, int imm12) -{ - tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); -} - -static void tcg_out_st32_12(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, int imm12) -{ - tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); -} - -static void tcg_out_ld32_r(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); -} - -static void tcg_out_st32_r(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); -} - -static void tcg_out_ldrd_8(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); -} - -static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); -} - -static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); -} - -static void tcg_out_strd_r(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); -} - -/* Register pre-increment with base writeback. */ -static void tcg_out_ld32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); -} - -static void tcg_out_st32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); -} - -static void tcg_out_ld16u_8(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); -} - -static void tcg_out_st16_8(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); -} - -static void tcg_out_ld16u_r(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); -} - -static void tcg_out_st16_r(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); -} - -static void tcg_out_ld16s_8(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); -} - -static void tcg_out_ld16s_r(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); -} - -static void tcg_out_ld8_12(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, int imm12) -{ - tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); -} - -static void tcg_out_st8_12(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, int imm12) -{ - tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); -} - -static void tcg_out_ld8_r(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); -} - -static void tcg_out_st8_r(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); -} - -static void tcg_out_ld8s_8(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); -} - -static void tcg_out_ld8s_r(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); -} - -static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, - TCGReg rd, uint32_t arg) -{ - new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); - tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); -} - -static void tcg_out_movi32(TCGContext *s, ARMCond cond, - TCGReg rd, uint32_t arg) -{ - int imm12, diff, opc, sh1, sh2; - uint32_t tt0, tt1, tt2; - - /* Check a single MOV/MVN before anything else. */ - imm12 =3D encode_imm(arg); - if (imm12 >=3D 0) { - tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, imm12); - return; - } - imm12 =3D encode_imm(~arg); - if (imm12 >=3D 0) { - tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, imm12); - return; - } - - /* Check for a pc-relative address. This will usually be the TB, - or within the TB, which is immediately before the code block. */ - diff =3D tcg_pcrel_diff(s, (void *)arg) - 8; - if (diff >=3D 0) { - imm12 =3D encode_imm(diff); - if (imm12 >=3D 0) { - tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, imm12); - return; - } - } else { - imm12 =3D encode_imm(-diff); - if (imm12 >=3D 0) { - tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, imm12); - return; - } - } - - /* Use movw + movt. */ - if (use_armv7_instructions) { - /* movw */ - tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12) - | ((arg << 4) & 0x000f0000) | (arg & 0xfff)); - if (arg & 0xffff0000) { - /* movt */ - tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12) - | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff)= ); - } - return; - } - - /* Look for sequences of two insns. If we have lots of 1's, we can - shorten the sequence by beginning with mvn and then clearing - higher bits with eor. */ - tt0 =3D arg; - opc =3D ARITH_MOV; - if (ctpop32(arg) > 16) { - tt0 =3D ~arg; - opc =3D ARITH_MVN; - } - sh1 =3D ctz32(tt0) & ~1; - tt1 =3D tt0 & ~(0xff << sh1); - sh2 =3D ctz32(tt1) & ~1; - tt2 =3D tt1 & ~(0xff << sh2); - if (tt2 =3D=3D 0) { - int rot; - - rot =3D ((32 - sh1) << 7) & 0xf00; - tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); - rot =3D ((32 - sh2) << 7) & 0xf00; - tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd, - ((tt0 >> sh2) & 0xff) | rot); - return; - } - - /* Otherwise, drop it into the constant pool. */ - tcg_out_movi_pool(s, cond, rd, arg); -} - -/* - * Emit either the reg,imm or reg,reg form of a data-processing insn. - * rhs must satisfy the "rI" constraint. - */ -static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, - TCGReg dst, TCGReg lhs, TCGArg rhs, int rhs_is_= const) -{ - if (rhs_is_const) { - tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); - } else { - tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); - } -} - -/* - * Emit either the reg,imm or reg,reg form of a data-processing insn. - * rhs must satisfy the "rIK" constraint. - */ -static void tcg_out_dat_IK(TCGContext *s, ARMCond cond, ARMInsn opc, - ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg = rhs) -{ - int imm12 =3D encode_imm(rhs); - if (imm12 < 0) { - imm12 =3D encode_imm_nofail(~rhs); - opc =3D opinv; - } - tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); -} - -static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc, - ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg = rhs, - bool rhs_is_const) -{ - if (rhs_is_const) { - tcg_out_dat_IK(s, cond, opc, opinv, dst, lhs, rhs); - } else { - tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); - } -} - -static void tcg_out_dat_IN(TCGContext *s, ARMCond cond, ARMInsn opc, - ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg r= hs) -{ - int imm12 =3D encode_imm(rhs); - if (imm12 < 0) { - imm12 =3D encode_imm_nofail(-rhs); - opc =3D opneg; - } - tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); -} - -static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, - ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg = rhs, - bool rhs_is_const) -{ - /* Emit either the reg,imm or reg,reg form of a data-processing insn. - * rhs must satisfy the "rIN" constraint. - */ - if (rhs_is_const) { - tcg_out_dat_IN(s, cond, opc, opneg, dst, lhs, rhs); - } else { - tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); - } -} - -static void tcg_out_ext8s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) -{ - /* sxtb */ - tcg_out32(s, 0x06af0070 | (COND_AL << 28) | (rd << 12) | rn); -} - -static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn) -{ - tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); -} - -static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) -{ - /* sxth */ - tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); -} - -static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) -{ - /* uxth */ - tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | (rd << 12) | rn); -} - -static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) -{ - g_assert_not_reached(); -} - -static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rn) -{ - g_assert_not_reached(); -} - -static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) -{ - g_assert_not_reached(); -} - -static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) -{ - g_assert_not_reached(); -} - -static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) -{ - g_assert_not_reached(); -} - -static void tgen_deposit(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, - TCGReg a2, unsigned ofs, unsigned len) -{ - /* bfi/bfc */ - tcg_debug_assert(a0 =3D=3D a1); - tcg_out32(s, 0x07c00010 | (COND_AL << 28) | (a0 << 12) | a2 - | (ofs << 7) | ((ofs + len - 1) << 16)); -} - -static void tgen_depositi(TCGContext *s, TCGType type, TCGReg a0, TCGReg a= 1, - tcg_target_long a2, unsigned ofs, unsigned len) -{ - /* bfi becomes bfc with rn =3D=3D 15. */ - tgen_deposit(s, type, a0, a1, 15, ofs, len); -} - -static const TCGOutOpDeposit outop_deposit =3D { - .base.static_constraint =3D C_O1_I2(r, 0, rZ), - .out_rrr =3D tgen_deposit, - .out_rri =3D tgen_depositi, -}; - -static void tgen_extract(TCGContext *s, TCGType type, TCGReg rd, TCGReg rn, - unsigned ofs, unsigned len) -{ - /* According to gcc, AND can be faster. */ - if (ofs =3D=3D 0 && len <=3D 8) { - tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, - encode_imm_nofail((1 << len) - 1)); - return; - } - - if (use_armv7_instructions) { - /* ubfx */ - tcg_out32(s, 0x07e00050 | (COND_AL << 28) | (rd << 12) | rn - | (ofs << 7) | ((len - 1) << 16)); - return; - } - - assert(ofs % 8 =3D=3D 0); - switch (len) { - case 8: - /* uxtb */ - tcg_out32(s, 0x06ef0070 | (COND_AL << 28) | - (rd << 12) | (ofs << 7) | rn); - break; - case 16: - /* uxth */ - tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | - (rd << 12) | (ofs << 7) | rn); - break; - default: - g_assert_not_reached(); - } -} - -static const TCGOutOpExtract outop_extract =3D { - .base.static_constraint =3D C_O1_I1(r, r), - .out_rr =3D tgen_extract, -}; - -static void tgen_sextract(TCGContext *s, TCGType type, TCGReg rd, TCGReg r= n, - unsigned ofs, unsigned len) -{ - if (use_armv7_instructions) { - /* sbfx */ - tcg_out32(s, 0x07a00050 | (COND_AL << 28) | (rd << 12) | rn - | (ofs << 7) | ((len - 1) << 16)); - return; - } - - assert(ofs % 8 =3D=3D 0); - switch (len) { - case 8: - /* sxtb */ - tcg_out32(s, 0x06af0070 | (COND_AL << 28) | - (rd << 12) | (ofs << 7) | rn); - break; - case 16: - /* sxth */ - tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | - (rd << 12) | (ofs << 7) | rn); - break; - default: - g_assert_not_reached(); - } -} - -static const TCGOutOpExtract outop_sextract =3D { - .base.static_constraint =3D C_O1_I1(r, r), - .out_rr =3D tgen_sextract, -}; - - -static void tcg_out_ld32u(TCGContext *s, ARMCond cond, - TCGReg rd, TCGReg rn, int32_t offset) -{ - if (offset > 0xfff || offset < -0xfff) { - tcg_out_movi32(s, cond, TCG_REG_TMP, offset); - tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP); - } else - tcg_out_ld32_12(s, cond, rd, rn, offset); -} - -static void tcg_out_st32(TCGContext *s, ARMCond cond, - TCGReg rd, TCGReg rn, int32_t offset) -{ - if (offset > 0xfff || offset < -0xfff) { - tcg_out_movi32(s, cond, TCG_REG_TMP, offset); - tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP); - } else - tcg_out_st32_12(s, cond, rd, rn, offset); -} - -/* - * The _goto case is normally between TBs within the same code buffer, and - * with the code buffer limited to 16MB we wouldn't need the long case. - * But we also use it for the tail-call to the qemu_ld/st helpers, which d= oes. - */ -static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit = *addr) -{ - intptr_t addri =3D (intptr_t)addr; - ptrdiff_t disp =3D tcg_pcrel_diff(s, addr); - bool arm_mode =3D !(addri & 1); - - if (arm_mode && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) { - tcg_out_b_imm(s, cond, disp); - return; - } - - /* LDR is interworking from v5t. */ - tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); -} - -/* - * The call case is mostly used for helpers - so it's not unreasonable - * for them to be beyond branch range. - */ -static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *addr) -{ - intptr_t addri =3D (intptr_t)addr; - ptrdiff_t disp =3D tcg_pcrel_diff(s, addr); - bool arm_mode =3D !(addri & 1); - - if (disp - 8 < 0x02000000 && disp - 8 >=3D -0x02000000) { - if (arm_mode) { - tcg_out_bl_imm(s, COND_AL, disp); - } else { - tcg_out_blx_imm(s, disp); - } - return; - } - - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); - tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); -} - -static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr, - const TCGHelperInfo *info) -{ - tcg_out_call_int(s, addr); -} - -static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) -{ - if (l->has_value) { - tcg_out_goto(s, cond, l->u.value_ptr); - } else { - tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0); - tcg_out_b_imm(s, cond, 0); - } -} - -static void tcg_out_br(TCGContext *s, TCGLabel *l) -{ - tcg_out_goto_label(s, COND_AL, l); -} - -static void tcg_out_mb(TCGContext *s, unsigned a0) -{ - if (use_armv7_instructions) { - tcg_out32(s, INSN_DMB_ISH); - } else { - tcg_out32(s, INSN_DMB_MCR); - } -} - -static TCGCond tgen_cmp(TCGContext *s, TCGCond cond, TCGReg a, TCGReg b) -{ - if (is_tst_cond(cond)) { - tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, a, b, SHIFT_IMM_LSL(0)); - return tcg_tst_eqne_cond(cond); - } - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, a, b, SHIFT_IMM_LSL(0)); - return cond; -} - -static TCGCond tgen_cmpi(TCGContext *s, TCGCond cond, TCGReg a, TCGArg b) -{ - int imm12; - - if (!is_tst_cond(cond)) { - tcg_out_dat_IN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a, b); - return cond; - } - - /* - * The compare constraints allow rIN, but TST does not support N. - * Be prepared to load the constant into a scratch register. - */ - imm12 =3D encode_imm(b); - if (imm12 >=3D 0) { - tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, a, imm12); - } else { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, b); - tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, - a, TCG_REG_TMP, SHIFT_IMM_LSL(0)); - } - return tcg_tst_eqne_cond(cond); -} - -static TCGCond tcg_out_cmp(TCGContext *s, TCGCond cond, TCGReg a, - TCGArg b, int b_const) -{ - if (b_const) { - return tgen_cmpi(s, cond, a, b); - } else { - return tgen_cmp(s, cond, a, b); - } -} - -static TCGCond tcg_out_cmp2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg= ah, - TCGArg bl, bool const_bl, TCGArg bh, bool cons= t_bh) -{ - switch (cond) { - case TCG_COND_EQ: - case TCG_COND_NE: - case TCG_COND_LTU: - case TCG_COND_LEU: - case TCG_COND_GTU: - case TCG_COND_GEU: - /* - * We perform a conditional comparison. If the high half is - * equal, then overwrite the flags with the comparison of the - * low half. The resulting flags cover the whole. - */ - tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh); - tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); - return cond; - - case TCG_COND_TSTEQ: - case TCG_COND_TSTNE: - /* Similar, but with TST instead of CMP. */ - tcg_out_dat_rI(s, COND_AL, ARITH_TST, 0, ah, bh, const_bh); - tcg_out_dat_rI(s, COND_EQ, ARITH_TST, 0, al, bl, const_bl); - return tcg_tst_eqne_cond(cond); - - case TCG_COND_LT: - case TCG_COND_GE: - /* We perform a double-word subtraction and examine the result. - We do not actually need the result of the subtract, so the - low part "subtract" is a compare. For the high half we have - no choice but to compute into a temporary. */ - tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl); - tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR, - TCG_REG_TMP, ah, bh, const_bh); - return cond; - - case TCG_COND_LE: - case TCG_COND_GT: - /* Similar, but with swapped arguments, via reversed subtract. */ - tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, - TCG_REG_TMP, al, bl, const_bl); - tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR, - TCG_REG_TMP, ah, bh, const_bh); - return tcg_swap_cond(cond); - - default: - g_assert_not_reached(); - } -} - -/* - * Note that TCGReg references Q-registers. - * Q-regno =3D 2 * D-regno, so shift left by 1 while inserting. - */ -static uint32_t encode_vd(TCGReg rd) -{ - tcg_debug_assert(rd >=3D TCG_REG_Q0); - return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13); -} - -static uint32_t encode_vn(TCGReg rn) -{ - tcg_debug_assert(rn >=3D TCG_REG_Q0); - return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17); -} - -static uint32_t encode_vm(TCGReg rm) -{ - tcg_debug_assert(rm >=3D TCG_REG_Q0); - return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1); -} - -static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece, - TCGReg d, TCGReg m) -{ - tcg_out32(s, insn | (vece << 18) | (q << 6) | - encode_vd(d) | encode_vm(m)); -} - -static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece, - TCGReg d, TCGReg n, TCGReg m) -{ - tcg_out32(s, insn | (vece << 20) | (q << 6) | - encode_vd(d) | encode_vn(n) | encode_vm(m)); -} - -static void tcg_out_vmovi(TCGContext *s, TCGReg rd, - int q, int op, int cmode, uint8_t imm8) -{ - tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5) - | (cmode << 8) | extract32(imm8, 0, 4) - | (extract32(imm8, 4, 3) << 16) - | (extract32(imm8, 7, 1) << 24)); -} - -static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q, - TCGReg rd, TCGReg rm, int l_imm6) -{ - tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) | - (extract32(l_imm6, 6, 1) << 7) | - (extract32(l_imm6, 0, 6) << 16)); -} - -static void tcg_out_vldst(TCGContext *s, ARMInsn insn, - TCGReg rd, TCGReg rn, int offset) -{ - if (offset !=3D 0) { - if (check_fit_imm(offset) || check_fit_imm(-offset)) { - tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, - TCG_REG_TMP, rn, offset, true); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); - tcg_out_dat_reg(s, COND_AL, ARITH_ADD, - TCG_REG_TMP, TCG_REG_TMP, rn, 0); - } - rn =3D TCG_REG_TMP; - } - tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); -} - -typedef struct { - ARMCond cond; - TCGReg base; - int index; - bool index_scratch; - TCGAtomAlign aa; -} HostAddress; - -bool tcg_target_has_memory_bswap(MemOp memop) -{ - return false; -} - -static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int ar= g) -{ - /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ - return TCG_REG_R14; -} - -static const TCGLdstHelperParam ldst_helper_param =3D { - .ra_gen =3D ldst_ra_gen, - .ntmp =3D 1, - .tmp =3D { TCG_REG_TMP }, -}; - -static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - MemOp opc =3D get_memop(lb->oi); - - if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { - return false; - } - - tcg_out_ld_helper_args(s, lb, &ldst_helper_param); - tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); - tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); - - tcg_out_goto(s, COND_AL, lb->raddr); - return true; -} - -static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - MemOp opc =3D get_memop(lb->oi); - - if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { - return false; - } - - tcg_out_st_helper_args(s, lb, &ldst_helper_param); - - /* Tail-call to the helper, which will return to the fast path. */ - tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); - return true; -} - -/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ -#define MIN_TLB_MASK_TABLE_OFS -256 - -static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, - TCGReg addr, MemOpIdx oi, bool = is_ld) -{ - TCGLabelQemuLdst *ldst =3D NULL; - MemOp opc =3D get_memop(oi); - unsigned a_mask; - - if (tcg_use_softmmu) { - *h =3D (HostAddress){ - .cond =3D COND_AL, - .base =3D addr, - .index =3D TCG_REG_R1, - .index_scratch =3D true, - }; - } else { - *h =3D (HostAddress){ - .cond =3D COND_AL, - .base =3D addr, - .index =3D guest_base ? TCG_REG_GUEST_BASE : -1, - .index_scratch =3D false, - }; - } - - h->aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); - a_mask =3D (1 << h->aa.align) - 1; - - if (tcg_use_softmmu) { - int mem_index =3D get_mmuidx(oi); - int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write); - int fast_off =3D tlb_mask_table_ofs(s, mem_index); - unsigned s_mask =3D (1 << (opc & MO_SIZE)) - 1; - TCGReg t_addr; - - ldst =3D new_ldst_label(s); - ldst->is_ld =3D is_ld; - ldst->oi =3D oi; - ldst->addr_reg =3D addr; - - /* Load CPUTLBDescFast.{mask,table} into {r0,r1}. */ - QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); - QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 4); - tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); - - /* Extract the tlb index from the address into R0. */ - tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, add= r, - SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BIT= S)); - - /* - * Add the tlb_table pointer, creating the CPUTLBEntry address in = R1. - * Load the tlb comparator into R2 and the fast path addend into R= 1. - */ - if (cmp_off =3D=3D 0) { - tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); - } else { - tcg_out_dat_reg(s, COND_AL, ARITH_ADD, - TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); - tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); - } - - /* Load the tlb addend. */ - tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, - offsetof(CPUTLBEntry, addend)); - - /* - * Check alignment, check comparators. - * Do this in 2-4 insns. Use MOVW for v7, if possible, - * to reduce the number of sequential conditional instructions. - * Almost all guests have at least 4k pages, which means that we n= eed - * to clear at least 9 bits even for an 8-byte memory, which means= it - * isn't worth checking for an immediate operand for BIC. - * - * For unaligned accesses, test the page of the last unit of align= ment. - * This leaves the least significant alignment bits unchanged, and= of - * course must be zero. - */ - t_addr =3D addr; - if (a_mask < s_mask) { - t_addr =3D TCG_REG_R0; - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, - addr, s_mask - a_mask); - } - if (use_armv7_instructions && TARGET_PAGE_BITS <=3D 16) { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(TARGET_PAGE_MASK | a= _mask)); - tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, - t_addr, TCG_REG_TMP, 0); - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, - TCG_REG_R2, TCG_REG_TMP, 0); - } else { - if (a_mask) { - tcg_debug_assert(a_mask <=3D 0xff); - tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); - } - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, - SHIFT_IMM_LSR(TARGET_PAGE_BITS)); - tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, - 0, TCG_REG_R2, TCG_REG_TMP, - SHIFT_IMM_LSL(TARGET_PAGE_BITS)); - } - } else if (a_mask) { - ldst =3D new_ldst_label(s); - ldst->is_ld =3D is_ld; - ldst->oi =3D oi; - ldst->addr_reg =3D addr; - - /* We are expecting alignment to max out at 7 */ - tcg_debug_assert(a_mask <=3D 0xff); - /* tst addr, #mask */ - tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask); - } - - return ldst; -} - -static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, - TCGReg datahi, HostAddress h) -{ - TCGReg base; - - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); - - switch (opc & MO_SSIZE) { - case MO_UB: - if (h.index < 0) { - tcg_out_ld8_12(s, h.cond, datalo, h.base, 0); - } else { - tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index); - } - break; - case MO_SB: - if (h.index < 0) { - tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0); - } else { - tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index); - } - break; - case MO_UW: - if (h.index < 0) { - tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0); - } else { - tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index); - } - break; - case MO_SW: - if (h.index < 0) { - tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0); - } else { - tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index); - } - break; - case MO_UL: - if (h.index < 0) { - tcg_out_ld32_12(s, h.cond, datalo, h.base, 0); - } else { - tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index); - } - break; - case MO_UQ: - /* We used pair allocation for datalo, so already should be aligne= d. */ - tcg_debug_assert((datalo & 1) =3D=3D 0); - tcg_debug_assert(datahi =3D=3D datalo + 1); - /* LDRD requires alignment; double-check that. */ - if (memop_alignment_bits(opc) >=3D MO_64) { - if (h.index < 0) { - tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); - break; - } - /* - * Rm (the second address op) must not overlap Rt or Rt + 1. - * Since datalo is aligned, we can simplify the test via align= ment. - * Flip the two address arguments if that works. - */ - if ((h.index & ~1) !=3D datalo) { - tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index); - break; - } - if ((h.base & ~1) !=3D datalo) { - tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base); - break; - } - } - if (h.index < 0) { - base =3D h.base; - if (datalo =3D=3D h.base) { - tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base); - base =3D TCG_REG_TMP; - } - } else if (h.index_scratch) { - tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base); - tcg_out_ld32_12(s, h.cond, datahi, h.index, 4); - break; - } else { - tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, - h.base, h.index, SHIFT_IMM_LSL(0)); - base =3D TCG_REG_TMP; - } - tcg_out_ld32_12(s, h.cond, datalo, base, 0); - tcg_out_ld32_12(s, h.cond, datahi, base, 4); - break; - default: - g_assert_not_reached(); - } -} - -static void tgen_qemu_ld(TCGContext *s, TCGType type, TCGReg data, - TCGReg addr, MemOpIdx oi) -{ - MemOp opc =3D get_memop(oi); - TCGLabelQemuLdst *ldst; - HostAddress h; - - ldst =3D prepare_host_addr(s, &h, addr, oi, true); - if (ldst) { - ldst->type =3D type; - ldst->datalo_reg =3D data; - ldst->datahi_reg =3D -1; - - /* - * This a conditional BL only to load a pointer within this - * opcode into LR for the slow path. We will not be using - * the value for a tail call. - */ - ldst->label_ptr[0] =3D s->code_ptr; - tcg_out_bl_imm(s, COND_NE, 0); - } - - tcg_out_qemu_ld_direct(s, opc, data, -1, h); - - if (ldst) { - ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); - } -} - -static const TCGOutOpQemuLdSt outop_qemu_ld =3D { - .base.static_constraint =3D C_O1_I1(r, q), - .out =3D tgen_qemu_ld, -}; - -static void tgen_qemu_ld2(TCGContext *s, TCGType type, TCGReg datalo, - TCGReg datahi, TCGReg addr, MemOpIdx oi) -{ - MemOp opc =3D get_memop(oi); - TCGLabelQemuLdst *ldst; - HostAddress h; - - ldst =3D prepare_host_addr(s, &h, addr, oi, true); - if (ldst) { - ldst->type =3D type; - ldst->datalo_reg =3D datalo; - ldst->datahi_reg =3D datahi; - - /* - * This a conditional BL only to load a pointer within this - * opcode into LR for the slow path. We will not be using - * the value for a tail call. - */ - ldst->label_ptr[0] =3D s->code_ptr; - tcg_out_bl_imm(s, COND_NE, 0); - } - - tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); - - if (ldst) { - ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); - } -} - -static const TCGOutOpQemuLdSt2 outop_qemu_ld2 =3D { - .base.static_constraint =3D C_O2_I1(e, p, q), - .out =3D tgen_qemu_ld2, -}; - -static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, - TCGReg datahi, HostAddress h) -{ - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); - - switch (opc & MO_SIZE) { - case MO_8: - if (h.index < 0) { - tcg_out_st8_12(s, h.cond, datalo, h.base, 0); - } else { - tcg_out_st8_r(s, h.cond, datalo, h.base, h.index); - } - break; - case MO_16: - if (h.index < 0) { - tcg_out_st16_8(s, h.cond, datalo, h.base, 0); - } else { - tcg_out_st16_r(s, h.cond, datalo, h.base, h.index); - } - break; - case MO_32: - if (h.index < 0) { - tcg_out_st32_12(s, h.cond, datalo, h.base, 0); - } else { - tcg_out_st32_r(s, h.cond, datalo, h.base, h.index); - } - break; - case MO_64: - /* We used pair allocation for datalo, so already should be aligne= d. */ - tcg_debug_assert((datalo & 1) =3D=3D 0); - tcg_debug_assert(datahi =3D=3D datalo + 1); - /* STRD requires alignment; double-check that. */ - if (memop_alignment_bits(opc) >=3D MO_64) { - if (h.index < 0) { - tcg_out_strd_8(s, h.cond, datalo, h.base, 0); - } else { - tcg_out_strd_r(s, h.cond, datalo, h.base, h.index); - } - } else if (h.index < 0) { - tcg_out_st32_12(s, h.cond, datalo, h.base, 0); - tcg_out_st32_12(s, h.cond, datahi, h.base, 4); - } else if (h.index_scratch) { - tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base); - tcg_out_st32_12(s, h.cond, datahi, h.index, 4); - } else { - tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, - h.base, h.index, SHIFT_IMM_LSL(0)); - tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0); - tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4); - } - break; - default: - g_assert_not_reached(); - } -} - -static void tgen_qemu_st(TCGContext *s, TCGType type, TCGReg data, - TCGReg addr, MemOpIdx oi) -{ - MemOp opc =3D get_memop(oi); - TCGLabelQemuLdst *ldst; - HostAddress h; - - ldst =3D prepare_host_addr(s, &h, addr, oi, false); - if (ldst) { - ldst->type =3D type; - ldst->datalo_reg =3D data; - ldst->datahi_reg =3D -1; - - h.cond =3D COND_EQ; - tcg_out_qemu_st_direct(s, opc, data, -1, h); - - /* The conditional call is last, as we're going to return here. */ - ldst->label_ptr[0] =3D s->code_ptr; - tcg_out_bl_imm(s, COND_NE, 0); - ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); - } else { - tcg_out_qemu_st_direct(s, opc, data, -1, h); - } -} - -static const TCGOutOpQemuLdSt outop_qemu_st =3D { - .base.static_constraint =3D C_O0_I2(q, q), - .out =3D tgen_qemu_st, -}; - -static void tgen_qemu_st2(TCGContext *s, TCGType type, TCGReg datalo, - TCGReg datahi, TCGReg addr, MemOpIdx oi) -{ - MemOp opc =3D get_memop(oi); - TCGLabelQemuLdst *ldst; - HostAddress h; - - ldst =3D prepare_host_addr(s, &h, addr, oi, false); - if (ldst) { - ldst->type =3D type; - ldst->datalo_reg =3D datalo; - ldst->datahi_reg =3D datahi; - - h.cond =3D COND_EQ; - tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); - - /* The conditional call is last, as we're going to return here. */ - ldst->label_ptr[0] =3D s->code_ptr; - tcg_out_bl_imm(s, COND_NE, 0); - ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); - } else { - tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); - } -} - -static const TCGOutOpQemuLdSt2 outop_qemu_st2 =3D { - .base.static_constraint =3D C_O0_I3(Q, p, q), - .out =3D tgen_qemu_st2, -}; - -static void tcg_out_epilogue(TCGContext *s); - -static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) -{ - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, arg); - tcg_out_epilogue(s); -} - -static void tcg_out_goto_tb(TCGContext *s, int which) -{ - uintptr_t i_addr; - intptr_t i_disp; - - /* Direct branch will be patched by tb_target_set_jmp_target. */ - set_jmp_insn_offset(s, which); - tcg_out32(s, INSN_NOP); - - /* When branch is out of range, fall through to indirect. */ - i_addr =3D get_jmp_target_addr(s, which); - i_disp =3D tcg_pcrel_diff(s, (void *)i_addr) - 8; - tcg_debug_assert(i_disp < 0); - if (i_disp >=3D -0xfff) { - tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, i_disp); - } else { - /* - * The TB is close, but outside the 12 bits addressable by - * the load. We can extend this to 20 bits with a sub of a - * shifted immediate from pc. - */ - int h =3D -i_disp; - int l =3D -(h & 0xfff); - - h =3D encode_imm_nofail(h + l); - tcg_out_dat_imm(s, COND_AL, ARITH_SUB, TCG_REG_R0, TCG_REG_PC, h); - tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, l); - } - set_jmp_reset_offset(s, which); -} - -static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0) -{ - tcg_out_b_reg(s, COND_AL, a0); -} - -void tb_target_set_jmp_target(const TranslationBlock *tb, int n, - uintptr_t jmp_rx, uintptr_t jmp_rw) -{ - uintptr_t addr =3D tb->jmp_target_addr[n]; - ptrdiff_t offset =3D addr - (jmp_rx + 8); - tcg_insn_unit insn; - - /* Either directly branch, or fall through to indirect branch. */ - if (offset =3D=3D sextract64(offset, 0, 26)) { - /* B */ - insn =3D deposit32((COND_AL << 28) | INSN_B, 0, 24, offset >> 2); - } else { - insn =3D INSN_NOP; - } - - qatomic_set((uint32_t *)jmp_rw, insn); - flush_idcache_range(jmp_rx, jmp_rw, 4); -} - - -static void tgen_add(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_ADD, a0, a1, a2, SHIFT_IMM_LSL(0)); -} - -static void tgen_addi(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, tcg_target_long a2) -{ - tcg_out_dat_IN(s, COND_AL, ARITH_ADD, ARITH_SUB, a0, a1, a2); -} - -static const TCGOutOpBinary outop_add =3D { - .base.static_constraint =3D C_O1_I2(r, r, rIN), - .out_rrr =3D tgen_add, - .out_rri =3D tgen_addi, -}; - -static void tgen_addco(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_ADD | TO_CPSR, - a0, a1, a2, SHIFT_IMM_LSL(0)); -} - -static void tgen_addco_imm(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, tcg_target_long a2) -{ - tcg_out_dat_IN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR, - a0, a1, a2); -} - -static const TCGOutOpBinary outop_addco =3D { - .base.static_constraint =3D C_O1_I2(r, r, rIN), - .out_rrr =3D tgen_addco, - .out_rri =3D tgen_addco_imm, -}; - -static void tgen_addci(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_ADC, a0, a1, a2, SHIFT_IMM_LSL(0)); -} - -static void tgen_addci_imm(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, tcg_target_long a2) -{ - tcg_out_dat_IK(s, COND_AL, ARITH_ADC, ARITH_SBC, a0, a1, a2); -} - -static const TCGOutOpAddSubCarry outop_addci =3D { - .base.static_constraint =3D C_O1_I2(r, r, rIK), - .out_rrr =3D tgen_addci, - .out_rri =3D tgen_addci_imm, -}; - -static void tgen_addcio(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_ADC | TO_CPSR, - a0, a1, a2, SHIFT_IMM_LSL(0)); -} - -static void tgen_addcio_imm(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, tcg_target_long a2) -{ - tcg_out_dat_IK(s, COND_AL, ARITH_ADC | TO_CPSR, ARITH_SBC | TO_CPSR, - a0, a1, a2); -} - -static const TCGOutOpBinary outop_addcio =3D { - .base.static_constraint =3D C_O1_I2(r, r, rIK), - .out_rrr =3D tgen_addcio, - .out_rri =3D tgen_addcio_imm, -}; - -/* Set C to @c; NZVQ all set to 0. */ -static void tcg_out_movi_apsr_c(TCGContext *s, bool c) -{ - int imm12 =3D encode_imm_nofail(c << 29); - tcg_out32(s, (COND_AL << 28) | INSN_MSRI_CPSR | 0x80000 | imm12); -} - -static void tcg_out_set_carry(TCGContext *s) -{ - tcg_out_movi_apsr_c(s, 1); -} - -static void tgen_and(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_AND, a0, a1, a2, SHIFT_IMM_LSL(0)); -} - -static void tgen_andi(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, tcg_target_long a2) -{ - tcg_out_dat_IK(s, COND_AL, ARITH_AND, ARITH_BIC, a0, a1, a2); -} - -static const TCGOutOpBinary outop_and =3D { - .base.static_constraint =3D C_O1_I2(r, r, rIK), - .out_rrr =3D tgen_and, - .out_rri =3D tgen_andi, -}; - -static void tgen_andc(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_BIC, a0, a1, a2, SHIFT_IMM_LSL(0)); -} - -static const TCGOutOpBinary outop_andc =3D { - .base.static_constraint =3D C_O1_I2(r, r, r), - .out_rrr =3D tgen_andc, -}; - -static void tgen_clz(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); - tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); - tcg_out_mov_reg(s, COND_EQ, a0, a2); -} - -static void tgen_clzi(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, tcg_target_long a2) -{ - if (a2 =3D=3D 32) { - tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); - } else { - tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); - tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); - tcg_out_movi32(s, COND_EQ, a0, a2); - } -} - -static const TCGOutOpBinary outop_clz =3D { - .base.static_constraint =3D C_O1_I2(r, r, rIK), - .out_rrr =3D tgen_clz, - .out_rri =3D tgen_clzi, -}; - -static const TCGOutOpUnary outop_ctpop =3D { - .base.static_constraint =3D C_NotImplemented, -}; - -static void tgen_ctz(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, a1, 0); - tgen_clz(s, TCG_TYPE_I32, a0, TCG_REG_TMP, a2); -} - -static void tgen_ctzi(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, tcg_target_long a2) -{ - tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, a1, 0); - tgen_clzi(s, TCG_TYPE_I32, a0, TCG_REG_TMP, a2); -} - -static TCGConstraintSetIndex cset_ctz(TCGType type, unsigned flags) -{ - return use_armv7_instructions ? C_O1_I2(r, r, rIK) : C_NotImplemented; -} - -static const TCGOutOpBinary outop_ctz =3D { - .base.static_constraint =3D C_Dynamic, - .base.dynamic_constraint =3D cset_ctz, - .out_rrr =3D tgen_ctz, - .out_rri =3D tgen_ctzi, -}; - -static TCGConstraintSetIndex cset_idiv(TCGType type, unsigned flags) -{ - return use_idiv_instructions ? C_O1_I2(r, r, r) : C_NotImplemented; -} - -static void tgen_divs(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - /* sdiv */ - tcg_out32(s, 0x0710f010 | (COND_AL << 28) | (a0 << 16) | a1 | (a2 << 8= )); -} - -static const TCGOutOpBinary outop_divs =3D { - .base.static_constraint =3D C_Dynamic, - .base.dynamic_constraint =3D cset_idiv, - .out_rrr =3D tgen_divs, -}; - -static const TCGOutOpDivRem outop_divs2 =3D { - .base.static_constraint =3D C_NotImplemented, -}; - -static void tgen_divu(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - /* udiv */ - tcg_out32(s, 0x0730f010 | (COND_AL << 28) | (a0 << 16) | a1 | (a2 << 8= )); -} - -static const TCGOutOpBinary outop_divu =3D { - .base.static_constraint =3D C_Dynamic, - .base.dynamic_constraint =3D cset_idiv, - .out_rrr =3D tgen_divu, -}; - -static const TCGOutOpDivRem outop_divu2 =3D { - .base.static_constraint =3D C_NotImplemented, -}; - -static const TCGOutOpBinary outop_eqv =3D { - .base.static_constraint =3D C_NotImplemented, -}; - -static void tgen_mul(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - /* mul */ - tcg_out32(s, (COND_AL << 28) | 0x90 | (a0 << 16) | (a1 << 8) | a2); -} - -static const TCGOutOpBinary outop_mul =3D { - .base.static_constraint =3D C_O1_I2(r, r, r), - .out_rrr =3D tgen_mul, -}; - -static void tgen_muls2(TCGContext *s, TCGType type, - TCGReg rd0, TCGReg rd1, TCGReg rn, TCGReg rm) -{ - /* smull */ - tcg_out32(s, (COND_AL << 28) | 0x00c00090 | - (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); -} - -static const TCGOutOpMul2 outop_muls2 =3D { - .base.static_constraint =3D C_O2_I2(r, r, r, r), - .out_rrrr =3D tgen_muls2, -}; - -static const TCGOutOpBinary outop_mulsh =3D { - .base.static_constraint =3D C_NotImplemented, -}; - -static void tgen_mulu2(TCGContext *s, TCGType type, - TCGReg rd0, TCGReg rd1, TCGReg rn, TCGReg rm) -{ - /* umull */ - tcg_out32(s, (COND_AL << 28) | 0x00800090 | - (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); -} - -static const TCGOutOpMul2 outop_mulu2 =3D { - .base.static_constraint =3D C_O2_I2(r, r, r, r), - .out_rrrr =3D tgen_mulu2, -}; - -static const TCGOutOpBinary outop_muluh =3D { - .base.static_constraint =3D C_NotImplemented, -}; - -static const TCGOutOpBinary outop_nand =3D { - .base.static_constraint =3D C_NotImplemented, -}; - -static const TCGOutOpBinary outop_nor =3D { - .base.static_constraint =3D C_NotImplemented, -}; - -static void tgen_or(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_ORR, a0, a1, a2, SHIFT_IMM_LSL(0)); -} - -static void tgen_ori(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, tcg_target_long a2) -{ - tcg_out_dat_imm(s, COND_AL, ARITH_ORR, a0, a1, encode_imm_nofail(a2)); -} - -static const TCGOutOpBinary outop_or =3D { - .base.static_constraint =3D C_O1_I2(r, r, rI), - .out_rrr =3D tgen_or, - .out_rri =3D tgen_ori, -}; - -static const TCGOutOpBinary outop_orc =3D { - .base.static_constraint =3D C_NotImplemented, -}; - -static const TCGOutOpBinary outop_rems =3D { - .base.static_constraint =3D C_NotImplemented, -}; - -static const TCGOutOpBinary outop_remu =3D { - .base.static_constraint =3D C_NotImplemented, -}; - -static const TCGOutOpBinary outop_rotl =3D { - .base.static_constraint =3D C_NotImplemented, -}; - -static void tgen_rotr(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_ROR(a2)); -} - -static void tgen_rotri(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, tcg_target_long a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_IMM_ROR(a2 & 0= x1f)); -} - -static const TCGOutOpBinary outop_rotr =3D { - .base.static_constraint =3D C_O1_I2(r, r, ri), - .out_rrr =3D tgen_rotr, - .out_rri =3D tgen_rotri, -}; - -static void tgen_sar(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_ASR(a2)); -} - -static void tgen_sari(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, tcg_target_long a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, - SHIFT_IMM_ASR(a2 & 0x1f)); -} - -static const TCGOutOpBinary outop_sar =3D { - .base.static_constraint =3D C_O1_I2(r, r, ri), - .out_rrr =3D tgen_sar, - .out_rri =3D tgen_sari, -}; - -static void tgen_shl(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_LSL(a2)); -} - -static void tgen_shli(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, tcg_target_long a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, - SHIFT_IMM_LSL(a2 & 0x1f)); -} - -static const TCGOutOpBinary outop_shl =3D { - .base.static_constraint =3D C_O1_I2(r, r, ri), - .out_rrr =3D tgen_shl, - .out_rri =3D tgen_shli, -}; - -static void tgen_shr(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_LSR(a2)); -} - -static void tgen_shri(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, tcg_target_long a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, - SHIFT_IMM_LSR(a2 & 0x1f)); -} - -static const TCGOutOpBinary outop_shr =3D { - .base.static_constraint =3D C_O1_I2(r, r, ri), - .out_rrr =3D tgen_shr, - .out_rri =3D tgen_shri, -}; - -static void tgen_sub(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_SUB, a0, a1, a2, SHIFT_IMM_LSL(0)); -} - -static void tgen_subfi(TCGContext *s, TCGType type, - TCGReg a0, tcg_target_long a1, TCGReg a2) -{ - tcg_out_dat_imm(s, COND_AL, ARITH_RSB, a0, a2, encode_imm_nofail(a1)); -} - -static const TCGOutOpSubtract outop_sub =3D { - .base.static_constraint =3D C_O1_I2(r, rI, r), - .out_rrr =3D tgen_sub, - .out_rir =3D tgen_subfi, -}; - -static void tgen_subbo_rrr(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_SUB | TO_CPSR, - a0, a1, a2, SHIFT_IMM_LSL(0)); -} - -static void tgen_subbo_rri(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, tcg_target_long a2) -{ - tcg_out_dat_IN(s, COND_AL, ARITH_SUB | TO_CPSR, ARITH_ADD | TO_CPSR, - a0, a1, a2); -} - -static void tgen_subbo_rir(TCGContext *s, TCGType type, - TCGReg a0, tcg_target_long a1, TCGReg a2) -{ - tcg_out_dat_imm(s, COND_AL, ARITH_RSB | TO_CPSR, - a0, a2, encode_imm_nofail(a1)); -} - -static void tgen_subbo_rii(TCGContext *s, TCGType type, - TCGReg a0, tcg_target_long a1, tcg_target_long = a2) -{ - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, a2); - tgen_subbo_rir(s, TCG_TYPE_I32, a0, a1, TCG_REG_TMP); -} - -static const TCGOutOpAddSubCarry outop_subbo =3D { - .base.static_constraint =3D C_O1_I2(r, rI, rIN), - .out_rrr =3D tgen_subbo_rrr, - .out_rri =3D tgen_subbo_rri, - .out_rir =3D tgen_subbo_rir, - .out_rii =3D tgen_subbo_rii, -}; - -static void tgen_subbi_rrr(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_SBC, - a0, a1, a2, SHIFT_IMM_LSL(0)); -} - -static void tgen_subbi_rri(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, tcg_target_long a2) -{ - tcg_out_dat_IK(s, COND_AL, ARITH_SBC, ARITH_ADC, a0, a1, a2); -} - -static void tgen_subbi_rir(TCGContext *s, TCGType type, - TCGReg a0, tcg_target_long a1, TCGReg a2) -{ - tcg_out_dat_imm(s, COND_AL, ARITH_RSC, a0, a2, encode_imm_nofail(a1)); -} - -static void tgen_subbi_rii(TCGContext *s, TCGType type, - TCGReg a0, tcg_target_long a1, tcg_target_long = a2) -{ - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, a2); - tgen_subbi_rir(s, TCG_TYPE_I32, a0, a1, TCG_REG_TMP); -} - -static const TCGOutOpAddSubCarry outop_subbi =3D { - .base.static_constraint =3D C_O1_I2(r, rI, rIK), - .out_rrr =3D tgen_subbi_rrr, - .out_rri =3D tgen_subbi_rri, - .out_rir =3D tgen_subbi_rir, - .out_rii =3D tgen_subbi_rii, -}; - -static void tgen_subbio_rrr(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_SBC | TO_CPSR, - a0, a1, a2, SHIFT_IMM_LSL(0)); -} - -static void tgen_subbio_rri(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, tcg_target_long a2) -{ - tcg_out_dat_IK(s, COND_AL, ARITH_SBC | TO_CPSR, ARITH_ADC | TO_CPSR, - a0, a1, a2); -} - -static void tgen_subbio_rir(TCGContext *s, TCGType type, - TCGReg a0, tcg_target_long a1, TCGReg a2) -{ - tcg_out_dat_imm(s, COND_AL, ARITH_RSC | TO_CPSR, - a0, a2, encode_imm_nofail(a1)); -} - -static void tgen_subbio_rii(TCGContext *s, TCGType type, - TCGReg a0, tcg_target_long a1, tcg_target_long= a2) -{ - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, a2); - tgen_subbio_rir(s, TCG_TYPE_I32, a0, a1, TCG_REG_TMP); -} - -static const TCGOutOpAddSubCarry outop_subbio =3D { - .base.static_constraint =3D C_O1_I2(r, rI, rIK), - .out_rrr =3D tgen_subbio_rrr, - .out_rri =3D tgen_subbio_rri, - .out_rir =3D tgen_subbio_rir, - .out_rii =3D tgen_subbio_rii, -}; - -static void tcg_out_set_borrow(TCGContext *s) -{ - tcg_out_movi_apsr_c(s, 0); /* borrow =3D !carry */ -} - -static void tgen_xor(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_EOR, a0, a1, a2, SHIFT_IMM_LSL(0)); -} - -static void tgen_xori(TCGContext *s, TCGType type, - TCGReg a0, TCGReg a1, tcg_target_long a2) -{ - tcg_out_dat_imm(s, COND_AL, ARITH_EOR, a0, a1, encode_imm_nofail(a2)); -} - -static const TCGOutOpBinary outop_xor =3D { - .base.static_constraint =3D C_O1_I2(r, r, rI), - .out_rrr =3D tgen_xor, - .out_rri =3D tgen_xori, -}; - -static void tgen_bswap16(TCGContext *s, TCGType type, - TCGReg rd, TCGReg rn, unsigned flags) -{ - if (flags & TCG_BSWAP_OS) { - /* revsh */ - tcg_out32(s, 0x06ff0fb0 | (COND_AL << 28) | (rd << 12) | rn); - return; - } - - /* rev16 */ - tcg_out32(s, 0x06bf0fb0 | (COND_AL << 28) | (rd << 12) | rn); - if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) =3D=3D TCG_BSWAP_OZ) { - tcg_out_ext16u(s, rd, rd); - } -} - -static const TCGOutOpBswap outop_bswap16 =3D { - .base.static_constraint =3D C_O1_I1(r, r), - .out_rr =3D tgen_bswap16, -}; - -static void tgen_bswap32(TCGContext *s, TCGType type, - TCGReg rd, TCGReg rn, unsigned flags) -{ - /* rev */ - tcg_out32(s, 0x06bf0f30 | (COND_AL << 28) | (rd << 12) | rn); -} - -static const TCGOutOpBswap outop_bswap32 =3D { - .base.static_constraint =3D C_O1_I1(r, r), - .out_rr =3D tgen_bswap32, -}; - -static const TCGOutOpUnary outop_bswap64 =3D { - .base.static_constraint =3D C_NotImplemented, -}; - -static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) -{ - tgen_subfi(s, type, a0, 0, a1); -} - -static const TCGOutOpUnary outop_neg =3D { - .base.static_constraint =3D C_O1_I1(r, r), - .out_rr =3D tgen_neg, -}; - -static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) -{ - tcg_out_dat_reg(s, COND_AL, ARITH_MVN, a0, 0, a1, SHIFT_IMM_LSL(0)); -} - -static const TCGOutOpUnary outop_not =3D { - .base.static_constraint =3D C_O1_I1(r, r), - .out_rr =3D tgen_not, -}; - -static void tgen_brcond(TCGContext *s, TCGType type, TCGCond cond, - TCGReg a0, TCGReg a1, TCGLabel *l) -{ - cond =3D tgen_cmp(s, cond, a0, a1); - tcg_out_goto_label(s, tcg_cond_to_arm_cond[cond], l); -} - -static void tgen_brcondi(TCGContext *s, TCGType type, TCGCond cond, - TCGReg a0, tcg_target_long a1, TCGLabel *l) -{ - cond =3D tgen_cmpi(s, cond, a0, a1); - tcg_out_goto_label(s, tcg_cond_to_arm_cond[cond], l); -} - -static const TCGOutOpBrcond outop_brcond =3D { - .base.static_constraint =3D C_O0_I2(r, rIN), - .out_rr =3D tgen_brcond, - .out_ri =3D tgen_brcondi, -}; - -static void finish_setcond(TCGContext *s, TCGCond cond, TCGReg ret, bool n= eg) -{ - tcg_out_movi32(s, tcg_cond_to_arm_cond[tcg_invert_cond(cond)], ret, 0); - tcg_out_movi32(s, tcg_cond_to_arm_cond[cond], ret, neg ? -1 : 1); -} - -static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - cond =3D tgen_cmp(s, cond, a1, a2); - finish_setcond(s, cond, a0, false); -} - -static void tgen_setcondi(TCGContext *s, TCGType type, TCGCond cond, - TCGReg a0, TCGReg a1, tcg_target_long a2) -{ - cond =3D tgen_cmpi(s, cond, a1, a2); - finish_setcond(s, cond, a0, false); -} - -static const TCGOutOpSetcond outop_setcond =3D { - .base.static_constraint =3D C_O1_I2(r, r, rIN), - .out_rrr =3D tgen_setcond, - .out_rri =3D tgen_setcondi, -}; - -static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, - TCGReg a0, TCGReg a1, TCGReg a2) -{ - cond =3D tgen_cmp(s, cond, a1, a2); - finish_setcond(s, cond, a0, true); -} - -static void tgen_negsetcondi(TCGContext *s, TCGType type, TCGCond cond, - TCGReg a0, TCGReg a1, tcg_target_long a2) -{ - cond =3D tgen_cmpi(s, cond, a1, a2); - finish_setcond(s, cond, a0, true); -} - -static const TCGOutOpSetcond outop_negsetcond =3D { - .base.static_constraint =3D C_O1_I2(r, r, rIN), - .out_rrr =3D tgen_negsetcond, - .out_rri =3D tgen_negsetcondi, -}; - -static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, - TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2, - TCGArg vt, bool const_vt, TCGArg vf, bool consf_v= f) -{ - cond =3D tcg_out_cmp(s, cond, c1, c2, const_c2); - tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[cond], ARITH_MOV, ARITH_MVN, - ret, 0, vt, const_vt); -} - -static const TCGOutOpMovcond outop_movcond =3D { - .base.static_constraint =3D C_O1_I4(r, r, rIN, rIK, 0), - .out =3D tgen_movcond, -}; - -static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, - TCGArg bl, bool const_bl, TCGArg bh, bool const_b= h, - TCGLabel *l) -{ - cond =3D tcg_out_cmp2(s, cond, al, ah, bl, const_bl, bh, const_bh); - tcg_out_goto_label(s, tcg_cond_to_arm_cond[cond], l); -} - -static const TCGOutOpBrcond2 outop_brcond2 =3D { - .base.static_constraint =3D C_O0_I4(r, r, rI, rI), - .out =3D tgen_brcond2, -}; - -static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg al, TCGReg ah, - TCGArg bl, bool const_bl, - TCGArg bh, bool const_bh) -{ - cond =3D tcg_out_cmp2(s, cond, al, ah, bl, const_bl, bh, const_bh); - finish_setcond(s, cond, ret, false); -} - -static const TCGOutOpSetcond2 outop_setcond2 =3D { - .base.static_constraint =3D C_O1_I4(r, r, r, rI, rI), - .out =3D tgen_setcond2, -}; - -static void tgen_extract2(TCGContext *s, TCGType type, TCGReg a0, - TCGReg a1, TCGReg a2, unsigned shr) -{ - /* We can do extract2 in 2 insns, vs the 3 required otherwise. */ - tgen_shli(s, TCG_TYPE_I32, TCG_REG_TMP, a2, 32 - shr); - tcg_out_dat_reg(s, COND_AL, ARITH_ORR, a0, TCG_REG_TMP, - a1, SHIFT_IMM_LSR(shr)); -} - -static const TCGOutOpExtract2 outop_extract2 =3D { - .base.static_constraint =3D C_O1_I2(r, r, r), - .out_rrr =3D tgen_extract2, -}; - -static void tgen_ld8u(TCGContext *s, TCGType type, TCGReg rd, - TCGReg rn, ptrdiff_t offset) -{ - if (offset > 0xfff || offset < -0xfff) { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, offset); - tcg_out_ld8_r(s, COND_AL, rd, rn, TCG_REG_TMP); - } else { - tcg_out_ld8_12(s, COND_AL, rd, rn, offset); - } -} - -static const TCGOutOpLoad outop_ld8u =3D { - .base.static_constraint =3D C_O1_I1(r, r), - .out =3D tgen_ld8u, -}; - -static void tgen_ld8s(TCGContext *s, TCGType type, TCGReg rd, - TCGReg rn, ptrdiff_t offset) -{ - if (offset > 0xff || offset < -0xff) { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, offset); - tcg_out_ld8s_r(s, COND_AL, rd, rn, TCG_REG_TMP); - } else { - tcg_out_ld8s_8(s, COND_AL, rd, rn, offset); - } -} - -static const TCGOutOpLoad outop_ld8s =3D { - .base.static_constraint =3D C_O1_I1(r, r), - .out =3D tgen_ld8s, -}; - -static void tgen_ld16u(TCGContext *s, TCGType type, TCGReg rd, - TCGReg rn, ptrdiff_t offset) -{ - if (offset > 0xff || offset < -0xff) { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, offset); - tcg_out_ld16u_r(s, COND_AL, rd, rn, TCG_REG_TMP); - } else { - tcg_out_ld16u_8(s, COND_AL, rd, rn, offset); - } -} - -static const TCGOutOpLoad outop_ld16u =3D { - .base.static_constraint =3D C_O1_I1(r, r), - .out =3D tgen_ld16u, -}; - -static void tgen_ld16s(TCGContext *s, TCGType type, TCGReg rd, - TCGReg rn, ptrdiff_t offset) -{ - if (offset > 0xff || offset < -0xff) { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, offset); - tcg_out_ld16s_r(s, COND_AL, rd, rn, TCG_REG_TMP); - } else { - tcg_out_ld16s_8(s, COND_AL, rd, rn, offset); - } -} - -static const TCGOutOpLoad outop_ld16s =3D { - .base.static_constraint =3D C_O1_I1(r, r), - .out =3D tgen_ld16s, -}; - -static void tgen_st8(TCGContext *s, TCGType type, TCGReg rd, - TCGReg rn, ptrdiff_t offset) -{ - if (offset > 0xfff || offset < -0xfff) { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, offset); - tcg_out_st8_r(s, COND_AL, rd, rn, TCG_REG_TMP); - } else { - tcg_out_st8_12(s, COND_AL, rd, rn, offset); - } -} - -static const TCGOutOpStore outop_st8 =3D { - .base.static_constraint =3D C_O0_I2(r, r), - .out_r =3D tgen_st8, -}; - -static void tgen_st16(TCGContext *s, TCGType type, TCGReg rd, - TCGReg rn, ptrdiff_t offset) -{ - if (offset > 0xff || offset < -0xff) { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, offset); - tcg_out_st16_r(s, COND_AL, rd, rn, TCG_REG_TMP); - } else { - tcg_out_st16_8(s, COND_AL, rd, rn, offset); - } -} - -static const TCGOutOpStore outop_st16 =3D { - .base.static_constraint =3D C_O0_I2(r, r), - .out_r =3D tgen_st16, -}; - -static const TCGOutOpStore outop_st =3D { - .base.static_constraint =3D C_O0_I2(r, r), - .out_r =3D tcg_out_st, -}; - -static TCGConstraintSetIndex -tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) -{ - switch (op) { - case INDEX_op_st_vec: - return C_O0_I2(w, r); - case INDEX_op_ld_vec: - case INDEX_op_dupm_vec: - return C_O1_I1(w, r); - case INDEX_op_dup_vec: - return C_O1_I1(w, wr); - case INDEX_op_abs_vec: - case INDEX_op_neg_vec: - case INDEX_op_not_vec: - case INDEX_op_shli_vec: - case INDEX_op_shri_vec: - case INDEX_op_sari_vec: - return C_O1_I1(w, w); - case INDEX_op_dup2_vec: - case INDEX_op_add_vec: - case INDEX_op_mul_vec: - case INDEX_op_smax_vec: - case INDEX_op_smin_vec: - case INDEX_op_ssadd_vec: - case INDEX_op_sssub_vec: - case INDEX_op_sub_vec: - case INDEX_op_umax_vec: - case INDEX_op_umin_vec: - case INDEX_op_usadd_vec: - case INDEX_op_ussub_vec: - case INDEX_op_xor_vec: - case INDEX_op_arm_sshl_vec: - case INDEX_op_arm_ushl_vec: - return C_O1_I2(w, w, w); - case INDEX_op_arm_sli_vec: - return C_O1_I2(w, 0, w); - case INDEX_op_or_vec: - case INDEX_op_andc_vec: - return C_O1_I2(w, w, wO); - case INDEX_op_and_vec: - case INDEX_op_orc_vec: - return C_O1_I2(w, w, wV); - case INDEX_op_cmp_vec: - return C_O1_I2(w, w, wZ); - case INDEX_op_bitsel_vec: - return C_O1_I3(w, w, w, w); - default: - return C_NotImplemented; - } -} - -static void tcg_target_init(TCGContext *s) -{ - /* - * Only probe for the platform and capabilities if we haven't already - * determined maximum values at compile time. - */ -#if !defined(use_idiv_instructions) || !defined(use_neon_instructions) - { - unsigned long hwcap =3D qemu_getauxval(AT_HWCAP); -#ifndef use_idiv_instructions - use_idiv_instructions =3D (hwcap & HWCAP_ARM_IDIVA) !=3D 0; -#endif -#ifndef use_neon_instructions - use_neon_instructions =3D (hwcap & HWCAP_ARM_NEON) !=3D 0; -#endif - } -#endif - - if (__ARM_ARCH < 7) { - const char *pl =3D (const char *)qemu_getauxval(AT_PLATFORM); - if (pl !=3D NULL && pl[0] =3D=3D 'v' && pl[1] >=3D '4' && pl[1] <= =3D '9') { - arm_arch =3D pl[1] - '0'; - } - - if (arm_arch < 6) { - error_report("TCG: ARMv%d is unsupported; exiting", arm_arch); - exit(EXIT_FAILURE); - } - } - - tcg_target_available_regs[TCG_TYPE_I32] =3D ALL_GENERAL_REGS; - - tcg_target_call_clobber_regs =3D 0; - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); - - if (use_neon_instructions) { - tcg_target_available_regs[TCG_TYPE_V64] =3D ALL_VECTOR_REGS; - tcg_target_available_regs[TCG_TYPE_V128] =3D ALL_VECTOR_REGS; - - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15); - } - - s->reserved_regs =3D 0; - tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); - tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); -} - -static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) -{ - switch (type) { - case TCG_TYPE_I32: - tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); - return; - case TCG_TYPE_V64: - /* regs 1; size 8; align 8 */ - tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); - return; - case TCG_TYPE_V128: - /* - * We have only 8-byte alignment for the stack per the ABI. - * Rather than dynamically re-align the stack, it's easier - * to simply not request alignment beyond that. So: - * regs 2; size 8; align 8 - */ - tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2); - return; - default: - g_assert_not_reached(); - } -} - -static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) -{ - switch (type) { - case TCG_TYPE_I32: - tcg_out_st32(s, COND_AL, arg, arg1, arg2); - return; - case TCG_TYPE_V64: - /* regs 1; size 8; align 8 */ - tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); - return; - case TCG_TYPE_V128: - /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */ - tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2); - return; - default: - g_assert_not_reached(); - } -} - -static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) -{ - return false; -} - -static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) -{ - if (ret =3D=3D arg) { - return true; - } - switch (type) { - case TCG_TYPE_I32: - if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) { - tcg_out_mov_reg(s, COND_AL, ret, arg); - return true; - } - return false; - - case TCG_TYPE_V64: - case TCG_TYPE_V128: - /* "VMOV D,N" is an alias for "VORR D,N,N". */ - tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg); - return true; - - default: - g_assert_not_reached(); - } -} - -static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) -{ - tcg_debug_assert(type =3D=3D TCG_TYPE_I32); - tcg_debug_assert(ret < TCG_REG_Q0); - tcg_out_movi32(s, COND_AL, ret, arg); -} - -static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) -{ - return false; -} - -static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, - tcg_target_long imm) -{ - int enc, opc =3D ARITH_ADD; - - /* All of the easiest immediates to encode are positive. */ - if (imm < 0) { - imm =3D -imm; - opc =3D ARITH_SUB; - } - enc =3D encode_imm(imm); - if (enc >=3D 0) { - tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); - } else { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); - tcg_out_dat_reg(s, COND_AL, opc, rd, rs, - TCG_REG_TMP, SHIFT_IMM_LSL(0)); - } -} - -/* Type is always V128, with I64 elements. */ -static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg r= h) -{ - /* Move high element into place first. */ - /* VMOV Dd+1, Ds */ - tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh); - /* Move low element into place; tcg_out_mov will check for nop. */ - tcg_out_mov(s, TCG_TYPE_V64, rd, rl); -} - -static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, - TCGReg rd, TCGReg rs) -{ - int q =3D type - TCG_TYPE_V64; - - if (vece =3D=3D MO_64) { - if (type =3D=3D TCG_TYPE_V128) { - tcg_out_dup2_vec(s, rd, rs, rs); - } else { - tcg_out_mov(s, TCG_TYPE_V64, rd, rs); - } - } else if (rs < TCG_REG_Q0) { - int b =3D (vece =3D=3D MO_8); - int e =3D (vece =3D=3D MO_16); - tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) | - encode_vn(rd) | (rs << 12)); - } else { - int imm4 =3D 1 << vece; - tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) | - encode_vd(rd) | encode_vm(rs)); - } - return true; -} - -static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, - TCGReg rd, TCGReg base, intptr_t offset) -{ - if (vece =3D=3D MO_64) { - tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset); - if (type =3D=3D TCG_TYPE_V128) { - tcg_out_dup2_vec(s, rd, rd, rd); - } - } else { - int q =3D type - TCG_TYPE_V64; - tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5), - rd, base, offset); - } - return true; -} - -static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, - TCGReg rd, int64_t v64) -{ - int q =3D type - TCG_TYPE_V64; - int cmode, imm8, i; - - /* Test all bytes equal first. */ - if (vece =3D=3D MO_8) { - tcg_out_vmovi(s, rd, q, 0, 0xe, v64); - return; - } - - /* - * Test all bytes 0x00 or 0xff second. This can match cases that - * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. - */ - for (i =3D imm8 =3D 0; i < 8; i++) { - uint8_t byte =3D v64 >> (i * 8); - if (byte =3D=3D 0xff) { - imm8 |=3D 1 << i; - } else if (byte !=3D 0) { - goto fail_bytes; - } - } - tcg_out_vmovi(s, rd, q, 1, 0xe, imm8); - return; - fail_bytes: - - /* - * Tests for various replications. For each element width, if we - * cannot find an expansion there's no point checking a larger - * width because we already know by replication it cannot match. - */ - if (vece =3D=3D MO_16) { - uint16_t v16 =3D v64; - - if (is_shimm16(v16, &cmode, &imm8)) { - tcg_out_vmovi(s, rd, q, 0, cmode, imm8); - return; - } - if (is_shimm16(~v16, &cmode, &imm8)) { - tcg_out_vmovi(s, rd, q, 1, cmode, imm8); - return; - } - - /* - * Otherwise, all remaining constants can be loaded in two insns: - * rd =3D v16 & 0xff, rd |=3D v16 & 0xff00. - */ - tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff); - tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8); /* VORRI */ - return; - } - - if (vece =3D=3D MO_32) { - uint32_t v32 =3D v64; - - if (is_shimm32(v32, &cmode, &imm8) || - is_soimm32(v32, &cmode, &imm8)) { - tcg_out_vmovi(s, rd, q, 0, cmode, imm8); - return; - } - if (is_shimm32(~v32, &cmode, &imm8) || - is_soimm32(~v32, &cmode, &imm8)) { - tcg_out_vmovi(s, rd, q, 1, cmode, imm8); - return; - } - - /* - * Restrict the set of constants to those we can load with - * two instructions. Others we load from the pool. - */ - i =3D is_shimm32_pair(v32, &cmode, &imm8); - if (i) { - tcg_out_vmovi(s, rd, q, 0, cmode, imm8); - tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8)); - return; - } - i =3D is_shimm32_pair(~v32, &cmode, &imm8); - if (i) { - tcg_out_vmovi(s, rd, q, 1, cmode, imm8); - tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8)); - return; - } - } - - /* - * As a last resort, load from the constant pool. - */ - if (!q || vece =3D=3D MO_64) { - new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32); - /* VLDR Dd, [pc + offset] */ - tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16)); - if (q) { - tcg_out_dup2_vec(s, rd, rd, rd); - } - } else { - new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0); - /* add tmp, pc, offset */ - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0); - tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0); - } -} - -static const ARMInsn vec_cmp_insn[16] =3D { - [TCG_COND_EQ] =3D INSN_VCEQ, - [TCG_COND_GT] =3D INSN_VCGT, - [TCG_COND_GE] =3D INSN_VCGE, - [TCG_COND_GTU] =3D INSN_VCGT_U, - [TCG_COND_GEU] =3D INSN_VCGE_U, -}; - -static const ARMInsn vec_cmp0_insn[16] =3D { - [TCG_COND_EQ] =3D INSN_VCEQ0, - [TCG_COND_GT] =3D INSN_VCGT0, - [TCG_COND_GE] =3D INSN_VCGE0, - [TCG_COND_LT] =3D INSN_VCLT0, - [TCG_COND_LE] =3D INSN_VCLE0, -}; - -static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, - unsigned vecl, unsigned vece, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) -{ - TCGType type =3D vecl + TCG_TYPE_V64; - unsigned q =3D vecl; - TCGArg a0, a1, a2, a3; - int cmode, imm8; - - a0 =3D args[0]; - a1 =3D args[1]; - a2 =3D args[2]; - - switch (opc) { - case INDEX_op_ld_vec: - tcg_out_ld(s, type, a0, a1, a2); - return; - case INDEX_op_st_vec: - tcg_out_st(s, type, a0, a1, a2); - return; - case INDEX_op_dupm_vec: - tcg_out_dupm_vec(s, type, vece, a0, a1, a2); - return; - case INDEX_op_dup2_vec: - tcg_out_dup2_vec(s, a0, a1, a2); - return; - case INDEX_op_abs_vec: - tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1); - return; - case INDEX_op_neg_vec: - tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1); - return; - case INDEX_op_not_vec: - tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1); - return; - case INDEX_op_add_vec: - tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2); - return; - case INDEX_op_mul_vec: - tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2); - return; - case INDEX_op_smax_vec: - tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2); - return; - case INDEX_op_smin_vec: - tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2); - return; - case INDEX_op_sub_vec: - tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); - return; - case INDEX_op_ssadd_vec: - tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2); - return; - case INDEX_op_sssub_vec: - tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2); - return; - case INDEX_op_umax_vec: - tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2); - return; - case INDEX_op_umin_vec: - tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2); - return; - case INDEX_op_usadd_vec: - tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2); - return; - case INDEX_op_ussub_vec: - tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2); - return; - case INDEX_op_xor_vec: - tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); - return; - case INDEX_op_arm_sshl_vec: - /* - * Note that Vm is the data and Vn is the shift count, - * therefore the arguments appear reversed. - */ - tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1); - return; - case INDEX_op_arm_ushl_vec: - /* See above. */ - tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1); - return; - case INDEX_op_shli_vec: - tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece)); - return; - case INDEX_op_shri_vec: - tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2); - return; - case INDEX_op_sari_vec: - tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2); - return; - case INDEX_op_arm_sli_vec: - tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece)); - return; - - case INDEX_op_andc_vec: - if (!const_args[2]) { - tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2); - return; - } - a2 =3D ~a2; - /* fall through */ - case INDEX_op_and_vec: - if (const_args[2]) { - is_shimm1632(~a2, &cmode, &imm8); - if (a0 =3D=3D a1) { - tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */ - return; - } - tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */ - a2 =3D a0; - } - tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2); - return; - - case INDEX_op_orc_vec: - if (!const_args[2]) { - tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2); - return; - } - a2 =3D ~a2; - /* fall through */ - case INDEX_op_or_vec: - if (const_args[2]) { - is_shimm1632(a2, &cmode, &imm8); - if (a0 =3D=3D a1) { - tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */ - return; - } - tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */ - a2 =3D a0; - } - tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2); - return; - - case INDEX_op_cmp_vec: - { - TCGCond cond =3D args[3]; - ARMInsn insn; - - switch (cond) { - case TCG_COND_NE: - if (const_args[2]) { - tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1); - } else { - tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2); - tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); - } - break; - - case TCG_COND_TSTNE: - case TCG_COND_TSTEQ: - if (const_args[2]) { - /* (x & 0) =3D=3D 0 */ - tcg_out_dupi_vec(s, type, MO_8, a0, - -(cond =3D=3D TCG_COND_TSTEQ)); - break; - } - tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a2); - if (cond =3D=3D TCG_COND_TSTEQ) { - tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0); - } - break; - - default: - if (const_args[2]) { - insn =3D vec_cmp0_insn[cond]; - if (insn) { - tcg_out_vreg2(s, insn, q, vece, a0, a1); - return; - } - tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); - a2 =3D TCG_VEC_TMP; - } - insn =3D vec_cmp_insn[cond]; - if (insn =3D=3D 0) { - TCGArg t; - t =3D a1, a1 =3D a2, a2 =3D t; - cond =3D tcg_swap_cond(cond); - insn =3D vec_cmp_insn[cond]; - tcg_debug_assert(insn !=3D 0); - } - tcg_out_vreg3(s, insn, q, vece, a0, a1, a2); - break; - } - } - return; - - case INDEX_op_bitsel_vec: - a3 =3D args[3]; - if (a0 =3D=3D a3) { - tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1); - } else if (a0 =3D=3D a2) { - tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1); - } else { - tcg_out_mov(s, type, a0, a1); - tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3); - } - return; - - case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ - case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ - default: - g_assert_not_reached(); - } -} - -int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) -{ - switch (opc) { - case INDEX_op_add_vec: - case INDEX_op_sub_vec: - case INDEX_op_and_vec: - case INDEX_op_andc_vec: - case INDEX_op_or_vec: - case INDEX_op_orc_vec: - case INDEX_op_xor_vec: - case INDEX_op_not_vec: - case INDEX_op_shli_vec: - case INDEX_op_shri_vec: - case INDEX_op_sari_vec: - case INDEX_op_ssadd_vec: - case INDEX_op_sssub_vec: - case INDEX_op_usadd_vec: - case INDEX_op_ussub_vec: - case INDEX_op_bitsel_vec: - return 1; - case INDEX_op_abs_vec: - case INDEX_op_cmp_vec: - case INDEX_op_mul_vec: - case INDEX_op_neg_vec: - case INDEX_op_smax_vec: - case INDEX_op_smin_vec: - case INDEX_op_umax_vec: - case INDEX_op_umin_vec: - return vece < MO_64; - case INDEX_op_shlv_vec: - case INDEX_op_shrv_vec: - case INDEX_op_sarv_vec: - case INDEX_op_rotli_vec: - case INDEX_op_rotlv_vec: - case INDEX_op_rotrv_vec: - return -1; - default: - return 0; - } -} - -void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, - TCGArg a0, ...) -{ - va_list va; - TCGv_vec v0, v1, v2, t1, t2, c1; - TCGArg a2; - - va_start(va, a0); - v0 =3D temp_tcgv_vec(arg_temp(a0)); - v1 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); - a2 =3D va_arg(va, TCGArg); - va_end(va); - - switch (opc) { - case INDEX_op_shlv_vec: - /* - * Merely propagate shlv_vec to arm_ushl_vec. - * In this way we don't set TCG_TARGET_HAS_shv_vec - * because everything is done via expansion. - */ - v2 =3D temp_tcgv_vec(arg_temp(a2)); - vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), - tcgv_vec_arg(v1), tcgv_vec_arg(v2)); - break; - - case INDEX_op_shrv_vec: - case INDEX_op_sarv_vec: - /* Right shifts are negative left shifts for NEON. */ - v2 =3D temp_tcgv_vec(arg_temp(a2)); - t1 =3D tcg_temp_new_vec(type); - tcg_gen_neg_vec(vece, t1, v2); - if (opc =3D=3D INDEX_op_shrv_vec) { - opc =3D INDEX_op_arm_ushl_vec; - } else { - opc =3D INDEX_op_arm_sshl_vec; - } - vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), - tcgv_vec_arg(v1), tcgv_vec_arg(t1)); - tcg_temp_free_vec(t1); - break; - - case INDEX_op_rotli_vec: - t1 =3D tcg_temp_new_vec(type); - tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); - vec_gen_4(INDEX_op_arm_sli_vec, type, vece, - tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2= ); - tcg_temp_free_vec(t1); - break; - - case INDEX_op_rotlv_vec: - v2 =3D temp_tcgv_vec(arg_temp(a2)); - t1 =3D tcg_temp_new_vec(type); - c1 =3D tcg_constant_vec(type, vece, 8 << vece); - tcg_gen_sub_vec(vece, t1, v2, c1); - /* Right shifts are negative left shifts for NEON. */ - vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), - tcgv_vec_arg(v1), tcgv_vec_arg(t1)); - vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0), - tcgv_vec_arg(v1), tcgv_vec_arg(v2)); - tcg_gen_or_vec(vece, v0, v0, t1); - tcg_temp_free_vec(t1); - break; - - case INDEX_op_rotrv_vec: - v2 =3D temp_tcgv_vec(arg_temp(a2)); - t1 =3D tcg_temp_new_vec(type); - t2 =3D tcg_temp_new_vec(type); - c1 =3D tcg_constant_vec(type, vece, 8 << vece); - tcg_gen_neg_vec(vece, t1, v2); - tcg_gen_sub_vec(vece, t2, c1, v2); - /* Right shifts are negative left shifts for NEON. */ - vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1), - tcgv_vec_arg(v1), tcgv_vec_arg(t1)); - vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2), - tcgv_vec_arg(v1), tcgv_vec_arg(t2)); - tcg_gen_or_vec(vece, v0, t1, t2); - tcg_temp_free_vec(t1); - tcg_temp_free_vec(t2); - break; - - default: - g_assert_not_reached(); - } -} - -static void tcg_out_nop_fill(tcg_insn_unit *p, int count) -{ - int i; - for (i =3D 0; i < count; ++i) { - p[i] =3D INSN_NOP; - } -} - -/* Compute frame size via macros, to share between tcg_target_qemu_prologue - and tcg_register_jit. */ - -#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long)) - -#define FRAME_SIZE \ - ((PUSH_SIZE \ - + TCG_STATIC_CALL_ARGS_SIZE \ - + CPU_TEMP_BUF_NLONGS * sizeof(long) \ - + TCG_TARGET_STACK_ALIGN - 1) \ - & -TCG_TARGET_STACK_ALIGN) - -#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE) - -static void tcg_target_qemu_prologue(TCGContext *s) -{ - /* Calling convention requires us to save r4-r11 and lr. */ - /* stmdb sp!, { r4 - r11, lr } */ - tcg_out_ldstm(s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK, - (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6= ) | - (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9= ) | - (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_= R14)); - - /* Reserve callee argument and tcg temp space. */ - tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, - TCG_REG_CALL_STACK, STACK_ADDEND, 1); - tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, - CPU_TEMP_BUF_NLONGS * sizeof(long)); - - tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); - - if (!tcg_use_softmmu && guest_base) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); - } - - tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); - - /* - * Return path for goto_ptr. Set return value to 0, a-la exit_tb, - * and fall through to the rest of the epilogue. - */ - tcg_code_gen_epilogue =3D tcg_splitwx_to_rx(s->code_ptr); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); - tcg_out_epilogue(s); -} - -static void tcg_out_epilogue(TCGContext *s) -{ - /* Release local stack frame. */ - tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK, - TCG_REG_CALL_STACK, STACK_ADDEND, 1); - - /* ldmia sp!, { r4 - r11, pc } */ - tcg_out_ldstm(s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK, - (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6= ) | - (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9= ) | - (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_= PC)); -} - -static void tcg_out_tb_start(TCGContext *s) -{ - /* nothing to do */ -} - -typedef struct { - DebugFrameHeader h; - uint8_t fde_def_cfa[4]; - uint8_t fde_reg_ofs[18]; -} DebugFrame; - -#define ELF_HOST_MACHINE EM_ARM - -/* We're expecting a 2 byte uleb128 encoded value. */ -QEMU_BUILD_BUG_ON(FRAME_SIZE >=3D (1 << 14)); - -static const DebugFrame debug_frame =3D { - .h.cie.len =3D sizeof(DebugFrameCIE)-4, /* length after .len member */ - .h.cie.id =3D -1, - .h.cie.version =3D 1, - .h.cie.code_align =3D 1, - .h.cie.data_align =3D 0x7c, /* sleb128 -4 */ - .h.cie.return_column =3D 14, - - /* Total FDE size does not include the "len" member. */ - .h.fde.len =3D sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_off= set), - - .fde_def_cfa =3D { - 12, 13, /* DW_CFA_def_cfa sp, ... */ - (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ - (FRAME_SIZE >> 7) - }, - .fde_reg_ofs =3D { - /* The following must match the stmdb in the prologue. */ - 0x8e, 1, /* DW_CFA_offset, lr, -4 */ - 0x8b, 2, /* DW_CFA_offset, r11, -8 */ - 0x8a, 3, /* DW_CFA_offset, r10, -12 */ - 0x89, 4, /* DW_CFA_offset, r9, -16 */ - 0x88, 5, /* DW_CFA_offset, r8, -20 */ - 0x87, 6, /* DW_CFA_offset, r7, -24 */ - 0x86, 7, /* DW_CFA_offset, r6, -28 */ - 0x85, 8, /* DW_CFA_offset, r5, -32 */ - 0x84, 9, /* DW_CFA_offset, r4, -36 */ - } -}; - -void tcg_register_jit(const void *buf, size_t buf_size) -{ - tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); -} --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774163; cv=none; d=zohomail.com; s=zohoarc; b=JKrv0FMQXMd8fJm+y5GbtQYFaTcZ5UXmThj58rThKyCfgmcTSivpMJp0odXHbl1EuoykpvyHwqcw0vNkZueVb4Q/yLIKCenAeWLPdgp9c1v4uFNI04MfRHz3wjjVTxaXvNitqRh6kZ7AFVrJrsb45hVDWfj9jNObaM2MzX9UDtc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768774163; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/x6/nMlfDysnN6nEcooEPelvvHCju41IIbLE1D7/Ks4=; b=lDqI7/LCI2FXHXEkzUV0jwwm3xekD0addKMiFtN9BaEFiPFSNus6AJ/0squrfUcYjMCMcGxlmPTAj24AyBthYIBwFuRk1jx2r9cF9EVAPdyKhj5ztF0zY8kyvfx0GszOLMCq5EttiHtgHN8IXpPdka0e0+z/AkiFL/qMYdwME3I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768774163204470.90279691795683; Sun, 18 Jan 2026 14:09:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhat7-0001IM-4K; Sun, 18 Jan 2026 17:04:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhasy-0000go-PC for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:41 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhasw-0000UF-46 for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:40 -0500 Received: by mail-pl1-x641.google.com with SMTP id d9443c01a7336-2a0d5c365ceso28192485ad.3 for ; Sun, 18 Jan 2026 14:04:37 -0800 (PST) Received: from stoup.. ([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7193dbb74sm74402865ad.56.2026.01.18.14.04.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:04:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768773877; x=1769378677; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/x6/nMlfDysnN6nEcooEPelvvHCju41IIbLE1D7/Ks4=; b=mSyGMmT/rGpvWBvQXBm5tpQA8mj9DLvZPLISNuGS7YF96fWQigY21zrssfKdFRIx5Z 1/F3Vw8Y21VdT0scPo+eoRO4LqDT9dpNXgOWlog6kNcAGXJfriZ3khUwU6Wn560wjcZJ QdWUwxclrwtZv9RVNcA39nu4eNB3aq5W45Vp4L/H3EuC/osSun6dns+5if24xJPGyboI YFLteYxsq7SPnCwlB8irVOROekGyW9rkoA43JK028TxXIN2L+bRIaXJKY8WDLVyIWjKh jwYMeFGUQUSnqqL+irCmS/12tb/ZpBAdmEEDHpsaD2Gbci019kuWFKaOYKs/1LsuINJR W/PQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768773877; x=1769378677; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=/x6/nMlfDysnN6nEcooEPelvvHCju41IIbLE1D7/Ks4=; b=buE/ONxnHUzysexenXuKsmWmLOnKzIgyVp77ZZ/P6KMnPxrkzQ2xhJJSazZDyBs8Zo WXIIt8caO7cZPGmeIgX4a2CnY3pNOgiiPHKJkKkjf5iuqpNaXJw51EE9oqrF0cHvkdtf 32jvve4AJxgq0tU/fMrKEi7BrO1UTrrUdUFFpVGBL/RXKeSMW/2kg39LF3HWy3Z1d2Sb VUD5zK5BBS5j5bB/UIH31YE8tTwzBH+ai+c+LCV1OnXqtdbJY9EpvDUR4FrSTTpZqQKj qklrb0YVGADd+p3UcZaZJkPJpU7tLdzRihKWWEGRwX6/A1JJOMTXXwP9lOvzWc6NRWdJ JIHw== X-Gm-Message-State: AOJu0Yzt2rAJnE6rRRtzyG6mDftoD+2sf6U38hpNQTPyyUK06Ftm/PAG lojH17niGiNZbr82LfWJuECZ1TCLwG73VhnjmrPKDfyCLqYSbqOn2l1MwdbrRwtja3iz5jQiyfH nQJxH9EnSwsRV X-Gm-Gg: AY/fxX6PzH3T8a/agstHJ70W7uY6iQTknrPLznjJDdk4QvZ1BnCF6Zsm0a33M0wOWcc xA23XqHzKMgUsCnOg1tODYvSI0xdzz8K2ZGHtPVJGwjhsmLQSnnFKODMCDD1lcmKDsZhW3sTKoS viD8vB2IIBkZvVQsl0ykUgruGzQCIDobsWcXzQ228FbbxaLPiWNNQSIh17KiA+Il0jGKNX2cq8N gpuXugA5V10r/l+yuKsyicIBStDYeU+4YbBTDzs/29p56uqxwfqDgFg0JgANQvII4bye5oGwl3p yGADNMSpZlTCUPX5jzPgZn64suWbKv5A+WZBXSaNTnKKtpt0Iq8VjnzzyaT3+aUyQ1eD7kx0WBn JAtIQ96XvC3o8ESHo14tSxMdUpvrViGqBxOcoKC9BtYUYMIj88DUUE+yFErVfsxxnmMZ5dAWGpw LGoe4yY6fp2j3yt4kn5owWR9gfveI0 X-Received: by 2002:a17:903:2f48:b0:2a5:99ec:16d7 with SMTP id d9443c01a7336-2a71888b5c5mr93271835ad.7.1768773876641; Sun, 18 Jan 2026 14:04:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Kyle Evans , Warner Losh , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 07/54] bsd-user: Fix __i386__ test for TARGET_HAS_STAT_TIME_T_EXT Date: Mon, 19 Jan 2026 09:03:27 +1100 Message-ID: <20260118220414.8177-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x641.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774164777158500 The target test is TARGET_I386, not __i386__. Cc: Kyle Evans Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- bsd-user/syscall_defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsd-user/syscall_defs.h b/bsd-user/syscall_defs.h index 52f84d5dd1..c49be32bdc 100644 --- a/bsd-user/syscall_defs.h +++ b/bsd-user/syscall_defs.h @@ -247,7 +247,7 @@ struct target_freebsd11_stat { unsigned int:(8 / 2) * (16 - (int)sizeof(struct target_freebsd_timespe= c)); } __packed; =20 -#if defined(__i386__) +#if defined(TARGET_I386) #define TARGET_HAS_STAT_TIME_T_EXT 1 #endif =20 --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768773944; cv=none; d=zohomail.com; s=zohoarc; b=A2R1yc7NYJd04IWuuRz7jB3xzlEygYl+2m+arHgmpFABCKxzZKWiuvLX9MkeDkg3MMBCRf3jNxNJtjvUFoql5PZgtZvcLOELoyq+T7nrieEuTfy1R8yWRYb67wmRdOPxz+IxCuhfmaOtqWHfS/ZJmTLWRhT1R8Q+vggH+FGrpp8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768773944; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=UDkM7uIkvNm6fLdpIQ/hnja2LnP7PMDxeJXBu7Pf1iw=; b=M0B0wgwn73sUfxro9wks6lVYFuVeOnI/9Fz7+/DgtILKWaub5XBTWDQT4bj2EQTyIu4GNZC8o8pSDmW63b/IxTsy2d8U3py2VBjoVwGQ6SshuEvX4ZMAZc3xlYCtDFsjIVUap8vWqZhqiubbi+SY9p/Rp6KL3SglLGjcTqmqkM4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17687739449771002.3145682234012; Sun, 18 Jan 2026 14:05:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhat5-00015o-Hy; Sun, 18 Jan 2026 17:04:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhat0-0000hx-9r for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:43 -0500 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhasy-0000UQ-9g for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:42 -0500 Received: by mail-pg1-x52b.google.com with SMTP id 41be03b00d2f7-bc29d64b39dso1202567a12.3 for ; Sun, 18 Jan 2026 14:04:39 -0800 (PST) Received: from stoup.. ([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7193dbb74sm74402865ad.56.2026.01.18.14.04.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:04:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768773879; x=1769378679; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UDkM7uIkvNm6fLdpIQ/hnja2LnP7PMDxeJXBu7Pf1iw=; b=hAsTayfj9iIMudjZH0uIdIjs20tWbVAxZcvzWKGhshMxFj069NjdcnKb5tne4nybgD Rs75STn95AjxjRJRDI4e4VhQEiip3iimo6r6kx2ZzxXIwlWsvcxyCHItg2pIClrQDnHj C0zlXaDRSH4GFEOu1ViFp9tzAVsr5sqHpdxqvnpAdPtl1XmHbDyVayzRNyRN7O/IqM3e fj1v3EIlSHT5IXepHyGgo8i5STNcBotnjcia+XgfraKicooLiGd5yF3J8IJdNvz8Ak/F PTgOkALV9Lj03mtGvC8kR06ft0PKtsRdzDGf9qOLnsqpV+8fnhziYacd3JlcD+6A+e4U 1oGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768773879; x=1769378679; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=UDkM7uIkvNm6fLdpIQ/hnja2LnP7PMDxeJXBu7Pf1iw=; b=TBUdcaBdgZ1HurBagS8fx7xlsn5eXAoZ+4wBZUyZ6OP1vAcImpTpPFOU4d7VuOg2zW wmTgYh+yQVzW69TRIstGY/rTHzutHlv+3eSz3DGuBVNMXe7yfFhtzuDZ+mmUwDR+NKye pQjbtwgJUnUqB52u2xf5saBFmiJUgCSGxSG1/vm1FrXKMkM2QJBsZy19mSqRiybajsqn tDBWn2xVKK4ca6Vsi2WZwef8P7hSOqtmGy6gDi4pMdOOOudlj7/CMX807STF5ADSE2za b09rSO2C1KJIeKL8q6qVOLvvmBTwC/YMqw+urkvSjs/VUe8hnZKx6VTKbCpddleH6CXX B3Lw== X-Gm-Message-State: AOJu0YwhhYVGLGX5ZQ/eMc67q111cIL9qSclQERlwjw0q5Dx5oubJhiu GVx3095hzQ1yht92lzU67d6oAjp3RISi3xKteCewzAblDgYI/Hy9lCyC7KYKjSHL4mMysu6d56j 17qnp/QBZLw== X-Gm-Gg: AY/fxX75RCfi7DqvIOdpf4t9fYRSxncPGKgb4UXp9107NJec+JuAKjWeWlDCAuZH6yQ 85+UumWl4EQEa2rQ4qIfjp9BVG6W/c3anSXFuqQx5+qlrq/DgMUw1CjQo4spmt3byxy+S4hoRHF gRqL2ZLuUJHudRuQjHSwmjs8iT/Dj+aZIwNcxCoXc+3KCgLrNw+uMchNWHn9n2Ys8J2Ai7UFOw+ e4wdg1BARPbsQoz/dyKRxYsymWccJGvNF91V5tysQbRJR8bjj/8w+0cT4zHH3kEq56UinGLatfv mbkmvfSu5uUA5vxjlItqL5XvvutZ512LHfPKW757QbqK+6o3IPwl+jnUQanIcQKXpOiNjWNJr3l cdEHuAbIo7y7qXwEIvEX1fah2ri9v5EI4xSDjA0kMl53zSRGLkQI63oZj7qzlfEYe4DWVoIjjIf 2hXSJCD1+ZqbTbeB+zEw== X-Received: by 2002:a17:902:db0a:b0:2a2:acc7:f1ea with SMTP id d9443c01a7336-2a71895bd7amr101732145ad.59.1768773878709; Sun, 18 Jan 2026 14:04:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 08/54] *: Remove __i386__ tests Date: Mon, 19 Jan 2026 09:03:28 +1100 Message-ID: <20260118220414.8177-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768773946124158500 Content-Type: text/plain; charset="utf-8" Remove instances of __i386__, except from tests and imported headers. Drop a block containing sanity check and fprintf error message for i386-on-i386 or x86_64-on-x86_64 emulation. If we really want something like this, we would do it via some form of compile-time check. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/qemu/atomic.h | 4 ++-- include/qemu/cacheflush.h | 2 +- include/qemu/osdep.h | 4 +--- include/qemu/processor.h | 2 +- include/qemu/timer.h | 9 --------- tcg/tci/tcg-target-mo.h | 2 +- accel/kvm/kvm-all.c | 2 +- disas/disas-host.c | 6 ------ hw/display/xenfb.c | 10 +--------- linux-user/syscall.c | 9 --------- target/i386/cpu.c | 10 ---------- util/cacheflush.c | 2 +- configure | 2 -- 13 files changed, 9 insertions(+), 55 deletions(-) diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h index f80cba24cf..c39dc99f2f 100644 --- a/include/qemu/atomic.h +++ b/include/qemu/atomic.h @@ -204,7 +204,7 @@ * the same semantics. */ #if !defined(QEMU_SANITIZE_THREAD) && \ - (defined(__i386__) || defined(__x86_64__) || defined(__s390x__)) + (defined(__x86_64__) || defined(__s390x__)) # define smp_mb__before_rmw() signal_barrier() # define smp_mb__after_rmw() signal_barrier() #else @@ -218,7 +218,7 @@ */ =20 #if !defined(QEMU_SANITIZE_THREAD) && \ - (defined(__i386__) || defined(__x86_64__) || defined(__s390x__)) + (defined(__x86_64__) || defined(__s390x__)) # define qatomic_set_mb(ptr, i) \ ({ (void)qatomic_xchg(ptr, i); smp_mb__after_rmw(); }) #else diff --git a/include/qemu/cacheflush.h b/include/qemu/cacheflush.h index 76eb55d818..8c64b87814 100644 --- a/include/qemu/cacheflush.h +++ b/include/qemu/cacheflush.h @@ -19,7 +19,7 @@ * mappings of the same physical page(s). */ =20 -#if defined(__i386__) || defined(__x86_64__) || defined(__s390__) +#if defined(__x86_64__) || defined(__s390__) =20 static inline void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t = len) { diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 4cdeda0b9c..b384b5b506 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -637,9 +637,7 @@ bool qemu_has_ofd_lock(void); =20 bool qemu_has_direct_io(void); =20 -#if defined(__HAIKU__) && defined(__i386__) -#define FMT_pid "%ld" -#elif defined(WIN64) +#ifdef WIN64 #define FMT_pid "%" PRId64 #else #define FMT_pid "%d" diff --git a/include/qemu/processor.h b/include/qemu/processor.h index 9f0dcdf28f..95b3262f8b 100644 --- a/include/qemu/processor.h +++ b/include/qemu/processor.h @@ -7,7 +7,7 @@ #ifndef QEMU_PROCESSOR_H #define QEMU_PROCESSOR_H =20 -#if defined(__i386__) || defined(__x86_64__) +#if defined(__x86_64__) # define cpu_relax() asm volatile("rep; nop" ::: "memory") =20 #elif defined(__aarch64__) diff --git a/include/qemu/timer.h b/include/qemu/timer.h index 8b561cd696..7c18da1652 100644 --- a/include/qemu/timer.h +++ b/include/qemu/timer.h @@ -866,15 +866,6 @@ static inline int64_t cpu_get_host_ticks(void) return retval; } =20 -#elif defined(__i386__) - -static inline int64_t cpu_get_host_ticks(void) -{ - int64_t val; - asm volatile ("rdtsc" : "=3DA" (val)); - return val; -} - #elif defined(__x86_64__) =20 static inline int64_t cpu_get_host_ticks(void) diff --git a/tcg/tci/tcg-target-mo.h b/tcg/tci/tcg-target-mo.h index 779872e39a..b5b389dafc 100644 --- a/tcg/tci/tcg-target-mo.h +++ b/tcg/tci/tcg-target-mo.h @@ -8,7 +8,7 @@ #define TCG_TARGET_MO_H =20 /* - * We could notice __i386__ or __s390x__ and reduce the barriers depending + * We could notice __x86_64__ or __s390x__ and reduce the barriers dependi= ng * on the host. But if you want performance, you use the normal backend. * We prefer consistency across hosts on this. */ diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index f85eb42d78..8301a512e7 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -61,7 +61,7 @@ #include #endif =20 -#if defined(__i386__) || defined(__x86_64__) || defined(__aarch64__) +#if defined(__x86_64__) || defined(__aarch64__) # define KVM_HAVE_MCE_INJECTION 1 #endif =20 diff --git a/disas/disas-host.c b/disas/disas-host.c index 88e7d8800c..7cf432938e 100644 --- a/disas/disas-host.c +++ b/disas/disas-host.c @@ -44,12 +44,6 @@ static void initialize_debug_host(CPUDebug *s) #endif #if defined(CONFIG_TCG_INTERPRETER) s->info.print_insn =3D print_insn_tci; -#elif defined(__i386__) - s->info.mach =3D bfd_mach_i386_i386; - s->info.cap_arch =3D CS_ARCH_X86; - s->info.cap_mode =3D CS_MODE_32; - s->info.cap_insn_unit =3D 1; - s->info.cap_insn_split =3D 8; #elif defined(__x86_64__) s->info.mach =3D bfd_mach_x86_64; s->info.cap_arch =3D CS_ARCH_X86; diff --git a/hw/display/xenfb.c b/hw/display/xenfb.c index 164fd0b248..ba886a940e 100644 --- a/hw/display/xenfb.c +++ b/hw/display/xenfb.c @@ -459,10 +459,7 @@ static int xenfb_map_fb(struct XenFB *xenfb) */ uint32_t *ptr32 =3D NULL; uint32_t *ptr64 =3D NULL; -#if defined(__i386__) - ptr32 =3D (void*)page->pd; - ptr64 =3D ((void*)page->pd) + 4; -#elif defined(__x86_64__) +#if defined(__x86_64__) ptr32 =3D ((void*)page->pd) - 4; ptr64 =3D (void*)page->pd; #endif @@ -480,11 +477,6 @@ static int xenfb_map_fb(struct XenFB *xenfb) /* 64bit dom0, 32bit domU */ mode =3D 32; pd =3D ((void*)page->pd) - 4; -#elif defined(__i386__) - } else if (strcmp(protocol, XEN_IO_PROTO_ABI_X86_64) =3D=3D 0) { - /* 32bit dom0, 64bit domU */ - mode =3D 64; - pd =3D ((void*)page->pd) + 4; #endif } =20 diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 67ad681098..3601715769 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -7452,15 +7452,6 @@ void syscall_init(void) ~(TARGET_IOC_SIZEMASK << TARGET_IOC_SIZESHIF= T)) | (size << TARGET_IOC_SIZESHIFT); } - - /* automatic consistency check if same arch */ -#if (defined(__i386__) && defined(TARGET_I386) && defined(TARGET_ABI32)) |= | \ - (defined(__x86_64__) && defined(TARGET_X86_64)) - if (unlikely(ie->target_cmd !=3D ie->host_cmd)) { - fprintf(stderr, "ERROR: ioctl(%s): target=3D0x%x host=3D0x%x\n= ", - ie->name, ie->target_cmd, ie->host_cmd); - } -#endif ie++; } } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 37803cd724..0b8cca7cec 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2251,16 +2251,6 @@ void host_cpuid(uint32_t function, uint32_t count, : "=3Da"(vec[0]), "=3Db"(vec[1]), "=3Dc"(vec[2]), "=3Dd"(vec[3]) : "0"(function), "c"(count) : "cc"); -#elif defined(__i386__) - asm volatile("pusha \n\t" - "cpuid \n\t" - "mov %%eax, 0(%2) \n\t" - "mov %%ebx, 4(%2) \n\t" - "mov %%ecx, 8(%2) \n\t" - "mov %%edx, 12(%2) \n\t" - "popa" - : : "a"(function), "c"(count), "S"(vec) - : "memory", "cc"); #else abort(); #endif diff --git a/util/cacheflush.c b/util/cacheflush.c index 69c9614e2c..99221a409f 100644 --- a/util/cacheflush.c +++ b/util/cacheflush.c @@ -225,7 +225,7 @@ static void __attribute__((constructor)) init_cache_inf= o(void) * Architecture (+ OS) specific cache flushing mechanisms. */ =20 -#if defined(__i386__) || defined(__x86_64__) || defined(__s390__) +#if defined(__x86_64__) || defined(__s390__) =20 /* Caches are coherent and do not require flushing; symbol inline. */ =20 diff --git a/configure b/configure index 0742f1212d..de0f3a8ebe 100755 --- a/configure +++ b/configure @@ -382,8 +382,6 @@ fi if test ! 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Remove linux-user/include/host/i386. Remove common-user/host/i386. Reviewed-by: Thomas Huth Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- host/include/i386/host/cpuinfo.h | 41 ------ host/include/i386/host/crypto/aes-round.h | 152 ------------------- host/include/i386/host/crypto/clmul.h | 29 ---- host/include/x86_64/host/cpuinfo.h | 42 +++++- host/include/x86_64/host/crypto/aes-round.h | 153 +++++++++++++++++++- host/include/x86_64/host/crypto/clmul.h | 30 +++- linux-user/include/host/i386/host-signal.h | 38 ----- common-user/host/i386/safe-syscall.inc.S | 127 ---------------- host/include/i386/host/bufferiszero.c.inc | 125 ---------------- host/include/x86_64/host/bufferiszero.c.inc | 126 +++++++++++++++- 10 files changed, 347 insertions(+), 516 deletions(-) delete mode 100644 host/include/i386/host/cpuinfo.h delete mode 100644 host/include/i386/host/crypto/aes-round.h delete mode 100644 host/include/i386/host/crypto/clmul.h delete mode 100644 linux-user/include/host/i386/host-signal.h delete mode 100644 common-user/host/i386/safe-syscall.inc.S delete mode 100644 host/include/i386/host/bufferiszero.c.inc diff --git a/host/include/i386/host/cpuinfo.h b/host/include/i386/host/cpui= nfo.h deleted file mode 100644 index 93d029d499..0000000000 --- a/host/include/i386/host/cpuinfo.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0-or-later - * Host specific cpu identification for x86. - */ - -#ifndef HOST_CPUINFO_H -#define HOST_CPUINFO_H - -/* Digested version of */ - -#define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */ -#define CPUINFO_OSXSAVE (1u << 1) -#define CPUINFO_MOVBE (1u << 2) -#define CPUINFO_LZCNT (1u << 3) -#define CPUINFO_POPCNT (1u << 4) -#define CPUINFO_BMI1 (1u << 5) -#define CPUINFO_BMI2 (1u << 6) -#define CPUINFO_SSE2 (1u << 7) -#define CPUINFO_AVX1 (1u << 9) -#define CPUINFO_AVX2 (1u << 10) -#define CPUINFO_AVX512F (1u << 11) -#define CPUINFO_AVX512VL (1u << 12) -#define CPUINFO_AVX512BW (1u << 13) -#define CPUINFO_AVX512DQ (1u << 14) -#define CPUINFO_AVX512VBMI2 (1u << 15) -#define CPUINFO_ATOMIC_VMOVDQA (1u << 16) -#define CPUINFO_ATOMIC_VMOVDQU (1u << 17) -#define CPUINFO_AES (1u << 18) -#define CPUINFO_PCLMUL (1u << 19) -#define CPUINFO_GFNI (1u << 20) - -/* Initialized with a constructor. */ -extern unsigned cpuinfo; - -/* - * We cannot rely on constructor ordering, so other constructors must - * use the function interface rather than the variable above. - */ -unsigned cpuinfo_init(void); - -#endif /* HOST_CPUINFO_H */ diff --git a/host/include/i386/host/crypto/aes-round.h b/host/include/i386/= host/crypto/aes-round.h deleted file mode 100644 index 59a64130f7..0000000000 --- a/host/include/i386/host/crypto/aes-round.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * x86 specific aes acceleration. - * SPDX-License-Identifier: GPL-2.0-or-later - */ - -#ifndef X86_HOST_CRYPTO_AES_ROUND_H -#define X86_HOST_CRYPTO_AES_ROUND_H - -#include "host/cpuinfo.h" -#include - -#if defined(__AES__) && defined(__SSSE3__) -# define HAVE_AES_ACCEL true -# define ATTR_AES_ACCEL -#else -# define HAVE_AES_ACCEL likely(cpuinfo & CPUINFO_AES) -# define ATTR_AES_ACCEL __attribute__((target("aes,ssse3"))) -#endif - -static inline __m128i ATTR_AES_ACCEL -aes_accel_bswap(__m128i x) -{ - return _mm_shuffle_epi8(x, _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, - 9, 10, 11, 12, 13, 14, 15)); -} - -static inline void ATTR_AES_ACCEL -aesenc_MC_accel(AESState *ret, const AESState *st, bool be) -{ - __m128i t =3D (__m128i)st->v; - __m128i z =3D _mm_setzero_si128(); - - if (be) { - t =3D aes_accel_bswap(t); - t =3D _mm_aesdeclast_si128(t, z); - t =3D _mm_aesenc_si128(t, z); - t =3D aes_accel_bswap(t); - } else { - t =3D _mm_aesdeclast_si128(t, z); - t =3D _mm_aesenc_si128(t, z); - } - ret->v =3D (AESStateVec)t; -} - -static inline void ATTR_AES_ACCEL -aesenc_SB_SR_AK_accel(AESState *ret, const AESState *st, - const AESState *rk, bool be) -{ - __m128i t =3D (__m128i)st->v; - __m128i k =3D (__m128i)rk->v; - - if (be) { - t =3D aes_accel_bswap(t); - k =3D aes_accel_bswap(k); - t =3D _mm_aesenclast_si128(t, k); - t =3D aes_accel_bswap(t); - } else { - t =3D _mm_aesenclast_si128(t, k); - } - ret->v =3D (AESStateVec)t; -} - -static inline void ATTR_AES_ACCEL -aesenc_SB_SR_MC_AK_accel(AESState *ret, const AESState *st, - const AESState *rk, bool be) -{ - __m128i t =3D (__m128i)st->v; - __m128i k =3D (__m128i)rk->v; - - if (be) { - t =3D aes_accel_bswap(t); - k =3D aes_accel_bswap(k); - t =3D _mm_aesenc_si128(t, k); - t =3D aes_accel_bswap(t); - } else { - t =3D _mm_aesenc_si128(t, k); - } - ret->v =3D (AESStateVec)t; -} - -static inline void ATTR_AES_ACCEL -aesdec_IMC_accel(AESState *ret, const AESState *st, bool be) -{ - __m128i t =3D (__m128i)st->v; - - if (be) { - t =3D aes_accel_bswap(t); - t =3D _mm_aesimc_si128(t); - t =3D aes_accel_bswap(t); - } else { - t =3D _mm_aesimc_si128(t); - } - ret->v =3D (AESStateVec)t; -} - -static inline void ATTR_AES_ACCEL -aesdec_ISB_ISR_AK_accel(AESState *ret, const AESState *st, - const AESState *rk, bool be) -{ - __m128i t =3D (__m128i)st->v; - __m128i k =3D (__m128i)rk->v; - - if (be) { - t =3D aes_accel_bswap(t); - k =3D aes_accel_bswap(k); - t =3D _mm_aesdeclast_si128(t, k); - t =3D aes_accel_bswap(t); - } else { - t =3D _mm_aesdeclast_si128(t, k); - } - ret->v =3D (AESStateVec)t; -} - -static inline void ATTR_AES_ACCEL -aesdec_ISB_ISR_AK_IMC_accel(AESState *ret, const AESState *st, - const AESState *rk, bool be) -{ - __m128i t =3D (__m128i)st->v; - __m128i k =3D (__m128i)rk->v; - - if (be) { - t =3D aes_accel_bswap(t); - k =3D aes_accel_bswap(k); - t =3D _mm_aesdeclast_si128(t, k); - t =3D _mm_aesimc_si128(t); - t =3D aes_accel_bswap(t); - } else { - t =3D _mm_aesdeclast_si128(t, k); - t =3D _mm_aesimc_si128(t); - } - ret->v =3D (AESStateVec)t; -} - -static inline void ATTR_AES_ACCEL -aesdec_ISB_ISR_IMC_AK_accel(AESState *ret, const AESState *st, - const AESState *rk, bool be) -{ - __m128i t =3D (__m128i)st->v; - __m128i k =3D (__m128i)rk->v; - - if (be) { - t =3D aes_accel_bswap(t); - k =3D aes_accel_bswap(k); - t =3D _mm_aesdec_si128(t, k); - t =3D aes_accel_bswap(t); - } else { - t =3D _mm_aesdec_si128(t, k); - } - ret->v =3D (AESStateVec)t; -} - -#endif /* X86_HOST_CRYPTO_AES_ROUND_H */ diff --git a/host/include/i386/host/crypto/clmul.h b/host/include/i386/host= /crypto/clmul.h deleted file mode 100644 index dc3c814797..0000000000 --- a/host/include/i386/host/crypto/clmul.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * x86 specific clmul acceleration. - * SPDX-License-Identifier: GPL-2.0-or-later - */ - -#ifndef X86_HOST_CRYPTO_CLMUL_H -#define X86_HOST_CRYPTO_CLMUL_H - -#include "host/cpuinfo.h" -#include - -#if defined(__PCLMUL__) -# define HAVE_CLMUL_ACCEL true -# define ATTR_CLMUL_ACCEL -#else -# define HAVE_CLMUL_ACCEL likely(cpuinfo & CPUINFO_PCLMUL) -# define ATTR_CLMUL_ACCEL __attribute__((target("pclmul"))) -#endif - -static inline Int128 ATTR_CLMUL_ACCEL -clmul_64_accel(uint64_t n, uint64_t m) -{ - union { __m128i v; Int128 s; } u; - - u.v =3D _mm_clmulepi64_si128(_mm_set_epi64x(0, n), _mm_set_epi64x(0, m= ), 0); - return u.s; -} - -#endif /* X86_HOST_CRYPTO_CLMUL_H */ diff --git a/host/include/x86_64/host/cpuinfo.h b/host/include/x86_64/host/= cpuinfo.h index 67debab9a0..93d029d499 100644 --- a/host/include/x86_64/host/cpuinfo.h +++ b/host/include/x86_64/host/cpuinfo.h @@ -1 +1,41 @@ -#include "host/include/i386/host/cpuinfo.h" +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Host specific cpu identification for x86. + */ + +#ifndef HOST_CPUINFO_H +#define HOST_CPUINFO_H + +/* Digested version of */ + +#define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */ +#define CPUINFO_OSXSAVE (1u << 1) +#define CPUINFO_MOVBE (1u << 2) +#define CPUINFO_LZCNT (1u << 3) +#define CPUINFO_POPCNT (1u << 4) +#define CPUINFO_BMI1 (1u << 5) +#define CPUINFO_BMI2 (1u << 6) +#define CPUINFO_SSE2 (1u << 7) +#define CPUINFO_AVX1 (1u << 9) +#define CPUINFO_AVX2 (1u << 10) +#define CPUINFO_AVX512F (1u << 11) +#define CPUINFO_AVX512VL (1u << 12) +#define CPUINFO_AVX512BW (1u << 13) +#define CPUINFO_AVX512DQ (1u << 14) +#define CPUINFO_AVX512VBMI2 (1u << 15) +#define CPUINFO_ATOMIC_VMOVDQA (1u << 16) +#define CPUINFO_ATOMIC_VMOVDQU (1u << 17) +#define CPUINFO_AES (1u << 18) +#define CPUINFO_PCLMUL (1u << 19) +#define CPUINFO_GFNI (1u << 20) + +/* Initialized with a constructor. */ +extern unsigned cpuinfo; + +/* + * We cannot rely on constructor ordering, so other constructors must + * use the function interface rather than the variable above. + */ +unsigned cpuinfo_init(void); + +#endif /* HOST_CPUINFO_H */ diff --git a/host/include/x86_64/host/crypto/aes-round.h b/host/include/x86= _64/host/crypto/aes-round.h index 2773cc9f10..59a64130f7 100644 --- a/host/include/x86_64/host/crypto/aes-round.h +++ b/host/include/x86_64/host/crypto/aes-round.h @@ -1 +1,152 @@ -#include "host/include/i386/host/crypto/aes-round.h" +/* + * x86 specific aes acceleration. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef X86_HOST_CRYPTO_AES_ROUND_H +#define X86_HOST_CRYPTO_AES_ROUND_H + +#include "host/cpuinfo.h" +#include + +#if defined(__AES__) && defined(__SSSE3__) +# define HAVE_AES_ACCEL true +# define ATTR_AES_ACCEL +#else +# define HAVE_AES_ACCEL likely(cpuinfo & CPUINFO_AES) +# define ATTR_AES_ACCEL __attribute__((target("aes,ssse3"))) +#endif + +static inline __m128i ATTR_AES_ACCEL +aes_accel_bswap(__m128i x) +{ + return _mm_shuffle_epi8(x, _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 13, 14, 15)); +} + +static inline void ATTR_AES_ACCEL +aesenc_MC_accel(AESState *ret, const AESState *st, bool be) +{ + __m128i t =3D (__m128i)st->v; + __m128i z =3D _mm_setzero_si128(); + + if (be) { + t =3D aes_accel_bswap(t); + t =3D _mm_aesdeclast_si128(t, z); + t =3D _mm_aesenc_si128(t, z); + t =3D aes_accel_bswap(t); + } else { + t =3D _mm_aesdeclast_si128(t, z); + t =3D _mm_aesenc_si128(t, z); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesenc_SB_SR_AK_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + __m128i t =3D (__m128i)st->v; + __m128i k =3D (__m128i)rk->v; + + if (be) { + t =3D aes_accel_bswap(t); + k =3D aes_accel_bswap(k); + t =3D _mm_aesenclast_si128(t, k); + t =3D aes_accel_bswap(t); + } else { + t =3D _mm_aesenclast_si128(t, k); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesenc_SB_SR_MC_AK_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + __m128i t =3D (__m128i)st->v; + __m128i k =3D (__m128i)rk->v; + + if (be) { + t =3D aes_accel_bswap(t); + k =3D aes_accel_bswap(k); + t =3D _mm_aesenc_si128(t, k); + t =3D aes_accel_bswap(t); + } else { + t =3D _mm_aesenc_si128(t, k); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesdec_IMC_accel(AESState *ret, const AESState *st, bool be) +{ + __m128i t =3D (__m128i)st->v; + + if (be) { + t =3D aes_accel_bswap(t); + t =3D _mm_aesimc_si128(t); + t =3D aes_accel_bswap(t); + } else { + t =3D _mm_aesimc_si128(t); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesdec_ISB_ISR_AK_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + __m128i t =3D (__m128i)st->v; + __m128i k =3D (__m128i)rk->v; + + if (be) { + t =3D aes_accel_bswap(t); + k =3D aes_accel_bswap(k); + t =3D _mm_aesdeclast_si128(t, k); + t =3D aes_accel_bswap(t); + } else { + t =3D _mm_aesdeclast_si128(t, k); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesdec_ISB_ISR_AK_IMC_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + __m128i t =3D (__m128i)st->v; + __m128i k =3D (__m128i)rk->v; + + if (be) { + t =3D aes_accel_bswap(t); + k =3D aes_accel_bswap(k); + t =3D _mm_aesdeclast_si128(t, k); + t =3D _mm_aesimc_si128(t); + t =3D aes_accel_bswap(t); + } else { + t =3D _mm_aesdeclast_si128(t, k); + t =3D _mm_aesimc_si128(t); + } + ret->v =3D (AESStateVec)t; +} + +static inline void ATTR_AES_ACCEL +aesdec_ISB_ISR_IMC_AK_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + __m128i t =3D (__m128i)st->v; + __m128i k =3D (__m128i)rk->v; + + if (be) { + t =3D aes_accel_bswap(t); + k =3D aes_accel_bswap(k); + t =3D _mm_aesdec_si128(t, k); + t =3D aes_accel_bswap(t); + } else { + t =3D _mm_aesdec_si128(t, k); + } + ret->v =3D (AESStateVec)t; +} + +#endif /* X86_HOST_CRYPTO_AES_ROUND_H */ diff --git a/host/include/x86_64/host/crypto/clmul.h b/host/include/x86_64/= host/crypto/clmul.h index f25eced416..dc3c814797 100644 --- a/host/include/x86_64/host/crypto/clmul.h +++ b/host/include/x86_64/host/crypto/clmul.h @@ -1 +1,29 @@ -#include "host/include/i386/host/crypto/clmul.h" +/* + * x86 specific clmul acceleration. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef X86_HOST_CRYPTO_CLMUL_H +#define X86_HOST_CRYPTO_CLMUL_H + +#include "host/cpuinfo.h" +#include + +#if defined(__PCLMUL__) +# define HAVE_CLMUL_ACCEL true +# define ATTR_CLMUL_ACCEL +#else +# define HAVE_CLMUL_ACCEL likely(cpuinfo & CPUINFO_PCLMUL) +# define ATTR_CLMUL_ACCEL __attribute__((target("pclmul"))) +#endif + +static inline Int128 ATTR_CLMUL_ACCEL +clmul_64_accel(uint64_t n, uint64_t m) +{ + union { __m128i v; Int128 s; } u; + + u.v =3D _mm_clmulepi64_si128(_mm_set_epi64x(0, n), _mm_set_epi64x(0, m= ), 0); + return u.s; +} + +#endif /* X86_HOST_CRYPTO_CLMUL_H */ diff --git a/linux-user/include/host/i386/host-signal.h b/linux-user/includ= e/host/i386/host-signal.h deleted file mode 100644 index e2b64f077f..0000000000 --- a/linux-user/include/host/i386/host-signal.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * host-signal.h: signal info dependent on the host architecture - * - * Copyright (c) 2003-2005 Fabrice Bellard - * Copyright (c) 2021 Linaro Limited - * - * This work is licensed under the terms of the GNU LGPL, version 2.1 or l= ater. - * See the COPYING file in the top-level directory. - */ - -#ifndef I386_HOST_SIGNAL_H -#define I386_HOST_SIGNAL_H - -/* The third argument to a SA_SIGINFO handler is ucontext_t. */ -typedef ucontext_t host_sigcontext; - -static inline uintptr_t host_signal_pc(host_sigcontext *uc) -{ - return uc->uc_mcontext.gregs[REG_EIP]; -} - -static inline void host_signal_set_pc(host_sigcontext *uc, uintptr_t pc) -{ - uc->uc_mcontext.gregs[REG_EIP] =3D pc; -} - -static inline void *host_signal_mask(host_sigcontext *uc) -{ - return &uc->uc_sigmask; -} - -static inline bool host_signal_write(siginfo_t *info, host_sigcontext *uc) -{ - return uc->uc_mcontext.gregs[REG_TRAPNO] =3D=3D 0xe - && (uc->uc_mcontext.gregs[REG_ERR] & 0x2); -} - -#endif diff --git a/common-user/host/i386/safe-syscall.inc.S b/common-user/host/i3= 86/safe-syscall.inc.S deleted file mode 100644 index db2ed09839..0000000000 --- a/common-user/host/i386/safe-syscall.inc.S +++ /dev/null @@ -1,127 +0,0 @@ -/* - * safe-syscall.inc.S : host-specific assembly fragment - * to handle signals occurring at the same time as system calls. - * This is intended to be included by common-user/safe-syscall.S - * - * Written by Richard Henderson - * Copyright (C) 2016 Red Hat, Inc. - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - */ - - .global safe_syscall_base - .global safe_syscall_start - .global safe_syscall_end - .type safe_syscall_base, @function - - /* This is the entry point for making a system call. The calling - * convention here is that of a C varargs function with the - * first argument an 'int *' to the signal_pending flag, the - * second one the system call number (as a 'long'), and all further - * arguments being syscall arguments (also 'long'). - */ -safe_syscall_base: - .cfi_startproc - push %ebp - .cfi_adjust_cfa_offset 4 - .cfi_rel_offset ebp, 0 - push %esi - .cfi_adjust_cfa_offset 4 - .cfi_rel_offset esi, 0 - push %edi - .cfi_adjust_cfa_offset 4 - .cfi_rel_offset edi, 0 - push %ebx - .cfi_adjust_cfa_offset 4 - .cfi_rel_offset ebx, 0 - - /* The syscall calling convention isn't the same as the C one: - * we enter with 0(%esp) =3D=3D return address - * 4(%esp) =3D=3D &signal_pending - * 8(%esp) =3D=3D syscall number - * 12(%esp) ... 32(%esp) =3D=3D syscall arguments - * and return the result in eax - * and the syscall instruction needs - * eax =3D=3D syscall number - * ebx, ecx, edx, esi, edi, ebp =3D=3D syscall argum= ents - * and returns the result in eax - * Shuffle everything around appropriately. - * Note the 16 bytes that we pushed to save registers. - */ - mov 12+16(%esp), %ebx /* the syscall arguments */ - mov 16+16(%esp), %ecx - mov 20+16(%esp), %edx - mov 24+16(%esp), %esi - mov 28+16(%esp), %edi - mov 32+16(%esp), %ebp - - /* This next sequence of code works in conjunction with the - * rewind_if_safe_syscall_function(). If a signal is taken - * and the interrupted PC is anywhere between 'safe_syscall_start' - * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start= '. - * The code sequence must therefore be able to cope with this, and - * the syscall instruction must be the final one in the sequence. - */ -safe_syscall_start: - /* if signal_pending is non-zero, don't do the call */ - mov 4+16(%esp), %eax /* signal_pending */ - cmpl $0, (%eax) - jnz 2f - mov 8+16(%esp), %eax /* syscall number */ - int $0x80 -safe_syscall_end: - - /* code path for having successfully executed the syscall */ -#if defined(__linux__) - /* Linux kernel returns (small) negative errno. */ - cmp $-4095, %eax - jae 0f -#elif defined(__FreeBSD__) - /* FreeBSD kernel returns positive errno and C bit set. */ - jc 1f -#else -#error "unsupported os" -#endif - pop %ebx - .cfi_remember_state - .cfi_adjust_cfa_offset -4 - .cfi_restore ebx - pop %edi - .cfi_adjust_cfa_offset -4 - .cfi_restore edi - pop %esi - .cfi_adjust_cfa_offset -4 - .cfi_restore esi - pop %ebp - .cfi_adjust_cfa_offset -4 - .cfi_restore ebp - ret - .cfi_restore_state - -#if defined(__linux__) -0: neg %eax - jmp 1f -#endif - - /* code path when we didn't execute the syscall */ -2: mov $QEMU_ERESTARTSYS, %eax - - /* code path setting errno */ -1: pop %ebx - .cfi_adjust_cfa_offset -4 - .cfi_restore ebx - pop %edi - .cfi_adjust_cfa_offset -4 - .cfi_restore edi - pop %esi - .cfi_adjust_cfa_offset -4 - .cfi_restore esi - pop %ebp - .cfi_adjust_cfa_offset -4 - .cfi_restore ebp - mov %eax, 4(%esp) - jmp safe_syscall_set_errno_tail - - .cfi_endproc - .size safe_syscall_base, .-safe_syscall_base diff --git a/host/include/i386/host/bufferiszero.c.inc b/host/include/i386/= host/bufferiszero.c.inc deleted file mode 100644 index 74ae98580f..0000000000 --- a/host/include/i386/host/bufferiszero.c.inc +++ /dev/null @@ -1,125 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0-or-later - * buffer_is_zero acceleration, x86 version. - */ - -#if defined(CONFIG_AVX2_OPT) || defined(__SSE2__) -#include - -/* Helper for preventing the compiler from reassociating - chains of binary vector operations. */ -#define SSE_REASSOC_BARRIER(vec0, vec1) asm("" : "+x"(vec0), "+x"(vec1)) - -/* Note that these vectorized functions may assume len >=3D 256. */ - -static bool __attribute__((target("sse2"))) -buffer_zero_sse2(const void *buf, size_t len) -{ - /* Unaligned loads at head/tail. */ - __m128i v =3D *(__m128i_u *)(buf); - __m128i w =3D *(__m128i_u *)(buf + len - 16); - /* Align head/tail to 16-byte boundaries. */ - const __m128i *p =3D QEMU_ALIGN_PTR_DOWN(buf + 16, 16); - const __m128i *e =3D QEMU_ALIGN_PTR_DOWN(buf + len - 1, 16); - __m128i zero =3D { 0 }; - - /* Collect a partial block at tail end. */ - v |=3D e[-1]; w |=3D e[-2]; - SSE_REASSOC_BARRIER(v, w); - v |=3D e[-3]; w |=3D e[-4]; - SSE_REASSOC_BARRIER(v, w); - v |=3D e[-5]; w |=3D e[-6]; - SSE_REASSOC_BARRIER(v, w); - v |=3D e[-7]; v |=3D w; - - /* - * Loop over complete 128-byte blocks. - * With the head and tail removed, e - p >=3D 14, so the loop - * must iterate at least once. - */ - do { - v =3D _mm_cmpeq_epi8(v, zero); - if (unlikely(_mm_movemask_epi8(v) !=3D 0xFFFF)) { - return false; - } - v =3D p[0]; w =3D p[1]; - SSE_REASSOC_BARRIER(v, w); - v |=3D p[2]; w |=3D p[3]; - SSE_REASSOC_BARRIER(v, w); - v |=3D p[4]; w |=3D p[5]; - SSE_REASSOC_BARRIER(v, w); - v |=3D p[6]; w |=3D p[7]; - SSE_REASSOC_BARRIER(v, w); - v |=3D w; - p +=3D 8; - } while (p < e - 7); - - return _mm_movemask_epi8(_mm_cmpeq_epi8(v, zero)) =3D=3D 0xFFFF; -} - -#ifdef CONFIG_AVX2_OPT -static bool __attribute__((target("avx2"))) -buffer_zero_avx2(const void *buf, size_t len) -{ - /* Unaligned loads at head/tail. */ - __m256i v =3D *(__m256i_u *)(buf); - __m256i w =3D *(__m256i_u *)(buf + len - 32); - /* Align head/tail to 32-byte boundaries. */ - const __m256i *p =3D QEMU_ALIGN_PTR_DOWN(buf + 32, 32); - const __m256i *e =3D QEMU_ALIGN_PTR_DOWN(buf + len - 1, 32); - __m256i zero =3D { 0 }; - - /* Collect a partial block at tail end. */ - v |=3D e[-1]; w |=3D e[-2]; - SSE_REASSOC_BARRIER(v, w); - v |=3D e[-3]; w |=3D e[-4]; - SSE_REASSOC_BARRIER(v, w); - v |=3D e[-5]; w |=3D e[-6]; - SSE_REASSOC_BARRIER(v, w); - v |=3D e[-7]; v |=3D w; - - /* Loop over complete 256-byte blocks. */ - for (; p < e - 7; p +=3D 8) { - /* PTEST is not profitable here. */ - v =3D _mm256_cmpeq_epi8(v, zero); - if (unlikely(_mm256_movemask_epi8(v) !=3D 0xFFFFFFFF)) { - return false; - } - v =3D p[0]; w =3D p[1]; - SSE_REASSOC_BARRIER(v, w); - v |=3D p[2]; w |=3D p[3]; - SSE_REASSOC_BARRIER(v, w); - v |=3D p[4]; w |=3D p[5]; - SSE_REASSOC_BARRIER(v, w); - v |=3D p[6]; w |=3D p[7]; - SSE_REASSOC_BARRIER(v, w); - v |=3D w; - } - - return _mm256_movemask_epi8(_mm256_cmpeq_epi8(v, zero)) =3D=3D 0xFFFFF= FFF; -} -#endif /* CONFIG_AVX2_OPT */ - -static biz_accel_fn const accel_table[] =3D { - buffer_is_zero_int_ge256, - buffer_zero_sse2, -#ifdef CONFIG_AVX2_OPT - buffer_zero_avx2, -#endif -}; - -static unsigned best_accel(void) -{ - unsigned info =3D cpuinfo_init(); - -#ifdef CONFIG_AVX2_OPT - if (info & CPUINFO_AVX2) { - return 2; - } -#endif - return info & CPUINFO_SSE2 ? 1 : 0; -} - -#else -# include "host/include/generic/host/bufferiszero.c.inc" -#endif diff --git a/host/include/x86_64/host/bufferiszero.c.inc b/host/include/x86= _64/host/bufferiszero.c.inc index 1d3f1fd6f5..74ae98580f 100644 --- a/host/include/x86_64/host/bufferiszero.c.inc +++ b/host/include/x86_64/host/bufferiszero.c.inc @@ -1 +1,125 @@ -#include "host/include/i386/host/bufferiszero.c.inc" +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * buffer_is_zero acceleration, x86 version. + */ + +#if defined(CONFIG_AVX2_OPT) || defined(__SSE2__) +#include + +/* Helper for preventing the compiler from reassociating + chains of binary vector operations. */ +#define SSE_REASSOC_BARRIER(vec0, vec1) asm("" : "+x"(vec0), "+x"(vec1)) + +/* Note that these vectorized functions may assume len >=3D 256. */ + +static bool __attribute__((target("sse2"))) +buffer_zero_sse2(const void *buf, size_t len) +{ + /* Unaligned loads at head/tail. */ + __m128i v =3D *(__m128i_u *)(buf); + __m128i w =3D *(__m128i_u *)(buf + len - 16); + /* Align head/tail to 16-byte boundaries. */ + const __m128i *p =3D QEMU_ALIGN_PTR_DOWN(buf + 16, 16); + const __m128i *e =3D QEMU_ALIGN_PTR_DOWN(buf + len - 1, 16); + __m128i zero =3D { 0 }; + + /* Collect a partial block at tail end. */ + v |=3D e[-1]; w |=3D e[-2]; + SSE_REASSOC_BARRIER(v, w); + v |=3D e[-3]; w |=3D e[-4]; + SSE_REASSOC_BARRIER(v, w); + v |=3D e[-5]; w |=3D e[-6]; + SSE_REASSOC_BARRIER(v, w); + v |=3D e[-7]; v |=3D w; + + /* + * Loop over complete 128-byte blocks. + * With the head and tail removed, e - p >=3D 14, so the loop + * must iterate at least once. + */ + do { + v =3D _mm_cmpeq_epi8(v, zero); + if (unlikely(_mm_movemask_epi8(v) !=3D 0xFFFF)) { + return false; + } + v =3D p[0]; w =3D p[1]; + SSE_REASSOC_BARRIER(v, w); + v |=3D p[2]; w |=3D p[3]; + SSE_REASSOC_BARRIER(v, w); + v |=3D p[4]; w |=3D p[5]; + SSE_REASSOC_BARRIER(v, w); + v |=3D p[6]; w |=3D p[7]; + SSE_REASSOC_BARRIER(v, w); + v |=3D w; + p +=3D 8; + } while (p < e - 7); + + return _mm_movemask_epi8(_mm_cmpeq_epi8(v, zero)) =3D=3D 0xFFFF; +} + +#ifdef CONFIG_AVX2_OPT +static bool __attribute__((target("avx2"))) +buffer_zero_avx2(const void *buf, size_t len) +{ + /* Unaligned loads at head/tail. */ + __m256i v =3D *(__m256i_u *)(buf); + __m256i w =3D *(__m256i_u *)(buf + len - 32); + /* Align head/tail to 32-byte boundaries. */ + const __m256i *p =3D QEMU_ALIGN_PTR_DOWN(buf + 32, 32); + const __m256i *e =3D QEMU_ALIGN_PTR_DOWN(buf + len - 1, 32); + __m256i zero =3D { 0 }; + + /* Collect a partial block at tail end. */ + v |=3D e[-1]; w |=3D e[-2]; + SSE_REASSOC_BARRIER(v, w); + v |=3D e[-3]; w |=3D e[-4]; + SSE_REASSOC_BARRIER(v, w); + v |=3D e[-5]; w |=3D e[-6]; + SSE_REASSOC_BARRIER(v, w); + v |=3D e[-7]; v |=3D w; + + /* Loop over complete 256-byte blocks. */ + for (; p < e - 7; p +=3D 8) { + /* PTEST is not profitable here. */ + v =3D _mm256_cmpeq_epi8(v, zero); + if (unlikely(_mm256_movemask_epi8(v) !=3D 0xFFFFFFFF)) { + return false; + } + v =3D p[0]; w =3D p[1]; + SSE_REASSOC_BARRIER(v, w); + v |=3D p[2]; w |=3D p[3]; + SSE_REASSOC_BARRIER(v, w); + v |=3D p[4]; w |=3D p[5]; + SSE_REASSOC_BARRIER(v, w); + v |=3D p[6]; w |=3D p[7]; + SSE_REASSOC_BARRIER(v, w); + v |=3D w; + } + + return _mm256_movemask_epi8(_mm256_cmpeq_epi8(v, zero)) =3D=3D 0xFFFFF= FFF; +} +#endif /* CONFIG_AVX2_OPT */ + +static biz_accel_fn const accel_table[] =3D { + buffer_is_zero_int_ge256, + buffer_zero_sse2, +#ifdef CONFIG_AVX2_OPT + buffer_zero_avx2, +#endif +}; + +static unsigned best_accel(void) +{ + unsigned info =3D cpuinfo_init(); + +#ifdef CONFIG_AVX2_OPT + if (info & CPUINFO_AVX2) { + return 2; + } +#endif + return info & CPUINFO_SSE2 ? 1 : 0; +} + +#else +# include "host/include/generic/host/bufferiszero.c.inc" +#endif --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7193dbb74sm74402865ad.56.2026.01.18.14.04.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:04:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768773884; x=1769378684; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cwGPpfxzsG4LOsiRJ3NVV7jG3uJ4HK6BFewRFRnb1bM=; b=L68JrP6Ie+SOKS2bFMK18qD6m0VhVgwWvAs47ZSca1ieY3/2IN883v2Zu/04baHEYJ WCwyA1uZb8Il9cbnnz6DUr5fTai1SFLmQM0f/zaYXZPxe13roNva5OcvNVMl1o73YyLT bDa+kavzVQB4G1tXW0wnuwgQtZBNOoc8XpGKVSk+LZ3PCZ32XIb1j5tuWjQRuZy9gBka Mm7qgyQ2bvLBs17NJcrsgl6S88Lbp1FTo5CMEX18PC1SpFEJyWtVoH9QvPhKmz6iTZLy irK3wc5/IHF/K7bH8zlXsS4vNVQkE6o3BHlIudGrx+UM84m71nJ2tkXCj0pYAodtW2Xv hhOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768773884; x=1769378684; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=cwGPpfxzsG4LOsiRJ3NVV7jG3uJ4HK6BFewRFRnb1bM=; b=ZpWCkQcv7onP139jaa1XdcO1o8estTivQp5ClM51OLMPbvGhOIcHcl7NsX/v+DxWuM M0kaQSdWQhpfK7H18MOC5bORF4yQ3K/INGikyxciky9gC7ylQ6pFpYcm5PkV5w1kKIIS PAPqWCa2x3xtTPMEnSHLsoR1d8wqJKpQ5QvZKi4vWtkaowqFepkK5VEfe0ts2vupVVtd pPgG5xLE910fx3D3RJJIJ7iUVjbU1oPuA44zPLY1TRFGNkz7WsaWnp8henJeYUKq16nB xr0w0FK1kVpjlZ9igTIHbgUEBBFw79oZul1j6aotbz2vneqBYCXOYp3H54Qymu3FleT9 FLqQ== X-Gm-Message-State: AOJu0Yw4gkaOQ2ba+YzhAjWOfXAQA924WAQCrBKdwMZhxeQb/pJVyDe8 MFUt129LwgyhPyC5Va3mKleVDGS47Hs6Ixh8ifGW8Z8LYvMJyvclGV9+4FrDwuiQdzZuImIrKeH IrVUEu5R3Kg== X-Gm-Gg: AY/fxX5QmBNSNywghv2bGQvaySj5fRyPThPLjLN9d913gfxLYDBtLTg0S5IASaR4rp0 gaIckilBxGD4WfS/+M2dt7lQzR+2K6UO2W6PlBmgf2BOYEm/42r3ToX599uu5tr5FAkyIcKa7iS 0TZhp0wE1l1NMyuOT47SN01+626dz1FCN/cD8jL5BvHQV1GPeJ3Rl4+RShxRtNZaJtPJLqDiudy yTaYadu4p3tYy9k8sfO2mw5lBEIQl4+BWm+cwe/pYr6yK57lZtvqTL5gZXh/XHo2dOyvDJs1eQX 1KWHT46698/oHOePMftGlexhhEbWDWnRvPF8hP0PhkQfV59UVz+hvk5jSKP9fAfVftdXbW9df+P PBc+F0/xmih9YiZ52cOSKkJ/VvzP2o32mAOv3LeTYKeU+DadN304lNbmPYelN41QZfzcQtpX17f tbVQKkGqSYIKRU9gJTaQ== X-Received: by 2002:a17:902:ce0a:b0:2a3:e7b6:ab53 with SMTP id d9443c01a7336-2a717554c25mr93798745ad.22.1768773883744; Sun, 18 Jan 2026 14:04:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Thomas Huth , Pierrick Bouvier Subject: [PULL 10/54] host/include/x86_64/bufferiszero: Remove no SSE2 fallback Date: Mon, 19 Jan 2026 09:03:30 +1100 Message-ID: <20260118220414.8177-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768773956150158500 Content-Type: text/plain; charset="utf-8" Since x86_64 always has SSE2, we can remove the fallback that was present for i686. Reviewed-by: Thomas Huth Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- host/include/x86_64/host/bufferiszero.c.inc | 5 ----- 1 file changed, 5 deletions(-) diff --git a/host/include/x86_64/host/bufferiszero.c.inc b/host/include/x86= _64/host/bufferiszero.c.inc index 74ae98580f..7e9d896a8d 100644 --- a/host/include/x86_64/host/bufferiszero.c.inc +++ b/host/include/x86_64/host/bufferiszero.c.inc @@ -3,7 +3,6 @@ * buffer_is_zero acceleration, x86 version. */ =20 -#if defined(CONFIG_AVX2_OPT) || defined(__SSE2__) #include =20 /* Helper for preventing the compiler from reassociating @@ -119,7 +118,3 @@ static unsigned best_accel(void) #endif return info & CPUINFO_SSE2 ? 1 : 0; } - -#else -# include "host/include/generic/host/bufferiszero.c.inc" -#endif --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768773935; cv=none; d=zohomail.com; s=zohoarc; b=KDaFLI4naTF5xl2q5+zXPRDFFl9XPS49yfgxgWvLQZpSgij8BKlKYCOViQBA7+PUpyKSCXb/7Cetj957R0MatZmR4zI+f/b7Ch1f7ymU2e9AwSIKQQc5O1inQBw4f4ieA/xp2JgJgIIDBZvVznGw632l7unrDTEGrwhiq7OJmj0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768773935; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=RAjiwiRuOWizs0EGl+79VhmlGSH6tR7oUS2c/1ByVNA=; b=jLY0rjTRxfpKAugx52VmvdlLlCKrZ5V35cH5SK5T2zw0g8CKirw2JW4vgYmSiPpIOuN01Ev75Mr5ikrYMDrGbZEfA9ydw5dxhgiLogaPiRfsZRQS8DXyu8ENXhN0WiLsO8FbiGtBL+8lOeh1pFqtZ1pMAqk1nzHbaPyUDzxq2y0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176877393534666.195231573059; Sun, 18 Jan 2026 14:05:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhatA-0001i8-85; Sun, 18 Jan 2026 17:04:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhat7-0001PQ-J6 for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:49 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhat5-0000Vm-Qk for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:49 -0500 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-2a110548cdeso24515255ad.0 for ; Sun, 18 Jan 2026 14:04:47 -0800 (PST) Received: from stoup.. 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Reviewed-by: Thomas Huth Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- configure | 16 +--------------- meson.build | 49 ++++++++++--------------------------------------- 2 files changed, 11 insertions(+), 54 deletions(-) diff --git a/configure b/configure index de0f3a8ebe..e9d0b9e2c0 100755 --- a/configure +++ b/configure @@ -447,13 +447,6 @@ case "$cpu" in linux_arch=3Darm64 ;; =20 - i386|i486|i586|i686) - cpu=3D"i386" - host_arch=3Di386 - linux_arch=3Dx86 - CPU_CFLAGS=3D"-m32" - ;; - loongarch*) cpu=3Dloongarch64 host_arch=3Dloongarch64 @@ -1944,14 +1937,7 @@ if test "$skip_meson" =3D no; then if test "$cross_compile" =3D "yes"; then echo "[host_machine]" >> $cross echo "system =3D '$host_os'" >> $cross - case "$cpu" in - i386) - echo "cpu_family =3D 'x86'" >> $cross - ;; - *) - echo "cpu_family =3D '$cpu'" >> $cross - ;; - esac + echo "cpu_family =3D '$cpu'" >> $cross echo "cpu =3D '$cpu'" >> $cross if test "$bigendian" =3D "yes" ; then echo "endian =3D 'big'" >> $cross diff --git a/meson.build b/meson.build index 137b2dcdc7..506904c7d7 100644 --- a/meson.build +++ b/meson.build @@ -50,7 +50,7 @@ qapi_trace_events =3D [] =20 bsd_oses =3D ['gnu/kfreebsd', 'freebsd', 'netbsd', 'openbsd', 'dragonfly',= 'darwin'] supported_oses =3D ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', '= sunos', 'linux', 'emscripten'] -supported_cpus =3D ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86', = 'x86_64', +supported_cpus =3D ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86_64= ', 'aarch64', 'loongarch64', 'mips64', 'sparc64', 'wasm64'] =20 cpu =3D host_machine.cpu_family() @@ -265,8 +265,6 @@ enable_modules =3D get_option('modules') \ =20 if cpu not in supported_cpus host_arch =3D 'unknown' -elif cpu =3D=3D 'x86' - host_arch =3D 'i386' elif cpu =3D=3D 'mips64' host_arch =3D 'mips' elif cpu in ['riscv32', 'riscv64'] @@ -275,9 +273,7 @@ else host_arch =3D cpu endif =20 -if cpu =3D=3D 'x86' - kvm_targets =3D ['i386-softmmu'] -elif cpu =3D=3D 'x86_64' +if cpu =3D=3D 'x86_64' kvm_targets =3D ['i386-softmmu', 'x86_64-softmmu'] elif cpu =3D=3D 'aarch64' kvm_targets =3D ['aarch64-softmmu'] @@ -300,9 +296,7 @@ else endif accelerator_targets =3D { 'CONFIG_KVM': kvm_targets } =20 -if cpu =3D=3D 'x86' - xen_targets =3D ['i386-softmmu'] -elif cpu =3D=3D 'x86_64' +if cpu =3D=3D 'x86_64' xen_targets =3D ['i386-softmmu', 'x86_64-softmmu'] elif cpu =3D=3D 'aarch64' # i386 emulator provides xenpv machine type for multiple architectures @@ -391,40 +385,17 @@ endif =20 qemu_isa_flags =3D [] =20 -# __sync_fetch_and_and requires at least -march=3Di486. Many toolchains -# use i686 as default anyway, but for those that don't, an explicit -# specification is necessary -if host_arch =3D=3D 'i386' and not cc.links(''' - static int sfaa(int *ptr) - { - return __sync_fetch_and_and(ptr, 0); - } - - int main(void) - { - int val =3D 42; - val =3D __sync_val_compare_and_swap(&val, 0, 1); - sfaa(&val); - return val; - }''') - qemu_isa_flags +=3D ['-march=3Di486'] -endif - # Pick x86-64 baseline version -if host_arch in ['i386', 'x86_64'] - if get_option('x86_version') =3D=3D '0' and host_arch =3D=3D 'x86_64' +if host_arch =3D=3D 'x86_64' + if get_option('x86_version') =3D=3D '0' error('x86_64-v1 required for x86-64 hosts') endif =20 # add flags for individual instruction set extensions if get_option('x86_version') >=3D '1' - if host_arch =3D=3D 'i386' - qemu_common_flags =3D ['-mfpmath=3Dsse'] + qemu_common_flags - else - # present on basically all processors but technically not part of - # x86-64-v1, so only include -mneeded for x86-64 version 2 and above - qemu_isa_flags +=3D ['-mcx16'] - endif + # present on basically all processors but technically not part of + # x86-64-v1, so only include -mneeded for x86-64 version 2 and above + qemu_isa_flags +=3D ['-mcx16'] endif if get_option('x86_version') >=3D '2' qemu_isa_flags +=3D ['-mpopcnt'] @@ -1040,7 +1011,7 @@ have_xen_pci_passthrough =3D get_option('xen_pci_pass= through') \ error_message: 'Xen PCI passthrough requested but Xen not enabl= ed') \ .require(host_os =3D=3D 'linux', error_message: 'Xen PCI passthrough not available on this platf= orm') \ - .require(cpu =3D=3D 'x86' or cpu =3D=3D 'x86_64', + .require(cpu =3D=3D 'x86_64', error_message: 'Xen PCI passthrough not available on this platf= orm') \ .allowed() =20 @@ -4564,7 +4535,7 @@ if have_tools libcap_ng, mpathpersist], install: true) =20 - if cpu in ['x86', 'x86_64'] + if cpu =3D=3D 'x86_64' executable('qemu-vmsr-helper', files('tools/i386/qemu-vmsr-helper.c'= ), dependencies: [authz, crypto, io, qom, qemuutil, libcap_ng, mpathpersist], --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774106; cv=none; d=zohomail.com; s=zohoarc; b=gE/sATq6kYfQJD6lv1Xu7nOGjcf6oAYAZmr86fQPeUcKh495AucExPmgiYb+zi1zjItmKfygE5k2urOjrCW6n4CiaLEdzyWoDxk1QyEk8bnKPk3LkKI7HScgfTvciYVDVUiLATt1I5YEFm1uwRWgq5f7K52TW5Adz+0o7S0lDlI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768774106; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=UanRVIi+nePBx9P9C2dWtHxLGCeZ+PWfJ962yXiADQc=; b=P+Y91t9JNLS7VdiKnML+Oq2ugWl5pWz0cLsr9KjCbMlXTTG+6sdPSGSXUeAY84lPtY4e4kzkUa+zQ9C7csu3eZ6vum8Ruc+dNvSJhNe5jByD/HNwzWim++6PL3Htmk5KE5jG+UdupSHoQCXluark+F9lg0nfBK+NR9nlJR0Yg4E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768774106046767.0207743807646; Sun, 18 Jan 2026 14:08:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhatI-00023H-3r; Sun, 18 Jan 2026 17:05:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhatB-0001pj-5w for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:53 -0500 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhat8-0000WJ-Ej for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:52 -0500 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-2a1022dda33so22054835ad.2 for ; Sun, 18 Jan 2026 14:04:50 -0800 (PST) Received: from stoup.. ([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7193dbb74sm74402865ad.56.2026.01.18.14.04.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:04:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768773889; x=1769378689; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UanRVIi+nePBx9P9C2dWtHxLGCeZ+PWfJ962yXiADQc=; b=BitKkuLNRHvAcIgf58hxp8T30f8baegGgA1O7hj7K81Vf0/nvhQxxFemTIpHoUY2Bf Bw323PSnTXlW2c9U4ldgqgZiHy1AQuiewkl0Vob6+93YpTP6JCTb/oTFA497q4fNIwVs oKsx45+DZ7ecdXbG/kCa74lGl9/+arG1s8fXnhGpOt+p0cM2j6/Rxdda/p3LE+/OeHR7 ISUEgg8+qAfPKjNoMiLeNdkK6yzfx3ygegioVum5kf20LsHRRF81coCX3/x9lstMHxyw aEA8qT0VU1nNwKLC4/pWyJOHzGtR4bQRpRgK9VwWaRqGh1AvilUgW1RJMNbSpGzuAW8k 3u4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768773889; x=1769378689; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=UanRVIi+nePBx9P9C2dWtHxLGCeZ+PWfJ962yXiADQc=; b=qf54zAe8nNORpWpzuSeH60BzkVQF7JVjBPe2bD5/KoZhbEaSTsoAcHPQMXyYjbky/r oDv6QpV73Aexrle7btYzndXj1Zo/QNfuUMjs1ZaJS28XkV4jB4S2FY+qE+JZXOHJnzkV 7iCBW+pHSsKviZkwL6kPoBVDJ9yKBDG2GzMS2EkuMPd5YcIkR9Yq/7lzPM6/HlWikgMF /2Cfgtp/jaquQJO31emK9mv91U3oF+PB3x28tUKZ9x64QhRwqL+laoMgPYM1dzWB9VD9 D8Uyl+CotS7aeyC+oKOy8qs2xkR0Utm359pfWrpaGTVooFtZeC9ZIQh6YmD48JolRlhU z7kA== X-Gm-Message-State: AOJu0YzZULAFyaQkLP4ZQzKbiMkEUvNBunH35Zf2MxKyCeMC/wuzOeTX miGWITPGQXZYFZLLlmvBv4V464j3bTpuQLP36jrGUIRpxgp2bQFIYbbBFPfdrvykTkZSAUdI79L Surqw6RtUBA== X-Gm-Gg: AY/fxX5F51zhte45Wxo3wAaKPAPrleocwtgVs2huMTSr3jCQ9mu8ubvo1k7WjrQJpbm U6ZHmH9FGfo652xAOH9WHS37eXtaOn99iKOb0hrxRyj0rqp3GmxUjj9Lhy2kEUwyRnR5cOItE3A bRU0pL+55I5V/1L7BF19wxsicfbPxb1W4KnUEzIY4M5/lMjoW0T0XB/GhwmTYgURkoUWaDT8XwS NFjBktPyJarf5h50MDWqj+fJhqBPkWtbbdYdtlfR9gmo7aGNXYqIzvw/37AR3rQ4RwukmE27//m hXwg/q9ISn6vniPW+C/Cz0hV/nh3N7m0LLGeq5nJKGHz/+bI+DXa9UnonBKt/rl9iKtXyQTOuIp t3OCzBZXiN38kZ9x65WPlx65ZX9WL2gnZ1Z+z+TP6B8bHkIsi3CLl3ZHpxqPDFJnKnCaV0XXOyw GuvKtg6tcHQW6xM8K4ZMWG0l4SePO4 X-Received: by 2002:a17:902:cf4c:b0:29f:2734:6ffb with SMTP id d9443c01a7336-2a717545acamr94899975ad.22.1768773888664; Sun, 18 Jan 2026 14:04:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Thomas Huth , Pierrick Bouvier Subject: [PULL 12/54] *: Remove ppc host support Date: Mon, 19 Jan 2026 09:03:32 +1100 Message-ID: <20260118220414.8177-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774106653158500 Content-Type: text/plain; charset="utf-8" Move the files from host/include/ppc to host/include/ppc64, replacing the stub headers that redirected to ppc. Remove linux-user/include/host/ppc. Remove common-user/host/ppc. Remove cpu =3D=3D ppc tests from meson. Reviewed-by: Thomas Huth Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- host/include/ppc/host/cpuinfo.h | 30 ---- host/include/ppc/host/crypto/aes-round.h | 182 -------------------- host/include/ppc64/host/cpuinfo.h | 31 +++- host/include/ppc64/host/crypto/aes-round.h | 183 ++++++++++++++++++++- linux-user/include/host/ppc/host-signal.h | 39 ----- common-user/host/ppc/safe-syscall.inc.S | 107 ------------ meson.build | 4 +- 7 files changed, 213 insertions(+), 363 deletions(-) delete mode 100644 host/include/ppc/host/cpuinfo.h delete mode 100644 host/include/ppc/host/crypto/aes-round.h delete mode 100644 linux-user/include/host/ppc/host-signal.h delete mode 100644 common-user/host/ppc/safe-syscall.inc.S diff --git a/host/include/ppc/host/cpuinfo.h b/host/include/ppc/host/cpuinf= o.h deleted file mode 100644 index 38b8eabe2a..0000000000 --- a/host/include/ppc/host/cpuinfo.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0-or-later - * Host specific cpu identification for ppc. - */ - -#ifndef HOST_CPUINFO_H -#define HOST_CPUINFO_H - -/* Digested version of */ - -#define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */ -#define CPUINFO_V2_06 (1u << 1) -#define CPUINFO_V2_07 (1u << 2) -#define CPUINFO_V3_0 (1u << 3) -#define CPUINFO_V3_1 (1u << 4) -#define CPUINFO_ISEL (1u << 5) -#define CPUINFO_ALTIVEC (1u << 6) -#define CPUINFO_VSX (1u << 7) -#define CPUINFO_CRYPTO (1u << 8) - -/* Initialized with a constructor. */ -extern unsigned cpuinfo; - -/* - * We cannot rely on constructor ordering, so other constructors must - * use the function interface rather than the variable above. - */ -unsigned cpuinfo_init(void); - -#endif /* HOST_CPUINFO_H */ diff --git a/host/include/ppc/host/crypto/aes-round.h b/host/include/ppc/ho= st/crypto/aes-round.h deleted file mode 100644 index 8062d2a537..0000000000 --- a/host/include/ppc/host/crypto/aes-round.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Power v2.07 specific aes acceleration. - * SPDX-License-Identifier: GPL-2.0-or-later - */ - -#ifndef PPC_HOST_CRYPTO_AES_ROUND_H -#define PPC_HOST_CRYPTO_AES_ROUND_H - -#ifdef __ALTIVEC__ -#include "host/cpuinfo.h" - -#ifdef __CRYPTO__ -# define HAVE_AES_ACCEL true -#else -# define HAVE_AES_ACCEL likely(cpuinfo & CPUINFO_CRYPTO) -#endif -#define ATTR_AES_ACCEL - -/* - * While there is , both gcc and clang "aid" with the - * endianness issues in different ways. Just use inline asm instead. - */ - -/* Bytes in memory are host-endian; bytes in register are @be. */ -static inline AESStateVec aes_accel_ld(const AESState *p, bool be) -{ - AESStateVec r; - - if (be) { - asm("lvx %0, 0, %1" : "=3Dv"(r) : "r"(p), "m"(*p)); - } else if (HOST_BIG_ENDIAN) { - AESStateVec rev =3D { - 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, - }; - asm("lvx %0, 0, %1\n\t" - "vperm %0, %0, %0, %2" - : "=3Dv"(r) : "r"(p), "v"(rev), "m"(*p)); - } else { -#ifdef __POWER9_VECTOR__ - asm("lxvb16x %x0, 0, %1" : "=3Dv"(r) : "r"(p), "m"(*p)); -#else - asm("lxvd2x %x0, 0, %1\n\t" - "xxpermdi %x0, %x0, %x0, 2" - : "=3Dv"(r) : "r"(p), "m"(*p)); -#endif - } - return r; -} - -static void aes_accel_st(AESState *p, AESStateVec r, bool be) -{ - if (be) { - asm("stvx %1, 0, %2" : "=3Dm"(*p) : "v"(r), "r"(p)); - } else if (HOST_BIG_ENDIAN) { - AESStateVec rev =3D { - 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, - }; - asm("vperm %1, %1, %1, %2\n\t" - "stvx %1, 0, %3" - : "=3Dm"(*p), "+v"(r) : "v"(rev), "r"(p)); - } else { -#ifdef __POWER9_VECTOR__ - asm("stxvb16x %x1, 0, %2" : "=3Dm"(*p) : "v"(r), "r"(p)); -#else - asm("xxpermdi %x1, %x1, %x1, 2\n\t" - "stxvd2x %x1, 0, %2" - : "=3Dm"(*p), "+v"(r) : "r"(p)); -#endif - } -} - -static inline AESStateVec aes_accel_vcipher(AESStateVec d, AESStateVec k) -{ - asm("vcipher %0, %0, %1" : "+v"(d) : "v"(k)); - return d; -} - -static inline AESStateVec aes_accel_vncipher(AESStateVec d, AESStateVec k) -{ - asm("vncipher %0, %0, %1" : "+v"(d) : "v"(k)); - return d; -} - -static inline AESStateVec aes_accel_vcipherlast(AESStateVec d, AESStateVec= k) -{ - asm("vcipherlast %0, %0, %1" : "+v"(d) : "v"(k)); - return d; -} - -static inline AESStateVec aes_accel_vncipherlast(AESStateVec d, AESStateVe= c k) -{ - asm("vncipherlast %0, %0, %1" : "+v"(d) : "v"(k)); - return d; -} - -static inline void -aesenc_MC_accel(AESState *ret, const AESState *st, bool be) -{ - AESStateVec t, z =3D { }; - - t =3D aes_accel_ld(st, be); - t =3D aes_accel_vncipherlast(t, z); - t =3D aes_accel_vcipher(t, z); - aes_accel_st(ret, t, be); -} - -static inline void -aesenc_SB_SR_AK_accel(AESState *ret, const AESState *st, - const AESState *rk, bool be) -{ - AESStateVec t, k; - - t =3D aes_accel_ld(st, be); - k =3D aes_accel_ld(rk, be); - t =3D aes_accel_vcipherlast(t, k); - aes_accel_st(ret, t, be); -} - -static inline void -aesenc_SB_SR_MC_AK_accel(AESState *ret, const AESState *st, - const AESState *rk, bool be) -{ - AESStateVec t, k; - - t =3D aes_accel_ld(st, be); - k =3D aes_accel_ld(rk, be); - t =3D aes_accel_vcipher(t, k); - aes_accel_st(ret, t, be); -} - -static inline void -aesdec_IMC_accel(AESState *ret, const AESState *st, bool be) -{ - AESStateVec t, z =3D { }; - - t =3D aes_accel_ld(st, be); - t =3D aes_accel_vcipherlast(t, z); - t =3D aes_accel_vncipher(t, z); - aes_accel_st(ret, t, be); -} - -static inline void -aesdec_ISB_ISR_AK_accel(AESState *ret, const AESState *st, - const AESState *rk, bool be) -{ - AESStateVec t, k; - - t =3D aes_accel_ld(st, be); - k =3D aes_accel_ld(rk, be); - t =3D aes_accel_vncipherlast(t, k); - aes_accel_st(ret, t, be); -} - -static inline void -aesdec_ISB_ISR_AK_IMC_accel(AESState *ret, const AESState *st, - const AESState *rk, bool be) -{ - AESStateVec t, k; - - t =3D aes_accel_ld(st, be); - k =3D aes_accel_ld(rk, be); - t =3D aes_accel_vncipher(t, k); - aes_accel_st(ret, t, be); -} - -static inline void -aesdec_ISB_ISR_IMC_AK_accel(AESState *ret, const AESState *st, - const AESState *rk, bool be) -{ - AESStateVec t, k, z =3D { }; - - t =3D aes_accel_ld(st, be); - k =3D aes_accel_ld(rk, be); - t =3D aes_accel_vncipher(t, z); - aes_accel_st(ret, t ^ k, be); -} -#else -/* Without ALTIVEC, we can't even write inline assembly. */ -#include "host/include/generic/host/crypto/aes-round.h" -#endif - -#endif /* PPC_HOST_CRYPTO_AES_ROUND_H */ diff --git a/host/include/ppc64/host/cpuinfo.h b/host/include/ppc64/host/cp= uinfo.h index 2f036a0627..38b8eabe2a 100644 --- a/host/include/ppc64/host/cpuinfo.h +++ b/host/include/ppc64/host/cpuinfo.h @@ -1 +1,30 @@ -#include "host/include/ppc/host/cpuinfo.h" +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Host specific cpu identification for ppc. + */ + +#ifndef HOST_CPUINFO_H +#define HOST_CPUINFO_H + +/* Digested version of */ + +#define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */ +#define CPUINFO_V2_06 (1u << 1) +#define CPUINFO_V2_07 (1u << 2) +#define CPUINFO_V3_0 (1u << 3) +#define CPUINFO_V3_1 (1u << 4) +#define CPUINFO_ISEL (1u << 5) +#define CPUINFO_ALTIVEC (1u << 6) +#define CPUINFO_VSX (1u << 7) +#define CPUINFO_CRYPTO (1u << 8) + +/* Initialized with a constructor. */ +extern unsigned cpuinfo; + +/* + * We cannot rely on constructor ordering, so other constructors must + * use the function interface rather than the variable above. + */ +unsigned cpuinfo_init(void); + +#endif /* HOST_CPUINFO_H */ diff --git a/host/include/ppc64/host/crypto/aes-round.h b/host/include/ppc6= 4/host/crypto/aes-round.h index 5eeba6dcb7..8062d2a537 100644 --- a/host/include/ppc64/host/crypto/aes-round.h +++ b/host/include/ppc64/host/crypto/aes-round.h @@ -1 +1,182 @@ -#include "host/include/ppc/host/crypto/aes-round.h" +/* + * Power v2.07 specific aes acceleration. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef PPC_HOST_CRYPTO_AES_ROUND_H +#define PPC_HOST_CRYPTO_AES_ROUND_H + +#ifdef __ALTIVEC__ +#include "host/cpuinfo.h" + +#ifdef __CRYPTO__ +# define HAVE_AES_ACCEL true +#else +# define HAVE_AES_ACCEL likely(cpuinfo & CPUINFO_CRYPTO) +#endif +#define ATTR_AES_ACCEL + +/* + * While there is , both gcc and clang "aid" with the + * endianness issues in different ways. Just use inline asm instead. + */ + +/* Bytes in memory are host-endian; bytes in register are @be. */ +static inline AESStateVec aes_accel_ld(const AESState *p, bool be) +{ + AESStateVec r; + + if (be) { + asm("lvx %0, 0, %1" : "=3Dv"(r) : "r"(p), "m"(*p)); + } else if (HOST_BIG_ENDIAN) { + AESStateVec rev =3D { + 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, + }; + asm("lvx %0, 0, %1\n\t" + "vperm %0, %0, %0, %2" + : "=3Dv"(r) : "r"(p), "v"(rev), "m"(*p)); + } else { +#ifdef __POWER9_VECTOR__ + asm("lxvb16x %x0, 0, %1" : "=3Dv"(r) : "r"(p), "m"(*p)); +#else + asm("lxvd2x %x0, 0, %1\n\t" + "xxpermdi %x0, %x0, %x0, 2" + : "=3Dv"(r) : "r"(p), "m"(*p)); +#endif + } + return r; +} + +static void aes_accel_st(AESState *p, AESStateVec r, bool be) +{ + if (be) { + asm("stvx %1, 0, %2" : "=3Dm"(*p) : "v"(r), "r"(p)); + } else if (HOST_BIG_ENDIAN) { + AESStateVec rev =3D { + 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, + }; + asm("vperm %1, %1, %1, %2\n\t" + "stvx %1, 0, %3" + : "=3Dm"(*p), "+v"(r) : "v"(rev), "r"(p)); + } else { +#ifdef __POWER9_VECTOR__ + asm("stxvb16x %x1, 0, %2" : "=3Dm"(*p) : "v"(r), "r"(p)); +#else + asm("xxpermdi %x1, %x1, %x1, 2\n\t" + "stxvd2x %x1, 0, %2" + : "=3Dm"(*p), "+v"(r) : "r"(p)); +#endif + } +} + +static inline AESStateVec aes_accel_vcipher(AESStateVec d, AESStateVec k) +{ + asm("vcipher %0, %0, %1" : "+v"(d) : "v"(k)); + return d; +} + +static inline AESStateVec aes_accel_vncipher(AESStateVec d, AESStateVec k) +{ + asm("vncipher %0, %0, %1" : "+v"(d) : "v"(k)); + return d; +} + +static inline AESStateVec aes_accel_vcipherlast(AESStateVec d, AESStateVec= k) +{ + asm("vcipherlast %0, %0, %1" : "+v"(d) : "v"(k)); + return d; +} + +static inline AESStateVec aes_accel_vncipherlast(AESStateVec d, AESStateVe= c k) +{ + asm("vncipherlast %0, %0, %1" : "+v"(d) : "v"(k)); + return d; +} + +static inline void +aesenc_MC_accel(AESState *ret, const AESState *st, bool be) +{ + AESStateVec t, z =3D { }; + + t =3D aes_accel_ld(st, be); + t =3D aes_accel_vncipherlast(t, z); + t =3D aes_accel_vcipher(t, z); + aes_accel_st(ret, t, be); +} + +static inline void +aesenc_SB_SR_AK_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + AESStateVec t, k; + + t =3D aes_accel_ld(st, be); + k =3D aes_accel_ld(rk, be); + t =3D aes_accel_vcipherlast(t, k); + aes_accel_st(ret, t, be); +} + +static inline void +aesenc_SB_SR_MC_AK_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + AESStateVec t, k; + + t =3D aes_accel_ld(st, be); + k =3D aes_accel_ld(rk, be); + t =3D aes_accel_vcipher(t, k); + aes_accel_st(ret, t, be); +} + +static inline void +aesdec_IMC_accel(AESState *ret, const AESState *st, bool be) +{ + AESStateVec t, z =3D { }; + + t =3D aes_accel_ld(st, be); + t =3D aes_accel_vcipherlast(t, z); + t =3D aes_accel_vncipher(t, z); + aes_accel_st(ret, t, be); +} + +static inline void +aesdec_ISB_ISR_AK_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + AESStateVec t, k; + + t =3D aes_accel_ld(st, be); + k =3D aes_accel_ld(rk, be); + t =3D aes_accel_vncipherlast(t, k); + aes_accel_st(ret, t, be); +} + +static inline void +aesdec_ISB_ISR_AK_IMC_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + AESStateVec t, k; + + t =3D aes_accel_ld(st, be); + k =3D aes_accel_ld(rk, be); + t =3D aes_accel_vncipher(t, k); + aes_accel_st(ret, t, be); +} + +static inline void +aesdec_ISB_ISR_IMC_AK_accel(AESState *ret, const AESState *st, + const AESState *rk, bool be) +{ + AESStateVec t, k, z =3D { }; + + t =3D aes_accel_ld(st, be); + k =3D aes_accel_ld(rk, be); + t =3D aes_accel_vncipher(t, z); + aes_accel_st(ret, t ^ k, be); +} +#else +/* Without ALTIVEC, we can't even write inline assembly. */ +#include "host/include/generic/host/crypto/aes-round.h" +#endif + +#endif /* PPC_HOST_CRYPTO_AES_ROUND_H */ diff --git a/linux-user/include/host/ppc/host-signal.h b/linux-user/include= /host/ppc/host-signal.h deleted file mode 100644 index de25c803f5..0000000000 --- a/linux-user/include/host/ppc/host-signal.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * host-signal.h: signal info dependent on the host architecture - * - * Copyright (c) 2022 Linaro Ltd. - * - * This work is licensed under the terms of the GNU LGPL, version 2.1 or l= ater. - * See the COPYING file in the top-level directory. - */ - -#ifndef PPC_HOST_SIGNAL_H -#define PPC_HOST_SIGNAL_H - -#include - -/* The third argument to a SA_SIGINFO handler is ucontext_t. */ -typedef ucontext_t host_sigcontext; - -static inline uintptr_t host_signal_pc(host_sigcontext *uc) -{ - return uc->uc_mcontext.regs->nip; -} - -static inline void host_signal_set_pc(host_sigcontext *uc, uintptr_t pc) -{ - uc->uc_mcontext.regs->nip =3D pc; -} - -static inline void *host_signal_mask(host_sigcontext *uc) -{ - return &uc->uc_sigmask; -} - -static inline bool host_signal_write(siginfo_t *info, host_sigcontext *uc) -{ - return uc->uc_mcontext.regs->trap !=3D 0x400 - && (uc->uc_mcontext.regs->dsisr & 0x02000000); -} - -#endif diff --git a/common-user/host/ppc/safe-syscall.inc.S b/common-user/host/ppc= /safe-syscall.inc.S deleted file mode 100644 index 0851f6c0b8..0000000000 --- a/common-user/host/ppc/safe-syscall.inc.S +++ /dev/null @@ -1,107 +0,0 @@ -/* - * safe-syscall.inc.S : host-specific assembly fragment - * to handle signals occurring at the same time as system calls. - * This is intended to be included by common-user/safe-syscall.S - * - * Copyright (C) 2022 Linaro, Ltd. - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - */ - -/* - * Standardize on the _CALL_FOO symbols used by GCC: - * Apple XCode does not define _CALL_DARWIN. - * Clang defines _CALL_ELF (64-bit) but not _CALL_SYSV (32-bit). - */ -#if !defined(_CALL_SYSV) && \ - !defined(_CALL_DARWIN) && \ - !defined(_CALL_AIX) && \ - !defined(_CALL_ELF) -# if defined(__APPLE__) -# define _CALL_DARWIN -# elif defined(__ELF__) && TCG_TARGET_REG_BITS =3D=3D 32 -# define _CALL_SYSV -# else -# error "Unknown ABI" -# endif -#endif=20 - -#ifndef _CALL_SYSV -# error "Unsupported ABI" -#endif - - - .global safe_syscall_base - .global safe_syscall_start - .global safe_syscall_end - .type safe_syscall_base, @function - - .text - - /* - * This is the entry point for making a system call. The calling - * convention here is that of a C varargs function with the - * first argument an 'int *' to the signal_pending flag, the - * second one the system call number (as a 'long'), and all further - * arguments being syscall arguments (also 'long'). - */ -safe_syscall_base: - .cfi_startproc - stwu 1, -8(1) - .cfi_def_cfa_offset 8 - stw 30, 4(1) - .cfi_offset 30, -4 - - /* - * We enter with r3 =3D=3D &signal_pending - * r4 =3D=3D syscall number - * r5 ... r10 =3D=3D syscall arguments - * and return the result in r3 - * and the syscall instruction needs - * r0 =3D=3D syscall number - * r3 ... r8 =3D=3D syscall arguments - * and returns the result in r3 - * Shuffle everything around appropriately. - */ - mr 30, 3 /* signal_pending */ - mr 0, 4 /* syscall number */ - mr 3, 5 /* syscall arguments */ - mr 4, 6 - mr 5, 7 - mr 6, 8 - mr 7, 9 - mr 8, 10 - - /* - * This next sequence of code works in conjunction with the - * rewind_if_safe_syscall_function(). If a signal is taken - * and the interrupted PC is anywhere between 'safe_syscall_start' - * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start= '. - * The code sequence must therefore be able to cope with this, and - * the syscall instruction must be the final one in the sequence. - */ -safe_syscall_start: - /* if signal_pending is non-zero, don't do the call */ - lwz 12, 0(30) - cmpwi 0, 12, 0 - bne- 2f - sc -safe_syscall_end: - /* code path when we did execute the syscall */ - lwz 30, 4(1) /* restore r30 */ - addi 1, 1, 8 /* restore stack */ - .cfi_restore 30 - .cfi_def_cfa_offset 0 - bnslr+ /* return on success */ - b safe_syscall_set_errno_tail - - /* code path when we didn't execute the syscall */ -2: lwz 30, 4(1) - addi 1, 1, 8 - addi 3, 0, QEMU_ERESTARTSYS - b safe_syscall_set_errno_tail - - .cfi_endproc - - .size safe_syscall_base, .-safe_syscall_base diff --git a/meson.build b/meson.build index 506904c7d7..7993e4cfb9 100644 --- a/meson.build +++ b/meson.build @@ -50,7 +50,7 @@ qapi_trace_events =3D [] =20 bsd_oses =3D ['gnu/kfreebsd', 'freebsd', 'netbsd', 'openbsd', 'dragonfly',= 'darwin'] supported_oses =3D ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', '= sunos', 'linux', 'emscripten'] -supported_cpus =3D ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86_64= ', +supported_cpus =3D ['ppc64', 's390x', 'riscv32', 'riscv64', 'x86_64', 'aarch64', 'loongarch64', 'mips64', 'sparc64', 'wasm64'] =20 cpu =3D host_machine.cpu_family() @@ -279,8 +279,6 @@ elif cpu =3D=3D 'aarch64' kvm_targets =3D ['aarch64-softmmu'] elif cpu =3D=3D 's390x' kvm_targets =3D ['s390x-softmmu'] -elif cpu =3D=3D 'ppc' - kvm_targets =3D ['ppc-softmmu'] elif cpu =3D=3D 'ppc64' kvm_targets =3D ['ppc-softmmu', 'ppc64-softmmu'] elif cpu =3D=3D 'mips64' --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774034; cv=none; d=zohomail.com; s=zohoarc; b=ZJ5mQ1J6DZm3sUb23ivBri7SJi3elnTOmeV8wK6/V1nbNLpuz21F3cz3Nu4CS0mpYKC073Zyk+lROjUnD2iprxGqsHOPnIKCsXsDJqhVovQQ/c6SjqQefDL4sZQ7kDlix4tBVjByqEhl2k3PgnyBeC0Tc6izLoZOi/iW4rgaCaY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768774034; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=26CJFt5jjtAelHleKcbXjpkWlgqm8e67WTCdKTvoCXk=; b=WrMVIvTd+oy3v2kUTI+Fm0RxOmAOxFpDInPHBQs7XwSd/zgvi2zDMSy08f3w0qY8hcEUG81UXYy5JsjsjY4aavT8fF1JBpqBiwb/Y+X1fq2NOcSTkk8szxsq8/r3u2G79VNlTOSmv4mR40uW0pWwXk+QVgzn3kkptms9xTAcFzk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768774034803485.98011448252646; Sun, 18 Jan 2026 14:07:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhatw-0003f5-U3; Sun, 18 Jan 2026 17:05:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhatE-00023E-Di for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:58 -0500 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhatA-0000WV-PL for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:04:56 -0500 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-2a09757004cso33072945ad.3 for ; Sun, 18 Jan 2026 14:04:52 -0800 (PST) Received: from stoup.. ([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7193dbb74sm74402865ad.56.2026.01.18.14.04.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:04:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768773891; x=1769378691; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=26CJFt5jjtAelHleKcbXjpkWlgqm8e67WTCdKTvoCXk=; b=kwBZ4nUO7k5mslAr6zVcuD/PIh5rh8+W0cKJ3sime4kIDLCQlPOtow1cMNG5zHJGrE y3FLXGnSfLvFi0J2y7yJu4keKdjLAI0QjwPFh8E7s48rljIFH7O+5geBCFJvjzqpC2kW XPfAZK+CW8HP21j1ZRsEAXxNyK0FBO5qpU03jLBp2le/e5BCDECAYHuLZcDr2SlReMZc 3iQyowJVr5dcZt9xkgdlkzLu4CcnhWLJsp2vt91KqeyFLEq/Y095eLZCMdmF7qel7i4/ MNNEKzpEJR4uCpOhHYoXw3UiRYnMuqYlnUCXMFC/ZcImhmrCOgA3hRLkTOJNi3rZIXWl wNew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768773891; x=1769378691; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=26CJFt5jjtAelHleKcbXjpkWlgqm8e67WTCdKTvoCXk=; b=ldVFVwPNI2Dc9g5ahxXDYDRpE4MiX30VN2MhgIe2Jhhvzp1v+rLGlV7qaLI/WQRJRc KE7TM5IDoEsmadjuYJLU4OMP24bmktNCHcL+sYuC78RCmAN705YXd+B/1UkG0kK2DRn0 Zfh9YWZR+l2KiiMiQ8rF4KpaTlJFYQsGr9gKHHRsNNfIVYVHTVU01/8D3tk7w92qDiep moeZ2o8i86K9v0tXHbNW6YWMFs1Sw2DVfTrv1QGGGMHQ9i//daif5FYFo+gp7HbGghro ei7JnKT32mgX2Axi8lQLwJ488Q8MQUgWmboQpSCe/Hldow52cZau0ed2O5gdkWBU5YzI VC2Q== X-Gm-Message-State: AOJu0Yzmpt5gVYay6K9KVD8+mRZOQhuHrbq8b+5J9YQxhl4+vIQPL9Gy knNmF4kVYwqPFsUJRU0hgvY+SWxCpB6CL10XBFhXDpm3Iht6jVNRbvsNMdhZbMWWAVPGQa1RI3n LCsNLGMhuRg== X-Gm-Gg: AY/fxX7RriHuTtIEruB5B7Ak2Nsg5Zo3sgLV4PFz6xYeR8AeR9n6qky8Qa6OlvC42Y8 1AM/0PRMNrNaLuQHrv9vuTWxamC7t/ZYAwnfHDvfXp+zFU0VQzgNmLW5J6rku6xAkNpRuJjwRxp xgFluVmr/3PygmKYga2Ps1xHzv9wHqtroHRKdt9pL4DWd0myicBeFxcbYDMFaEnFG3W2LOqAkC+ DZsFCgzRv3AVAX729fOBLi5DT0jep4mVthB3QJ/Fk40DktXY2WyFfHjljDVFtAtBpbrwmgRqIUk Q4zMuk+ENAJbwK61kAhIOj5ua1ul/VNBjGUHuBQoMQFBsSzOAjzfJwBdNcTJKADL3Lu+orgaFpv 7e7YWehIBoIvUDLx5SPailGwrQDtl77XJvHD2sg4sCHrHE/6in6Eai/ydFOU19dXXA4Qp30TUXw 01yuyKsO4a1wymbeC/lg== X-Received: by 2002:a17:903:fae:b0:295:8c51:64ff with SMTP id d9443c01a7336-2a7175a2b50mr81446305ad.29.1768773890997; Sun, 18 Jan 2026 14:04:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Thomas Huth Subject: [PULL 13/54] tcg/i386: Remove TCG_TARGET_REG_BITS tests Date: Mon, 19 Jan 2026 09:03:33 +1100 Message-ID: <20260118220414.8177-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774036428158500 Content-Type: text/plain; charset="utf-8" We now only support 64-bit code generation. Reviewed-by: Thomas Huth Signed-off-by: Richard Henderson --- tcg/i386/tcg-target-has.h | 8 +- tcg/i386/tcg-target-reg-bits.h | 2 +- tcg/i386/tcg-target.h | 13 +- tcg/i386/tcg-target.c.inc | 552 ++++++--------------------------- 4 files changed, 97 insertions(+), 478 deletions(-) diff --git a/tcg/i386/tcg-target-has.h b/tcg/i386/tcg-target-has.h index 42647fabbd..d249c1b3e7 100644 --- a/tcg/i386/tcg-target-has.h +++ b/tcg/i386/tcg-target-has.h @@ -26,13 +26,10 @@ #define have_avx512vbmi2 ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512v= l) =20 /* optional instructions */ -#if TCG_TARGET_REG_BITS =3D=3D 64 /* Keep 32-bit values zero-extended in a register. */ #define TCG_TARGET_HAS_extr_i64_i32 1 -#endif =20 -#define TCG_TARGET_HAS_qemu_ldst_i128 \ - (TCG_TARGET_REG_BITS =3D=3D 64 && (cpuinfo & CPUINFO_ATOMIC_VMOVDQA)) +#define TCG_TARGET_HAS_qemu_ldst_i128 (cpuinfo & CPUINFO_ATOMIC_VMOVDQA) =20 #define TCG_TARGET_HAS_tst 1 =20 @@ -63,8 +60,7 @@ #define TCG_TARGET_HAS_tst_vec have_avx512bw =20 #define TCG_TARGET_deposit_valid(type, ofs, len) \ - (((ofs) =3D=3D 0 && ((len) =3D=3D 8 || (len) =3D=3D 16)) || \ - (TCG_TARGET_REG_BITS =3D=3D 32 && (ofs) =3D=3D 8 && (len) =3D=3D 8)) + ((ofs) =3D=3D 0 && ((len) =3D=3D 8 || (len) =3D=3D 16)) =20 /* * Check for the possibility of low byte/word extraction, high-byte extrac= tion diff --git a/tcg/i386/tcg-target-reg-bits.h b/tcg/i386/tcg-target-reg-bits.h index aa386050eb..fc3377e829 100644 --- a/tcg/i386/tcg-target-reg-bits.h +++ b/tcg/i386/tcg-target-reg-bits.h @@ -10,7 +10,7 @@ #ifdef __x86_64__ # define TCG_TARGET_REG_BITS 64 #else -# define TCG_TARGET_REG_BITS 32 +# error #endif =20 #endif diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 3cbdfbca52..7ebae56a7d 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -27,13 +27,8 @@ =20 #define TCG_TARGET_INSN_UNIT_SIZE 1 =20 -#ifdef __x86_64__ -# define TCG_TARGET_NB_REGS 32 -# define MAX_CODE_GEN_BUFFER_SIZE (2 * GiB) -#else -# define TCG_TARGET_NB_REGS 24 -# define MAX_CODE_GEN_BUFFER_SIZE UINT32_MAX -#endif +#define TCG_TARGET_NB_REGS 32 +#define MAX_CODE_GEN_BUFFER_SIZE (2 * GiB) =20 typedef enum { TCG_REG_EAX =3D 0, @@ -45,8 +40,6 @@ typedef enum { TCG_REG_ESI, TCG_REG_EDI, =20 - /* 64-bit registers; always define the symbols to avoid - too much if-deffing. */ TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, @@ -64,8 +57,6 @@ typedef enum { TCG_REG_XMM5, TCG_REG_XMM6, TCG_REG_XMM7, - - /* 64-bit registers; likewise always define. */ TCG_REG_XMM8, TCG_REG_XMM9, TCG_REG_XMM10, diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index ee27266861..92251f8327 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -34,32 +34,22 @@ #if defined(_WIN64) # define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF # define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_VEC -#elif TCG_TARGET_REG_BITS =3D=3D 64 -# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL -# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL #else # define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL -# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF +# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL #endif =20 #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { -#if TCG_TARGET_REG_BITS =3D=3D 64 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", -#else - "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", -#endif "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7", -#if TCG_TARGET_REG_BITS =3D=3D 64 "%xmm8", "%xmm9", "%xmm10", "%xmm11", "%xmm12", "%xmm13", "%xmm14", "%xmm15", -#endif }; #endif =20 static const int tcg_target_reg_alloc_order[] =3D { -#if TCG_TARGET_REG_BITS =3D=3D 64 TCG_REG_RBP, TCG_REG_RBX, TCG_REG_R12, @@ -75,15 +65,6 @@ static const int tcg_target_reg_alloc_order[] =3D { TCG_REG_RSI, TCG_REG_RDI, TCG_REG_RAX, -#else - TCG_REG_EBX, - TCG_REG_ESI, - TCG_REG_EDI, - TCG_REG_EBP, - TCG_REG_ECX, - TCG_REG_EDX, - TCG_REG_EAX, -#endif TCG_REG_XMM0, TCG_REG_XMM1, TCG_REG_XMM2, @@ -95,7 +76,6 @@ static const int tcg_target_reg_alloc_order[] =3D { any of them. Therefore only allow xmm0-xmm5 to be allocated. */ TCG_REG_XMM6, TCG_REG_XMM7, -#if TCG_TARGET_REG_BITS =3D=3D 64 TCG_REG_XMM8, TCG_REG_XMM9, TCG_REG_XMM10, @@ -105,13 +85,11 @@ static const int tcg_target_reg_alloc_order[] =3D { TCG_REG_XMM14, TCG_REG_XMM15, #endif -#endif }; =20 #define TCG_TMP_VEC TCG_REG_XMM5 =20 static const int tcg_target_call_iarg_regs[] =3D { -#if TCG_TARGET_REG_BITS =3D=3D 64 #if defined(_WIN64) TCG_REG_RCX, TCG_REG_RDX, @@ -123,9 +101,6 @@ static const int tcg_target_call_iarg_regs[] =3D { #endif TCG_REG_R8, TCG_REG_R9, -#else - /* 32 bit mode uses stack based calling convention (GCC default). */ -#endif }; =20 static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) @@ -152,26 +127,13 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnK= ind kind, int slot) #define TCG_CT_CONST_TST 0x1000 #define TCG_CT_CONST_ZERO 0x2000 =20 -/* Registers used with L constraint, which are the first argument - registers on x86_64, and two random call clobbered registers on - i386. */ -#if TCG_TARGET_REG_BITS =3D=3D 64 -# define TCG_REG_L0 tcg_target_call_iarg_regs[0] -# define TCG_REG_L1 tcg_target_call_iarg_regs[1] -#else -# define TCG_REG_L0 TCG_REG_EAX -# define TCG_REG_L1 TCG_REG_EDX -#endif +/* Registers used with L constraint. */ +#define TCG_REG_L0 tcg_target_call_iarg_regs[0] +#define TCG_REG_L1 tcg_target_call_iarg_regs[1] =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -# define ALL_GENERAL_REGS 0x0000ffffu -# define ALL_VECTOR_REGS 0xffff0000u -# define ALL_BYTEL_REGS ALL_GENERAL_REGS -#else -# define ALL_GENERAL_REGS 0x000000ffu -# define ALL_VECTOR_REGS 0x00ff0000u -# define ALL_BYTEL_REGS 0x0000000fu -#endif +#define ALL_GENERAL_REGS 0x0000ffffu +#define ALL_VECTOR_REGS 0xffff0000u +#define ALL_BYTEL_REGS ALL_GENERAL_REGS #define SOFTMMU_RESERVE_REGS \ (tcg_use_softmmu ? (1 << TCG_REG_L0) | (1 << TCG_REG_L1) : 0) =20 @@ -184,14 +146,12 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, intptr_t value, intptr_t addend) { value +=3D addend; - switch(type) { + switch (type) { case R_386_PC32: value -=3D (uintptr_t)tcg_splitwx_to_rx(code_ptr); if (value !=3D (int32_t)value) { return false; } - /* FALLTHRU */ - case R_386_32: tcg_patch32(code_ptr, value); break; case R_386_PC8: @@ -256,17 +216,10 @@ static bool tcg_target_const_match(int64_t val, int c= t, #define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */ #define P_DATA16 0x400 /* 0x66 opcode prefix */ #define P_VEXW 0x1000 /* Set VEX.W =3D 1 */ -#if TCG_TARGET_REG_BITS =3D=3D 64 -# define P_REXW P_VEXW /* Set REX.W =3D 1; match VEXW */ -# define P_REXB_R 0x2000 /* REG field as byte register */ -# define P_REXB_RM 0x4000 /* R/M field as byte register */ -# define P_GS 0x8000 /* gs segment override */ -#else -# define P_REXW 0 -# define P_REXB_R 0 -# define P_REXB_RM 0 -# define P_GS 0 -#endif +#define P_REXW P_VEXW /* Set REX.W =3D 1; match VEXW */ +#define P_REXB_R 0x2000 /* REG field as byte register */ +#define P_REXB_RM 0x4000 /* R/M field as byte register */ +#define P_GS 0x8000 /* gs segment override */ #define P_EXT3A 0x10000 /* 0x0f 0x3a opcode prefix */ #define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */ #define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */ @@ -571,7 +524,6 @@ static const uint8_t tcg_cond_to_jcc[] =3D { [TCG_COND_TSTNE] =3D JCC_JNE, }; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) { int rex; @@ -619,32 +571,6 @@ static void tcg_out_opc(TCGContext *s, int opc, int r,= int rm, int x) =20 tcg_out8(s, opc); } -#else -static void tcg_out_opc(TCGContext *s, int opc) -{ - if (opc & P_DATA16) { - tcg_out8(s, 0x66); - } - if (opc & P_SIMDF3) { - tcg_out8(s, 0xf3); - } else if (opc & P_SIMDF2) { - tcg_out8(s, 0xf2); - } - if (opc & (P_EXT | P_EXT38 | P_EXT3A)) { - tcg_out8(s, 0x0f); - if (opc & P_EXT38) { - tcg_out8(s, 0x38); - } else if (opc & P_EXT3A) { - tcg_out8(s, 0x3a); - } - } - tcg_out8(s, opc); -} -/* Discard the register arguments to tcg_out_opc early, so as not to penal= ize - the 32-bit compilation paths. This method works with all versions of g= cc, - whereas relying on optimization may not be able to exclude them. */ -#define tcg_out_opc(s, opc, r, rm, x) (tcg_out_opc)(s, opc) -#endif =20 static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) { @@ -790,35 +716,32 @@ static void tcg_out_sib_offset(TCGContext *s, int r, = int rm, int index, int mod, len; =20 if (index < 0 && rm < 0) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - /* Try for a rip-relative addressing mode. This has replaced - the 32-bit-mode absolute addressing encoding. */ - intptr_t pc =3D (intptr_t)s->code_ptr + 5 + ~rm; - intptr_t disp =3D offset - pc; - if (disp =3D=3D (int32_t)disp) { - tcg_out8(s, (LOWREGMASK(r) << 3) | 5); - tcg_out32(s, disp); - return; - } + /* + * Try for a rip-relative addressing mode. This has replaced + * the 32-bit-mode absolute addressing encoding. + */ + intptr_t pc =3D (intptr_t)s->code_ptr + 5 + ~rm; + intptr_t disp =3D offset - pc; + if (disp =3D=3D (int32_t)disp) { + tcg_out8(s, (LOWREGMASK(r) << 3) | 5); + tcg_out32(s, disp); + return; + } =20 - /* Try for an absolute address encoding. This requires the - use of the MODRM+SIB encoding and is therefore larger than - rip-relative addressing. */ - if (offset =3D=3D (int32_t)offset) { - tcg_out8(s, (LOWREGMASK(r) << 3) | 4); - tcg_out8(s, (4 << 3) | 5); - tcg_out32(s, offset); - return; - } - - /* ??? The memory isn't directly addressable. */ - g_assert_not_reached(); - } else { - /* Absolute address. */ - tcg_out8(s, (r << 3) | 5); + /* + * Try for an absolute address encoding. This requires the + * use of the MODRM+SIB encoding and is therefore larger than + * rip-relative addressing. + */ + if (offset =3D=3D (int32_t)offset) { + tcg_out8(s, (LOWREGMASK(r) << 3) | 4); + tcg_out8(s, (4 << 3) | 5); tcg_out32(s, offset); return; } + + /* ??? The memory isn't directly addressable. */ + g_assert_not_reached(); } =20 /* Find the length of the immediate addend. Note that the encoding @@ -1045,27 +968,14 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType = type, unsigned vece, return; } =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 && vece < MO_64) { - if (have_avx2) { - tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret); - } else { - tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret); - } - new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); + if (type =3D=3D TCG_TYPE_V64) { + tcg_out_vex_modrm_pool(s, OPC_MOVQ_VqWq, ret); + } else if (have_avx2) { + tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTQ + vex_l, ret); } else { - if (type =3D=3D TCG_TYPE_V64) { - tcg_out_vex_modrm_pool(s, OPC_MOVQ_VqWq, ret); - } else if (have_avx2) { - tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTQ + vex_l, ret); - } else { - tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret); - } - if (TCG_TARGET_REG_BITS =3D=3D 64) { - new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); - } else { - new_pool_l2(s, R_386_32, s->code_ptr - 4, 0, arg, arg >> 32); - } + tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret); } + new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); } =20 static void tcg_out_movi_vec(TCGContext *s, TCGType type, @@ -1082,11 +992,7 @@ static void tcg_out_movi_vec(TCGContext *s, TCGType t= ype, =20 int rexw =3D (type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW); tcg_out_vex_modrm_pool(s, OPC_MOVD_VyEy + rexw, ret); - if (TCG_TARGET_REG_BITS =3D=3D 64) { - new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); - } else { - new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); - } + new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); } =20 static void tcg_out_movi_int(TCGContext *s, TCGType type, @@ -1127,9 +1033,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, { switch (type) { case TCG_TYPE_I32: -#if TCG_TARGET_REG_BITS =3D=3D 64 case TCG_TYPE_I64: -#endif if (ret < 16) { tcg_out_movi_int(s, type, ret, arg); } else { @@ -1292,7 +1196,7 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, = TCGArg val, TCGReg base, intptr_t ofs) { int rexw =3D 0; - if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64) { + if (type =3D=3D TCG_TYPE_I64) { if (val !=3D (int32_t)val) { return false; } @@ -1331,31 +1235,12 @@ static inline void tcg_out_rolw_8(TCGContext *s, in= t reg) =20 static void tcg_out_ext8u(TCGContext *s, TCGReg dest, TCGReg src) { - if (TCG_TARGET_REG_BITS =3D=3D 32 && src >=3D 4) { - tcg_out_mov(s, TCG_TYPE_I32, dest, src); - if (dest >=3D 4) { - tcg_out_modrm(s, OPC_ARITH_EvIz, ARITH_AND, dest); - tcg_out32(s, 0xff); - return; - } - src =3D dest; - } tcg_out_modrm(s, OPC_MOVZBL + P_REXB_RM, dest, src); } =20 static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg= src) { int rexw =3D type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW; - - if (TCG_TARGET_REG_BITS =3D=3D 32 && src >=3D 4) { - tcg_out_mov(s, TCG_TYPE_I32, dest, src); - if (dest >=3D 4) { - tcg_out_shifti(s, SHIFT_SHL, dest, 24); - tcg_out_shifti(s, SHIFT_SAR, dest, 24); - return; - } - src =3D dest; - } tcg_out_modrm(s, OPC_MOVSBL + P_REXB_RM + rexw, dest, src); } =20 @@ -1380,7 +1265,6 @@ static void tcg_out_ext32u(TCGContext *s, TCGReg dest= , TCGReg src) =20 static void tcg_out_ext32s(TCGContext *s, TCGReg dest, TCGReg src) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_modrm(s, OPC_MOVSLQ, dest, src); } =20 @@ -1409,12 +1293,9 @@ static inline void tcg_out_bswap64(TCGContext *s, in= t reg) static void tgen_arithi(TCGContext *s, int c, int r0, tcg_target_long val, int cf) { - int rexw =3D 0; + int rexw =3D c & -8; =20 - if (TCG_TARGET_REG_BITS =3D=3D 64) { - rexw =3D c & -8; - c &=3D 7; - } + c &=3D 7; =20 switch (c) { case ARITH_ADD: @@ -1427,16 +1308,12 @@ static void tgen_arithi(TCGContext *s, int c, int r= 0, */ if (val =3D=3D 1 || val =3D=3D -1) { int is_inc =3D (c =3D=3D ARITH_ADD) ^ (val < 0); - if (TCG_TARGET_REG_BITS =3D=3D 64) { - /* - * The single-byte increment encodings are re-tasked - * as the REX prefixes. Use the MODRM encoding. - */ - tcg_out_modrm(s, OPC_GRP5 + rexw, - (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0= ); - } else { - tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0); - } + /* + * The single-byte increment encodings are re-tasked + * as the REX prefixes. Use the MODRM encoding. + */ + tcg_out_modrm(s, OPC_GRP5 + rexw, + (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0); return; } if (val =3D=3D 128) { @@ -1451,17 +1328,15 @@ static void tgen_arithi(TCGContext *s, int c, int r= 0, break; =20 case ARITH_AND: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (val =3D=3D 0xffffffffu) { - tcg_out_ext32u(s, r0, r0); - return; - } - if (val =3D=3D (uint32_t)val) { - /* AND with no high bits set can use a 32-bit operation. = */ - rexw =3D 0; - } + if (val =3D=3D 0xffffffffu) { + tcg_out_ext32u(s, r0, r0); + return; } - if (val =3D=3D 0xffu && (r0 < 4 || TCG_TARGET_REG_BITS =3D=3D 64))= { + if (val =3D=3D (uint32_t)val) { + /* AND with no high bits set can use a 32-bit operation. */ + rexw =3D 0; + } + if (val =3D=3D 0xffu) { tcg_out_ext8u(s, r0, r0); return; } @@ -1473,8 +1348,7 @@ static void tgen_arithi(TCGContext *s, int c, int r0, =20 case ARITH_OR: case ARITH_XOR: - if (val >=3D 0x80 && val <=3D 0xff - && (r0 < 4 || TCG_TARGET_REG_BITS =3D=3D 64)) { + if (val >=3D 0x80 && val <=3D 0xff) { tcg_out_modrm(s, OPC_ARITH_EbIb + P_REXB_RM, c, r0); tcg_out8(s, val); return; @@ -1577,7 +1451,7 @@ static int tcg_out_cmp(TCGContext *s, TCGCond cond, T= CGArg arg1, return jz; } =20 - if (arg2 <=3D 0xff && (TCG_TARGET_REG_BITS =3D=3D 64 || arg1 < 4)) { + if (arg2 <=3D 0xff) { if (arg2 =3D=3D 0x80) { tcg_out_modrm(s, OPC_TESTB | P_REXB_R, arg1, arg1); return js; @@ -1669,53 +1543,6 @@ static const TCGOutOpBrcond outop_brcond =3D { .out_ri =3D tgen_brcondi, }; =20 -static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, - TCGReg ah, TCGArg bl, bool blconst, - TCGArg bh, bool bhconst, - TCGLabel *label_this, bool small) -{ - TCGLabel *label_next =3D gen_new_label(); - - switch (cond) { - case TCG_COND_EQ: - case TCG_COND_TSTEQ: - tcg_out_brcond(s, 0, tcg_invert_cond(cond), - al, bl, blconst, label_next, true); - tcg_out_brcond(s, 0, cond, ah, bh, bhconst, label_this, small); - break; - - case TCG_COND_NE: - case TCG_COND_TSTNE: - tcg_out_brcond(s, 0, cond, al, bl, blconst, label_this, small); - tcg_out_brcond(s, 0, cond, ah, bh, bhconst, label_this, small); - break; - - default: - tcg_out_brcond(s, 0, tcg_high_cond(cond), - ah, bh, bhconst, label_this, small); - tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond(s, 0, tcg_unsigned_cond(cond), - al, bl, blconst, label_this, small); - break; - } - tcg_out_label(s, label_next); -} - -static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, - TCGReg ah, TCGArg bl, bool blconst, - TCGArg bh, bool bhconst, TCGLabel *l) -{ - tcg_out_brcond2(s, cond, al, ah, bl, blconst, bh, bhconst, l, false); -} - -#if TCG_TARGET_REG_BITS !=3D 32 -__attribute__((unused)) -#endif -static const TCGOutOpBrcond2 outop_brcond2 =3D { - .base.static_constraint =3D C_O0_I4(r, r, ri, ri), - .out =3D tgen_brcond2, -}; - static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, TCGReg dest, TCGReg arg1, TCGArg arg2, bool const_arg2, bool neg) @@ -1867,54 +1694,6 @@ static const TCGOutOpSetcond outop_negsetcond =3D { .out_rri =3D tgen_negsetcondi, }; =20 -static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg al, TCGReg ah, - TCGArg bl, bool const_bl, - TCGArg bh, bool const_bh) -{ - TCGLabel *label_over =3D gen_new_label(); - - if (ret =3D=3D al || ret =3D=3D ah - || (!const_bl && ret =3D=3D bl) - || (!const_bh && ret =3D=3D bh)) { - /* - * When the destination overlaps with one of the argument - * registers, don't do anything tricky. - */ - TCGLabel *label_true =3D gen_new_label(); - - tcg_out_brcond2(s, cond, al, ah, bl, const_bl, - bh, const_bh, label_true, true); - - tcg_out_movi(s, TCG_TYPE_I32, ret, 0); - tcg_out_jxx(s, JCC_JMP, label_over, 1); - tcg_out_label(s, label_true); - - tcg_out_movi(s, TCG_TYPE_I32, ret, 1); - } else { - /* - * When the destination does not overlap one of the arguments, - * clear the destination first, jump if cond false, and emit an - * increment in the true case. This results in smaller code. - */ - tcg_out_movi(s, TCG_TYPE_I32, ret, 0); - - tcg_out_brcond2(s, tcg_invert_cond(cond), al, ah, bl, const_bl, - bh, const_bh, label_over, true); - - tgen_arithi(s, ARITH_ADD, ret, 1, 0); - } - tcg_out_label(s, label_over); -} - -#if TCG_TARGET_REG_BITS !=3D 32 -__attribute__((unused)) -#endif -static const TCGOutOpSetcond2 outop_setcond2 =3D { - .base.static_constraint =3D C_O1_I4(r, r, r, ri, ri), - .out =3D tgen_setcond2, -}; - static void tcg_out_cmov(TCGContext *s, int jcc, int rexw, TCGReg dest, TCGReg v1) { @@ -1959,22 +1738,6 @@ static void tcg_out_call(TCGContext *s, const tcg_in= sn_unit *dest, const TCGHelperInfo *info) { tcg_out_branch(s, 1, dest); - -#ifndef _WIN32 - if (TCG_TARGET_REG_BITS =3D=3D 32 && info->out_kind =3D=3D TCG_CALL_RE= T_BY_REF) { - /* - * The sysv i386 abi for struct return places a reference as the - * first argument of the stack, and pops that argument with the - * return statement. Since we want to retain the aligned stack - * pointer for the callee, we do not want to actually push that - * argument before the call but rely on the normal store to the - * stack slot. But we do need to compensate for the pop in order - * to reset our correct stack pointer value. - * Pushing a garbage value back onto the stack is quickest. - */ - tcg_out_push(s, TCG_REG_EAX); - } -#endif } =20 static void tcg_out_jmp(TCGContext *s, const tcg_insn_unit *dest) @@ -2025,15 +1788,13 @@ bool tcg_target_has_memory_bswap(MemOp memop) } =20 /* - * Because i686 has no register parameters and because x86_64 has xchg - * to handle addr/data register overlap, we have placed all input arguments - * before we need might need a scratch reg. + * Because x86_64 has xchg to handle addr/data register overlap, we have + * placed all input arguments before we need might need a scratch reg. * * Even then, a scratch is only needed for l->raddr. Rather than expose * a general-purpose scratch when we don't actually know it's available, * use the ra_gen hook to load into RAX if needed. */ -#if TCG_TARGET_REG_BITS =3D=3D 64 static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int ar= g) { if (arg < 0) { @@ -2042,12 +1803,10 @@ static TCGReg ldst_ra_gen(TCGContext *s, const TCGL= abelQemuLdst *l, int arg) tcg_out_movi(s, TCG_TYPE_PTR, arg, (uintptr_t)l->raddr); return arg; } + static const TCGLdstHelperParam ldst_helper_param =3D { .ra_gen =3D ldst_ra_gen }; -#else -static const TCGLdstHelperParam ldst_helper_param =3D { }; -#endif =20 static void tcg_out_vec_to_pair(TCGContext *s, TCGType type, TCGReg l, TCGReg h, TCGReg v) @@ -2121,7 +1880,7 @@ static HostAddress x86_guest_base =3D { .index =3D -1 }; =20 -#if defined(__x86_64__) && defined(__linux__) +#if defined(__linux__) # include # include int arch_prctl(int code, unsigned long addr); @@ -2133,8 +1892,7 @@ static inline int setup_guest_base_seg(void) return 0; } #define setup_guest_base_seg setup_guest_base_seg -#elif defined(__x86_64__) && \ - (defined (__FreeBSD__) || defined (__FreeBSD_kernel__)) +#elif defined (__FreeBSD__) || defined (__FreeBSD_kernel__) # include static inline int setup_guest_base_seg(void) { @@ -2195,14 +1953,12 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, ldst->oi =3D oi; ldst->addr_reg =3D addr; =20 - if (TCG_TARGET_REG_BITS =3D=3D 64) { - ttype =3D s->addr_type; - trexw =3D (ttype =3D=3D TCG_TYPE_I32 ? 0 : P_REXW); - if (TCG_TYPE_PTR =3D=3D TCG_TYPE_I64) { - hrexw =3D P_REXW; - tlbtype =3D TCG_TYPE_I64; - tlbrexw =3D P_REXW; - } + ttype =3D s->addr_type; + trexw =3D (ttype =3D=3D TCG_TYPE_I32 ? 0 : P_REXW); + if (TCG_TYPE_PTR =3D=3D TCG_TYPE_I64) { + hrexw =3D P_REXW; + tlbtype =3D TCG_TYPE_I64; + tlbrexw =3D P_REXW; } =20 tcg_out_mov(s, tlbtype, TCG_REG_L0, addr); @@ -2314,7 +2070,6 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, h.base, h.index, 0, h.ofs); break; -#if TCG_TARGET_REG_BITS =3D=3D 64 case MO_SL: if (use_movbe) { tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + h.seg, datalo, @@ -2325,34 +2080,12 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, h.base, h.index, 0, h.ofs); } break; -#endif case MO_UQ: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, - h.base, h.index, 0, h.ofs); - break; - } - if (use_movbe) { - TCGReg t =3D datalo; - datalo =3D datahi; - datahi =3D t; - } - if (h.base =3D=3D datalo || h.index =3D=3D datalo) { - tcg_out_modrm_sib_offset(s, OPC_LEA, datahi, - h.base, h.index, 0, h.ofs); - tcg_out_modrm_offset(s, movop + h.seg, datalo, datahi, 0); - tcg_out_modrm_offset(s, movop + h.seg, datahi, datahi, 4); - } else { - tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, - h.base, h.index, 0, h.ofs); - tcg_out_modrm_sib_offset(s, movop + h.seg, datahi, - h.base, h.index, 0, h.ofs + 4); - } + tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, + h.base, h.index, 0, h.ofs); break; =20 case MO_128: - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); - /* * Without 16-byte atomicity, use integer regs. * That is where we want the data, and it allows bswaps. @@ -2483,8 +2216,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, =20 switch (memop & MO_SIZE) { case MO_8: - /* This is handled with constraints in cset_qemu_st(). */ - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || datalo < 4); tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + h.seg, datalo, h.base, h.index, 0, h.ofs); break; @@ -2497,25 +2228,11 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, h.base, h.index, 0, h.ofs); break; case MO_64: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, - h.base, h.index, 0, h.ofs); - } else { - if (use_movbe) { - TCGReg t =3D datalo; - datalo =3D datahi; - datahi =3D t; - } - tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, - h.base, h.index, 0, h.ofs); - tcg_out_modrm_sib_offset(s, movop + h.seg, datahi, - h.base, h.index, 0, h.ofs + 4); - } + tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, + h.base, h.index, 0, h.ofs); break; =20 case MO_128: - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); - /* * Without 16-byte atomicity, use integer regs. * That is where we have the data, and it allows bswaps. @@ -2592,16 +2309,8 @@ static void tgen_qemu_st(TCGContext *s, TCGType type= , TCGReg data, } } =20 -static TCGConstraintSetIndex cset_qemu_st(TCGType type, unsigned flags) -{ - return flags =3D=3D MO_8 ? C_O0_I2(s, L) : C_O0_I2(L, L); -} - static const TCGOutOpQemuLdSt outop_qemu_st =3D { - .base.static_constraint =3D - TCG_TARGET_REG_BITS =3D=3D 32 ? C_Dynamic : C_O0_I2(L, L), - .base.dynamic_constraint =3D - TCG_TARGET_REG_BITS =3D=3D 32 ? cset_qemu_st : NULL, + .base.static_constraint =3D C_O0_I2(L, L), .out =3D tgen_qemu_st, }; =20 @@ -2958,7 +2667,6 @@ static const TCGOutOpBinary outop_eqv =3D { .base.static_constraint =3D C_NotImplemented, }; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 static void tgen_extrh_i64_i32(TCGContext *s, TCGType t, TCGReg a0, TCGReg= a1) { tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32); @@ -2968,7 +2676,6 @@ static const TCGOutOpUnary outop_extrh_i64_i32 =3D { .base.static_constraint =3D C_O1_I1(r, 0), .out_rr =3D tgen_extrh_i64_i32, }; -#endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ =20 static void tgen_mul(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) @@ -3320,7 +3027,6 @@ static const TCGOutOpBswap outop_bswap32 =3D { .out_rr =3D tgen_bswap32, }; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) { tcg_out_bswap64(s, a0); @@ -3330,7 +3036,6 @@ static const TCGOutOpUnary outop_bswap64 =3D { .base.static_constraint =3D C_O1_I1(r, 0), .out_rr =3D tgen_bswap64, }; -#endif =20 static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) { @@ -3361,8 +3066,6 @@ static void tgen_deposit(TCGContext *s, TCGType type,= TCGReg a0, TCGReg a1, tcg_out_modrm(s, OPC_MOVB_EvGv | P_REXB_R | P_REXB_RM, a2, a0); } else if (ofs =3D=3D 0 && len =3D=3D 16) { tcg_out_modrm(s, OPC_MOVL_EvGv | P_DATA16, a2, a0); - } else if (TCG_TARGET_REG_BITS =3D=3D 32 && ofs =3D=3D 8 && len =3D=3D= 8) { - tcg_out_modrm(s, OPC_MOVB_EvGv, a2, a0 + 4); } else { g_assert_not_reached(); } @@ -3377,9 +3080,6 @@ static void tgen_depositi(TCGContext *s, TCGType type= , TCGReg a0, TCGReg a1, } else if (ofs =3D=3D 0 && len =3D=3D 16) { tcg_out_opc(s, OPC_MOVL_Iv | P_DATA16 | LOWREGMASK(a0), 0, a0, 0); tcg_out16(s, a2); - } else if (TCG_TARGET_REG_BITS =3D=3D 32 && ofs =3D=3D 8 && len =3D=3D= 8) { - tcg_out8(s, OPC_MOVB_Ib + a0 + 4); - tcg_out8(s, a2); } else { g_assert_not_reached(); } @@ -3406,7 +3106,7 @@ static void tgen_extract(TCGContext *s, TCGType type,= TCGReg a0, TCGReg a1, tcg_out_ext32u(s, a0, a1); return; } - } else if (TCG_TARGET_REG_BITS =3D=3D 64 && ofs + len =3D=3D 32) { + } else if (ofs + len =3D=3D 32) { /* This is a 32-bit zero-extending right shift. */ tcg_out_mov(s, TCG_TYPE_I32, a0, a1); tcg_out_shifti(s, SHIFT_SHR, a0, ofs); @@ -3417,7 +3117,7 @@ static void tgen_extract(TCGContext *s, TCGType type,= TCGReg a0, TCGReg a1, * Otherwise we emit the same ext16 + shift pattern that we * would have gotten from the normal tcg-op.c expansion. */ - if (a1 < 4 && (TCG_TARGET_REG_BITS =3D=3D 32 || a0 < 8)) { + if (a1 < 4 && a0 < 8) { tcg_out_modrm(s, OPC_MOVZBL, a0, a1 + 4); } else { tcg_out_ext16u(s, a0, a1); @@ -3526,7 +3226,6 @@ static const TCGOutOpLoad outop_ld16s =3D { .out =3D tgen_ld16s, }; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 static void tgen_ld32u(TCGContext *s, TCGType type, TCGReg dest, TCGReg base, ptrdiff_t offset) { @@ -3548,7 +3247,6 @@ static const TCGOutOpLoad outop_ld32s =3D { .base.static_constraint =3D C_O1_I1(r, r), .out =3D tgen_ld32s, }; -#endif =20 static void tgen_st8_r(TCGContext *s, TCGType type, TCGReg data, TCGReg base, ptrdiff_t offset) @@ -3990,16 +3688,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, a1 =3D a2; a2 =3D args[3]; goto gen_simd; -#if TCG_TARGET_REG_BITS =3D=3D 32 - case INDEX_op_dup2_vec: - /* First merge the two 32-bit inputs to a single 64-bit element. */ - tcg_out_vex_modrm(s, OPC_PUNPCKLDQ, a0, a1, a2); - /* Then replicate the 64-bit elements across the rest of the vecto= r. */ - if (type !=3D TCG_TYPE_V64) { - tcg_out_dup_vec(s, type, MO_64, a0, a0); - } - break; -#endif case INDEX_op_abs_vec: insn =3D abs_insn[vece]; a2 =3D a1; @@ -4194,9 +3882,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigne= d flags) case INDEX_op_x86_punpckh_vec: case INDEX_op_x86_vpshldi_vec: case INDEX_op_x86_vgf2p8affineqb_vec: -#if TCG_TARGET_REG_BITS =3D=3D 32 - case INDEX_op_dup2_vec: -#endif return C_O1_I2(x, x, x); =20 case INDEX_op_abs_vec: @@ -4732,7 +4417,6 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, u= nsigned vece, } =20 static const int tcg_target_callee_save_regs[] =3D { -#if TCG_TARGET_REG_BITS =3D=3D 64 TCG_REG_RBP, TCG_REG_RBX, #if defined(_WIN64) @@ -4743,20 +4427,13 @@ static const int tcg_target_callee_save_regs[] =3D { TCG_REG_R13, TCG_REG_R14, /* Currently used for the global env. */ TCG_REG_R15, -#else - TCG_REG_EBP, /* Currently used for the global env. */ - TCG_REG_EBX, - TCG_REG_ESI, - TCG_REG_EDI, -#endif }; =20 /* Compute frame size via macros, to share between tcg_target_qemu_prologue and tcg_register_jit. */ =20 #define PUSH_SIZE \ - ((1 + ARRAY_SIZE(tcg_target_callee_save_regs)) \ - * (TCG_TARGET_REG_BITS / 8)) + ((1 + ARRAY_SIZE(tcg_target_callee_save_regs)) * sizeof(tcg_target_lon= g)) =20 #define FRAME_SIZE \ ((PUSH_SIZE \ @@ -4789,7 +4466,6 @@ static void tcg_target_qemu_prologue(TCGContext *s) } else if (guest_base =3D=3D (int32_t)guest_base) { x86_guest_base.ofs =3D guest_base; } else { - assert(TCG_TARGET_REG_BITS =3D=3D 64); /* Choose R12 because, as a base, it requires a SIB byte. */ x86_guest_base.index =3D TCG_REG_R12; tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base.index, guest_base= ); @@ -4797,20 +4473,10 @@ static void tcg_target_qemu_prologue(TCGContext *s) } } =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, - (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4); - tcg_out_addi(s, TCG_REG_ESP, -stack_addend); - /* jmp *tb. */ - tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP, - (ARRAY_SIZE(tcg_target_callee_save_regs) + 2)= * 4 - + stack_addend); - } else { - tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[= 0]); - tcg_out_addi(s, TCG_REG_ESP, -stack_addend); - /* jmp *tb. */ - tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs= [1]); - } + tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); + tcg_out_addi(s, TCG_REG_ESP, -stack_addend); + /* jmp *tb. */ + tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]); =20 /* * Return path for goto_ptr. Set return value to 0, a-la exit_tb, @@ -4846,9 +4512,7 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int co= unt) static void tcg_target_init(TCGContext *s) { tcg_target_available_regs[TCG_TYPE_I32] =3D ALL_GENERAL_REGS; - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_target_available_regs[TCG_TYPE_I64] =3D ALL_GENERAL_REGS; - } + tcg_target_available_regs[TCG_TYPE_I64] =3D ALL_GENERAL_REGS; if (have_avx1) { tcg_target_available_regs[TCG_TYPE_V64] =3D ALL_VECTOR_REGS; tcg_target_available_regs[TCG_TYPE_V128] =3D ALL_VECTOR_REGS; @@ -4861,16 +4525,14 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EDX); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_ECX); - if (TCG_TARGET_REG_BITS =3D=3D 64) { #if !defined(_WIN64) - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RDI); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RSI); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RDI); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RSI); #endif - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); - } + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); =20 s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); @@ -4899,10 +4561,9 @@ typedef struct { /* We're expecting a 2 byte uleb128 encoded value. */ QEMU_BUILD_BUG_ON(FRAME_SIZE >=3D (1 << 14)); =20 -#if !defined(__ELF__) - /* Host machine without ELF. */ -#elif TCG_TARGET_REG_BITS =3D=3D 64 +#ifdef __ELF__ #define ELF_HOST_MACHINE EM_X86_64 + static const DebugFrame debug_frame =3D { .h.cie.len =3D sizeof(DebugFrameCIE)-4, /* length after .len member */ .h.cie.id =3D -1, @@ -4930,36 +4591,7 @@ static const DebugFrame debug_frame =3D { 0x8f, 7, /* DW_CFA_offset, %r15, -56 */ } }; -#else -#define ELF_HOST_MACHINE EM_386 -static const DebugFrame debug_frame =3D { - .h.cie.len =3D sizeof(DebugFrameCIE)-4, /* length after .len member */ - .h.cie.id =3D -1, - .h.cie.version =3D 1, - .h.cie.code_align =3D 1, - .h.cie.data_align =3D 0x7c, /* sleb128 -4 */ - .h.cie.return_column =3D 8, =20 - /* Total FDE size does not include the "len" member. */ - .h.fde.len =3D sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_off= set), - - .fde_def_cfa =3D { - 12, 4, /* DW_CFA_def_cfa %esp, ... */ - (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ - (FRAME_SIZE >> 7) - }, - .fde_reg_ofs =3D { - 0x88, 1, /* DW_CFA_offset, %eip, -4 */ - /* The following ordering must match tcg_target_callee_save_regs. = */ - 0x85, 2, /* DW_CFA_offset, %ebp, -8 */ - 0x83, 3, /* DW_CFA_offset, %ebx, -12 */ - 0x86, 4, /* DW_CFA_offset, %esi, -16 */ - 0x87, 5, /* DW_CFA_offset, %edi, -20 */ - } -}; -#endif - -#if defined(ELF_HOST_MACHINE) void tcg_register_jit(const void *buf, size_t buf_size) { tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 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([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7193dbb74sm74402865ad.56.2026.01.18.14.04.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:04:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768773894; x=1769378694; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7DzNQby4LQPUtVLwqs2IyxJ1FWe8jwshY5ovM9t1IBI=; b=AexYOkVuzDgojLEiFY5jIX2z7WC/gDCD0B1QXFr0XXw4RScvIZUHXkADVMfsBGP/ab k8ccj6/aBQIR6/G0GhPan8K/uvVDTZTKmjmgxAG8DByEOiowDdC+h/bjJ+HnLWoLNZez iCi2NrBc00jJmbh4653KQTyF2R+XGWL+x8pDQKZJZvwdSQPq8mU6JPiZhocasXBl2ffs Q7Nz5NO5dLu36VH873jz2fAgSj8uSc2naFScLo6LGrh/2Oqj/1KXfrkAZNQ35HnVgyR0 YmZBX1sQaGOgIGJ7jhyik8StK1MbJfHeC9ddeAalwf/uFvi8VvuDfH3Zjx65heZ3ELNH boGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768773894; x=1769378694; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=7DzNQby4LQPUtVLwqs2IyxJ1FWe8jwshY5ovM9t1IBI=; b=dUjIJKj59e0xk4e6hgyr2MPL8mp00hEdlBkcw/UiDdFvZZt8ZpvVpe1zLY4YXaK7o5 NaaraWSa1uEGlNF3KTCNW31B+t08xX5DsWwfxdH8PWGmW3LTcQ7kSAZWchAI4dBkvrVd pomgNKGj/reVqNKXhDKhnOEK2n+3m4QC9yPVob1Z2uqv+ZSFdV3qw5VKO18EfeUjM2wK eTU9jp2qlKz+DkvymneLlYT4TYzVcC+21I8ofxymanl/83pIGNIyQM1WXYBdl0TurTkA a210U4EdOUrSnCDhA5L3CnXh7yj5p5CZPNFVKXBpFmiJZVtKUCdM5lU++nmrol62mpvN WrUg== X-Gm-Message-State: AOJu0Yz8tvBaF2Im0iyutfIB9yqZSNpaFkq1FKgZ+wMmOu8gKo7n3PT5 fJih2t5BV/h6oEWn4XHRJLHqAy2Zk5T14UUiHDdZCwj+AjN9ACIP1OPJq0+jMYs/gJf14XBQjfw ELzPIltmc7A== X-Gm-Gg: AY/fxX4lim6S3FGx1hcXDB7se3vZClRjgDn1rDLqS0+Kb6sItic99fnLPWyZeBHa/7M ofVvgv71yTLXgOdtSTGPUAFpWuxmyNoPWOcWhRk/YJ5ym2ShSMgshm5JTwWsdfxl9euhNxPAHyO 5qkhwydzcoOJTa8MkuslUMjl5i5HFq2o5ghuIJi2ynr9H2onUgAkPKEMZeFkMPSxuizgretqSV5 vgCyd4y6yMWIbri87mpIAS8b9LHnIVpPqETXuAYXCDuW4kjmxRi2QmYIr+NnVwm208dON3O1MZT PtHohxkwlvX8ezdF3DREXSABjkZRqeOMeYM9ugtVElZKhT/Kg8dWRIu4TsSRdVwrZp5kluQeDfA elyycoGdZZDDoy3XcWHcAa1a32f9aLkt/LeHiF5+oO6290+bVbsp39KgPaL79FsDVtc2g+QJGQ4 DcmS5NtXJuMqVGo2pFTw== X-Received: by 2002:a17:903:4b43:b0:2a7:3dab:ca99 with SMTP id d9443c01a7336-2a73dabcafcmr14650045ad.26.1768773894171; Sun, 18 Jan 2026 14:04:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 14/54] tcg/x86_64: Rename from i386 Date: Mon, 19 Jan 2026 09:03:34 +1100 Message-ID: <20260118220414.8177-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768773941984158500 Emphasize that we're generating 64-bit code. Drop the explicit rename from meson's cpu. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/{i386 =3D> x86_64}/tcg-target-con-set.h | 0 tcg/{i386 =3D> x86_64}/tcg-target-con-str.h | 0 tcg/{i386 =3D> x86_64}/tcg-target-has.h | 0 tcg/{i386 =3D> x86_64}/tcg-target-mo.h | 0 tcg/{i386 =3D> x86_64}/tcg-target-reg-bits.h | 0 tcg/{i386 =3D> x86_64}/tcg-target.h | 0 MAINTAINERS | 4 ++-- meson.build | 2 -- tcg/{i386 =3D> x86_64}/tcg-target-opc.h.inc | 0 tcg/{i386 =3D> x86_64}/tcg-target.c.inc | 0 10 files changed, 2 insertions(+), 4 deletions(-) rename tcg/{i386 =3D> x86_64}/tcg-target-con-set.h (100%) rename tcg/{i386 =3D> x86_64}/tcg-target-con-str.h (100%) rename tcg/{i386 =3D> x86_64}/tcg-target-has.h (100%) rename tcg/{i386 =3D> x86_64}/tcg-target-mo.h (100%) rename tcg/{i386 =3D> x86_64}/tcg-target-reg-bits.h (100%) rename tcg/{i386 =3D> x86_64}/tcg-target.h (100%) rename tcg/{i386 =3D> x86_64}/tcg-target-opc.h.inc (100%) rename tcg/{i386 =3D> x86_64}/tcg-target.c.inc (100%) diff --git a/tcg/i386/tcg-target-con-set.h b/tcg/x86_64/tcg-target-con-set.h similarity index 100% rename from tcg/i386/tcg-target-con-set.h rename to tcg/x86_64/tcg-target-con-set.h diff --git a/tcg/i386/tcg-target-con-str.h b/tcg/x86_64/tcg-target-con-str.h similarity index 100% rename from tcg/i386/tcg-target-con-str.h rename to tcg/x86_64/tcg-target-con-str.h diff --git a/tcg/i386/tcg-target-has.h b/tcg/x86_64/tcg-target-has.h similarity index 100% rename from tcg/i386/tcg-target-has.h rename to tcg/x86_64/tcg-target-has.h diff --git a/tcg/i386/tcg-target-mo.h b/tcg/x86_64/tcg-target-mo.h similarity index 100% rename from tcg/i386/tcg-target-mo.h rename to tcg/x86_64/tcg-target-mo.h diff --git a/tcg/i386/tcg-target-reg-bits.h b/tcg/x86_64/tcg-target-reg-bit= s.h similarity index 100% rename from tcg/i386/tcg-target-reg-bits.h rename to tcg/x86_64/tcg-target-reg-bits.h diff --git a/tcg/i386/tcg-target.h b/tcg/x86_64/tcg-target.h similarity index 100% rename from tcg/i386/tcg-target.h rename to tcg/x86_64/tcg-target.h diff --git a/MAINTAINERS b/MAINTAINERS index 1a6e5bbafe..c39a8f54e8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4057,10 +4057,10 @@ S: Maintained L: qemu-arm@nongnu.org F: tcg/aarch64/ =20 -i386 TCG target +X86 TCG target M: Richard Henderson S: Maintained -F: tcg/i386/ +F: tcg/x86_64/ =20 LoongArch64 TCG target M: WANG Xuerui diff --git a/meson.build b/meson.build index 7993e4cfb9..594e7d42c0 100644 --- a/meson.build +++ b/meson.build @@ -907,8 +907,6 @@ if have_tcg endif if get_option('tcg_interpreter') tcg_arch =3D 'tci' - elif host_arch =3D=3D 'x86_64' - tcg_arch =3D 'i386' elif host_arch =3D=3D 'ppc64' tcg_arch =3D 'ppc' endif diff --git a/tcg/i386/tcg-target-opc.h.inc b/tcg/x86_64/tcg-target-opc.h.inc similarity index 100% rename from tcg/i386/tcg-target-opc.h.inc rename to tcg/x86_64/tcg-target-opc.h.inc diff --git a/tcg/i386/tcg-target.c.inc b/tcg/x86_64/tcg-target.c.inc similarity index 100% rename from tcg/i386/tcg-target.c.inc rename to tcg/x86_64/tcg-target.c.inc --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7193dbb74sm74402865ad.56.2026.01.18.14.04.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:04:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768773897; x=1769378697; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=92HxQ69qgo/2VgbhtKQwCIAt9EeS2yQ9NqJlStKghbs=; b=A2EjFy6Eu4gtloGFlVw5tdkLB8lIIBeJSKsdtxfYdLAdq3Hc9IXEX1dHhldctZmYYa mZH0ZKI6iVYNF10cijbN8McwcncV4C9UHTzGCOSPeCuKsTIg655fcDaHUc8UZmmMYuzA iw3XLXn8b1PceZ5/VuZiJTRtmZ0TQwBWTxK2kk1Smdu3DWv0iPIbLTdx6vvFgIChoD8s D48Dq14j0qOUYo/HPSwMSl/R3uEeP0rMTHJhoTi1ZeBn2zS5ixiIBi2CdxHgW/96FY7r iumFI11L4hbiRtsUmReB2L7hraqs3nXSWjOrPTqJzH5ZJYjfuECsN5i1mXkTCg3lL5SS Iq8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768773897; x=1769378697; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=92HxQ69qgo/2VgbhtKQwCIAt9EeS2yQ9NqJlStKghbs=; b=SmRAW1GbAE21Pb2X+4ub0Rxarol0EqNkAA6Sasjy9AoQDZ9KJoxbdY4F4bLue/FQ54 ijaSMc74/5PxPXCuLmDotjraTutKpLQpQ3n0Ci+2uqh0uQjTV0Qg7Yc24279tA//q3AO 4mBqj4dxwCOwjK00/1zyQqZ7xkeBDBhhI2dmFH4OGgBPOb3MeOGAsWgfIwr5UvTVMedw BWBBKgDmhgQfiRmOSCdZ74nRxdlHFrcqZv3C3CPar2FyaYCI035MGw352IxJgxODPHRR S2dt/Y45hJyO9rzCmzNyq3mXY7n9YuTV+UjEyS6NqH6kD7RCj1dVr9VaCd+py44dVGFX MaYw== X-Gm-Message-State: AOJu0YyWlyIsAlQ+EqIiEyKyJ4J+9UM4KjFkAACVIOeUDhiMa287o0V4 41GEhtIBL8IQ3wjQjxSHgdgmQjWq3yU4stK22ej23+RilvIhkFjoUS7XDFWWrR8AgBcsBI7yIeq r/n9BRlchPQ== X-Gm-Gg: AY/fxX5O96fBSXNxETzrR0wVGsbN6GdmQACkc3VW6Pc2ll1Q/j3fILsKdvlcth5mLE4 EWIbsv4EziG+9odf9zdy8rB90U81lVTDcz2FDZej2Z816oCVPhpH0Ov3qx8702ehxRtXBF8q7Bv iIFzeehwcs9cHkRaNnuh2zpVvMdcHIeckStsK1ZYziGyWcM5ke/AYvFzw3v3gCHqQaK+ejrZMjK Vdn4RTRAuKwzS1ujCx8XvnTbCp24r2y8ZVasAbbEmdGcE/e0SYN8AxSYZjgtfiIMathQgrJq025 wKhZ39w8V4TQiCNLShiie/GvUVOOdZaoQRJoHQrLQCVeimeqUCJpq5t2oOr0tl2WuLfM5KGyeEz ogpi7lE0OikPaKmPPXblAT1LpyP4eP/hL0jWxwUH3+w7ZStkBMt3yVSLzI9tJ9NIU4HKadaR4uF IG3f/O1frDEFqt6pWu7Q== X-Received: by 2002:a17:903:2f8a:b0:2a1:3cd9:a73a with SMTP id d9443c01a7336-2a7189482fbmr79829645ad.40.1768773896594; Sun, 18 Jan 2026 14:04:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 15/54] tcg/ppc64: Rename from ppc Date: Mon, 19 Jan 2026 09:03:35 +1100 Message-ID: <20260118220414.8177-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768773950195158500 Emphasize that we're generating 64-bit code. Drop the explicit rename from meson's cpu. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/{ppc =3D> ppc64}/tcg-target-con-set.h | 0 tcg/{ppc =3D> ppc64}/tcg-target-con-str.h | 0 tcg/{ppc =3D> ppc64}/tcg-target-has.h | 0 tcg/{ppc =3D> ppc64}/tcg-target-mo.h | 0 tcg/{ppc =3D> ppc64}/tcg-target-reg-bits.h | 0 tcg/{ppc =3D> ppc64}/tcg-target.h | 0 MAINTAINERS | 2 +- meson.build | 2 -- tcg/{ppc =3D> ppc64}/tcg-target-opc.h.inc | 0 tcg/{ppc =3D> ppc64}/tcg-target.c.inc | 0 10 files changed, 1 insertion(+), 3 deletions(-) rename tcg/{ppc =3D> ppc64}/tcg-target-con-set.h (100%) rename tcg/{ppc =3D> ppc64}/tcg-target-con-str.h (100%) rename tcg/{ppc =3D> ppc64}/tcg-target-has.h (100%) rename tcg/{ppc =3D> ppc64}/tcg-target-mo.h (100%) rename tcg/{ppc =3D> ppc64}/tcg-target-reg-bits.h (100%) rename tcg/{ppc =3D> ppc64}/tcg-target.h (100%) rename tcg/{ppc =3D> ppc64}/tcg-target-opc.h.inc (100%) rename tcg/{ppc =3D> ppc64}/tcg-target.c.inc (100%) diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc64/tcg-target-con-set.h similarity index 100% rename from tcg/ppc/tcg-target-con-set.h rename to tcg/ppc64/tcg-target-con-set.h diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc64/tcg-target-con-str.h similarity index 100% rename from tcg/ppc/tcg-target-con-str.h rename to tcg/ppc64/tcg-target-con-str.h diff --git a/tcg/ppc/tcg-target-has.h b/tcg/ppc64/tcg-target-has.h similarity index 100% rename from tcg/ppc/tcg-target-has.h rename to tcg/ppc64/tcg-target-has.h diff --git a/tcg/ppc/tcg-target-mo.h b/tcg/ppc64/tcg-target-mo.h similarity index 100% rename from tcg/ppc/tcg-target-mo.h rename to tcg/ppc64/tcg-target-mo.h diff --git a/tcg/ppc/tcg-target-reg-bits.h b/tcg/ppc64/tcg-target-reg-bits.h similarity index 100% rename from tcg/ppc/tcg-target-reg-bits.h rename to tcg/ppc64/tcg-target-reg-bits.h diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc64/tcg-target.h similarity index 100% rename from tcg/ppc/tcg-target.h rename to tcg/ppc64/tcg-target.h diff --git a/MAINTAINERS b/MAINTAINERS index c39a8f54e8..c58fa93fd5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4079,7 +4079,7 @@ F: tcg/mips/ PPC TCG target M: Richard Henderson S: Odd Fixes -F: tcg/ppc/ +F: tcg/ppc64/ =20 RISC-V TCG target M: Palmer Dabbelt diff --git a/meson.build b/meson.build index 594e7d42c0..0647ca0c89 100644 --- a/meson.build +++ b/meson.build @@ -907,8 +907,6 @@ if have_tcg endif if get_option('tcg_interpreter') tcg_arch =3D 'tci' - elif host_arch =3D=3D 'ppc64' - tcg_arch =3D 'ppc' endif add_project_arguments('-iquote', meson.current_source_dir() / 'tcg' / tc= g_arch, language: all_languages) diff --git a/tcg/ppc/tcg-target-opc.h.inc b/tcg/ppc64/tcg-target-opc.h.inc similarity index 100% rename from tcg/ppc/tcg-target-opc.h.inc rename to tcg/ppc64/tcg-target-opc.h.inc diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc64/tcg-target.c.inc similarity index 100% rename from tcg/ppc/tcg-target.c.inc rename to tcg/ppc64/tcg-target.c.inc --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7193dbb74sm74402865ad.56.2026.01.18.14.04.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:04:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768773899; x=1769378699; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KL546BRv3o5TBcmNuNTcD1O7NivqyCwfyc6P5AJbIyY=; b=Bvt0hEl81D1xNi8zeBV5X04qu9FORe3GNBGpMGL6zdPLMkB6Jq1Y+O3EYUIP8lz9Mo s6mDP5BP4tg98DUo1RuHs53PuRyfUg/QMrjGebcnWvKqR5DobpGxkaStrkm0IrCmSbOz Eu25hnz/ZwRZENAFTZ2CNv8aiUmyCBlSYgRQVtOnexjBsj+5ILGDY/JYIdISh45Wxpr+ hqk4yHDwv3040bglVn9d+LhsM+j8st2zthMeeVhzgOzjXpEdjU9Jui2xvSsloKS6yULU Tzg7hEvadZCK+S9BqsnSc30XQzOROeqepENPnu7BopD40sCnApvcK2/gjyunY+B/joF2 dEDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768773899; x=1769378699; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=KL546BRv3o5TBcmNuNTcD1O7NivqyCwfyc6P5AJbIyY=; b=dgbuWGWqPtMCtyz6xMxJAIdmwZy9eOSJUQ1+c9iavNdkkAIgLxrq0lx4gmWU1ytog/ oFBDCfGHDpSAtAmm3DpWI1Ur8Qhuo6vXmG7kVEHpo/mwreYmJu5Y7EG3SL0ik6JCc83o IxzyTvuxAC8f2SBp+0PeccWPNnx6ZGA6B70krYHlj/ZJ3FyrtHw2r9IkFrkiazaHgNus MmcVTz23Gs8vMLkobMT+Wg3fY2g5o8ICcG9QW/p7ma6K3erLZBCaUhCg64WzsDxKFVAu MpMr+ynyOdX/Nd2AGMYfmKVAFu4EViNRhNySbajmyjuYpApmlqtsKlNcEHAOBJlaKuDX SnOA== X-Gm-Message-State: AOJu0YxAPlx/FUtXnkv9ThiAnrzqqbzmRycZ1CK7pcZYvNP3tMdP/ruT 7Atc1Wvz9u6Hf2RLeFMWGR1rvFGvoEszV1z8PY+LeJQ3be082F1shk58NOcbhuPyZNaHLL1XcGI cdCdBsSUNGw== X-Gm-Gg: AY/fxX6p1HxE8pKgqEVuAkwOVtt0iw4wChHIJcUbP/I5yKfTb9+fQ8qpnmfBtWAim9N NbD65aOgBbEi1aufqLxk7BHDo2AWbciFE+ddxNFEm/kMpRUHK9o4w9sERrm3WZJ/MJQllIr/iYD IIxGFdwxUNdLcKvKaBZ20rxlruX7msfEPMX4HrH5/+/eDsTZxu+/qTGWduu+PONKTzTbNVLwv+k PS8u5Qd/mllpQ345iyq3hHjtkXSjGYOMJCJsO783qUmxfqQkT6pJLHh0gwe9+wPBYsazgKA2BM9 SgU5QRLCXf++28yTjU9d0VV0cNsXPZW0W7KUiqQ+SkuSORlbwA69XbhSeS3gtBaW/LOByugnoDp x5WJD6KjJQ4H4cXJvnzH+2EVOVKV3JiJhSZttBxRhNU2Ks6oC15QJszyW87eZVOPvyB6hrQIAh6 CR35/3llvbqwsPoEN5KMHQTaBzii5V X-Received: by 2002:a17:903:b4e:b0:295:5da6:600c with SMTP id d9443c01a7336-2a71752979dmr104849255ad.2.1768773898985; Sun, 18 Jan 2026 14:04:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 16/54] meson: Drop host_arch rename for mips64 Date: Mon, 19 Jan 2026 09:03:36 +1100 Message-ID: <20260118220414.8177-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768773946095158500 This requires renaming several directories: tcg/mips, linux-user/include/host/mips, and common-user/host/mips. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- linux-user/include/host/{mips =3D> mips64}/host-signal.h | 0 tcg/{mips =3D> mips64}/tcg-target-con-set.h | 0 tcg/{mips =3D> mips64}/tcg-target-con-str.h | 0 tcg/{mips =3D> mips64}/tcg-target-has.h | 0 tcg/{mips =3D> mips64}/tcg-target-mo.h | 0 tcg/{mips =3D> mips64}/tcg-target-reg-bits.h | 0 tcg/{mips =3D> mips64}/tcg-target.h | 0 MAINTAINERS | 2 +- common-user/host/{mips =3D> mips64}/safe-syscall.inc.S | 0 configure | 8 +++----- meson.build | 2 -- tcg/{mips =3D> mips64}/tcg-target-opc.h.inc | 0 tcg/{mips =3D> mips64}/tcg-target.c.inc | 0 13 files changed, 4 insertions(+), 8 deletions(-) rename linux-user/include/host/{mips =3D> mips64}/host-signal.h (100%) rename tcg/{mips =3D> mips64}/tcg-target-con-set.h (100%) rename tcg/{mips =3D> mips64}/tcg-target-con-str.h (100%) rename tcg/{mips =3D> mips64}/tcg-target-has.h (100%) rename tcg/{mips =3D> mips64}/tcg-target-mo.h (100%) rename tcg/{mips =3D> mips64}/tcg-target-reg-bits.h (100%) rename tcg/{mips =3D> mips64}/tcg-target.h (100%) rename common-user/host/{mips =3D> mips64}/safe-syscall.inc.S (100%) rename tcg/{mips =3D> mips64}/tcg-target-opc.h.inc (100%) rename tcg/{mips =3D> mips64}/tcg-target.c.inc (100%) diff --git a/linux-user/include/host/mips/host-signal.h b/linux-user/includ= e/host/mips64/host-signal.h similarity index 100% rename from linux-user/include/host/mips/host-signal.h rename to linux-user/include/host/mips64/host-signal.h diff --git a/tcg/mips/tcg-target-con-set.h b/tcg/mips64/tcg-target-con-set.h similarity index 100% rename from tcg/mips/tcg-target-con-set.h rename to tcg/mips64/tcg-target-con-set.h diff --git a/tcg/mips/tcg-target-con-str.h b/tcg/mips64/tcg-target-con-str.h similarity index 100% rename from tcg/mips/tcg-target-con-str.h rename to tcg/mips64/tcg-target-con-str.h diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips64/tcg-target-has.h similarity index 100% rename from tcg/mips/tcg-target-has.h rename to tcg/mips64/tcg-target-has.h diff --git a/tcg/mips/tcg-target-mo.h b/tcg/mips64/tcg-target-mo.h similarity index 100% rename from tcg/mips/tcg-target-mo.h rename to tcg/mips64/tcg-target-mo.h diff --git a/tcg/mips/tcg-target-reg-bits.h b/tcg/mips64/tcg-target-reg-bit= s.h similarity index 100% rename from tcg/mips/tcg-target-reg-bits.h rename to tcg/mips64/tcg-target-reg-bits.h diff --git a/tcg/mips/tcg-target.h b/tcg/mips64/tcg-target.h similarity index 100% rename from tcg/mips/tcg-target.h rename to tcg/mips64/tcg-target.h diff --git a/MAINTAINERS b/MAINTAINERS index c58fa93fd5..d3e6041186 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4074,7 +4074,7 @@ R: Huacai Chen R: Jiaxun Yang R: Aleksandar Rikalo S: Odd Fixes -F: tcg/mips/ +F: tcg/mips64/ =20 PPC TCG target M: Richard Henderson diff --git a/common-user/host/mips/safe-syscall.inc.S b/common-user/host/mi= ps64/safe-syscall.inc.S similarity index 100% rename from common-user/host/mips/safe-syscall.inc.S rename to common-user/host/mips64/safe-syscall.inc.S diff --git a/configure b/configure index e9d0b9e2c0..04d0b214b6 100755 --- a/configure +++ b/configure @@ -400,10 +400,8 @@ elif check_define _ARCH_PPC64 ; then else cpu=3D"ppc64" fi -elif check_define __mips__ ; then - if check_define __mips64 ; then - cpu=3D"mips64" - fi +elif check_define __mips64 ; then + cpu=3D"mips64" elif check_define __s390__ ; then if check_define __s390x__ ; then cpu=3D"s390x" @@ -455,7 +453,7 @@ case "$cpu" in =20 mips64*|mipsisa64*) cpu=3Dmips64 - host_arch=3Dmips + host_arch=3Dmips64 linux_arch=3Dmips ;; =20 diff --git a/meson.build b/meson.build index 0647ca0c89..c36f2f6962 100644 --- a/meson.build +++ b/meson.build @@ -265,8 +265,6 @@ enable_modules =3D get_option('modules') \ =20 if cpu not in supported_cpus host_arch =3D 'unknown' -elif cpu =3D=3D 'mips64' - host_arch =3D 'mips' elif cpu in ['riscv32', 'riscv64'] host_arch =3D 'riscv' else diff --git a/tcg/mips/tcg-target-opc.h.inc b/tcg/mips64/tcg-target-opc.h.inc similarity index 100% rename from tcg/mips/tcg-target-opc.h.inc rename to tcg/mips64/tcg-target-opc.h.inc diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips64/tcg-target.c.inc similarity index 100% rename from tcg/mips/tcg-target.c.inc rename to tcg/mips64/tcg-target.c.inc --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- host/include/{riscv =3D> riscv64}/host/cpuinfo.h | 0 linux-user/include/host/{riscv =3D> riscv64}/host-signal.h | 0 tcg/{riscv =3D> riscv64}/tcg-target-con-set.h | 0 tcg/{riscv =3D> riscv64}/tcg-target-con-str.h | 0 tcg/{riscv =3D> riscv64}/tcg-target-has.h | 0 tcg/{riscv =3D> riscv64}/tcg-target-mo.h | 0 tcg/{riscv =3D> riscv64}/tcg-target-reg-bits.h | 0 tcg/{riscv =3D> riscv64}/tcg-target.h | 0 MAINTAINERS | 2 +- common-user/host/{riscv =3D> riscv64}/safe-syscall.inc.S | 0 configure | 4 ++-- meson.build | 2 -- tcg/{riscv =3D> riscv64}/tcg-target-opc.h.inc | 0 tcg/{riscv =3D> riscv64}/tcg-target.c.inc | 0 14 files changed, 3 insertions(+), 5 deletions(-) rename host/include/{riscv =3D> riscv64}/host/cpuinfo.h (100%) rename linux-user/include/host/{riscv =3D> riscv64}/host-signal.h (100%) rename tcg/{riscv =3D> riscv64}/tcg-target-con-set.h (100%) rename tcg/{riscv =3D> riscv64}/tcg-target-con-str.h (100%) rename tcg/{riscv =3D> riscv64}/tcg-target-has.h (100%) rename tcg/{riscv =3D> riscv64}/tcg-target-mo.h (100%) rename tcg/{riscv =3D> riscv64}/tcg-target-reg-bits.h (100%) rename tcg/{riscv =3D> riscv64}/tcg-target.h (100%) rename common-user/host/{riscv =3D> riscv64}/safe-syscall.inc.S (100%) rename tcg/{riscv =3D> riscv64}/tcg-target-opc.h.inc (100%) rename tcg/{riscv =3D> riscv64}/tcg-target.c.inc (100%) diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv64/host/= cpuinfo.h similarity index 100% rename from host/include/riscv/host/cpuinfo.h rename to host/include/riscv64/host/cpuinfo.h diff --git a/linux-user/include/host/riscv/host-signal.h b/linux-user/inclu= de/host/riscv64/host-signal.h similarity index 100% rename from linux-user/include/host/riscv/host-signal.h rename to linux-user/include/host/riscv64/host-signal.h diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv64/tcg-target-con-se= t.h similarity index 100% rename from tcg/riscv/tcg-target-con-set.h rename to tcg/riscv64/tcg-target-con-set.h diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv64/tcg-target-con-st= r.h similarity index 100% rename from tcg/riscv/tcg-target-con-str.h rename to tcg/riscv64/tcg-target-con-str.h diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv64/tcg-target-has.h similarity index 100% rename from tcg/riscv/tcg-target-has.h rename to tcg/riscv64/tcg-target-has.h diff --git a/tcg/riscv/tcg-target-mo.h b/tcg/riscv64/tcg-target-mo.h similarity index 100% rename from tcg/riscv/tcg-target-mo.h rename to tcg/riscv64/tcg-target-mo.h diff --git a/tcg/riscv/tcg-target-reg-bits.h b/tcg/riscv64/tcg-target-reg-b= its.h similarity index 100% rename from tcg/riscv/tcg-target-reg-bits.h rename to tcg/riscv64/tcg-target-reg-bits.h diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv64/tcg-target.h similarity index 100% rename from tcg/riscv/tcg-target.h rename to tcg/riscv64/tcg-target.h diff --git a/MAINTAINERS b/MAINTAINERS index d3e6041186..c1e586c58f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4086,7 +4086,7 @@ M: Palmer Dabbelt M: Alistair Francis L: qemu-riscv@nongnu.org S: Maintained -F: tcg/riscv/ +F: tcg/riscv64/ F: disas/riscv.[ch] =20 S390 TCG target diff --git a/common-user/host/riscv/safe-syscall.inc.S b/common-user/host/r= iscv64/safe-syscall.inc.S similarity index 100% rename from common-user/host/riscv/safe-syscall.inc.S rename to common-user/host/riscv64/safe-syscall.inc.S diff --git a/configure b/configure index 04d0b214b6..ee09f90125 100755 --- a/configure +++ b/configure @@ -469,8 +469,8 @@ case "$cpu" in CPU_CFLAGS=3D"-m64 -mlittle-endian" ;; =20 - riscv32 | riscv64) - host_arch=3Driscv + riscv64) + host_arch=3Driscv64 linux_arch=3Driscv ;; =20 diff --git a/meson.build b/meson.build index c36f2f6962..e1ac764793 100644 --- a/meson.build +++ b/meson.build @@ -265,8 +265,6 @@ enable_modules =3D get_option('modules') \ =20 if cpu not in supported_cpus host_arch =3D 'unknown' -elif cpu in ['riscv32', 'riscv64'] - host_arch =3D 'riscv' else host_arch =3D cpu endif diff --git a/tcg/riscv/tcg-target-opc.h.inc b/tcg/riscv64/tcg-target-opc.h.= inc similarity index 100% rename from tcg/riscv/tcg-target-opc.h.inc rename to tcg/riscv64/tcg-target-opc.h.inc diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc similarity index 100% rename from tcg/riscv/tcg-target.c.inc rename to tcg/riscv64/tcg-target.c.inc --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7193dbb74sm74402865ad.56.2026.01.18.14.05.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:05:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768773904; x=1769378704; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tsCu8YjwoP3qndepqs66QlB075g8dS34UiTzdMRlo7I=; b=RDoukg824a2Zia3MQGgRz1VK341lszvmEwiXZqjDdBL05tpCTfsi33+huvd69bbBGG VMtPPUiZtUyaYwQoC1r3yXgESSOJvihWVhaZLJmfPc6YsA98WSUDQAYbaVSa0R1AfyNZ iZa+7iYmcF3T+5cqSIdFt8qVGdUNu+E1vhIbidORsDv475wIfKpeIHjt3M8EqOCWAzF9 Iu0/HsSRI3xQitEcn+1X6nmfRXVUFzf4HgxFI9A+zvdcrS8tAMUDBvAAHBdzE47DWMdT C5d8WRU3ja1L48UdEw3gFR4OXNglicKN86x8DXHpTdmA0UjxilwUdO4EwuOfM4BWVva1 Bp4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768773904; x=1769378704; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=tsCu8YjwoP3qndepqs66QlB075g8dS34UiTzdMRlo7I=; b=YUmToM3ZuRBDjy2LRLTvFius4vbCAVQ1V+gRPm8iDR6Bo1mYqkk9QXmlMEYwW0TUwn IkEUScx3a1V6FnCJXAIhXDWjmpAQ1RBXfujaE0LZzBXlIYGaUWC6qHbxUuJOXQI3vEb2 2DcJaf6EA18Mvy+jJSImjTkzcb28jJR5njdE+v411YBJQWm6bimaFte01jcMN/uDoryo 5O1I8qdPwYlAWavK1T7M1sGRrRAMlWkvNdEVfTMFBcHcB5QxliGN0n8OwSbY3ZYsaKam X7jst5/8hBs52oDWML+hNOZYAAfDo556UrZfrHGzhYEDrbIjBpERV8d08wHuxeMJMk0w 05Cw== X-Gm-Message-State: AOJu0YykoSi5HOpbJjs9ACycrw9HZYsuNgQDUIPm3vBdsUepE05IPCx3 rCRmbOPWEsJT+ASnkaWdQ6fSvDCltU96tVxkdXc+XhmmwwdRVwZ3MEOe+vs5pVg+BXocfJUUzpy weYC1DFYB4w== X-Gm-Gg: AY/fxX7wvy1e5WcDKpgCQfJa/4AKclD19eT0PQyvMFCSiy+QzC0JZy9fz3IUZaXhX+n 7WZ8u+UBqpGrT3Nc4CZ1OHnpgp0b2cVJQY3Ng4Jclj3hfOH19rBMZR4IiDrprpWyUVfBf6SvaJL kvbG2UAKNpu/9Ha49p0YtezzAbwN4jl/7OxojSQKWFb/jJY/L6reKgLE3+eKGfFh7dB1uUxCM3I hWNHGLkPfNw/bNL1rVj+umUk6F/Ybp8NXMACWDwSSQmvyBngG5z0rEdH+bxslXYarQHcsPUo3TO 85MTrmf/O+wDu1mebpKwOWW12u4kFUWZSGGGmqC0i1Cbxr26saH2iyLALx2Hzm9wVSBwVyMHi7r OwdbFeKB9i0fWuNqCnjocqqWj59ZM0Vu/F8wophVVj1w+HOZ/+nWX8dGZre1kIPoA5JGgNQwAQ/ dTdz9+Ed0R/eMPOk2xpA== X-Received: by 2002:a17:902:8ecc:b0:29e:5623:7fc3 with SMTP id d9443c01a7336-2a71751c5d0mr60501765ad.12.1768773904089; Sun, 18 Jan 2026 14:05:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 18/54] meson: Remove cpu == riscv32 tests Date: Mon, 19 Jan 2026 09:03:38 +1100 Message-ID: <20260118220414.8177-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774146717158500 The 32-bit riscv host is no longer supported. Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- configure | 10 +++------- meson.build | 4 +--- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/configure b/configure index ee09f90125..e69b3e474e 100755 --- a/configure +++ b/configure @@ -408,12 +408,8 @@ elif check_define __s390__ ; then else cpu=3D"s390" fi -elif check_define __riscv ; then - if check_define _LP64 ; then - cpu=3D"riscv64" - else - cpu=3D"riscv32" - fi +elif check_define __riscv && check_define _LP64 ; then + cpu=3D"riscv64" elif check_define __aarch64__ ; then cpu=3D"aarch64" elif check_define __loongarch64 ; then @@ -1280,7 +1276,7 @@ EOF test "$bigendian" =3D no && rust_arch=3D${rust_arch}el ;; =20 - riscv32|riscv64) + riscv64) # e.g. riscv64gc-unknown-linux-gnu, but riscv64-linux-android test "$android" =3D no && rust_arch=3D${rust_arch}gc ;; diff --git a/meson.build b/meson.build index e1ac764793..0189d8fd44 100644 --- a/meson.build +++ b/meson.build @@ -50,7 +50,7 @@ qapi_trace_events =3D [] =20 bsd_oses =3D ['gnu/kfreebsd', 'freebsd', 'netbsd', 'openbsd', 'dragonfly',= 'darwin'] supported_oses =3D ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', '= sunos', 'linux', 'emscripten'] -supported_cpus =3D ['ppc64', 's390x', 'riscv32', 'riscv64', 'x86_64', +supported_cpus =3D ['ppc64', 's390x', 'riscv64', 'x86_64', 'aarch64', 'loongarch64', 'mips64', 'sparc64', 'wasm64'] =20 cpu =3D host_machine.cpu_family() @@ -279,8 +279,6 @@ elif cpu =3D=3D 'ppc64' kvm_targets =3D ['ppc-softmmu', 'ppc64-softmmu'] elif cpu =3D=3D 'mips64' kvm_targets =3D ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mi= ps64el-softmmu'] -elif cpu =3D=3D 'riscv32' - kvm_targets =3D ['riscv32-softmmu'] elif cpu =3D=3D 'riscv64' kvm_targets =3D ['riscv64-softmmu'] elif cpu =3D=3D 'loongarch64' --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774093; cv=none; d=zohomail.com; s=zohoarc; b=ff2xI/F8Sudm9xBuu6e1vnMIXazskKqDEvRVnMV88K0L+MiqldbGaeWESTFXFaaFby+fUpCrqZCfCuZGGKQPMYTdBwd7ZDpL90bUENGSvQ8/V6bqSD4Ra2Gh5GTY/X4yLjaWEH0m9jK8F/tdxbKOt8YQXOeVnh0djEVXjD79gnE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768774093; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=C9G7CRzjGckeYSeIr9MRvFLtIOKXPKdQ7GnAe48PSp8=; b=lW3KaKN4Hm8YdxHhqXOhUzrf7slPwSJ/rQEExnzwvPucTEKcPlexMSOzjYZihKRCbSXamDlVx28nmSz0L+jV9S+lDHSuWY2uoqTXYnUuyx/oDSKEso/3mRzJJG8nx2Ougr3OPfG0R+UjcnUQMP0iYbaHIyvH7WXukmVesY/UlXU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768774093449383.3080742452703; Sun, 18 Jan 2026 14:08:13 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhatw-0003eg-VF; Sun, 18 Jan 2026 17:05:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhatT-0002I8-La for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:15 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhatP-0000oW-VY for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:09 -0500 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-2a081c163b0so19914595ad.0 for ; Sun, 18 Jan 2026 14:05:07 -0800 (PST) Received: from stoup.. ([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7193dbb74sm74402865ad.56.2026.01.18.14.05.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:05:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768773907; x=1769378707; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C9G7CRzjGckeYSeIr9MRvFLtIOKXPKdQ7GnAe48PSp8=; b=XA2mRoBzAjbShPR/+5Leae0ZZlN7SVDHJ5Vaah/qWZpAU+rjgeBJ60wCLbluFPJKq5 xyQyIVzzMSMHhF6jX84pfax9LgA3dttOFaFKqACzwv3QPuGERGlUol1gyx1MkVb62g1+ emWIkfv9cm2/hjiDCQH7s0Lb+uQTpWubWsSny5mI2L/1nYi256i/Veugv2MBKbpbO8Io 3q8aBrh+P5jukbhYPqNX6pR9EiCnhvBZVjRgevUH+ZvdbXuoLF+VaPZpyK131Dl/rAps jYQR8miDX86uLaE6SIUVN7brjFcPEuepazrAG20D22BkBVBXzEFotLU3d0XPlZ+I6sn1 Rd8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768773907; x=1769378707; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=C9G7CRzjGckeYSeIr9MRvFLtIOKXPKdQ7GnAe48PSp8=; b=IcFXCzgudWGJZmVqLGzLm99qNJp5YcsEik+wd6ZtiPJ03aNaeqkjpuVWbJ+UxNdJ1W /3UuVjhYPCmZ7JcaMx91rLOZlDxJneIrgA99LA4+KPK7k88b/SPNza/emW93ByMgK1IT KpTN2RMLE4hIs2vp8o+aN5nzgvLbgOfYaic0HW+3WnhnPJuzyLPGUmiCnHHFokiZkTqi QAQIloVEui3ApCGswlK9c4rgI0MhYs3e/QNGcHX8lahB4b2byqoN/VzikMdl1KRMv/kk e66nE5BcUvqnEc3VNA2essWFvIV/JBXkpfPXdclzmexwHbJLrMqeghYvZJKNZW7C7bKc Cknw== X-Gm-Message-State: AOJu0Yy1CNrOFxFbjzuwoYlkalSzm/Ml/7ASNGyt1L3j9DCMR+bQMsLV Y5BjW1djAHN6WKhHT9RfKbMQqZH78qyvX21tmzfPpH7i5CJiY6kNNzaZEx9O+WGVcFAVT3Lh0ze zsVooyQoYPQ== X-Gm-Gg: AY/fxX7Rq6nEYTmeujBaPVxXD5/KZdFZgGSFFaJvI4MVcGRLj9lGddyH1gDlnfRnww/ nNxJzdxf6Sl1/ULgHGCgLIjYhkpcZE0rtT7mSDp4MKjYecvEFIJdoMFs/GGBiZDMCNhIdvEOUr2 9fH/s49T6ZF2lRQ5DmPSTF/x8g59roqNmx50yu3JSZXE4O52iZ999etiQ9FzmW3DUlAku/mtV3w i6jY8PUmVfAgH8t2dCah5OPuo7qYBIYtLSbBwK27sVMZDbXD+Maa5cINNTlnJ5kaMpTGrpsVdc0 yeCQdaZt0K091nQzqLnjJ2YWw81ksTfs7uJJa1cwbB+MyTdZLajaYuUD+f9++O+s0tHAiWmFVah m2QNhcUZ21+kAjgLt3sfIvnVdHUDeVLynUcEAPreu0i/RSkzTuRgsnxO4GWO6YKLnv44G1kVcFb a2z8R+Sa1ndd2hvXHh0g== X-Received: by 2002:a17:902:db07:b0:2a0:d074:e9f4 with SMTP id d9443c01a7336-2a71780bf89mr102598285ad.59.1768773906538; Sun, 18 Jan 2026 14:05:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 19/54] tcg: Make TCG_TARGET_REG_BITS common Date: Mon, 19 Jan 2026 09:03:39 +1100 Message-ID: <20260118220414.8177-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774094533158500 Since we only support 64-bit hosts, there's no real need to parameterize TCG_TARGET_REG_BITS. It seems worth holding on to the identifier though, for documentation purposes. Move one tcg/*/tcg-target-reg-bits.h to tcg/target-reg-bits.h and remove the others. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/helper-info.h | 2 +- .../tcg/target-reg-bits.h | 8 +++---- include/tcg/tcg.h | 2 +- tcg/aarch64/tcg-target-reg-bits.h | 12 ----------- tcg/loongarch64/tcg-target-reg-bits.h | 21 ------------------- tcg/mips64/tcg-target-reg-bits.h | 16 -------------- tcg/riscv64/tcg-target-reg-bits.h | 19 ----------------- tcg/s390x/tcg-target-reg-bits.h | 17 --------------- tcg/sparc64/tcg-target-reg-bits.h | 12 ----------- tcg/tci/tcg-target-reg-bits.h | 18 ---------------- tcg/x86_64/tcg-target-reg-bits.h | 16 -------------- 11 files changed, 6 insertions(+), 137 deletions(-) rename tcg/ppc64/tcg-target-reg-bits.h =3D> include/tcg/target-reg-bits.h = (71%) delete mode 100644 tcg/aarch64/tcg-target-reg-bits.h delete mode 100644 tcg/loongarch64/tcg-target-reg-bits.h delete mode 100644 tcg/mips64/tcg-target-reg-bits.h delete mode 100644 tcg/riscv64/tcg-target-reg-bits.h delete mode 100644 tcg/s390x/tcg-target-reg-bits.h delete mode 100644 tcg/sparc64/tcg-target-reg-bits.h delete mode 100644 tcg/tci/tcg-target-reg-bits.h delete mode 100644 tcg/x86_64/tcg-target-reg-bits.h diff --git a/include/tcg/helper-info.h b/include/tcg/helper-info.h index 49a27e4eae..d5bda83a2e 100644 --- a/include/tcg/helper-info.h +++ b/include/tcg/helper-info.h @@ -24,7 +24,7 @@ #include #pragma GCC diagnostic pop #endif -#include "tcg-target-reg-bits.h" +#include "tcg/target-reg-bits.h" =20 #define MAX_CALL_IARGS 7 =20 diff --git a/tcg/ppc64/tcg-target-reg-bits.h b/include/tcg/target-reg-bits.h similarity index 71% rename from tcg/ppc64/tcg-target-reg-bits.h rename to include/tcg/target-reg-bits.h index 3a15d7bee4..8f4ad3ed99 100644 --- a/tcg/ppc64/tcg-target-reg-bits.h +++ b/include/tcg/target-reg-bits.h @@ -7,10 +7,10 @@ #ifndef TCG_TARGET_REG_BITS_H #define TCG_TARGET_REG_BITS_H =20 -#ifndef _ARCH_PPC64 -# error Expecting 64-bit host architecture -#endif - +/* + * We only support 64-bit hosts now. + * Retain the identifier for documentation. + */ #define TCG_TARGET_REG_BITS 64 =20 #endif diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index a6d9aa50d4..067150c542 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -31,7 +31,7 @@ #include "qemu/plugin.h" #include "qemu/queue.h" #include "tcg/tcg-mo.h" -#include "tcg-target-reg-bits.h" +#include "tcg/target-reg-bits.h" #include "tcg-target.h" #include "tcg/tcg-cond.h" #include "tcg/insn-start-words.h" diff --git a/tcg/aarch64/tcg-target-reg-bits.h b/tcg/aarch64/tcg-target-reg= -bits.h deleted file mode 100644 index 3b57a1aafb..0000000000 --- a/tcg/aarch64/tcg-target-reg-bits.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Define target-specific register size - * Copyright (c) 2023 Linaro - */ - -#ifndef TCG_TARGET_REG_BITS_H -#define TCG_TARGET_REG_BITS_H - -#define TCG_TARGET_REG_BITS 64 - -#endif diff --git a/tcg/loongarch64/tcg-target-reg-bits.h b/tcg/loongarch64/tcg-ta= rget-reg-bits.h deleted file mode 100644 index 51373ad70a..0000000000 --- a/tcg/loongarch64/tcg-target-reg-bits.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Define target-specific register size - * Copyright (c) 2021 WANG Xuerui - */ - -#ifndef TCG_TARGET_REG_BITS_H -#define TCG_TARGET_REG_BITS_H - -/* - * Loongson removed the (incomplete) 32-bit support from kernel and toolch= ain - * for the initial upstreaming of this architecture, so don't bother and j= ust - * support the LP64* ABI for now. - */ -#if defined(__loongarch64) -# define TCG_TARGET_REG_BITS 64 -#else -# error unsupported LoongArch register size -#endif - -#endif diff --git a/tcg/mips64/tcg-target-reg-bits.h b/tcg/mips64/tcg-target-reg-b= its.h deleted file mode 100644 index ee346a3f25..0000000000 --- a/tcg/mips64/tcg-target-reg-bits.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Define target-specific register size - * Copyright (c) 2008-2009 Arnaud Patard - */ - -#ifndef TCG_TARGET_REG_BITS_H -#define TCG_TARGET_REG_BITS_H - -#if !defined(_MIPS_SIM) || _MIPS_SIM !=3D _ABI64 -# error "Unknown ABI" -#endif - -#define TCG_TARGET_REG_BITS 64 - -#endif diff --git a/tcg/riscv64/tcg-target-reg-bits.h b/tcg/riscv64/tcg-target-reg= -bits.h deleted file mode 100644 index 761ca0d774..0000000000 --- a/tcg/riscv64/tcg-target-reg-bits.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Define target-specific register size - * Copyright (c) 2018 SiFive, Inc - */ - -#ifndef TCG_TARGET_REG_BITS_H -#define TCG_TARGET_REG_BITS_H - -/* - * We don't support oversize guests. - * Since we will only build tcg once, this in turn requires a 64-bit host. - */ -#if __riscv_xlen !=3D 64 -#error "unsupported code generation mode" -#endif -#define TCG_TARGET_REG_BITS 64 - -#endif diff --git a/tcg/s390x/tcg-target-reg-bits.h b/tcg/s390x/tcg-target-reg-bit= s.h deleted file mode 100644 index b01414e09d..0000000000 --- a/tcg/s390x/tcg-target-reg-bits.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Define target-specific register size - * Copyright (c) 2009 Ulrich Hecht - */ - -#ifndef TCG_TARGET_REG_BITS_H -#define TCG_TARGET_REG_BITS_H - -/* We only support generating code for 64-bit mode. */ -#if UINTPTR_MAX =3D=3D UINT64_MAX -# define TCG_TARGET_REG_BITS 64 -#else -# error "unsupported code generation mode" -#endif - -#endif diff --git a/tcg/sparc64/tcg-target-reg-bits.h b/tcg/sparc64/tcg-target-reg= -bits.h deleted file mode 100644 index 34a6711013..0000000000 --- a/tcg/sparc64/tcg-target-reg-bits.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Define target-specific register size - * Copyright (c) 2023 Linaro - */ - -#ifndef TCG_TARGET_REG_BITS_H -#define TCG_TARGET_REG_BITS_H - -#define TCG_TARGET_REG_BITS 64 - -#endif diff --git a/tcg/tci/tcg-target-reg-bits.h b/tcg/tci/tcg-target-reg-bits.h deleted file mode 100644 index dcb1a203f8..0000000000 --- a/tcg/tci/tcg-target-reg-bits.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Define target-specific register size - * Copyright (c) 2009, 2011 Stefan Weil - */ - -#ifndef TCG_TARGET_REG_BITS_H -#define TCG_TARGET_REG_BITS_H - -#if UINTPTR_MAX =3D=3D UINT32_MAX -# define TCG_TARGET_REG_BITS 32 -#elif UINTPTR_MAX =3D=3D UINT64_MAX -# define TCG_TARGET_REG_BITS 64 -#else -# error Unknown pointer size for tci target -#endif - -#endif diff --git a/tcg/x86_64/tcg-target-reg-bits.h b/tcg/x86_64/tcg-target-reg-b= its.h deleted file mode 100644 index fc3377e829..0000000000 --- a/tcg/x86_64/tcg-target-reg-bits.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Define target-specific register size - * Copyright (c) 2008 Fabrice Bellard - */ - -#ifndef TCG_TARGET_REG_BITS_H -#define TCG_TARGET_REG_BITS_H - -#ifdef __x86_64__ -# define TCG_TARGET_REG_BITS 64 -#else -# error -#endif - -#endif --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768773960; cv=none; d=zohomail.com; s=zohoarc; b=cTiEC37ART8f4BVTYHsGioi9Sq3fbUgH61+PR2bOrBe6pdzAF2qyd9P2MFoHO5UgepFFuSN4oMzDDXEcbOTD8HifxKxxEDdjfldDqlD0AaEdKH75I+dnU8siFW82kGpHkI+/c05Y+eCBH8PDgJUvf7CzVk+VFocfSdf/CpvhBs4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768773960; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=U5sBU2zk1bX0ddl3O5KkamyL/V1clpqH1xPWvT/iVmQ=; b=kfbSx6o99IejRPluAWHZh3oOOjmVIGnMIjLMUH4UBnKR9x/gocLvBbLw+ciYnShPPfmySnMlds7+Fm/NWMfwX+lfqnLzL/RL0hV44TnqitwpRfX4WkQov+gf/qHuhgcmD9NCrCDnba9lKnYlDzHyUjdRP5S/EbVDFKZSUzUKyjU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176877396002177.24883258833938; Sun, 18 Jan 2026 14:06:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhatq-0002sE-Uu; Sun, 18 Jan 2026 17:05:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhatV-0002K8-NR for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:22 -0500 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhatT-0000p1-Du for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:12 -0500 Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-c47ee987401so1508587a12.1 for ; Sun, 18 Jan 2026 14:05:10 -0800 (PST) Received: from stoup.. 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Reviewed-by: Thomas Huth Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.c | 2 +- tcg/loongarch64/tcg-target.c.inc | 4 ++-- tcg/ppc64/tcg-target.c.inc | 2 +- tcg/riscv64/tcg-target.c.inc | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 2d184547ba..9c33430638 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -607,7 +607,7 @@ static void do_dup(unsigned vece, TCGv_ptr dbase, uint3= 2_t dofs, } =20 /* Otherwise, inline with an integer type, unless "large". */ - if (check_size_impl(oprsz, TCG_TARGET_REG_BITS / 8)) { + if (check_size_impl(oprsz, sizeof(tcg_target_long))) { t_64 =3D NULL; t_32 =3D NULL; =20 diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 10c69211ac..c3350c90fc 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -2604,7 +2604,7 @@ static const int tcg_target_callee_save_regs[] =3D { }; =20 /* Stack frame parameters. */ -#define REG_SIZE (TCG_TARGET_REG_BITS / 8) +#define REG_SIZE ((int)sizeof(tcg_target_long)) #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZ= E) #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ @@ -2731,7 +2731,7 @@ static const DebugFrame debug_frame =3D { .h.cie.id =3D -1, .h.cie.version =3D 1, .h.cie.code_align =3D 1, - .h.cie.data_align =3D -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ + .h.cie.data_align =3D -sizeof(tcg_target_long) & 0x7f, /* sleb128 */ .h.cie.return_column =3D TCG_REG_RA, =20 /* Total FDE size does not include the "len" member. */ diff --git a/tcg/ppc64/tcg-target.c.inc b/tcg/ppc64/tcg-target.c.inc index 3c36b26f25..b54afa0b6d 100644 --- a/tcg/ppc64/tcg-target.c.inc +++ b/tcg/ppc64/tcg-target.c.inc @@ -70,7 +70,7 @@ #define SZP ((int)sizeof(void *)) =20 /* Shorthand for size of a register. */ -#define SZR (TCG_TARGET_REG_BITS / 8) +#define SZR ((int)sizeof(tcg_target_long)) =20 #define TCG_CT_CONST_S16 0x00100 #define TCG_CT_CONST_U16 0x00200 diff --git a/tcg/riscv64/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc index 0967a445a3..76dd4fca97 100644 --- a/tcg/riscv64/tcg-target.c.inc +++ b/tcg/riscv64/tcg-target.c.inc @@ -2934,7 +2934,7 @@ static const int tcg_target_callee_save_regs[] =3D { }; =20 /* Stack frame parameters. */ -#define REG_SIZE (TCG_TARGET_REG_BITS / 8) +#define REG_SIZE ((int)sizeof(tcg_target_long)) #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZ= E) #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ @@ -3114,7 +3114,7 @@ static const DebugFrame debug_frame =3D { .h.cie.id =3D -1, .h.cie.version =3D 1, .h.cie.code_align =3D 1, - .h.cie.data_align =3D -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ + .h.cie.data_align =3D -sizeof(tcg_target_long) & 0x7f, /* sleb128 */ .h.cie.return_column =3D TCG_REG_RA, =20 /* Total FDE size does not include the "len" member. */ --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/gengvec.c | 32 ++++++------- target/arm/tcg/gengvec64.c | 4 +- target/arm/tcg/translate-sve.c | 26 +++++------ tcg/tcg-op-gvec.c | 62 ++++++++++++------------- target/i386/tcg/emit.c.inc | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 6 files changed, 64 insertions(+), 64 deletions(-) diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c index 01867f8ace..f97d63549c 100644 --- a/target/arm/tcg/gengvec.c +++ b/target/arm/tcg/gengvec.c @@ -165,7 +165,7 @@ void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint= 32_t rm_ofs, { .fni8 =3D gen_ssra64_i64, .fniv =3D gen_ssra_vec, .fno =3D gen_helper_gvec_ssra_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .load_dest =3D true, .vece =3D MO_64 }, @@ -241,7 +241,7 @@ void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint= 32_t rm_ofs, { .fni8 =3D gen_usra64_i64, .fniv =3D gen_usra_vec, .fno =3D gen_helper_gvec_usra_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .load_dest =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64, }, @@ -349,7 +349,7 @@ void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uin= t32_t rm_ofs, { .fni8 =3D gen_srshr64_i64, .fniv =3D gen_srshr_vec, .fno =3D gen_helper_gvec_srshr_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64 }, }; @@ -439,7 +439,7 @@ void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uin= t32_t rm_ofs, { .fni8 =3D gen_srsra64_i64, .fniv =3D gen_srsra_vec, .fno =3D gen_helper_gvec_srsra_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .load_dest =3D true, .vece =3D MO_64 }, @@ -543,7 +543,7 @@ void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uin= t32_t rm_ofs, { .fni8 =3D gen_urshr64_i64, .fniv =3D gen_urshr_vec, .fno =3D gen_helper_gvec_urshr_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64 }, }; @@ -652,7 +652,7 @@ void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uin= t32_t rm_ofs, { .fni8 =3D gen_ursra64_i64, .fniv =3D gen_ursra_vec, .fno =3D gen_helper_gvec_ursra_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .load_dest =3D true, .vece =3D MO_64 }, @@ -736,7 +736,7 @@ void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint3= 2_t rm_ofs, { .fni8 =3D gen_shr64_ins_i64, .fniv =3D gen_shr_ins_vec, .fno =3D gen_helper_gvec_sri_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .load_dest =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64 }, @@ -823,7 +823,7 @@ void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint3= 2_t rm_ofs, { .fni8 =3D gen_shl64_ins_i64, .fniv =3D gen_shl_ins_vec, .fno =3D gen_helper_gvec_sli_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .load_dest =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64 }, @@ -927,7 +927,7 @@ void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint3= 2_t rn_ofs, .vece =3D MO_32 }, { .fni8 =3D gen_mla64_i64, .fniv =3D gen_mla_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .load_dest =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64 }, @@ -959,7 +959,7 @@ void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint3= 2_t rn_ofs, .vece =3D MO_32 }, { .fni8 =3D gen_mls64_i64, .fniv =3D gen_mls_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .load_dest =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64 }, @@ -1002,7 +1002,7 @@ void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, u= int32_t rn_ofs, .vece =3D MO_32 }, { .fni8 =3D gen_cmtst_i64, .fniv =3D gen_cmtst_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64 }, }; @@ -1691,7 +1691,7 @@ void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, ui= nt32_t rn_ofs, { .fni8 =3D gen_sabd_i64, .fniv =3D gen_sabd_vec, .fno =3D gen_helper_gvec_sabd_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64 }, }; @@ -1748,7 +1748,7 @@ void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, ui= nt32_t rn_ofs, { .fni8 =3D gen_uabd_i64, .fniv =3D gen_uabd_vec, .fno =3D gen_helper_gvec_uabd_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64 }, }; @@ -1803,7 +1803,7 @@ void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, ui= nt32_t rn_ofs, { .fni8 =3D gen_saba_i64, .fniv =3D gen_saba_vec, .fno =3D gen_helper_gvec_saba_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .load_dest =3D true, .vece =3D MO_64 }, @@ -1859,7 +1859,7 @@ void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, ui= nt32_t rn_ofs, { .fni8 =3D gen_uaba_i64, .fniv =3D gen_uaba_vec, .fno =3D gen_helper_gvec_uaba_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .load_dest =3D true, .vece =3D MO_64 }, @@ -2429,7 +2429,7 @@ void gen_gvec_rev32(unsigned vece, uint32_t rd_ofs, u= int32_t rn_ofs, static const GVecGen2 g =3D { .fni8 =3D gen_bswap32_i64, .fni4 =3D tcg_gen_bswap32_i32, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_32 }; =20 diff --git a/target/arm/tcg/gengvec64.c b/target/arm/tcg/gengvec64.c index 2429cab1b8..c425d2b149 100644 --- a/target/arm/tcg/gengvec64.c +++ b/target/arm/tcg/gengvec64.c @@ -157,7 +157,7 @@ void gen_gvec_eor3(unsigned vece, uint32_t d, uint32_t = n, uint32_t m, .fniv =3D gen_eor3_vec, .fno =3D gen_helper_sve2_eor3, .vece =3D MO_64, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); } @@ -183,7 +183,7 @@ void gen_gvec_bcax(unsigned vece, uint32_t d, uint32_t = n, uint32_t m, .fniv =3D gen_bcax_vec, .fno =3D gen_helper_sve2_bcax, .vece =3D MO_64, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); } diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 07b827fa8e..64adb5c1ce 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -623,7 +623,7 @@ static void gen_bsl1n(unsigned vece, uint32_t d, uint32= _t n, uint32_t m, .fniv =3D gen_bsl1n_vec, .fno =3D gen_helper_sve2_bsl1n, .vece =3D MO_64, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); } @@ -661,7 +661,7 @@ static void gen_bsl2n(unsigned vece, uint32_t d, uint32= _t n, uint32_t m, .fniv =3D gen_bsl2n_vec, .fno =3D gen_helper_sve2_bsl2n, .vece =3D MO_64, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); } @@ -690,7 +690,7 @@ static void gen_nbsl(unsigned vece, uint32_t d, uint32_= t n, uint32_t m, .fniv =3D gen_nbsl_vec, .fno =3D gen_helper_sve2_nbsl, .vece =3D MO_64, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); } @@ -1367,7 +1367,7 @@ static bool trans_AND_pppp(DisasContext *s, arg_rprr_= s *a) .fni8 =3D gen_and_pg_i64, .fniv =3D gen_and_pg_vec, .fno =3D gen_helper_sve_and_pppp, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (!dc_isar_feature(aa64_sve, s)) { @@ -1405,7 +1405,7 @@ static bool trans_BIC_pppp(DisasContext *s, arg_rprr_= s *a) .fni8 =3D gen_bic_pg_i64, .fniv =3D gen_bic_pg_vec, .fno =3D gen_helper_sve_bic_pppp, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (!dc_isar_feature(aa64_sve, s)) { @@ -1436,7 +1436,7 @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_= s *a) .fni8 =3D gen_eor_pg_i64, .fniv =3D gen_eor_pg_vec, .fno =3D gen_helper_sve_eor_pppp, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (!dc_isar_feature(aa64_sve, s)) { @@ -1483,7 +1483,7 @@ static bool trans_ORR_pppp(DisasContext *s, arg_rprr_= s *a) .fni8 =3D gen_orr_pg_i64, .fniv =3D gen_orr_pg_vec, .fno =3D gen_helper_sve_orr_pppp, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (!dc_isar_feature(aa64_sve, s)) { @@ -1514,7 +1514,7 @@ static bool trans_ORN_pppp(DisasContext *s, arg_rprr_= s *a) .fni8 =3D gen_orn_pg_i64, .fniv =3D gen_orn_pg_vec, .fno =3D gen_helper_sve_orn_pppp, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (!dc_isar_feature(aa64_sve, s)) { @@ -1542,7 +1542,7 @@ static bool trans_NOR_pppp(DisasContext *s, arg_rprr_= s *a) .fni8 =3D gen_nor_pg_i64, .fniv =3D gen_nor_pg_vec, .fno =3D gen_helper_sve_nor_pppp, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (!dc_isar_feature(aa64_sve, s)) { @@ -1570,7 +1570,7 @@ static bool trans_NAND_pppp(DisasContext *s, arg_rprr= _s *a) .fni8 =3D gen_nand_pg_i64, .fniv =3D gen_nand_pg_vec, .fno =3D gen_helper_sve_nand_pppp, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (!dc_isar_feature(aa64_sve, s)) { @@ -3680,7 +3680,7 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_e= sz *a) .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_sve_subri_d, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64, .scalar_first =3D true } }; @@ -8024,7 +8024,7 @@ static void gen_sclamp(unsigned vece, uint32_t d, uin= t32_t n, uint32_t m, .fno =3D gen_helper_gvec_sclamp_d, .opt_opc =3D vecop, .vece =3D MO_64, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64 } + .prefer_i64 =3D true } }; tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]); } @@ -8075,7 +8075,7 @@ static void gen_uclamp(unsigned vece, uint32_t d, uin= t32_t n, uint32_t m, .fno =3D gen_helper_gvec_uclamp_d, .opt_opc =3D vecop, .vece =3D MO_64, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64 } + .prefer_i64 =3D true } }; tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]); } diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 9c33430638..2cfc7e9409 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -1754,7 +1754,7 @@ void tcg_gen_gvec_mov_var(unsigned vece, TCGv_ptr dba= se, uint32_t dofs, .fni8 =3D tcg_gen_mov_i64, .fniv =3D vec_mov2, .fno =3D gen_helper_gvec_mov, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (dofs =3D=3D aofs && dbase =3D=3D abase) { @@ -1917,7 +1917,7 @@ void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, u= int32_t aofs, .fni8 =3D tcg_gen_not_i64, .fniv =3D tcg_gen_not_vec, .fno =3D gen_helper_gvec_not, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g); } @@ -2030,7 +2030,7 @@ void tcg_gen_gvec_add_var(unsigned vece, TCGv_ptr dba= se, uint32_t dofs, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_add64, .opt_opc =3D vecop_list_add, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -2069,7 +2069,7 @@ void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, = uint32_t aofs, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_adds64, .opt_opc =3D vecop_list_add, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -2109,7 +2109,7 @@ void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, = uint32_t aofs, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_subs64, .opt_opc =3D vecop_list_sub, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -2221,7 +2221,7 @@ void tcg_gen_gvec_sub_var(unsigned vece, TCGv_ptr dba= se, uint32_t dofs, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_sub64, .opt_opc =3D vecop_list_sub, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -2260,7 +2260,7 @@ void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, u= int32_t aofs, .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_mul64, .opt_opc =3D vecop_list_mul, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -2289,7 +2289,7 @@ void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, = uint32_t aofs, .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_muls64, .opt_opc =3D vecop_list_mul, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -2618,7 +2618,7 @@ void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, u= int32_t aofs, .fniv =3D tcg_gen_neg_vec, .fno =3D gen_helper_gvec_neg64, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -2682,7 +2682,7 @@ void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, u= int32_t aofs, .fniv =3D tcg_gen_abs_vec, .fno =3D gen_helper_gvec_abs64, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -2697,7 +2697,7 @@ void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, u= int32_t aofs, .fni8 =3D tcg_gen_and_i64, .fniv =3D tcg_gen_and_vec, .fno =3D gen_helper_gvec_and, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (aofs =3D=3D bofs) { @@ -2714,7 +2714,7 @@ void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, ui= nt32_t aofs, .fni8 =3D tcg_gen_or_i64, .fniv =3D tcg_gen_or_vec, .fno =3D gen_helper_gvec_or, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (aofs =3D=3D bofs) { @@ -2731,7 +2731,7 @@ void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, u= int32_t aofs, .fni8 =3D tcg_gen_xor_i64, .fniv =3D tcg_gen_xor_vec, .fno =3D gen_helper_gvec_xor, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (aofs =3D=3D bofs) { @@ -2748,7 +2748,7 @@ void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, = uint32_t aofs, .fni8 =3D tcg_gen_andc_i64, .fniv =3D tcg_gen_andc_vec, .fno =3D gen_helper_gvec_andc, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (aofs =3D=3D bofs) { @@ -2765,7 +2765,7 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, u= int32_t aofs, .fni8 =3D tcg_gen_orc_i64, .fniv =3D tcg_gen_orc_vec, .fno =3D gen_helper_gvec_orc, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (aofs =3D=3D bofs) { @@ -2782,7 +2782,7 @@ void tcg_gen_gvec_nand(unsigned vece, uint32_t dofs, = uint32_t aofs, .fni8 =3D tcg_gen_nand_i64, .fniv =3D tcg_gen_nand_vec, .fno =3D gen_helper_gvec_nand, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (aofs =3D=3D bofs) { @@ -2799,7 +2799,7 @@ void tcg_gen_gvec_nor(unsigned vece, uint32_t dofs, u= int32_t aofs, .fni8 =3D tcg_gen_nor_i64, .fniv =3D tcg_gen_nor_vec, .fno =3D gen_helper_gvec_nor, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (aofs =3D=3D bofs) { @@ -2816,7 +2816,7 @@ void tcg_gen_gvec_eqv(unsigned vece, uint32_t dofs, u= int32_t aofs, .fni8 =3D tcg_gen_eqv_i64, .fniv =3D tcg_gen_eqv_vec, .fno =3D gen_helper_gvec_eqv, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (aofs =3D=3D bofs) { @@ -2830,7 +2830,7 @@ static const GVecGen2s gop_ands =3D { .fni8 =3D tcg_gen_and_i64, .fniv =3D tcg_gen_and_vec, .fno =3D gen_helper_gvec_ands, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }; =20 @@ -2857,7 +2857,7 @@ void tcg_gen_gvec_andcs(unsigned vece, uint32_t dofs,= uint32_t aofs, .fni8 =3D tcg_gen_andc_i64, .fniv =3D tcg_gen_andc_vec, .fno =3D gen_helper_gvec_andcs, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }; =20 @@ -2871,7 +2871,7 @@ static const GVecGen2s gop_xors =3D { .fni8 =3D tcg_gen_xor_i64, .fniv =3D tcg_gen_xor_vec, .fno =3D gen_helper_gvec_xors, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }; =20 @@ -2895,7 +2895,7 @@ static const GVecGen2s gop_ors =3D { .fni8 =3D tcg_gen_or_i64, .fniv =3D tcg_gen_or_vec, .fno =3D gen_helper_gvec_ors, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }; =20 @@ -2967,7 +2967,7 @@ void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, = uint32_t aofs, .fniv =3D tcg_gen_shli_vec, .fno =3D gen_helper_gvec_shl64i, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -3032,7 +3032,7 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, = uint32_t aofs, .fniv =3D tcg_gen_shri_vec, .fno =3D gen_helper_gvec_shr64i, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -3125,7 +3125,7 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, = uint32_t aofs, .fniv =3D tcg_gen_sari_vec, .fno =3D gen_helper_gvec_sar64i, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -3184,7 +3184,7 @@ void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs,= uint32_t aofs, .fniv =3D tcg_gen_rotli_vec, .fno =3D gen_helper_gvec_rotl64i, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -3513,7 +3513,7 @@ void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, = uint32_t aofs, .fniv =3D tcg_gen_shlv_mod_vec, .fno =3D gen_helper_gvec_shl64v, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -3576,7 +3576,7 @@ void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, = uint32_t aofs, .fniv =3D tcg_gen_shrv_mod_vec, .fno =3D gen_helper_gvec_shr64v, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -3639,7 +3639,7 @@ void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, = uint32_t aofs, .fniv =3D tcg_gen_sarv_mod_vec, .fno =3D gen_helper_gvec_sar64v, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -3702,7 +3702,7 @@ void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs,= uint32_t aofs, .fniv =3D tcg_gen_rotlv_mod_vec, .fno =3D gen_helper_gvec_rotl64v, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -3761,7 +3761,7 @@ void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs,= uint32_t aofs, .fniv =3D tcg_gen_rotrv_mod_vec, .fno =3D gen_helper_gvec_rotr64v, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index bc3a07f972..41bf047b8d 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -3006,7 +3006,7 @@ static void gen_PMOVMSKB(DisasContext *s, X86DecodedI= nsn *decode) .fniv =3D gen_pmovmskb_vec, .opt_opc =3D vecop_list, .vece =3D MO_64, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64 + .prefer_i64 =3D true }; MemOp ot =3D decode->op[2].ot; int vec_len =3D vector_len(s, decode); diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 2a487179f6..caefd38216 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1489,7 +1489,7 @@ static void tcg_gen_gvec_rsubs(unsigned vece, uint32_= t dofs, uint32_t aofs, .fniv =3D gen_rsub_vec, .fno =3D gen_helper_vec_rsubs64, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Thomas Huth Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 1 - tcg/optimize.c | 99 ---------------------------------------- tcg/tcg-op.c | 32 ++----------- tcg/tcg.c | 34 -------------- docs/devel/tcg-ops.rst | 7 +-- tcg/tci/tcg-target.c.inc | 17 ------- 6 files changed, 4 insertions(+), 186 deletions(-) diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index e988edd93a..55283af326 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -103,7 +103,6 @@ DEF(subb1o, 1, 2, 0, TCG_OPF_INT | TCG_OPF_CARRY_OUT) DEF(subbi, 1, 2, 0, TCG_OPF_INT | TCG_OPF_CARRY_IN) DEF(subbio, 1, 2, 0, TCG_OPF_INT | TCG_OPF_CARRY_IN | TCG_OPF_CARRY_OUT) =20 -DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH) DEF(setcond2_i32, 1, 4, 1, 0) =20 /* size changing ops */ diff --git a/tcg/optimize.c b/tcg/optimize.c index 5ae26e4a10..a544c055b8 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1597,102 +1597,6 @@ static bool fold_brcond(OptContext *ctx, TCGOp *op) return true; } =20 -static bool fold_brcond2(OptContext *ctx, TCGOp *op) -{ - TCGCond cond; - TCGArg label; - int i, inv =3D 0; - - i =3D do_constant_folding_cond2(ctx, op, &op->args[0]); - cond =3D op->args[4]; - label =3D op->args[5]; - if (i >=3D 0) { - goto do_brcond_const; - } - - switch (cond) { - case TCG_COND_LT: - case TCG_COND_GE: - /* - * Simplify LT/GE comparisons vs zero to a single compare - * vs the high word of the input. - */ - if (arg_is_const_val(op->args[2], 0) && - arg_is_const_val(op->args[3], 0)) { - goto do_brcond_high; - } - break; - - case TCG_COND_NE: - inv =3D 1; - QEMU_FALLTHROUGH; - case TCG_COND_EQ: - /* - * Simplify EQ/NE comparisons where one of the pairs - * can be simplified. - */ - i =3D do_constant_folding_cond(TCG_TYPE_I32, op->args[0], - op->args[2], cond); - switch (i ^ inv) { - case 0: - goto do_brcond_const; - case 1: - goto do_brcond_high; - } - - i =3D do_constant_folding_cond(TCG_TYPE_I32, op->args[1], - op->args[3], cond); - switch (i ^ inv) { - case 0: - goto do_brcond_const; - case 1: - goto do_brcond_low; - } - break; - - case TCG_COND_TSTEQ: - case TCG_COND_TSTNE: - if (arg_is_const_val(op->args[2], 0)) { - goto do_brcond_high; - } - if (arg_is_const_val(op->args[3], 0)) { - goto do_brcond_low; - } - break; - - default: - break; - - do_brcond_low: - op->opc =3D INDEX_op_brcond; - op->args[1] =3D op->args[2]; - op->args[2] =3D cond; - op->args[3] =3D label; - return fold_brcond(ctx, op); - - do_brcond_high: - op->opc =3D INDEX_op_brcond; - op->args[0] =3D op->args[1]; - op->args[1] =3D op->args[3]; - op->args[2] =3D cond; - op->args[3] =3D label; - return fold_brcond(ctx, op); - - do_brcond_const: - if (i =3D=3D 0) { - tcg_op_remove(ctx->tcg, op); - return true; - } - op->opc =3D INDEX_op_br; - op->args[0] =3D label; - finish_ebb(ctx); - return true; - } - - finish_bb(ctx); - return true; -} - static bool fold_bswap(OptContext *ctx, TCGOp *op) { uint64_t z_mask, o_mask, s_mask; @@ -3163,9 +3067,6 @@ void tcg_optimize(TCGContext *s) case INDEX_op_brcond: done =3D fold_brcond(&ctx, op); break; - case INDEX_op_brcond2_i32: - done =3D fold_brcond2(&ctx, op); - break; case INDEX_op_bswap16: case INDEX_op_bswap32: case INDEX_op_bswap64: diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index ab7b409be6..61f6fd9095 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -265,14 +265,6 @@ static void DNI tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i= 64 a1, TCGv_i64 a2, tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6); } =20 -static TCGOp * DNI tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 = a2, - TCGv_i32 a3, TCGv_i32 a4, - TCGArg a5, TCGArg a6) -{ - return tcg_gen_op6(opc, TCG_TYPE_I32, tcgv_i32_arg(a1), tcgv_i32_arg(a= 2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6); -} - /* Generic ops. */ =20 void gen_set_label(TCGLabel *l) @@ -1873,33 +1865,15 @@ void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1= , TCGv_i64 arg2, TCGLabel *l) if (cond =3D=3D TCG_COND_ALWAYS) { tcg_gen_br(l); } else if (cond !=3D TCG_COND_NEVER) { - TCGOp *op; - if (TCG_TARGET_REG_BITS =3D=3D 32) { - op =3D tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, TCGV_LOW(arg1), - TCGV_HIGH(arg1), TCGV_LOW(arg2), - TCGV_HIGH(arg2), cond, label_arg(l)); - } else { - op =3D tcg_gen_op4ii_i64(INDEX_op_brcond, arg1, arg2, cond, - label_arg(l)); - } + TCGOp *op =3D tcg_gen_op4ii_i64(INDEX_op_brcond, arg1, arg2, cond, + label_arg(l)); add_as_label_use(l, op); } } =20 void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLab= el *l) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_brcond_i64(cond, arg1, tcg_constant_i64(arg2), l); - } else if (cond =3D=3D TCG_COND_ALWAYS) { - tcg_gen_br(l); - } else if (cond !=3D TCG_COND_NEVER) { - TCGOp *op =3D tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, - TCGV_LOW(arg1), TCGV_HIGH(arg1), - tcg_constant_i32(arg2), - tcg_constant_i32(arg2 >> 32), - cond, label_arg(l)); - add_as_label_use(l, op); - } + tcg_gen_brcond_i64(cond, arg1, tcg_constant_i64(arg2), l); } =20 void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, diff --git a/tcg/tcg.c b/tcg/tcg.c index fbf09f5c82..0521767c46 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1010,13 +1010,6 @@ typedef struct TCGOutOpBrcond { TCGReg a1, tcg_target_long a2, TCGLabel *label); } TCGOutOpBrcond; =20 -typedef struct TCGOutOpBrcond2 { - TCGOutOp base; - void (*out)(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, - TCGArg bl, bool const_bl, - TCGArg bh, bool const_bh, TCGLabel *l); -} TCGOutOpBrcond2; - typedef struct TCGOutOpBswap { TCGOutOp base; void (*out_rr)(TCGContext *s, TCGType type, @@ -1248,7 +1241,6 @@ static const TCGOutOp * const all_outop[NB_OPS] =3D { [INDEX_op_goto_ptr] =3D &outop_goto_ptr, =20 #if TCG_TARGET_REG_BITS =3D=3D 32 - OUTOP(INDEX_op_brcond2_i32, TCGOutOpBrcond2, outop_brcond2), OUTOP(INDEX_op_setcond2_i32, TCGOutOpSetcond2, outop_setcond2), #else OUTOP(INDEX_op_bswap64, TCGOutOpUnary, outop_bswap64), @@ -2490,7 +2482,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, uns= igned flags) case INDEX_op_xor: return has_type; =20 - case INDEX_op_brcond2_i32: case INDEX_op_setcond2_i32: return TCG_TARGET_REG_BITS =3D=3D 32; =20 @@ -3022,7 +3013,6 @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_p= refs) case INDEX_op_setcond: case INDEX_op_negsetcond: case INDEX_op_movcond: - case INDEX_op_brcond2_i32: case INDEX_op_setcond2_i32: case INDEX_op_cmp_vec: case INDEX_op_cmpsel_vec: @@ -3106,7 +3096,6 @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_p= refs) case INDEX_op_set_label: case INDEX_op_br: case INDEX_op_brcond: - case INDEX_op_brcond2_i32: col +=3D ne_fprintf(f, "%s$L%d", k ? "," : "", arg_label(op->args[k])->id); i++, k++; @@ -3563,9 +3552,6 @@ void tcg_op_remove(TCGContext *s, TCGOp *op) case INDEX_op_brcond: remove_label_use(op, 3); break; - case INDEX_op_brcond2_i32: - remove_label_use(op, 5); - break; default: break; } @@ -3664,9 +3650,6 @@ static void move_label_uses(TCGLabel *to, TCGLabel *f= rom) case INDEX_op_brcond: op->args[3] =3D label_arg(to); break; - case INDEX_op_brcond2_i32: - op->args[5] =3D label_arg(to); - break; default: g_assert_not_reached(); } @@ -5285,9 +5268,6 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) case INDEX_op_cmp_vec: op_cond =3D op->args[3]; break; - case INDEX_op_brcond2_i32: - op_cond =3D op->args[4]; - break; case INDEX_op_movcond: case INDEX_op_setcond2_i32: case INDEX_op_cmpsel_vec: @@ -5890,19 +5870,6 @@ static void tcg_reg_alloc_op(TCGContext *s, const TC= GOp *op) break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 - case INDEX_op_brcond2_i32: - { - const TCGOutOpBrcond2 *out =3D &outop_brcond2; - TCGCond cond =3D new_args[4]; - TCGLabel *label =3D arg_label(new_args[5]); - - tcg_debug_assert(!const_args[0]); - tcg_debug_assert(!const_args[1]); - out->out(s, cond, new_args[0], new_args[1], - new_args[2], const_args[2], - new_args[3], const_args[3], label); - } - break; case INDEX_op_setcond2_i32: { const TCGOutOpSetcond2 *out =3D &outop_setcond2; @@ -5915,7 +5882,6 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) } break; #else - case INDEX_op_brcond2_i32: case INDEX_op_setcond2_i32: g_assert_not_reached(); #endif diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst index f26b837a30..10d5edb4ca 100644 --- a/docs/devel/tcg-ops.rst +++ b/docs/devel/tcg-ops.rst @@ -705,11 +705,6 @@ They are emitted as needed by inline functions within = ``tcg-op.h``. =20 .. list-table:: =20 - * - brcond2_i32 *t0_low*, *t0_high*, *t1_low*, *t1_high*, *cond*, *labe= l* - - - | Similar to brcond, except that the 64-bit values *t0* and *t1* - are formed from two 32-bit arguments. - * - setcond2_i32 *dest*, *t1_low*, *t1_high*, *t2_low*, *t2_high*, *con= d* =20 - | Similar to setcond, except that the 64-bit values *t1* and *t2* a= re @@ -940,7 +935,7 @@ The target word size (``TCG_TARGET_REG_BITS``) is expec= ted to be 32 bit or =20 On a 32 bit target, all 64 bit operations are converted to 32 bits. A few specific operations must be implemented to allow it -(see brcond2_i32, setcond2_i32). +(see setcond2_i32). =20 On a 64 bit target, the values are transferred between 32 and 64-bit registers using the following ops: diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 532f87262c..1756ffc59c 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -1047,23 +1047,6 @@ static const TCGOutOpMovcond outop_movcond =3D { .out =3D tgen_movcond, }; =20 -static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, - TCGArg bl, bool const_bl, - TCGArg bh, bool const_bh, TCGLabel *l) -{ - tcg_out_op_rrrrrc(s, INDEX_op_setcond2_i32, TCG_REG_TMP, - al, ah, bl, bh, cond); - tcg_out_op_rl(s, INDEX_op_brcond, TCG_REG_TMP, l); -} - -#if TCG_TARGET_REG_BITS !=3D 32 -__attribute__((unused)) -#endif -static const TCGOutOpBrcond2 outop_brcond2 =3D { - .base.static_constraint =3D C_O0_I4(r, r, r, r), - .out =3D tgen_brcond2, -}; - static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg al, TCGReg ah, TCGArg bl, bool const_bl, --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774082; cv=none; d=zohomail.com; s=zohoarc; b=GOQ1yOptMIrQfmClre7cV0ggNz59C/uTvR/FqWVs41jj0KJF9k5Lofa7YPtbNsrJt5l1SnVMg9xvEA6oRtChAnhtWPfbEEUg6JxgnNEC4Qozw3Vc0dFAAWa+IPp5D1ZXtVxSrBdko3y1z2F+xdgf2MYcRf3p25mmk1c8Bl0ll+U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768774082; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xxGjmvi5stD/pKxpCi2bexDDgM4UjuXeBBR0I0HBVUM=; b=R5ABCwTrSAKhnkATzveAzAAdwmiwFvh7IzQ8OtdkeZfwCgYm0zikZvnjIfYMOTWVoPQ3ij0+g0a3y3xV6UfAkaypqJfRjUoOUulftSCUEJVbqi2M2wowenZeb25Ss140Y0/Amv9UCOjsTUGiUdvJBo3Eqw0JO0D4yxP+qb2IFd4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768774082016184.9247320116839; Sun, 18 Jan 2026 14:08:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhatt-0003BG-E2; Sun, 18 Jan 2026 17:05:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhate-0002Lf-HN for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:24 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhatb-0000rH-2s for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:21 -0500 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-2a07fac8aa1so25765605ad.1 for ; Sun, 18 Jan 2026 14:05:18 -0800 (PST) Received: from stoup.. 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Reviewed-by: Thomas Huth Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 2 - tcg/optimize.c | 205 --------------------------------------- tcg/tcg-op.c | 47 +-------- tcg/tcg.c | 32 ------ tcg/tci.c | 10 -- docs/devel/tcg-ops.rst | 27 +----- tcg/tci/tcg-target.c.inc | 16 --- 7 files changed, 8 insertions(+), 331 deletions(-) diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 55283af326..fc1270f01e 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -103,8 +103,6 @@ DEF(subb1o, 1, 2, 0, TCG_OPF_INT | TCG_OPF_CARRY_OUT) DEF(subbi, 1, 2, 0, TCG_OPF_INT | TCG_OPF_CARRY_IN) DEF(subbio, 1, 2, 0, TCG_OPF_INT | TCG_OPF_CARRY_IN | TCG_OPF_CARRY_OUT) =20 -DEF(setcond2_i32, 1, 4, 1, 0) - /* size changing ops */ DEF(ext_i32_i64, 1, 1, 0, 0) DEF(extu_i32_i64, 1, 1, 0, 0) diff --git a/tcg/optimize.c b/tcg/optimize.c index a544c055b8..d845c7eef2 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -764,22 +764,6 @@ static bool swap_commutative(TCGArg dest, TCGArg *p1, = TCGArg *p2) return false; } =20 -static bool swap_commutative2(TCGArg *p1, TCGArg *p2) -{ - int sum =3D 0; - sum +=3D pref_commutative(arg_info(p1[0])); - sum +=3D pref_commutative(arg_info(p1[1])); - sum -=3D pref_commutative(arg_info(p2[0])); - sum -=3D pref_commutative(arg_info(p2[1])); - if (sum > 0) { - TCGArg t; - t =3D p1[0], p1[0] =3D p2[0], p2[0] =3D t; - t =3D p1[1], p1[1] =3D p2[1], p2[1] =3D t; - return true; - } - return false; -} - /* * Return -1 if the condition can't be simplified, * and the result of the condition (0 or 1) if it can. @@ -844,108 +828,6 @@ static int do_constant_folding_cond1(OptContext *ctx,= TCGOp *op, TCGArg dest, return -1; } =20 -static int do_constant_folding_cond2(OptContext *ctx, TCGOp *op, TCGArg *a= rgs) -{ - TCGArg al, ah, bl, bh; - TCGCond c; - bool swap; - int r; - - swap =3D swap_commutative2(args, args + 2); - c =3D args[4]; - if (swap) { - args[4] =3D c =3D tcg_swap_cond(c); - } - - al =3D args[0]; - ah =3D args[1]; - bl =3D args[2]; - bh =3D args[3]; - - if (arg_is_const(bl) && arg_is_const(bh)) { - tcg_target_ulong blv =3D arg_const_val(bl); - tcg_target_ulong bhv =3D arg_const_val(bh); - uint64_t b =3D deposit64(blv, 32, 32, bhv); - - if (arg_is_const(al) && arg_is_const(ah)) { - tcg_target_ulong alv =3D arg_const_val(al); - tcg_target_ulong ahv =3D arg_const_val(ah); - uint64_t a =3D deposit64(alv, 32, 32, ahv); - - r =3D do_constant_folding_cond_64(a, b, c); - if (r >=3D 0) { - return r; - } - } - - if (b =3D=3D 0) { - switch (c) { - case TCG_COND_LTU: - case TCG_COND_TSTNE: - return 0; - case TCG_COND_GEU: - case TCG_COND_TSTEQ: - return 1; - default: - break; - } - } - - /* TSTNE x,-1 -> NE x,0 */ - if (b =3D=3D -1 && is_tst_cond(c)) { - args[3] =3D args[2] =3D arg_new_constant(ctx, 0); - args[4] =3D tcg_tst_eqne_cond(c); - return -1; - } - - /* TSTNE x,sign -> LT x,0 */ - if (b =3D=3D INT64_MIN && is_tst_cond(c)) { - /* bl must be 0, so copy that to bh */ - args[3] =3D bl; - args[4] =3D tcg_tst_ltge_cond(c); - return -1; - } - } - - if (args_are_copies(al, bl) && args_are_copies(ah, bh)) { - r =3D do_constant_folding_cond_eq(c); - if (r >=3D 0) { - return r; - } - - /* TSTNE x,x -> NE x,0 */ - if (is_tst_cond(c)) { - args[3] =3D args[2] =3D arg_new_constant(ctx, 0); - args[4] =3D tcg_tst_eqne_cond(c); - return -1; - } - } - - /* Expand to AND with a temporary if no backend support. */ - if (!TCG_TARGET_HAS_tst && is_tst_cond(c)) { - TCGOp *op1 =3D opt_insert_before(ctx, op, INDEX_op_and, 3); - TCGOp *op2 =3D opt_insert_before(ctx, op, INDEX_op_and, 3); - TCGArg t1 =3D arg_new_temp(ctx); - TCGArg t2 =3D arg_new_temp(ctx); - - op1->args[0] =3D t1; - op1->args[1] =3D al; - op1->args[2] =3D bl; - fold_and(ctx, op1); - - op2->args[0] =3D t2; - op2->args[1] =3D ah; - op2->args[2] =3D bh; - fold_and(ctx, op1); - - args[0] =3D t1; - args[1] =3D t2; - args[3] =3D args[2] =3D arg_new_constant(ctx, 0); - args[4] =3D tcg_tst_eqne_cond(c); - } - return -1; -} - static void init_arguments(OptContext *ctx, TCGOp *op, int nb_args) { for (int i =3D 0; i < nb_args; i++) { @@ -2503,90 +2385,6 @@ static bool fold_negsetcond(OptContext *ctx, TCGOp *= op) return fold_masks_s(ctx, op, -1); } =20 -static bool fold_setcond2(OptContext *ctx, TCGOp *op) -{ - TCGCond cond; - int i, inv =3D 0; - - i =3D do_constant_folding_cond2(ctx, op, &op->args[1]); - cond =3D op->args[5]; - if (i >=3D 0) { - goto do_setcond_const; - } - - switch (cond) { - case TCG_COND_LT: - case TCG_COND_GE: - /* - * Simplify LT/GE comparisons vs zero to a single compare - * vs the high word of the input. - */ - if (arg_is_const_val(op->args[3], 0) && - arg_is_const_val(op->args[4], 0)) { - goto do_setcond_high; - } - break; - - case TCG_COND_NE: - inv =3D 1; - QEMU_FALLTHROUGH; - case TCG_COND_EQ: - /* - * Simplify EQ/NE comparisons where one of the pairs - * can be simplified. - */ - i =3D do_constant_folding_cond(TCG_TYPE_I32, op->args[1], - op->args[3], cond); - switch (i ^ inv) { - case 0: - goto do_setcond_const; - case 1: - goto do_setcond_high; - } - - i =3D do_constant_folding_cond(TCG_TYPE_I32, op->args[2], - op->args[4], cond); - switch (i ^ inv) { - case 0: - goto do_setcond_const; - case 1: - goto do_setcond_low; - } - break; - - case TCG_COND_TSTEQ: - case TCG_COND_TSTNE: - if (arg_is_const_val(op->args[3], 0)) { - goto do_setcond_high; - } - if (arg_is_const_val(op->args[4], 0)) { - goto do_setcond_low; - } - break; - - default: - break; - - do_setcond_low: - op->args[2] =3D op->args[3]; - op->args[3] =3D cond; - op->opc =3D INDEX_op_setcond; - return fold_setcond(ctx, op); - - do_setcond_high: - op->args[1] =3D op->args[2]; - op->args[2] =3D op->args[4]; - op->args[3] =3D cond; - op->opc =3D INDEX_op_setcond; - return fold_setcond(ctx, op); - } - - return fold_masks_z(ctx, op, 1); - - do_setcond_const: - return tcg_opt_gen_movi(ctx, op, op->args[0], i); -} - static bool fold_sextract(OptContext *ctx, TCGOp *op) { uint64_t z_mask, o_mask, s_mask, a_mask; @@ -3202,9 +3000,6 @@ void tcg_optimize(TCGContext *s) case INDEX_op_negsetcond: done =3D fold_negsetcond(&ctx, op); break; - case INDEX_op_setcond2_i32: - done =3D fold_setcond2(&ctx, op); - break; case INDEX_op_cmp_vec: done =3D fold_cmp_vec(&ctx, op); break; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 61f6fd9095..d20888dd8f 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1884,33 +1884,14 @@ void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, } else if (cond =3D=3D TCG_COND_NEVER) { tcg_gen_movi_i64(ret, 0); } else { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), - TCGV_LOW(arg1), TCGV_HIGH(arg1), - TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - } else { - tcg_gen_op4i_i64(INDEX_op_setcond, ret, arg1, arg2, cond); - } + tcg_gen_op4i_i64(INDEX_op_setcond, ret, arg1, arg2, cond); } } =20 void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_setcond_i64(cond, ret, arg1, tcg_constant_i64(arg2)); - } else if (cond =3D=3D TCG_COND_ALWAYS) { - tcg_gen_movi_i64(ret, 1); - } else if (cond =3D=3D TCG_COND_NEVER) { - tcg_gen_movi_i64(ret, 0); - } else { - tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), - TCGV_LOW(arg1), TCGV_HIGH(arg1), - tcg_constant_i32(arg2), - tcg_constant_i32(arg2 >> 32), cond); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - } + tcg_gen_setcond_i64(cond, ret, arg1, tcg_constant_i64(arg2)); } =20 void tcg_gen_negsetcondi_i64(TCGCond cond, TCGv_i64 ret, @@ -1926,14 +1907,8 @@ void tcg_gen_negsetcond_i64(TCGCond cond, TCGv_i64 r= et, tcg_gen_movi_i64(ret, -1); } else if (cond =3D=3D TCG_COND_NEVER) { tcg_gen_movi_i64(ret, 0); - } else if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_op4i_i64(INDEX_op_negsetcond, ret, arg1, arg2, cond); } else { - tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), - TCGV_LOW(arg1), TCGV_HIGH(arg1), - TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); - tcg_gen_neg_i32(TCGV_LOW(ret), TCGV_LOW(ret)); - tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_LOW(ret)); + tcg_gen_op4i_i64(INDEX_op_negsetcond, ret, arg1, arg2, cond); } } =20 @@ -2777,22 +2752,8 @@ void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret,= TCGv_i64 c1, tcg_gen_mov_i64(ret, v1); } else if (cond =3D=3D TCG_COND_NEVER) { tcg_gen_mov_i64(ret, v2); - } else if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_op6i_i64(INDEX_op_movcond, ret, c1, c2, v1, v2, cond); } else { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 zero =3D tcg_constant_i32(0); - - tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0, - TCGV_LOW(c1), TCGV_HIGH(c1), - TCGV_LOW(c2), TCGV_HIGH(c2), cond); - - tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, zero, - TCGV_LOW(v1), TCGV_LOW(v2)); - tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, zero, - TCGV_HIGH(v1), TCGV_HIGH(v2)); - - tcg_temp_free_i32(t0); + tcg_gen_op6i_i64(INDEX_op_movcond, ret, c1, c2, v1, v2, cond); } } =20 diff --git a/tcg/tcg.c b/tcg/tcg.c index 0521767c46..b6a65fe224 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1088,12 +1088,6 @@ typedef struct TCGOutOpSetcond { TCGReg ret, TCGReg a1, tcg_target_long a2); } TCGOutOpSetcond; =20 -typedef struct TCGOutOpSetcond2 { - TCGOutOp base; - void (*out)(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg al, TCGReg= ah, - TCGArg bl, bool const_bl, TCGArg bh, bool const_bh); -} TCGOutOpSetcond2; - typedef struct TCGOutOpStore { TCGOutOp base; void (*out_r)(TCGContext *s, TCGType type, TCGReg data, @@ -1240,9 +1234,6 @@ static const TCGOutOp * const all_outop[NB_OPS] =3D { =20 [INDEX_op_goto_ptr] =3D &outop_goto_ptr, =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 - OUTOP(INDEX_op_setcond2_i32, TCGOutOpSetcond2, outop_setcond2), -#else OUTOP(INDEX_op_bswap64, TCGOutOpUnary, outop_bswap64), OUTOP(INDEX_op_ext_i32_i64, TCGOutOpUnary, outop_exts_i32_i64), OUTOP(INDEX_op_extu_i32_i64, TCGOutOpUnary, outop_extu_i32_i64), @@ -1251,7 +1242,6 @@ static const TCGOutOp * const all_outop[NB_OPS] =3D { OUTOP(INDEX_op_ld32u, TCGOutOpLoad, outop_ld32u), OUTOP(INDEX_op_ld32s, TCGOutOpLoad, outop_ld32s), OUTOP(INDEX_op_st32, TCGOutOpStore, outop_st), -#endif }; =20 #undef OUTOP @@ -2482,9 +2472,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, uns= igned flags) case INDEX_op_xor: return has_type; =20 - case INDEX_op_setcond2_i32: - return TCG_TARGET_REG_BITS =3D=3D 32; - case INDEX_op_ld32u: case INDEX_op_ld32s: case INDEX_op_st32: @@ -3013,7 +3000,6 @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_p= refs) case INDEX_op_setcond: case INDEX_op_negsetcond: case INDEX_op_movcond: - case INDEX_op_setcond2_i32: case INDEX_op_cmp_vec: case INDEX_op_cmpsel_vec: if (op->args[k] < ARRAY_SIZE(cond_name) @@ -5269,7 +5255,6 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) op_cond =3D op->args[3]; break; case INDEX_op_movcond: - case INDEX_op_setcond2_i32: case INDEX_op_cmpsel_vec: op_cond =3D op->args[5]; break; @@ -5869,23 +5854,6 @@ static void tcg_reg_alloc_op(TCGContext *s, const TC= GOp *op) } break; =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 - case INDEX_op_setcond2_i32: - { - const TCGOutOpSetcond2 *out =3D &outop_setcond2; - TCGCond cond =3D new_args[5]; - - tcg_debug_assert(!const_args[1]); - tcg_debug_assert(!const_args[2]); - out->out(s, cond, new_args[0], new_args[1], new_args[2], - new_args[3], const_args[3], new_args[4], const_args[4= ]); - } - break; -#else - case INDEX_op_setcond2_i32: - g_assert_not_reached(); -#endif - case INDEX_op_goto_ptr: tcg_debug_assert(!const_args[0]); tcg_out_goto_ptr(s, new_args[0]); diff --git a/tcg/tci.c b/tcg/tci.c index e15d4e8e08..7f3ba9b5da 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -418,14 +418,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_args_l(insn, tb_ptr, &ptr); tb_ptr =3D ptr; continue; -#if TCG_TARGET_REG_BITS =3D=3D 32 - case INDEX_op_setcond2_i32: - tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); - regs[r0] =3D tci_compare64(tci_uint64(regs[r2], regs[r1]), - tci_uint64(regs[r4], regs[r3]), - condition); - break; -#elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond: tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] =3D tci_compare64(regs[r1], regs[r2], condition); @@ -435,7 +427,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tmp32 =3D tci_compare64(regs[r1], regs[r2], condition); regs[r0] =3D regs[tmp32 ? r3 : r4]; break; -#endif case INDEX_op_mov: tci_args_rr(insn, &r0, &r1); regs[r0] =3D regs[r1]; @@ -1040,7 +1031,6 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) =20 case INDEX_op_tci_movcond32: case INDEX_op_movcond: - case INDEX_op_setcond2_i32: tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c); info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s", op_name, str_r(r0), str_r(r1), str_r(r2), diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst index 10d5edb4ca..fd3a50bf4c 100644 --- a/docs/devel/tcg-ops.rst +++ b/docs/devel/tcg-ops.rst @@ -696,21 +696,6 @@ Memory Barrier support | Please see :ref:`atomics-ref` for more information on memory barr= iers. =20 =20 -64-bit guest on 32-bit host support ------------------------------------ - -The following opcodes are internal to TCG. Thus they are to be implemente= d by -32-bit host code generators, but are not to be emitted by guest translator= s. -They are emitted as needed by inline functions within ``tcg-op.h``. - -.. list-table:: - - * - setcond2_i32 *dest*, *t1_low*, *t1_high*, *t2_low*, *t2_high*, *con= d* - - - | Similar to setcond, except that the 64-bit values *t1* and *t2* a= re - formed from two 32-bit arguments. The result is a 32-bit value. - - QEMU specific operations ------------------------ =20 @@ -930,15 +915,11 @@ than being a standalone C file. Assumptions ----------- =20 -The target word size (``TCG_TARGET_REG_BITS``) is expected to be 32 bit or -64 bit. It is expected that the pointer has the same size as the word. +The target word size (``TCG_TARGET_REG_BITS``) is expected to be 64 bit. +It is expected that the pointer has the same size as the word. =20 -On a 32 bit target, all 64 bit operations are converted to 32 bits. -A few specific operations must be implemented to allow it -(see setcond2_i32). - -On a 64 bit target, the values are transferred between 32 and 64-bit -registers using the following ops: +Values are transferred between 32 and 64-bit registers using the +following ops: =20 - extrl_i64_i32 - extrh_i64_i32 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 1756ffc59c..8bd8db4401 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -1047,22 +1047,6 @@ static const TCGOutOpMovcond outop_movcond =3D { .out =3D tgen_movcond, }; =20 -static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg al, TCGReg ah, - TCGArg bl, bool const_bl, - TCGArg bh, bool const_bh) -{ - tcg_out_op_rrrrrc(s, INDEX_op_setcond2_i32, ret, al, ah, bl, bh, cond); -} - -#if TCG_TARGET_REG_BITS !=3D 32 -__attribute__((unused)) -#endif -static const TCGOutOpSetcond2 outop_setcond2 =3D { - .base.static_constraint =3D C_O1_I4(r, r, r, r, r), - .out =3D tgen_setcond2, -}; - static void tcg_out_mb(TCGContext *s, unsigned a0) { tcg_out_op_v(s, INDEX_op_mb); --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774088; cv=none; d=zohomail.com; s=zohoarc; b=ZmuGGdQKczDANg2qCbWnvWAHp2fFLdU7oSZj++9zj8QN413XcMdkqvkFONIHTfkIHhw+xQpjRcf+2x9uCjJtuZiC+2LpDHx4osHumnyel3deu0WIHTdrVXESwM0nQp0lblVbz0g3vSTpW8LX4hNvtB/ApQ4JyRpTizoxqQBD79Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768774088; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=lyHPNybRY+NoN8XylpS1cgArMSCY+8ib77S0l59/9JY=; b=B27T2V3kfimkwsSy29WWg3CYQNfe42+k6xkrBETzzJBFJ16DMiv0ofSeI4PLmkti9YRk6LLgycjOvPB/dUM5Tm1Z/h9laSNv9Vx/SAFpHClzO9cm35iKa4vihJ/mTdIhL2C6GLBw3JVhNnodQOQjkSQxHR5pGcB3oKsXehYu8Lc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768774088871833.6075636714422; Sun, 18 Jan 2026 14:08:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhatt-0003B2-BO; Sun, 18 Jan 2026 17:05:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhatf-0002Mb-AE for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:26 -0500 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhatd-0000rW-3b for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:23 -0500 Received: by mail-pg1-x52b.google.com with SMTP id 41be03b00d2f7-bc0d7255434so1445343a12.0 for ; Sun, 18 Jan 2026 14:05:20 -0800 (PST) Received: from stoup.. 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 1 - tcg/optimize.c | 18 --------- tcg/tcg-op-vec.c | 14 +------ tcg/tcg.c | 94 ------------------------------------------- 4 files changed, 2 insertions(+), 125 deletions(-) diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index fc1270f01e..28806057c5 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -130,7 +130,6 @@ DEF(qemu_st2, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_S= IDE_EFFECTS | TCG_OPF_INT DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) =20 DEF(dup_vec, 1, 1, 0, TCG_OPF_VECTOR) -DEF(dup2_vec, 1, 2, 0, TCG_OPF_VECTOR) =20 DEF(ld_vec, 1, 1, 1, TCG_OPF_VECTOR) DEF(st_vec, 0, 2, 1, TCG_OPF_VECTOR) diff --git a/tcg/optimize.c b/tcg/optimize.c index d845c7eef2..801a0a2c68 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1716,21 +1716,6 @@ static bool fold_dup(OptContext *ctx, TCGOp *op) return finish_folding(ctx, op); } =20 -static bool fold_dup2(OptContext *ctx, TCGOp *op) -{ - if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { - uint64_t t =3D deposit64(arg_const_val(op->args[1]), 32, 32, - arg_const_val(op->args[2])); - return tcg_opt_gen_movi(ctx, op, op->args[0], t); - } - - if (args_are_copies(op->args[1], op->args[2])) { - op->opc =3D INDEX_op_dup_vec; - TCGOP_VECE(op) =3D MO_32; - } - return finish_folding(ctx, op); -} - static bool fold_eqv(OptContext *ctx, TCGOp *op) { uint64_t z_mask, o_mask, s_mask; @@ -2887,9 +2872,6 @@ void tcg_optimize(TCGContext *s) case INDEX_op_dup_vec: done =3D fold_dup(&ctx, op); break; - case INDEX_op_dup2_vec: - done =3D fold_dup2(&ctx, op); - break; case INDEX_op_eqv: case INDEX_op_eqv_vec: done =3D fold_eqv(&ctx, op); diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 893d68e7d8..67e837174b 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -75,7 +75,6 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list, case INDEX_op_xor_vec: case INDEX_op_mov_vec: case INDEX_op_dup_vec: - case INDEX_op_dup2_vec: case INDEX_op_ld_vec: case INDEX_op_st_vec: case INDEX_op_bitsel_vec: @@ -228,20 +227,11 @@ void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint= 64_t a) void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a) { TCGArg ri =3D tcgv_vec_arg(r); + TCGArg ai =3D tcgv_i64_arg(a); TCGTemp *rt =3D arg_temp(ri); TCGType type =3D rt->base_type; =20 - if (TCG_TARGET_REG_BITS =3D=3D 64) { - TCGArg ai =3D tcgv_i64_arg(a); - vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); - } else if (vece =3D=3D MO_64) { - TCGArg al =3D tcgv_i32_arg(TCGV_LOW(a)); - TCGArg ah =3D tcgv_i32_arg(TCGV_HIGH(a)); - vec_gen_3(INDEX_op_dup2_vec, type, MO_64, ri, al, ah); - } else { - TCGArg ai =3D tcgv_i32_arg(TCGV_LOW(a)); - vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); - } + vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); } =20 void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec r, TCGv_i32 a) diff --git a/tcg/tcg.c b/tcg/tcg.c index b6a65fe224..2b3bcbe750 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2493,8 +2493,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, uns= igned flags) case INDEX_op_xor_vec: case INDEX_op_cmp_vec: return has_type; - case INDEX_op_dup2_vec: - return has_type && TCG_TARGET_REG_BITS =3D=3D 32; case INDEX_op_not_vec: return has_type && TCG_TARGET_HAS_not_vec; case INDEX_op_neg_vec: @@ -5888,93 +5886,6 @@ static void tcg_reg_alloc_op(TCGContext *s, const TC= GOp *op) } } =20 -static bool tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op) -{ - const TCGLifeData arg_life =3D op->life; - TCGTemp *ots, *itsl, *itsh; - TCGType vtype =3D TCGOP_TYPE(op); - - /* This opcode is only valid for 32-bit hosts, for 64-bit elements. */ - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); - tcg_debug_assert(TCGOP_VECE(op) =3D=3D MO_64); - - ots =3D arg_temp(op->args[0]); - itsl =3D arg_temp(op->args[1]); - itsh =3D arg_temp(op->args[2]); - - /* ENV should not be modified. */ - tcg_debug_assert(!temp_readonly(ots)); - - /* Allocate the output register now. */ - if (ots->val_type !=3D TEMP_VAL_REG) { - TCGRegSet allocated_regs =3D s->reserved_regs; - TCGRegSet dup_out_regs =3D opcode_args_ct(op)[0].regs; - TCGReg oreg; - - /* Make sure to not spill the input registers. */ - if (!IS_DEAD_ARG(1) && itsl->val_type =3D=3D TEMP_VAL_REG) { - tcg_regset_set_reg(allocated_regs, itsl->reg); - } - if (!IS_DEAD_ARG(2) && itsh->val_type =3D=3D TEMP_VAL_REG) { - tcg_regset_set_reg(allocated_regs, itsh->reg); - } - - oreg =3D tcg_reg_alloc(s, dup_out_regs, allocated_regs, - output_pref(op, 0), ots->indirect_base); - set_temp_val_reg(s, ots, oreg); - } - - /* Promote dup2 of immediates to dupi_vec. */ - if (itsl->val_type =3D=3D TEMP_VAL_CONST && itsh->val_type =3D=3D TEMP= _VAL_CONST) { - uint64_t val =3D deposit64(itsl->val, 32, 32, itsh->val); - MemOp vece =3D MO_64; - - if (val =3D=3D dup_const(MO_8, val)) { - vece =3D MO_8; - } else if (val =3D=3D dup_const(MO_16, val)) { - vece =3D MO_16; - } else if (val =3D=3D dup_const(MO_32, val)) { - vece =3D MO_32; - } - - tcg_out_dupi_vec(s, vtype, vece, ots->reg, val); - goto done; - } - - /* If the two inputs form one 64-bit value, try dupm_vec. */ - if (itsl->temp_subindex =3D=3D HOST_BIG_ENDIAN && - itsh->temp_subindex =3D=3D !HOST_BIG_ENDIAN && - itsl =3D=3D itsh + (HOST_BIG_ENDIAN ? 1 : -1)) { - TCGTemp *its =3D itsl - HOST_BIG_ENDIAN; - - temp_sync(s, its + 0, s->reserved_regs, 0, 0); - temp_sync(s, its + 1, s->reserved_regs, 0, 0); - - if (tcg_out_dupm_vec(s, vtype, MO_64, ots->reg, - its->mem_base->reg, its->mem_offset)) { - goto done; - } - } - - /* Fall back to generic expansion. */ - return false; - - done: - ots->mem_coherent =3D 0; - if (IS_DEAD_ARG(1)) { - temp_dead(s, itsl); - } - if (IS_DEAD_ARG(2)) { - temp_dead(s, itsh); - } - if (NEED_SYNC_ARG(0)) { - temp_sync(s, ots, s->reserved_regs, 0, IS_DEAD_ARG(0)); - } else if (IS_DEAD_ARG(0)) { - temp_dead(s, ots); - } - return true; -} - static void load_arg_reg(TCGContext *s, TCGReg reg, TCGTemp *ts, TCGRegSet allocated_regs) { @@ -6939,11 +6850,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb= , uint64_t pc_start) case INDEX_op_mb: tcg_out_mb(s, op->args[0]); break; - case INDEX_op_dup2_vec: - if (tcg_reg_alloc_dup2(s, op)) { - break; - } - /* fall through */ default: do_default: /* Sanity check that we've not introduced any unhandled opcode= s. */ --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Sun, 18 Jan 2026 14:05:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 25/54] tcg/tci: Drop TCG_TARGET_REG_BITS tests Date: Mon, 19 Jan 2026 09:03:45 +1100 Message-ID: <20260118220414.8177-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774086549158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-has.h | 2 -- tcg/tci.c | 50 ++------------------------------------- tcg/tci/tcg-target.c.inc | 51 ++++++---------------------------------- 3 files changed, 9 insertions(+), 94 deletions(-) diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-has.h index ab07ce1fcb..64742cf0b7 100644 --- a/tcg/tci/tcg-target-has.h +++ b/tcg/tci/tcg-target-has.h @@ -7,9 +7,7 @@ #ifndef TCG_TARGET_HAS_H #define TCG_TARGET_HAS_H =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 #define TCG_TARGET_HAS_extr_i64_i32 0 -#endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ =20 #define TCG_TARGET_HAS_qemu_ldst_i128 0 =20 diff --git a/tcg/tci.c b/tcg/tci.c index 7f3ba9b5da..f71993c287 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -43,19 +43,6 @@ =20 __thread uintptr_t tci_tb_ptr; =20 -static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, - uint32_t low_index, uint64_t value) -{ - regs[low_index] =3D (uint32_t)value; - regs[high_index] =3D value >> 32; -} - -/* Create a 64 bit value from two 32 bit values. */ -static uint64_t tci_uint64(uint32_t high, uint32_t low) -{ - return ((uint64_t)high << 32) + low; -} - /* * Load sets of arguments all at once. The naming convention is: * tci_args_ @@ -352,7 +339,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, TCGCond condition; uint8_t pos, len; uint32_t tmp32; - uint64_t tmp64, taddr; + uint64_t taddr; MemOpIdx oi; int32_t ofs; void *ptr; @@ -400,10 +387,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, } break; case 2: /* uint64_t */ - /* - * For TCG_TARGET_REG_BITS =3D=3D 32, the register pair - * must stay in host memory order. - */ memcpy(®s[TCG_REG_R0], stack, 8); break; case 3: /* Int128 */ @@ -586,21 +569,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; case INDEX_op_muls2: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); -#if TCG_TARGET_REG_BITS =3D=3D 32 - tmp64 =3D (int64_t)(int32_t)regs[r2] * (int32_t)regs[r3]; - tci_write_reg64(regs, r1, r0, tmp64); -#else muls64(®s[r0], ®s[r1], regs[r2], regs[r3]); -#endif break; case INDEX_op_mulu2: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); -#if TCG_TARGET_REG_BITS =3D=3D 32 - tmp64 =3D (uint64_t)(uint32_t)regs[r2] * (uint32_t)regs[r3]; - tci_write_reg64(regs, r1, r0, tmp64); -#else mulu64(®s[r0], ®s[r1], regs[r2], regs[r3]); -#endif break; =20 /* Arithmetic operations (32 bit). */ @@ -690,7 +663,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_args_rr(insn, &r0, &r1); regs[r0] =3D bswap32(regs[r1]); break; -#if TCG_TARGET_REG_BITS =3D=3D 64 + /* Load/store operations (64 bit). */ =20 case INDEX_op_ld32u: @@ -758,7 +731,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_args_rr(insn, &r0, &r1); regs[r0] =3D bswap64(regs[r1]); break; -#endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ =20 /* QEMU specific operations. */ =20 @@ -804,24 +776,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr); break; =20 - case INDEX_op_qemu_ld2: - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); - tci_args_rrrr(insn, &r0, &r1, &r2, &r3); - taddr =3D regs[r2]; - oi =3D regs[r3]; - tmp64 =3D tci_qemu_ld(env, taddr, oi, tb_ptr); - tci_write_reg64(regs, r1, r0, tmp64); - break; - - case INDEX_op_qemu_st2: - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); - tci_args_rrrr(insn, &r0, &r1, &r2, &r3); - tmp64 =3D tci_uint64(regs[r1], regs[r0]); - taddr =3D regs[r2]; - oi =3D regs[r3]; - tci_qemu_st(env, taddr, tmp64, oi, tb_ptr); - break; - case INDEX_op_mb: /* Ensure ordering for all kinds */ smp_mb(); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8bd8db4401..1b22c70616 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -25,15 +25,9 @@ /* Used for function call generation. */ #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_STACK_ALIGN 8 -#if TCG_TARGET_REG_BITS =3D=3D 32 -# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EVEN -# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN -# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN -#else -# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL -# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL -# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL -#endif +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 static TCGConstraintSetIndex @@ -320,7 +314,7 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCG= Reg val, TCGReg base, { TCGOpcode op =3D INDEX_op_ld; =20 - if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I32) { + if (type =3D=3D TCG_TYPE_I32) { op =3D INDEX_op_ld32u; } tcg_out_ldst(s, op, val, base, offset); @@ -337,11 +331,9 @@ static void tcg_out_movi(TCGContext *s, TCGType type, { switch (type) { case TCG_TYPE_I32: -#if TCG_TARGET_REG_BITS =3D=3D 64 arg =3D (int32_t)arg; /* fall through */ case TCG_TYPE_I64: -#endif break; default: g_assert_not_reached(); @@ -407,13 +399,11 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg rd, = TCGReg rs) =20 static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_sextract(s, TCG_TYPE_I64, rd, rs, 0, 32); } =20 static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rs) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_extract(s, TCG_TYPE_I64, rd, rs, 0, 32); } =20 @@ -429,7 +419,6 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg = rd, TCGReg rs) =20 static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_mov(s, TCG_TYPE_I32, rd, rs); } =20 @@ -654,7 +643,6 @@ static const TCGOutOpBinary outop_eqv =3D { .out_rrr =3D tgen_eqv, }; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 static void tgen_extrh_i64_i32(TCGContext *s, TCGType t, TCGReg a0, TCGReg= a1) { tcg_out_extract(s, TCG_TYPE_I64, a0, a1, 32, 32); @@ -664,7 +652,6 @@ static const TCGOutOpUnary outop_extrh_i64_i32 =3D { .base.static_constraint =3D C_O1_I1(r, r), .out_rr =3D tgen_extrh_i64_i32, }; -#endif =20 static void tgen_mul(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) @@ -962,7 +949,6 @@ static const TCGOutOpBswap outop_bswap32 =3D { .out_rr =3D tgen_bswap32, }; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) { tcg_out_op_rr(s, INDEX_op_bswap64, a0, a1); @@ -972,7 +958,6 @@ static const TCGOutOpUnary outop_bswap64 =3D { .base.static_constraint =3D C_O1_I1(r, r), .out_rr =3D tgen_bswap64, }; -#endif =20 static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) { @@ -1101,7 +1086,6 @@ static const TCGOutOpLoad outop_ld16s =3D { .out =3D tgen_ld16s, }; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 static void tgen_ld32u(TCGContext *s, TCGType type, TCGReg dest, TCGReg base, ptrdiff_t offset) { @@ -1123,7 +1107,6 @@ static const TCGOutOpLoad outop_ld32s =3D { .base.static_constraint =3D C_O1_I1(r, r), .out =3D tgen_ld32s, }; -#endif =20 static void tgen_st8(TCGContext *s, TCGType type, TCGReg data, TCGReg base, ptrdiff_t offset) @@ -1168,18 +1151,8 @@ static const TCGOutOpQemuLdSt outop_qemu_ld =3D { .out =3D tgen_qemu_ld, }; =20 -static void tgen_qemu_ld2(TCGContext *s, TCGType type, TCGReg datalo, - TCGReg datahi, TCGReg addr, MemOpIdx oi) -{ - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, oi); - tcg_out_op_rrrr(s, INDEX_op_qemu_ld2, datalo, datahi, addr, TCG_REG_TM= P); -} - static const TCGOutOpQemuLdSt2 outop_qemu_ld2 =3D { - .base.static_constraint =3D - TCG_TARGET_REG_BITS =3D=3D 64 ? C_NotImplemented : C_O2_I1(r, r, r= ), - .out =3D - TCG_TARGET_REG_BITS =3D=3D 64 ? NULL : tgen_qemu_ld2, + .base.static_constraint =3D C_NotImplemented, }; =20 static void tgen_qemu_st(TCGContext *s, TCGType type, TCGReg data, @@ -1198,18 +1171,8 @@ static const TCGOutOpQemuLdSt outop_qemu_st =3D { .out =3D tgen_qemu_st, }; =20 -static void tgen_qemu_st2(TCGContext *s, TCGType type, TCGReg datalo, - TCGReg datahi, TCGReg addr, MemOpIdx oi) -{ - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, oi); - tcg_out_op_rrrr(s, INDEX_op_qemu_st2, datalo, datahi, addr, TCG_REG_TM= P); -} - static const TCGOutOpQemuLdSt2 outop_qemu_st2 =3D { - .base.static_constraint =3D - TCG_TARGET_REG_BITS =3D=3D 64 ? C_NotImplemented : C_O0_I3(r, r, r= ), - .out =3D - TCG_TARGET_REG_BITS =3D=3D 64 ? NULL : tgen_qemu_st2, + .base.static_constraint =3D C_NotImplemented, }; =20 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, @@ -1217,7 +1180,7 @@ static void tcg_out_st(TCGContext *s, TCGType type, T= CGReg val, TCGReg base, { TCGOpcode op =3D INDEX_op_st; =20 - if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I32) { + if (type =3D=3D TCG_TYPE_I32) { op =3D INDEX_op_st32; } tcg_out_ldst(s, op, val, base, offset); --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774185; cv=none; d=zohomail.com; s=zohoarc; b=OeH/MrhVEcohK3VJbNIzSA+Xmysas0Ngd5zy3/Nquyl4daLpNbcVerl3Iwm7bNVTUc6FiTrX+1RkFUhT9ec7npgy+HNsu+dXUF6f4ltRDc7zb7TJdnr5USi48i6pemisPmfALDkDFOWlsYAr+MM7Xv5MTtNrL2b9gb1Onw3kCMI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768774185; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=E3quorIoavgbRlUqCdA1N/hSlFNVi1G5ba+Ci7qX808=; b=e+slvinPKyqH3wDj6rLQBNCYAM83C2afor26JNWPDwBC10Te/VGQLUeuw7+EYuZ8VAUx1iLgwzOV8bMXoc8C7W3YZVK12dZ4n1xpgtU90T377isj+NTdWvVKcrrbvLkMLSxA8BSffd5ydZjOx5yWuD0AhThDot6hoJTgJ+rKGT0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768774184865435.49922825182887; Sun, 18 Jan 2026 14:09:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhatv-0003Og-09; Sun, 18 Jan 2026 17:05:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhati-0002RC-SP for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:28 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhath-0000sO-CK for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:26 -0500 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-2a102494058so22840015ad.0 for ; Sun, 18 Jan 2026 14:05:24 -0800 (PST) Received: from stoup.. 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Sun, 18 Jan 2026 14:05:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 26/54] tcg/tci: Remove glue TCG_TARGET_REG_BITS renames Date: Mon, 19 Jan 2026 09:03:46 +1100 Message-ID: <20260118220414.8177-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774186732158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tci.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index f71993c287..29ecb39929 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -26,11 +26,6 @@ #include =20 =20 -#define ctpop_tr glue(ctpop, TCG_TARGET_REG_BITS) -#define deposit_tr glue(deposit, TCG_TARGET_REG_BITS) -#define extract_tr glue(extract, TCG_TARGET_REG_BITS) -#define sextract_tr glue(sextract, TCG_TARGET_REG_BITS) - /* * Enable TCI assertions only when debugging TCG (and without NDEBUG defin= ed). * Without assertions, the interpreter runs much faster. @@ -525,7 +520,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; case INDEX_op_ctpop: tci_args_rr(insn, &r0, &r1); - regs[r0] =3D ctpop_tr(regs[r1]); + regs[r0] =3D ctpop64(regs[r1]); break; case INDEX_op_addco: tci_args_rrr(insn, &r0, &r1, &r2); @@ -639,15 +634,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; case INDEX_op_deposit: tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); - regs[r0] =3D deposit_tr(regs[r1], pos, len, regs[r2]); + regs[r0] =3D deposit64(regs[r1], pos, len, regs[r2]); break; case INDEX_op_extract: tci_args_rrbb(insn, &r0, &r1, &pos, &len); - regs[r0] =3D extract_tr(regs[r1], pos, len); + regs[r0] =3D extract64(regs[r1], pos, len); break; case INDEX_op_sextract: tci_args_rrbb(insn, &r0, &r1, &pos, &len); - regs[r0] =3D sextract_tr(regs[r1], pos, len); + regs[r0] =3D sextract64(regs[r1], pos, len); break; case INDEX_op_brcond: tci_args_rl(insn, tb_ptr, &r0, &ptr); --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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On these systems - * we utilise a static code generation buffer directly in the binary. - */ -#define USE_STATIC_CODE_GEN_BUFFER -#endif -#else /* TCG_TARGET_REG_BITS =3D=3D 64 */ #ifdef CONFIG_USER_ONLY /* * As user-mode emulation typically means running multiple instances @@ -490,7 +479,6 @@ static size_t tcg_n_regions(size_t tb_size, unsigned ma= x_threads) */ #define DEFAULT_CODE_GEN_BUFFER_SIZE_1 (1 * GiB) #endif -#endif =20 #define DEFAULT_CODE_GEN_BUFFER_SIZE \ (DEFAULT_CODE_GEN_BUFFER_SIZE_1 < MAX_CODE_GEN_BUFFER_SIZE \ --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774145; cv=none; d=zohomail.com; s=zohoarc; b=HugLpSAF69Eb2BJjyPXBHvISA5h27rUKWfcsy4TrZGb7BFsgd0KtBcPdmUq3JwJsAcNo9jfVBlYVHTkDwqJObhdfWptUtW4PYcr8rudDneNpewieDrMG4a9sn+vtaNBn2XMMu9e5T+WREc/RKHR3bRmgv7vZroyqoexMn4pVQhE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768774145; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/I60gyIokTIrbunC9gly6yzJgKVfoNKqDR47yyL6wsE=; b=NEbidht7VclIeTw7kNPIvYUq0PGLMzXKtnUVz7YN1hL3kQgcQg3YIk5T+SahAsZvygyGj8rUa42EGtZUuAMNR1RbV9nrCuVSsYPlCMxZ06ebopr/VaRvI+oy4cNTc4sl80D3Ga0Ndb77nidbJHfYPxzShc8WMLWDOFqsdf26kdE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768774144970671.3178769932779; Sun, 18 Jan 2026 14:09:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhauA-0004wc-E4; Sun, 18 Jan 2026 17:05:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhatp-0002rc-UO for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:34 -0500 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhatm-0000tR-9i for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:33 -0500 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-81dab89f286so1662763b3a.2 for ; Sun, 18 Jan 2026 14:05:29 -0800 (PST) Received: from stoup.. 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Sun, 18 Jan 2026 14:05:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 28/54] tcg: Drop TCG_TARGET_REG_BITS tests in tcg-op.c Date: Mon, 19 Jan 2026 09:03:48 +1100 Message-ID: <20260118220414.8177-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774146650158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 686 +++++++-------------------------------------------- 1 file changed, 90 insertions(+), 596 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index d20888dd8f..8d67acc4fc 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1154,7 +1154,7 @@ void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv= _i32 arg1, TCGv_i32 arg2) tcg_gen_op3_i32(INDEX_op_muluh, rh, arg1, arg2); tcg_gen_mov_i32(rl, t); tcg_temp_free_i32(t); - } else if (TCG_TARGET_REG_BITS =3D=3D 64) { + } else { TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); tcg_gen_extu_i32_i64(t0, arg1); @@ -1163,8 +1163,6 @@ void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv= _i32 arg1, TCGv_i32 arg2) tcg_gen_extr_i64_i32(rl, rh, t0); tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); - } else { - g_assert_not_reached(); } } =20 @@ -1178,24 +1176,6 @@ void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCG= v_i32 arg1, TCGv_i32 arg2) tcg_gen_op3_i32(INDEX_op_mulsh, rh, arg1, arg2); tcg_gen_mov_i32(rl, t); tcg_temp_free_i32(t); - } else if (TCG_TARGET_REG_BITS =3D=3D 32) { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 t1 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 t2 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 t3 =3D tcg_temp_ebb_new_i32(); - tcg_gen_mulu2_i32(t0, t1, arg1, arg2); - /* Adjust for negative inputs. */ - tcg_gen_sari_i32(t2, arg1, 31); - tcg_gen_sari_i32(t3, arg2, 31); - tcg_gen_and_i32(t2, t2, arg2); - tcg_gen_and_i32(t3, t3, arg1); - tcg_gen_sub_i32(rh, t1, t2); - tcg_gen_sub_i32(rh, rh, t3); - tcg_gen_mov_i32(rl, t0); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } else { TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); @@ -1210,29 +1190,14 @@ void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TC= Gv_i32 arg1, TCGv_i32 arg2) =20 void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 = arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 t1 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 t2 =3D tcg_temp_ebb_new_i32(); - tcg_gen_mulu2_i32(t0, t1, arg1, arg2); - /* Adjust for negative input for the signed arg1. */ - tcg_gen_sari_i32(t2, arg1, 31); - tcg_gen_and_i32(t2, t2, arg2); - tcg_gen_sub_i32(rh, t1, t2); - tcg_gen_mov_i32(rl, t0); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); - } else { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); - tcg_gen_ext_i32_i64(t0, arg1); - tcg_gen_extu_i32_i64(t1, arg2); - tcg_gen_mul_i64(t0, t0, t1); - tcg_gen_extr_i64_i32(rl, rh, t0); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - } + TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); + TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); + tcg_gen_ext_i32_i64(t0, arg1); + tcg_gen_extu_i32_i64(t1, arg2); + tcg_gen_mul_i64(t0, t0, t1); + tcg_gen_extr_i64_i32(rl, rh, t0); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } =20 void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg) @@ -1414,263 +1379,119 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2,= tcg_target_long offset) =20 void tcg_gen_discard_i64(TCGv_i64 arg) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_op1_i64(INDEX_op_discard, TCG_TYPE_I64, arg); - } else { - tcg_gen_discard_i32(TCGV_LOW(arg)); - tcg_gen_discard_i32(TCGV_HIGH(arg)); - } + tcg_gen_op1_i64(INDEX_op_discard, TCG_TYPE_I64, arg); } =20 void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) { - if (ret =3D=3D arg) { - return; - } - if (TCG_TARGET_REG_BITS =3D=3D 64) { + if (ret !=3D arg) { tcg_gen_op2_i64(INDEX_op_mov, ret, arg); - } else { - TCGTemp *ts =3D tcgv_i64_temp(arg); - - /* Canonicalize TCGv_i64 TEMP_CONST into TCGv_i32 TEMP_CONST. */ - if (ts->kind =3D=3D TEMP_CONST) { - tcg_gen_movi_i64(ret, ts->val); - } else { - tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); - tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); - } } } =20 void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_mov_i64(ret, tcg_constant_i64(arg)); - } else { - tcg_gen_movi_i32(TCGV_LOW(ret), arg); - tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32); - } + tcg_gen_mov_i64(ret, tcg_constant_i64(arg)); } =20 void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_ldst_op_i64(INDEX_op_ld8u, ret, arg2, offset); - } else { - tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - } + tcg_gen_ldst_op_i64(INDEX_op_ld8u, ret, arg2, offset); } =20 void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_ldst_op_i64(INDEX_op_ld8s, ret, arg2, offset); - } else { - tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset); - tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); - } + tcg_gen_ldst_op_i64(INDEX_op_ld8s, ret, arg2, offset); } =20 void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_ldst_op_i64(INDEX_op_ld16u, ret, arg2, offset); - } else { - tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - } + tcg_gen_ldst_op_i64(INDEX_op_ld16u, ret, arg2, offset); } =20 void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_ldst_op_i64(INDEX_op_ld16s, ret, arg2, offset); - } else { - tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset); - tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); - } + tcg_gen_ldst_op_i64(INDEX_op_ld16s, ret, arg2, offset); } =20 void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_ldst_op_i64(INDEX_op_ld32u, ret, arg2, offset); - } else { - tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - } + tcg_gen_ldst_op_i64(INDEX_op_ld32u, ret, arg2, offset); } =20 void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_ldst_op_i64(INDEX_op_ld32s, ret, arg2, offset); - } else { - tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); - tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); - } + tcg_gen_ldst_op_i64(INDEX_op_ld32s, ret, arg2, offset); } =20 void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { - /* - * For 32-bit host, since arg2 and ret have different types, - * they cannot be the same temporary -- no chance of overlap. - */ - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_ldst_op_i64(INDEX_op_ld, ret, arg2, offset); - } else if (HOST_BIG_ENDIAN) { - tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); - tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4); - } else { - tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); - tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4); - } + tcg_gen_ldst_op_i64(INDEX_op_ld, ret, arg2, offset); } =20 void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_ldst_op_i64(INDEX_op_st8, arg1, arg2, offset); - } else { - tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); - } + tcg_gen_ldst_op_i64(INDEX_op_st8, arg1, arg2, offset); } =20 void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_ldst_op_i64(INDEX_op_st16, arg1, arg2, offset); - } else { - tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); - } + tcg_gen_ldst_op_i64(INDEX_op_st16, arg1, arg2, offset); } =20 void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_ldst_op_i64(INDEX_op_st32, arg1, arg2, offset); - } else { - tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); - } + tcg_gen_ldst_op_i64(INDEX_op_st32, arg1, arg2, offset); } =20 void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); - } else if (HOST_BIG_ENDIAN) { - tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); - tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4); - } else { - tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); - tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4); - } + tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); } =20 void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_op3_i64(INDEX_op_add, ret, arg1, arg2); - } else { - tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), - TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); - } + tcg_gen_op3_i64(INDEX_op_add, ret, arg1, arg2); } =20 void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_op3_i64(INDEX_op_sub, ret, arg1, arg2); - } else { - tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), - TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); - } + tcg_gen_op3_i64(INDEX_op_sub, ret, arg1, arg2); } =20 void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_op3_i64(INDEX_op_and, ret, arg1, arg2); - } else { - tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); - tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); - } + tcg_gen_op3_i64(INDEX_op_and, ret, arg1, arg2); } =20 void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_op3_i64(INDEX_op_or, ret, arg1, arg2); - } else { - tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); - tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); - } + tcg_gen_op3_i64(INDEX_op_or, ret, arg1, arg2); } =20 void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_op3_i64(INDEX_op_xor, ret, arg1, arg2); - } else { - tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); - tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); - } + tcg_gen_op3_i64(INDEX_op_xor, ret, arg1, arg2); } =20 void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_op3_i64(INDEX_op_shl, ret, arg1, arg2); - } else { - gen_helper_shl_i64(ret, arg1, arg2); - } + tcg_gen_op3_i64(INDEX_op_shl, ret, arg1, arg2); } =20 void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_op3_i64(INDEX_op_shr, ret, arg1, arg2); - } else { - gen_helper_shr_i64(ret, arg1, arg2); - } + tcg_gen_op3_i64(INDEX_op_shr, ret, arg1, arg2); } =20 void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_op3_i64(INDEX_op_sar, ret, arg1, arg2); - } else { - gen_helper_sar_i64(ret, arg1, arg2); - } + tcg_gen_op3_i64(INDEX_op_sar, ret, arg1, arg2); } =20 void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - TCGv_i64 t0; - TCGv_i32 t1; - - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_op3_i64(INDEX_op_mul, ret, arg1, arg2); - return; - } - - - t0 =3D tcg_temp_ebb_new_i64(); - t1 =3D tcg_temp_ebb_new_i32(); - - tcg_gen_mulu2_i32(TCGV_LOW(t0), TCGV_HIGH(t0), - TCGV_LOW(arg1), TCGV_LOW(arg2)); - - tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2)); - tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); - tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2)); - tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); - - tcg_gen_mov_i64(ret, t0); - tcg_temp_free_i64(t0); - tcg_temp_free_i32(t1); + tcg_gen_op3_i64(INDEX_op_mul, ret, arg1, arg2); } =20 void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) @@ -1678,12 +1499,8 @@ void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, i= nt64_t arg2) /* some cases can be optimized here */ if (arg2 =3D=3D 0) { tcg_gen_mov_i64(ret, arg1); - } else if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_add_i64(ret, arg1, tcg_constant_i64(arg2)); } else { - tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), - TCGV_LOW(arg1), TCGV_HIGH(arg1), - tcg_constant_i32(arg2), tcg_constant_i32(arg2 >> = 32)); + tcg_gen_add_i64(ret, arg1, tcg_constant_i64(arg2)); } } =20 @@ -1691,12 +1508,8 @@ void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, T= CGv_i64 arg2) { if (arg1 =3D=3D 0) { tcg_gen_neg_i64(ret, arg2); - } else if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_sub_i64(ret, tcg_constant_i64(arg1), arg2); } else { - tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), - tcg_constant_i32(arg1), tcg_constant_i32(arg1 >> = 32), - TCGV_LOW(arg2), TCGV_HIGH(arg2)); + tcg_gen_sub_i64(ret, tcg_constant_i64(arg1), arg2); } } =20 @@ -1707,23 +1520,11 @@ void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, = int64_t arg2) =20 void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_gen_op2_i64(INDEX_op_neg, ret, arg); - } else { - TCGv_i32 zero =3D tcg_constant_i32(0); - tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), - zero, zero, TCGV_LOW(arg), TCGV_HIGH(arg)); - } + tcg_gen_op2_i64(INDEX_op_neg, ret, arg); } =20 void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); - tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); - return; - } - /* Some cases can be optimized here. */ switch (arg2) { case 0: @@ -1754,11 +1555,6 @@ void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, i= nt64_t arg2) =20 void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); - tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); - return; - } /* Some cases can be optimized here. */ if (arg2 =3D=3D -1) { tcg_gen_movi_i64(ret, -1); @@ -1771,11 +1567,6 @@ void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, in= t64_t arg2) =20 void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); - tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); - return; - } /* Some cases can be optimized here. */ if (arg2 =3D=3D 0) { tcg_gen_mov_i64(ret, arg1); @@ -1788,48 +1579,10 @@ void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, = int64_t arg2) } } =20 -static inline void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1, - unsigned c, bool right, bool arith) -{ - tcg_debug_assert(c < 64); - if (c =3D=3D 0) { - tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); - tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1)); - } else if (c >=3D 32) { - c -=3D 32; - if (right) { - if (arith) { - tcg_gen_sari_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), c); - tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), 31); - } else { - tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), c); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - } - } else { - tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_LOW(arg1), c); - tcg_gen_movi_i32(TCGV_LOW(ret), 0); - } - } else if (right) { - tcg_gen_extract2_i32(TCGV_LOW(ret), TCGV_LOW(arg1), - TCGV_HIGH(arg1), c); - if (arith) { - tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c); - } else { - tcg_gen_shri_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c); - } - } else { - tcg_gen_extract2_i32(TCGV_HIGH(ret), TCGV_LOW(arg1), - TCGV_HIGH(arg1), 32 - c); - tcg_gen_shli_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c); - } -} - void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { tcg_debug_assert(arg2 >=3D 0 && arg2 < 64); - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); - } else if (arg2 =3D=3D 0) { + if (arg2 =3D=3D 0) { tcg_gen_mov_i64(ret, arg1); } else { tcg_gen_shl_i64(ret, arg1, tcg_constant_i64(arg2)); @@ -1839,9 +1592,7 @@ void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, in= t64_t arg2) void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { tcg_debug_assert(arg2 >=3D 0 && arg2 < 64); - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); - } else if (arg2 =3D=3D 0) { + if (arg2 =3D=3D 0) { tcg_gen_mov_i64(ret, arg1); } else { tcg_gen_shr_i64(ret, arg1, tcg_constant_i64(arg2)); @@ -1851,9 +1602,7 @@ void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, in= t64_t arg2) void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { tcg_debug_assert(arg2 >=3D 0 && arg2 < 64); - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); - } else if (arg2 =3D=3D 0) { + if (arg2 =3D=3D 0) { tcg_gen_mov_i64(ret, arg1); } else { tcg_gen_sar_i64(ret, arg1, tcg_constant_i64(arg2)); @@ -2034,14 +1783,7 @@ void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg,= int flags) /* Only one extension flag may be present. */ tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ)); =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg), flags); - if (flags & TCG_BSWAP_OS) { - tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); - } else { - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - } - } else if (tcg_op_supported(INDEX_op_bswap16, TCG_TYPE_I64, 0)) { + if (tcg_op_supported(INDEX_op_bswap16, TCG_TYPE_I64, 0)) { tcg_gen_op3i_i64(INDEX_op_bswap16, ret, arg, flags); } else { TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); @@ -2084,14 +1826,7 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg,= int flags) /* Only one extension flag may be present. */ tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ)); =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg)); - if (flags & TCG_BSWAP_OS) { - tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); - } else { - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - } - } else if (tcg_op_supported(INDEX_op_bswap32, TCG_TYPE_I64, 0)) { + if (tcg_op_supported(INDEX_op_bswap32, TCG_TYPE_I64, 0)) { tcg_gen_op3i_i64(INDEX_op_bswap32, ret, arg, flags); } else { TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); @@ -2127,18 +1862,7 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg,= int flags) */ void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - TCGv_i32 t0, t1; - t0 =3D tcg_temp_ebb_new_i32(); - t1 =3D tcg_temp_ebb_new_i32(); - - tcg_gen_bswap32_i32(t0, TCGV_LOW(arg)); - tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg)); - tcg_gen_mov_i32(TCGV_LOW(ret), t1); - tcg_gen_mov_i32(TCGV_HIGH(ret), t0); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); - } else if (tcg_op_supported(INDEX_op_bswap64, TCG_TYPE_I64, 0)) { + if (tcg_op_supported(INDEX_op_bswap64, TCG_TYPE_I64, 0)) { tcg_gen_op3i_i64(INDEX_op_bswap64, ret, arg, 0); } else { TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); @@ -2207,10 +1931,7 @@ void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg) =20 void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg)); - tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); - } else if (tcg_op_supported(INDEX_op_not, TCG_TYPE_I64, 0)) { + if (tcg_op_supported(INDEX_op_not, TCG_TYPE_I64, 0)) { tcg_gen_op2_i64(INDEX_op_not, ret, arg); } else { tcg_gen_xori_i64(ret, arg, -1); @@ -2219,10 +1940,7 @@ void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) =20 void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); - tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); - } else if (tcg_op_supported(INDEX_op_andc, TCG_TYPE_I64, 0)) { + if (tcg_op_supported(INDEX_op_andc, TCG_TYPE_I64, 0)) { tcg_gen_op3_i64(INDEX_op_andc, ret, arg1, arg2); } else { TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); @@ -2234,10 +1952,7 @@ void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, T= CGv_i64 arg2) =20 void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); - tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); - } else if (tcg_op_supported(INDEX_op_eqv, TCG_TYPE_I64, 0)) { + if (tcg_op_supported(INDEX_op_eqv, TCG_TYPE_I64, 0)) { tcg_gen_op3_i64(INDEX_op_eqv, ret, arg1, arg2); } else { tcg_gen_xor_i64(ret, arg1, arg2); @@ -2247,10 +1962,7 @@ void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TC= Gv_i64 arg2) =20 void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); - tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); - } else if (tcg_op_supported(INDEX_op_nand, TCG_TYPE_I64, 0)) { + if (tcg_op_supported(INDEX_op_nand, TCG_TYPE_I64, 0)) { tcg_gen_op3_i64(INDEX_op_nand, ret, arg1, arg2); } else { tcg_gen_and_i64(ret, arg1, arg2); @@ -2260,10 +1972,7 @@ void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, T= CGv_i64 arg2) =20 void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); - tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); - } else if (tcg_op_supported(INDEX_op_nor, TCG_TYPE_I64, 0)) { + if (tcg_op_supported(INDEX_op_nor, TCG_TYPE_I64, 0)) { tcg_gen_op3_i64(INDEX_op_nor, ret, arg1, arg2); } else { tcg_gen_or_i64(ret, arg1, arg2); @@ -2273,10 +1982,7 @@ void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TC= Gv_i64 arg2) =20 void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); - tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); - } else if (tcg_op_supported(INDEX_op_orc, TCG_TYPE_I64, 0)) { + if (tcg_op_supported(INDEX_op_orc, TCG_TYPE_I64, 0)) { tcg_gen_op3_i64(INDEX_op_orc, ret, arg1, arg2); } else { TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); @@ -2297,18 +2003,7 @@ void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TC= Gv_i64 arg2) =20 void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 32 - && arg2 <=3D 0xffffffffu - && tcg_op_supported(INDEX_op_clz, TCG_TYPE_I32, 0)) { - TCGv_i32 t =3D tcg_temp_ebb_new_i32(); - tcg_gen_clzi_i32(t, TCGV_LOW(arg1), arg2 - 32); - tcg_gen_addi_i32(t, t, 32); - tcg_gen_clz_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), t); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - tcg_temp_free_i32(t); - } else { - tcg_gen_clz_i64(ret, arg1, tcg_constant_i64(arg2)); - } + tcg_gen_clz_i64(ret, arg1, tcg_constant_i64(arg2)); } =20 void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) @@ -2342,18 +2037,9 @@ void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TC= Gv_i64 arg2) =20 void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) { - if (TCG_TARGET_REG_BITS =3D=3D 32 - && arg2 <=3D 0xffffffffu - && tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I32, 0)) { - TCGv_i32 t32 =3D tcg_temp_ebb_new_i32(); - tcg_gen_ctzi_i32(t32, TCGV_HIGH(arg1), arg2 - 32); - tcg_gen_addi_i32(t32, t32, 32); - tcg_gen_ctz_i32(TCGV_LOW(ret), TCGV_LOW(arg1), t32); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - tcg_temp_free_i32(t32); - } else if (arg2 =3D=3D 64 - && !tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I64, 0) - && tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I64, 0)) { + if (arg2 =3D=3D 64 + && !tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I64, 0) + && tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I64, 0)) { /* This equivalence has the advantage of not requiring a fixup. */ TCGv_i64 t =3D tcg_temp_ebb_new_i64(); tcg_gen_subi_i64(t, arg1, 1); @@ -2381,21 +2067,11 @@ void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg) =20 void tcg_gen_ctpop_i64(TCGv_i64 ret, TCGv_i64 arg1) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I64, 0)) { - tcg_gen_op2_i64(INDEX_op_ctpop, ret, arg1); - return; - } + if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I64, 0)) { + tcg_gen_op2_i64(INDEX_op_ctpop, ret, arg1); } else { - if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I32, 0)) { - tcg_gen_ctpop_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1)); - tcg_gen_ctpop_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); - tcg_gen_add_i32(TCGV_LOW(ret), TCGV_LOW(ret), TCGV_HIGH(ret)); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - return; - } + gen_helper_ctpop_i64(ret, arg1); } - gen_helper_ctpop_i64(ret, arg1); } =20 void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) @@ -2485,24 +2161,9 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1= , TCGv_i64 arg2, return; } =20 - if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (TCG_TARGET_deposit_valid(TCG_TYPE_I64, ofs, len)) { - tcg_gen_op5ii_i64(INDEX_op_deposit, ret, arg1, arg2, ofs, len); - return; - } - } else { - if (ofs >=3D 32) { - tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), - TCGV_LOW(arg2), ofs - 32, len); - tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); - return; - } - if (ofs + len <=3D 32) { - tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1), - TCGV_LOW(arg2), ofs, len); - tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1)); - return; - } + if (TCG_TARGET_deposit_valid(TCG_TYPE_I64, ofs, len)) { + tcg_gen_op5ii_i64(INDEX_op_deposit, ret, arg1, arg2, ofs, len); + return; } =20 t1 =3D tcg_temp_ebb_new_i64(); @@ -2545,24 +2206,10 @@ void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 a= rg, tcg_gen_shli_i64(ret, arg, ofs); } else if (ofs =3D=3D 0) { tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); - } else if (TCG_TARGET_REG_BITS =3D=3D 64 && - TCG_TARGET_deposit_valid(TCG_TYPE_I64, ofs, len)) { + } else if (TCG_TARGET_deposit_valid(TCG_TYPE_I64, ofs, len)) { TCGv_i64 zero =3D tcg_constant_i64(0); tcg_gen_op5ii_i64(INDEX_op_deposit, ret, zero, arg, ofs, len); } else { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - if (ofs >=3D 32) { - tcg_gen_deposit_z_i32(TCGV_HIGH(ret), TCGV_LOW(arg), - ofs - 32, len); - tcg_gen_movi_i32(TCGV_LOW(ret), 0); - return; - } - if (ofs + len <=3D 32) { - tcg_gen_deposit_z_i32(TCGV_LOW(ret), TCGV_LOW(arg), ofs, l= en); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - return; - } - } /* * To help two-operand hosts we prefer to zero-extend first, * which allows ARG to stay live. @@ -2597,32 +2244,6 @@ void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, return; } =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - /* Look for a 32-bit extract within one of the two words. */ - if (ofs >=3D 32) { - tcg_gen_extract_i32(TCGV_LOW(ret), TCGV_HIGH(arg), ofs - 32, l= en); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - return; - } - if (ofs + len <=3D 32) { - tcg_gen_extract_i32(TCGV_LOW(ret), TCGV_LOW(arg), ofs, len); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - return; - } - - /* The field is split across two words. */ - tcg_gen_extract2_i32(TCGV_LOW(ret), TCGV_LOW(arg), - TCGV_HIGH(arg), ofs); - if (len <=3D 32) { - tcg_gen_extract_i32(TCGV_LOW(ret), TCGV_LOW(ret), 0, len); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - } else { - tcg_gen_extract_i32(TCGV_HIGH(ret), TCGV_HIGH(arg), - ofs, len - 32); - } - return; - } - if (TCG_TARGET_extract_valid(TCG_TYPE_I64, ofs, len)) { tcg_gen_op4ii_i64(INDEX_op_extract, ret, arg, ofs, len); return; @@ -2668,38 +2289,6 @@ void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, return; } =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - /* Look for a 32-bit extract within one of the two words. */ - if (ofs >=3D 32) { - tcg_gen_sextract_i32(TCGV_LOW(ret), TCGV_HIGH(arg), ofs - 32, = len); - } else if (ofs + len <=3D 32) { - tcg_gen_sextract_i32(TCGV_LOW(ret), TCGV_LOW(arg), ofs, len); - } else if (ofs =3D=3D 0) { - tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); - tcg_gen_sextract_i32(TCGV_HIGH(ret), TCGV_HIGH(arg), 0, len - = 32); - return; - } else if (len > 32) { - TCGv_i32 t =3D tcg_temp_ebb_new_i32(); - /* Extract the bits for the high word normally. */ - tcg_gen_sextract_i32(t, TCGV_HIGH(arg), ofs + 32, len - 32); - /* Shift the field down for the low part. */ - tcg_gen_shri_i64(ret, arg, ofs); - /* Overwrite the shift into the high part. */ - tcg_gen_mov_i32(TCGV_HIGH(ret), t); - tcg_temp_free_i32(t); - return; - } else { - /* Shift the field down for the low part, such that the - field sits at the MSB. */ - tcg_gen_shri_i64(ret, arg, ofs + len - 32); - /* Shift the field down from the MSB, sign extending. */ - tcg_gen_sari_i32(TCGV_LOW(ret), TCGV_LOW(ret), 32 - len); - } - /* Sign-extend the field from 32 bits. */ - tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); - return; - } - if (TCG_TARGET_sextract_valid(TCG_TYPE_I64, ofs, len)) { tcg_gen_op4ii_i64(INDEX_op_sextract, ret, arg, ofs, len); return; @@ -2763,20 +2352,8 @@ void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv= _i64 al, if (tcg_op_supported(INDEX_op_addci, TCG_TYPE_REG, 0)) { TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_op3_i32(INDEX_op_addco, TCGV_LOW(t0), - TCGV_LOW(al), TCGV_LOW(bl)); - tcg_gen_op3_i32(INDEX_op_addcio, TCGV_HIGH(t0), - TCGV_HIGH(al), TCGV_HIGH(bl)); - tcg_gen_op3_i32(INDEX_op_addcio, TCGV_LOW(rh), - TCGV_LOW(ah), TCGV_LOW(bh)); - tcg_gen_op3_i32(INDEX_op_addci, TCGV_HIGH(rh), - TCGV_HIGH(ah), TCGV_HIGH(bh)); - } else { - tcg_gen_op3_i64(INDEX_op_addco, t0, al, bl); - tcg_gen_op3_i64(INDEX_op_addci, rh, ah, bh); - } - + tcg_gen_op3_i64(INDEX_op_addco, t0, al, bl); + tcg_gen_op3_i64(INDEX_op_addci, rh, ah, bh); tcg_gen_mov_i64(rl, t0); tcg_temp_free_i64(t0); } else { @@ -2795,68 +2372,27 @@ void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCG= v_i64 al, void tcg_gen_addcio_i64(TCGv_i64 r, TCGv_i64 co, TCGv_i64 a, TCGv_i64 b, TCGv_i64 ci) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (tcg_op_supported(INDEX_op_addci, TCG_TYPE_I64, 0)) { - TCGv_i64 discard =3D tcg_temp_ebb_new_i64(); - TCGv_i64 zero =3D tcg_constant_i64(0); - TCGv_i64 mone =3D tcg_constant_i64(-1); + if (tcg_op_supported(INDEX_op_addci, TCG_TYPE_I64, 0)) { + TCGv_i64 discard =3D tcg_temp_ebb_new_i64(); + TCGv_i64 zero =3D tcg_constant_i64(0); + TCGv_i64 mone =3D tcg_constant_i64(-1); =20 - tcg_gen_op3_i64(INDEX_op_addco, discard, ci, mone); - tcg_gen_op3_i64(INDEX_op_addcio, r, a, b); - tcg_gen_op3_i64(INDEX_op_addci, co, zero, zero); - tcg_temp_free_i64(discard); - } else { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); - - tcg_gen_add_i64(t0, a, b); - tcg_gen_setcond_i64(TCG_COND_LTU, t1, t0, a); - tcg_gen_add_i64(r, t0, ci); - tcg_gen_setcond_i64(TCG_COND_LTU, t0, r, t0); - tcg_gen_or_i64(co, t0, t1); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - } + tcg_gen_op3_i64(INDEX_op_addco, discard, ci, mone); + tcg_gen_op3_i64(INDEX_op_addcio, r, a, b); + tcg_gen_op3_i64(INDEX_op_addci, co, zero, zero); + tcg_temp_free_i64(discard); } else { - if (tcg_op_supported(INDEX_op_addci, TCG_TYPE_I32, 0)) { - TCGv_i32 discard =3D tcg_temp_ebb_new_i32(); - TCGv_i32 zero =3D tcg_constant_i32(0); - TCGv_i32 mone =3D tcg_constant_i32(-1); + TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); + TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); =20 - tcg_gen_op3_i32(INDEX_op_addco, discard, TCGV_LOW(ci), mone); - tcg_gen_op3_i32(INDEX_op_addcio, discard, TCGV_HIGH(ci), mone); - tcg_gen_op3_i32(INDEX_op_addcio, TCGV_LOW(r), - TCGV_LOW(a), TCGV_LOW(b)); - tcg_gen_op3_i32(INDEX_op_addcio, TCGV_HIGH(r), - TCGV_HIGH(a), TCGV_HIGH(b)); - tcg_gen_op3_i32(INDEX_op_addci, TCGV_LOW(co), zero, zero); - tcg_temp_free_i32(discard); - } else { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 c0 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 c1 =3D tcg_temp_ebb_new_i32(); + tcg_gen_add_i64(t0, a, b); + tcg_gen_setcond_i64(TCG_COND_LTU, t1, t0, a); + tcg_gen_add_i64(r, t0, ci); + tcg_gen_setcond_i64(TCG_COND_LTU, t0, r, t0); + tcg_gen_or_i64(co, t0, t1); =20 - tcg_gen_or_i32(c1, TCGV_LOW(ci), TCGV_HIGH(ci)); - tcg_gen_setcondi_i32(TCG_COND_NE, c1, c1, 0); - - tcg_gen_add_i32(t0, TCGV_LOW(a), TCGV_LOW(b)); - tcg_gen_setcond_i32(TCG_COND_LTU, c0, t0, TCGV_LOW(a)); - tcg_gen_add_i32(TCGV_LOW(r), t0, c1); - tcg_gen_setcond_i32(TCG_COND_LTU, c1, TCGV_LOW(r), c1); - tcg_gen_or_i32(c1, c1, c0); - - tcg_gen_add_i32(t0, TCGV_HIGH(a), TCGV_HIGH(b)); - tcg_gen_setcond_i32(TCG_COND_LTU, c0, t0, TCGV_HIGH(a)); - tcg_gen_add_i32(TCGV_HIGH(r), t0, c1); - tcg_gen_setcond_i32(TCG_COND_LTU, c1, TCGV_HIGH(r), c1); - tcg_gen_or_i32(TCGV_LOW(co), c0, c1); - - tcg_temp_free_i32(t0); - tcg_temp_free_i32(c0); - tcg_temp_free_i32(c1); - } - tcg_gen_movi_i32(TCGV_HIGH(co), 0); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } } =20 @@ -2866,20 +2402,8 @@ void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv= _i64 al, if (tcg_op_supported(INDEX_op_subbi, TCG_TYPE_REG, 0)) { TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_op3_i32(INDEX_op_subbo, TCGV_LOW(t0), - TCGV_LOW(al), TCGV_LOW(bl)); - tcg_gen_op3_i32(INDEX_op_subbio, TCGV_HIGH(t0), - TCGV_HIGH(al), TCGV_HIGH(bl)); - tcg_gen_op3_i32(INDEX_op_subbio, TCGV_LOW(rh), - TCGV_LOW(ah), TCGV_LOW(bh)); - tcg_gen_op3_i32(INDEX_op_subbi, TCGV_HIGH(rh), - TCGV_HIGH(ah), TCGV_HIGH(bh)); - } else { - tcg_gen_op3_i64(INDEX_op_subbo, t0, al, bl); - tcg_gen_op3_i64(INDEX_op_subbi, rh, ah, bh); - } - + tcg_gen_op3_i64(INDEX_op_subbo, t0, al, bl); + tcg_gen_op3_i64(INDEX_op_subbi, rh, ah, bh); tcg_gen_mov_i64(rl, t0); tcg_temp_free_i64(t0); } else { @@ -3002,57 +2526,32 @@ void tcg_gen_abs_i64(TCGv_i64 ret, TCGv_i64 a) =20 void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_mov_i32(ret, TCGV_LOW(arg)); - } else { - tcg_gen_op2(INDEX_op_extrl_i64_i32, TCG_TYPE_I32, - tcgv_i32_arg(ret), tcgv_i64_arg(arg)); - } + tcg_gen_op2(INDEX_op_extrl_i64_i32, TCG_TYPE_I32, + tcgv_i32_arg(ret), tcgv_i64_arg(arg)); } =20 void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_mov_i32(ret, TCGV_HIGH(arg)); - } else { - tcg_gen_op2(INDEX_op_extrh_i64_i32, TCG_TYPE_I32, - tcgv_i32_arg(ret), tcgv_i64_arg(arg)); - } + tcg_gen_op2(INDEX_op_extrh_i64_i32, TCG_TYPE_I32, + tcgv_i32_arg(ret), tcgv_i64_arg(arg)); } =20 void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_mov_i32(TCGV_LOW(ret), arg); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - } else { - tcg_gen_op2(INDEX_op_extu_i32_i64, TCG_TYPE_I64, - tcgv_i64_arg(ret), tcgv_i32_arg(arg)); - } + tcg_gen_op2(INDEX_op_extu_i32_i64, TCG_TYPE_I64, + tcgv_i64_arg(ret), tcgv_i32_arg(arg)); } =20 void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_mov_i32(TCGV_LOW(ret), arg); - tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); - } else { - tcg_gen_op2(INDEX_op_ext_i32_i64, TCG_TYPE_I64, - tcgv_i64_arg(ret), tcgv_i32_arg(arg)); - } + tcg_gen_op2(INDEX_op_ext_i32_i64, TCG_TYPE_I64, + tcgv_i64_arg(ret), tcgv_i32_arg(arg)); } =20 void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high) { - TCGv_i64 tmp; + TCGv_i64 tmp =3D tcg_temp_ebb_new_i64(); =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_mov_i32(TCGV_LOW(dest), low); - tcg_gen_mov_i32(TCGV_HIGH(dest), high); - return; - } - - tmp =3D tcg_temp_ebb_new_i64(); /* These extensions are only needed for type correctness. We may be able to do better given target specific information. */ tcg_gen_extu_i32_i64(tmp, high); @@ -3070,13 +2569,8 @@ void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 = low, TCGv_i32 high) =20 void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_mov_i32(lo, TCGV_LOW(arg)); - tcg_gen_mov_i32(hi, TCGV_HIGH(arg)); - } else { - tcg_gen_extrl_i64_i32(lo, arg); - tcg_gen_extrh_i64_i32(hi, arg); - } + tcg_gen_extrl_i64_i32(lo, arg); + tcg_gen_extrh_i64_i32(hi, arg); } =20 void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg) --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768773977; cv=none; d=zohomail.com; s=zohoarc; b=i7s3kVbedt5VQajgLGOzLmy5U7U3Zh0t42kv4T+y0AYSGgGXT/KSPCB2ivNfNQ5Y8gEVifCBTIZyDx9zn1kUi4k7D+JQcTTCJF/Nf5Wk08GlsfEYzSVt38t6wR0kWNOvhv+U4c8ms+1rH4Sw1+uLVQneaSylzEEbAEl8JUFGdx0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768773977; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qmAp6PNa9duSslOM86Ejx4hWWn+4Ohddq0ga5kua76c=; b=i2AtGM2fWQseiIirllp1qmCFf7tciqoqAKw05PW3M9fTs+Bgsvhf0lgfkCf01p1tRFn+dI0ROG2M231El3ZHHSWj/jSc4k8iTPadsq7KPgqI98SgDxe5HNAC9uNeZlRWi2E/Pa0EyTZ34/wmySWQKRVrgrA8N6tdddAdaOoywO8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768773977975300.41182830287823; Sun, 18 Jan 2026 14:06:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhauB-0004zX-Ig; Sun, 18 Jan 2026 17:05:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhatp-0002rY-Td for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:34 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhatn-0000tV-Or for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:33 -0500 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-2a09757004cso33074655ad.3 for ; Sun, 18 Jan 2026 14:05:31 -0800 (PST) Received: from stoup.. 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Sun, 18 Jan 2026 14:05:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 29/54] tcg: Drop TCG_TARGET_REG_BITS tests in tcg-op-gvec.c Date: Mon, 19 Jan 2026 09:03:49 +1100 Message-ID: <20260118220414.8177-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768773980172158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.c | 49 +++++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 25 deletions(-) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 2cfc7e9409..bc323e2500 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -586,12 +586,11 @@ static void do_dup(unsigned vece, TCGv_ptr dbase, uin= t32_t dofs, } } =20 - /* Implement inline with a vector type, if possible. - * Prefer integer when 64-bit host and no variable dup. + /* + * Implement inline with a vector type, if possible; + * prefer_i64 with 64-bit variable dup. */ - type =3D choose_vector_type(NULL, vece, oprsz, - (TCG_TARGET_REG_BITS =3D=3D 64 && in_32 =3D= =3D NULL - && (in_64 =3D=3D NULL || vece =3D=3D MO_64)= )); + type =3D choose_vector_type(NULL, vece, oprsz, vece =3D=3D MO_64 && in= _64); if (type !=3D 0) { TCGv_vec t_vec =3D tcg_temp_new_vec(type); =20 @@ -612,11 +611,11 @@ static void do_dup(unsigned vece, TCGv_ptr dbase, uin= t32_t dofs, t_32 =3D NULL; =20 if (in_32) { - /* We are given a 32-bit variable input. For a 64-bit host, - use a 64-bit operation unless the 32-bit operation would - be simple enough. */ - if (TCG_TARGET_REG_BITS =3D=3D 64 - && (vece !=3D MO_32 || !check_size_impl(oprsz, 4))) { + /* + * We are given a 32-bit variable input. Use a 64-bit operati= on + * unless the 32-bit operation would be simple enough. + */ + if (vece !=3D MO_32 || !check_size_impl(oprsz, 4)) { t_64 =3D tcg_temp_ebb_new_i64(); tcg_gen_extu_i32_i64(t_64, in_32); tcg_gen_dup_i64(vece, t_64, t_64); @@ -629,14 +628,16 @@ static void do_dup(unsigned vece, TCGv_ptr dbase, uin= t32_t dofs, t_64 =3D tcg_temp_ebb_new_i64(); tcg_gen_dup_i64(vece, t_64, in_64); } else { - /* We are given a constant input. */ - /* For 64-bit hosts, use 64-bit constants for "simple" constan= ts - or when we'd need too many 32-bit stores, or when a 64-bit - constant is really required. */ + /* + * We are given a constant input. + * Use 64-bit constants for "simple" constants or when we'd + * need too many 32-bit stores, or when a 64-bit constant + * is really required. + */ if (vece =3D=3D MO_64 - || (TCG_TARGET_REG_BITS =3D=3D 64 - && (in_c =3D=3D 0 || in_c =3D=3D -1 - || !check_size_impl(oprsz, 4)))) { + || in_c =3D=3D 0 + || in_c =3D=3D -1 + || !check_size_impl(oprsz, 4)) { t_64 =3D tcg_constant_i64(in_c); } else { t_32 =3D tcg_constant_i32(in_c); @@ -3872,12 +3873,11 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, = uint32_t dofs, } =20 /* - * Implement inline with a vector type, if possible. - * Prefer integer when 64-bit host and 64-bit comparison. + * Implement inline with a vector type, if possible; + * prefer_i64 for a 64-bit comparison. */ hold_list =3D tcg_swap_vecop_list(cmp_list); - type =3D choose_vector_type(cmp_list, vece, oprsz, - TCG_TARGET_REG_BITS =3D=3D 64 && vece =3D=3D= MO_64); + type =3D choose_vector_type(cmp_list, vece, oprsz, vece =3D=3D MO_64); switch (type) { case TCG_TYPE_V256: /* Recall that ARM SVE allows vector sizes that are not a @@ -3992,11 +3992,10 @@ void tcg_gen_gvec_cmps(TCGCond cond, unsigned vece,= uint32_t dofs, } =20 /* - * Implement inline with a vector type, if possible. - * Prefer integer when 64-bit host and 64-bit comparison. + * Implement inline with a vector type, if possible; + * prefer_i64 for a 64-bit comparison. */ - type =3D choose_vector_type(cmp_list, vece, oprsz, - TCG_TARGET_REG_BITS =3D=3D 64 && vece =3D=3D= MO_64); + type =3D choose_vector_type(cmp_list, vece, oprsz, vece =3D=3D MO_64); if (type !=3D 0) { const TCGOpcode *hold_list =3D tcg_swap_vecop_list(cmp_list); TCGv_vec t_vec =3D tcg_temp_new_vec(type); --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774037; cv=none; d=zohomail.com; s=zohoarc; b=AocT8CV8V71uObDAPaoyrXJGDlTdeUmhqFifSIq1M3gfrezoCY3gKoKxm76QZzzgUUe1lfZULKtr8aMNSwm4+ICeX3gFVEdBmnsoSIGBCddsgcRbt0SUtvJL+jwKhdCZ6xUQCpTU8v8h0Pwsn0Ar37QPuaoWIuXB7qy6TnpQ4G0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768774037; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ecDzOzqQ/C38Xzf0BO7uae6DhF/wcxQYsp2ETvYgWSM=; b=EBiqT57CsBgvI0Ldef+5zlQ/lY+2lfqvr4lO2XbmyliLb8HEaI+w1NZ79MPbftCcf762ZjmBHl5uFjLGWwSD/yXwpLuGWAsgjNcG/JY6Irf/MdC/WUHt15FxgufX2wIoos6mM/2bqgyWbbaqHA9b1WYXUhC2sf8+ijk3jCzY0cw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768774037885185.82599110777926; Sun, 18 Jan 2026 14:07:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhau3-0004QT-O3; Sun, 18 Jan 2026 17:05:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhats-00036V-HE for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:36 -0500 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhatq-0000tt-Be for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:36 -0500 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-2a102494058so22840115ad.0 for ; Sun, 18 Jan 2026 14:05:33 -0800 (PST) Received: from stoup.. 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Sun, 18 Jan 2026 14:05:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 30/54] tcg: Drop TCG_TARGET_REG_BITS tests in tcg-op-ldst.c Date: Mon, 19 Jan 2026 09:03:50 +1100 Message-ID: <20260118220414.8177-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774038295158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg-op-ldst.c | 113 +++++++++++----------------------------------- 1 file changed, 27 insertions(+), 86 deletions(-) diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 7716c3ad7c..55bfbf3a20 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -106,24 +106,12 @@ static void gen_ldst2(TCGOpcode opc, TCGType type, TC= GTemp *vl, TCGTemp *vh, =20 static void gen_ld_i64(TCGv_i64 v, TCGTemp *addr, MemOpIdx oi) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - gen_ldst2(INDEX_op_qemu_ld2, TCG_TYPE_I64, - tcgv_i32_temp(TCGV_LOW(v)), tcgv_i32_temp(TCGV_HIGH(v)), - addr, oi); - } else { - gen_ldst1(INDEX_op_qemu_ld, TCG_TYPE_I64, tcgv_i64_temp(v), addr, = oi); - } + gen_ldst1(INDEX_op_qemu_ld, TCG_TYPE_I64, tcgv_i64_temp(v), addr, oi); } =20 static void gen_st_i64(TCGv_i64 v, TCGTemp *addr, MemOpIdx oi) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - gen_ldst2(INDEX_op_qemu_st2, TCG_TYPE_I64, - tcgv_i32_temp(TCGV_LOW(v)), tcgv_i32_temp(TCGV_HIGH(v)), - addr, oi); - } else { - gen_ldst1(INDEX_op_qemu_st, TCG_TYPE_I64, tcgv_i64_temp(v), addr, = oi); - } + gen_ldst1(INDEX_op_qemu_st, TCG_TYPE_I64, tcgv_i64_temp(v), addr, oi); } =20 static void tcg_gen_req_mo(TCGBar type) @@ -143,7 +131,7 @@ static TCGTemp *tci_extend_addr(TCGTemp *addr) * Compare to the extension performed by tcg_out_{ld,st}_helper_args * for native code generation. */ - if (TCG_TARGET_REG_BITS =3D=3D 64 && tcg_ctx->addr_type =3D=3D TCG_TYP= E_I32) { + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { TCGv_i64 temp =3D tcg_temp_ebb_new_i64(); tcg_gen_extu_i32_i64(temp, temp_tcgv_i32(addr)); return tcgv_i64_temp(temp); @@ -356,16 +344,6 @@ static void tcg_gen_qemu_ld_i64_int(TCGv_i64 val, TCGT= emp *addr, TCGv_i64 copy_addr; TCGTemp *addr_new; =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { - tcg_gen_qemu_ld_i32_int(TCGV_LOW(val), addr, idx, memop); - if (memop & MO_SIGN) { - tcg_gen_sari_i32(TCGV_HIGH(val), TCGV_LOW(val), 31); - } else { - tcg_gen_movi_i32(TCGV_HIGH(val), 0); - } - return; - } - tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); orig_memop =3D memop =3D tcg_canonicalize_memop(memop, 1, 0); orig_oi =3D oi =3D make_memop_idx(memop, idx); @@ -421,11 +399,6 @@ static void tcg_gen_qemu_st_i64_int(TCGv_i64 val, TCGT= emp *addr, MemOpIdx orig_oi, oi; TCGTemp *addr_new; =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { - tcg_gen_qemu_st_i32_int(TCGV_LOW(val), addr, idx, memop); - return; - } - tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop =3D tcg_canonicalize_memop(memop, 1, 1); orig_oi =3D oi =3D make_memop_idx(memop, idx); @@ -577,7 +550,7 @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCG= Temp *addr, orig_oi =3D make_memop_idx(memop, idx); =20 /* TODO: For now, force 32-bit hosts to use the helper. */ - if (TCG_TARGET_HAS_qemu_ldst_i128 && TCG_TARGET_REG_BITS =3D=3D 64) { + if (TCG_TARGET_HAS_qemu_ldst_i128) { TCGv_i64 lo, hi; bool need_bswap =3D false; MemOpIdx oi =3D orig_oi; @@ -691,7 +664,7 @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCG= Temp *addr, =20 /* TODO: For now, force 32-bit hosts to use the helper. */ =20 - if (TCG_TARGET_HAS_qemu_ldst_i128 && TCG_TARGET_REG_BITS =3D=3D 64) { + if (TCG_TARGET_HAS_qemu_ldst_i128) { TCGv_i64 lo, hi; MemOpIdx oi =3D orig_oi; bool need_bswap =3D false; @@ -950,17 +923,6 @@ static void tcg_gen_nonatomic_cmpxchg_i64_int(TCGv_i64= retv, TCGTemp *addr, { TCGv_i64 t1, t2; =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { - tcg_gen_nonatomic_cmpxchg_i32_int(TCGV_LOW(retv), addr, TCGV_LOW(c= mpv), - TCGV_LOW(newv), idx, memop); - if (memop & MO_SIGN) { - tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); - } else { - tcg_gen_movi_i32(TCGV_HIGH(retv), 0); - } - return; - } - t1 =3D tcg_temp_ebb_new_i64(); t2 =3D tcg_temp_ebb_new_i64(); =20 @@ -1019,17 +981,6 @@ static void tcg_gen_atomic_cmpxchg_i64_int(TCGv_i64 r= etv, TCGTemp *addr, * is removed. */ tcg_gen_movi_i64(retv, 0); - return; - } - - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_atomic_cmpxchg_i32_int(TCGV_LOW(retv), addr, TCGV_LOW(cmpv= ), - TCGV_LOW(newv), idx, memop); - if (memop & MO_SIGN) { - tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); - } else { - tcg_gen_movi_i32(TCGV_HIGH(retv), 0); - } } else { TCGv_i32 c32 =3D tcg_temp_ebb_new_i32(); TCGv_i32 n32 =3D tcg_temp_ebb_new_i32(); @@ -1064,43 +1015,33 @@ static void tcg_gen_nonatomic_cmpxchg_i128_int(TCGv= _i128 retv, TCGTemp *addr, TCGv_i128 cmpv, TCGv_i128 n= ewv, TCGArg idx, MemOp memop) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - /* Inline expansion below is simply too large for 32-bit hosts. */ - MemOpIdx oi =3D make_memop_idx(memop, idx); - TCGv_i64 a64 =3D maybe_extend_addr64(addr); + TCGv_i128 oldv =3D tcg_temp_ebb_new_i128(); + TCGv_i128 tmpv =3D tcg_temp_ebb_new_i128(); + TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); + TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); + TCGv_i64 z =3D tcg_constant_i64(0); =20 - gen_helper_nonatomic_cmpxchgo(retv, tcg_env, a64, cmpv, newv, - tcg_constant_i32(oi)); - maybe_free_addr64(a64); - } else { - TCGv_i128 oldv =3D tcg_temp_ebb_new_i128(); - TCGv_i128 tmpv =3D tcg_temp_ebb_new_i128(); - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 z =3D tcg_constant_i64(0); + tcg_gen_qemu_ld_i128_int(oldv, addr, idx, memop); =20 - tcg_gen_qemu_ld_i128_int(oldv, addr, idx, memop); + /* Compare i128 */ + tcg_gen_xor_i64(t0, TCGV128_LOW(oldv), TCGV128_LOW(cmpv)); + tcg_gen_xor_i64(t1, TCGV128_HIGH(oldv), TCGV128_HIGH(cmpv)); + tcg_gen_or_i64(t0, t0, t1); =20 - /* Compare i128 */ - tcg_gen_xor_i64(t0, TCGV128_LOW(oldv), TCGV128_LOW(cmpv)); - tcg_gen_xor_i64(t1, TCGV128_HIGH(oldv), TCGV128_HIGH(cmpv)); - tcg_gen_or_i64(t0, t0, t1); + /* tmpv =3D equal ? newv : oldv */ + tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_LOW(tmpv), t0, z, + TCGV128_LOW(newv), TCGV128_LOW(oldv)); + tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_HIGH(tmpv), t0, z, + TCGV128_HIGH(newv), TCGV128_HIGH(oldv)); =20 - /* tmpv =3D equal ? newv : oldv */ - tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_LOW(tmpv), t0, z, - TCGV128_LOW(newv), TCGV128_LOW(oldv)); - tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_HIGH(tmpv), t0, z, - TCGV128_HIGH(newv), TCGV128_HIGH(oldv)); + /* Unconditional writeback. */ + tcg_gen_qemu_st_i128_int(tmpv, addr, idx, memop); + tcg_gen_mov_i128(retv, oldv); =20 - /* Unconditional writeback. */ - tcg_gen_qemu_st_i128_int(tmpv, addr, idx, memop); - tcg_gen_mov_i128(retv, oldv); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i128(tmpv); - tcg_temp_free_i128(oldv); - } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i128(tmpv); + tcg_temp_free_i128(oldv); } =20 void tcg_gen_nonatomic_cmpxchg_i128_chk(TCGv_i128 retv, TCGTemp *addr, --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Sun, 18 Jan 2026 14:05:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 31/54] tcg: Drop TCG_TARGET_REG_BITS tests in tcg.c Date: Mon, 19 Jan 2026 09:03:51 +1100 Message-ID: <20260118220414.8177-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774094589158501 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg.c | 216 +++++++++--------------------------------------------- 1 file changed, 36 insertions(+), 180 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 2b3bcbe750..e7bf4dad4e 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -215,10 +215,8 @@ static void * const qemu_ld_helpers[MO_SSIZE + 1] __at= tribute__((unused)) =3D { [MO_SW] =3D helper_ldsw_mmu, [MO_UL] =3D helper_ldul_mmu, [MO_UQ] =3D helper_ldq_mmu, -#if TCG_TARGET_REG_BITS =3D=3D 64 [MO_SL] =3D helper_ldsl_mmu, [MO_128] =3D helper_ld16_mmu, -#endif }; =20 static void * const qemu_st_helpers[MO_SIZE + 1] __attribute__((unused)) = =3D { @@ -226,9 +224,7 @@ static void * const qemu_st_helpers[MO_SIZE + 1] __attr= ibute__((unused)) =3D { [MO_16] =3D helper_stw_mmu, [MO_32] =3D helper_stl_mmu, [MO_64] =3D helper_stq_mmu, -#if TCG_TARGET_REG_BITS =3D=3D 64 [MO_128] =3D helper_st16_mmu, -#endif }; =20 typedef struct { @@ -504,7 +500,6 @@ static void tcg_out_movext(TCGContext *s, TCGType dst_t= ype, TCGReg dst, } break; case MO_UQ: - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); if (dst_type =3D=3D TCG_TYPE_I32) { tcg_out_extrl_i64_i32(s, dst, src); } else { @@ -1113,7 +1108,6 @@ QEMU_BUILD_BUG_ON((int)(offsetof(CPUNegativeOffsetSta= te, tlb.f[0]) - < MIN_TLB_MASK_TABLE_OFS); #endif =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 /* * We require these functions for slow-path function calls. * Adapt them generically for opcode output. @@ -1148,7 +1142,6 @@ static const TCGOutOpUnary outop_extrl_i64_i32 =3D { .base.static_constraint =3D C_O1_I1(r, r), .out_rr =3D TCG_TARGET_HAS_extr_i64_i32 ? tgen_extrl_i64_i32 : NULL, }; -#endif =20 static const TCGOutOp outop_goto_ptr =3D { .static_constraint =3D C_O0_I1(r), @@ -1360,11 +1353,7 @@ void tcg_pool_reset(TCGContext *s) * the helpers, with the end result that it's easier to build manually. */ =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 -# define dh_typecode_ttl dh_typecode_i32 -#else -# define dh_typecode_ttl dh_typecode_i64 -#endif +#define dh_typecode_ttl dh_typecode_i64 =20 static TCGHelperInfo info_helper_ld32_mmu =3D { .flags =3D TCG_CALL_NO_WG, @@ -1615,17 +1604,12 @@ static void init_call_layout(TCGHelperInfo *info) break; case dh_typecode_i32: case dh_typecode_s32: + case dh_typecode_i64: + case dh_typecode_s64: case dh_typecode_ptr: info->nr_out =3D 1; info->out_kind =3D TCG_CALL_RET_NORMAL; break; - case dh_typecode_i64: - case dh_typecode_s64: - info->nr_out =3D 64 / TCG_TARGET_REG_BITS; - info->out_kind =3D TCG_CALL_RET_NORMAL; - /* Query the last register now to trigger any assert early. */ - tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); - break; case dh_typecode_i128: info->nr_out =3D 128 / TCG_TARGET_REG_BITS; info->out_kind =3D TCG_TARGET_CALL_RET_I128; @@ -1705,11 +1689,7 @@ static void init_call_layout(TCGHelperInfo *info) layout_arg_even(&cum); /* fall through */ case TCG_CALL_ARG_NORMAL: - if (TCG_TARGET_REG_BITS =3D=3D 32) { - layout_arg_normal_n(&cum, info, 2); - } else { - layout_arg_1(&cum, info, TCG_CALL_ARG_NORMAL); - } + layout_arg_1(&cum, info, TCG_CALL_ARG_NORMAL); break; default: qemu_build_not_reached(); @@ -2002,11 +1982,8 @@ static TCGTemp *tcg_global_alloc(TCGContext *s) static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, TCGReg reg, const char *name) { - TCGTemp *ts; + TCGTemp *ts =3D tcg_global_alloc(s); =20 - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); - - ts =3D tcg_global_alloc(s); ts->base_type =3D type; ts->type =3D type; ts->kind =3D TEMP_FIXED; @@ -2040,48 +2017,20 @@ static TCGTemp *tcg_global_mem_new_internal(TCGv_pt= r base, intptr_t offset, /* We do not support double-indirect registers. */ tcg_debug_assert(!base_ts->indirect_reg); base_ts->indirect_base =3D 1; - s->nb_indirects +=3D (TCG_TARGET_REG_BITS =3D=3D 32 && type =3D=3D= TCG_TYPE_I64 - ? 2 : 1); + s->nb_indirects +=3D 1; indirect_reg =3D 1; break; default: g_assert_not_reached(); } =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 && type =3D=3D TCG_TYPE_I64) { - TCGTemp *ts2 =3D tcg_global_alloc(s); - char buf[64]; - - ts->base_type =3D TCG_TYPE_I64; - ts->type =3D TCG_TYPE_I32; - ts->indirect_reg =3D indirect_reg; - ts->mem_allocated =3D 1; - ts->mem_base =3D base_ts; - ts->mem_offset =3D offset; - pstrcpy(buf, sizeof(buf), name); - pstrcat(buf, sizeof(buf), "_0"); - ts->name =3D strdup(buf); - - tcg_debug_assert(ts2 =3D=3D ts + 1); - ts2->base_type =3D TCG_TYPE_I64; - ts2->type =3D TCG_TYPE_I32; - ts2->indirect_reg =3D indirect_reg; - ts2->mem_allocated =3D 1; - ts2->mem_base =3D base_ts; - ts2->mem_offset =3D offset + 4; - ts2->temp_subindex =3D 1; - pstrcpy(buf, sizeof(buf), name); - pstrcat(buf, sizeof(buf), "_1"); - ts2->name =3D strdup(buf); - } else { - ts->base_type =3D type; - ts->type =3D type; - ts->indirect_reg =3D indirect_reg; - ts->mem_allocated =3D 1; - ts->mem_base =3D base_ts; - ts->mem_offset =3D offset; - ts->name =3D name; - } + ts->base_type =3D type; + ts->type =3D type; + ts->indirect_reg =3D indirect_reg; + ts->mem_allocated =3D 1; + ts->mem_base =3D base_ts; + ts->mem_offset =3D offset; + ts->name =3D name; return ts; } =20 @@ -2128,14 +2077,12 @@ TCGTemp *tcg_temp_new_internal(TCGType type, TCGTem= pKind kind) =20 switch (type) { case TCG_TYPE_I32: + case TCG_TYPE_I64: case TCG_TYPE_V64: case TCG_TYPE_V128: case TCG_TYPE_V256: n =3D 1; break; - case TCG_TYPE_I64: - n =3D 64 / TCG_TARGET_REG_BITS; - break; case TCG_TYPE_I128: n =3D 128 / TCG_TARGET_REG_BITS; break; @@ -2300,43 +2247,13 @@ TCGTemp *tcg_constant_internal(TCGType type, int64_= t val) =20 ts =3D g_hash_table_lookup(h, &val); if (ts =3D=3D NULL) { - int64_t *val_ptr; - ts =3D tcg_temp_alloc(s); - - if (TCG_TARGET_REG_BITS =3D=3D 32 && type =3D=3D TCG_TYPE_I64) { - TCGTemp *ts2 =3D tcg_temp_alloc(s); - - tcg_debug_assert(ts2 =3D=3D ts + 1); - - ts->base_type =3D TCG_TYPE_I64; - ts->type =3D TCG_TYPE_I32; - ts->kind =3D TEMP_CONST; - ts->temp_allocated =3D 1; - - ts2->base_type =3D TCG_TYPE_I64; - ts2->type =3D TCG_TYPE_I32; - ts2->kind =3D TEMP_CONST; - ts2->temp_allocated =3D 1; - ts2->temp_subindex =3D 1; - - /* - * Retain the full value of the 64-bit constant in the low - * part, so that the hash table works. Actual uses will - * truncate the value to the low part. - */ - ts[HOST_BIG_ENDIAN].val =3D val; - ts[!HOST_BIG_ENDIAN].val =3D val >> 32; - val_ptr =3D &ts[HOST_BIG_ENDIAN].val; - } else { - ts->base_type =3D type; - ts->type =3D type; - ts->kind =3D TEMP_CONST; - ts->temp_allocated =3D 1; - ts->val =3D val; - val_ptr =3D &ts->val; - } - g_hash_table_insert(h, val_ptr, ts); + ts->base_type =3D type; + ts->type =3D type; + ts->kind =3D TEMP_CONST; + ts->temp_allocated =3D 1; + ts->val =3D val; + g_hash_table_insert(h, &ts->val, ts); } =20 return ts; @@ -2405,10 +2322,8 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, un= signed flags) =20 switch (type) { case TCG_TYPE_I32: - has_type =3D true; - break; case TCG_TYPE_I64: - has_type =3D TCG_TARGET_REG_BITS =3D=3D 64; + has_type =3D true; break; case TCG_TYPE_V64: has_type =3D TCG_TARGET_HAS_v64; @@ -2443,10 +2358,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, un= signed flags) =20 case INDEX_op_qemu_ld2: case INDEX_op_qemu_st2: - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_debug_assert(type =3D=3D TCG_TYPE_I64); - return true; - } tcg_debug_assert(type =3D=3D TCG_TYPE_I128); goto do_lookup; =20 @@ -2479,7 +2390,7 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, uns= igned flags) case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: - return TCG_TARGET_REG_BITS =3D=3D 64; + return true; =20 case INDEX_op_mov_vec: case INDEX_op_dup_vec: @@ -2792,11 +2703,9 @@ static char *tcg_get_arg_str_ptr(TCGContext *s, char= *buf, int buf_size, case TCG_TYPE_I32: snprintf(buf, buf_size, "$0x%x", (int32_t)ts->val); break; -#if TCG_TARGET_REG_BITS > 32 case TCG_TYPE_I64: snprintf(buf, buf_size, "$0x%" PRIx64, ts->val); break; -#endif case TCG_TYPE_V64: case TCG_TYPE_V128: case TCG_TYPE_V256: @@ -5654,8 +5563,6 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: - assert(TCG_TARGET_REG_BITS =3D=3D 64); - /* fall through */ case INDEX_op_ctpop: case INDEX_op_neg: case INDEX_op_not: @@ -6179,9 +6086,7 @@ static int tcg_out_helper_stk_ofs(TCGType type, unsig= ned slot) * Each stack slot is TCG_TARGET_LONG_BITS. If the host does not * require extension to uint64_t, adjust the address for uint32_t. */ - if (HOST_BIG_ENDIAN && - TCG_TARGET_REG_BITS =3D=3D 64 && - type =3D=3D TCG_TYPE_I32) { + if (HOST_BIG_ENDIAN && type =3D=3D TCG_TYPE_I32) { ofs +=3D 4; } return ofs; @@ -6390,13 +6295,8 @@ static unsigned tcg_out_helper_add_mov(TCGMovExtend = *mov, return 1; } =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - assert(dst_type =3D=3D TCG_TYPE_I64); - reg_mo =3D MO_32; - } else { - assert(dst_type =3D=3D TCG_TYPE_I128); - reg_mo =3D MO_64; - } + assert(dst_type =3D=3D TCG_TYPE_I128); + reg_mo =3D MO_64; =20 mov[0].dst =3D loc[HOST_BIG_ENDIAN].arg_slot; mov[0].src =3D lo; @@ -6442,26 +6342,10 @@ static void tcg_out_ld_helper_args(TCGContext *s, c= onst TCGLabelQemuLdst *ldst, next_arg =3D 1; =20 loc =3D &info->in[next_arg]; - if (TCG_TARGET_REG_BITS =3D=3D 32 && s->addr_type =3D=3D TCG_TYPE_I32)= { - /* - * 32-bit host with 32-bit guest: zero-extend the guest address - * to 64-bits for the helper by storing the low part, then - * load a zero for the high part. - */ - tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN, - TCG_TYPE_I32, TCG_TYPE_I32, - ldst->addr_reg, -1); - tcg_out_helper_load_slots(s, 1, mov, parm); - - tcg_out_helper_load_imm(s, loc[!HOST_BIG_ENDIAN].arg_slot, - TCG_TYPE_I32, 0, parm); - next_arg +=3D 2; - } else { - nmov =3D tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_ty= pe, - ldst->addr_reg, -1); - tcg_out_helper_load_slots(s, nmov, mov, parm); - next_arg +=3D nmov; - } + nmov =3D tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type, + ldst->addr_reg, -1); + tcg_out_helper_load_slots(s, nmov, mov, parm); + next_arg +=3D nmov; =20 switch (info->out_kind) { case TCG_CALL_RET_NORMAL: @@ -6503,13 +6387,8 @@ static void tcg_out_ld_helper_ret(TCGContext *s, con= st TCGLabelQemuLdst *ldst, int ofs_slot0; =20 switch (ldst->type) { - case TCG_TYPE_I64: - if (TCG_TARGET_REG_BITS =3D=3D 32) { - break; - } - /* fall through */ - case TCG_TYPE_I32: + case TCG_TYPE_I64: mov[0].dst =3D ldst->datalo_reg; mov[0].src =3D tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, 0); mov[0].dst_type =3D ldst->type; @@ -6526,7 +6405,7 @@ static void tcg_out_ld_helper_ret(TCGContext *s, cons= t TCGLabelQemuLdst *ldst, * helper functions. */ if (load_sign || !(mop & MO_SIGN)) { - if (TCG_TARGET_REG_BITS =3D=3D 32 || ldst->type =3D=3D TCG_TYP= E_I32) { + if (ldst->type =3D=3D TCG_TYPE_I32) { mov[0].src_ext =3D MO_32; } else { mov[0].src_ext =3D MO_64; @@ -6538,7 +6417,6 @@ static void tcg_out_ld_helper_ret(TCGContext *s, cons= t TCGLabelQemuLdst *ldst, return; =20 case TCG_TYPE_I128: - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); ofs_slot0 =3D TCG_TARGET_CALL_STACK_OFFSET; switch (TCG_TARGET_CALL_RET_I128) { case TCG_CALL_RET_NORMAL: @@ -6568,14 +6446,14 @@ static void tcg_out_ld_helper_ret(TCGContext *s, co= nst TCGLabelQemuLdst *ldst, tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, HOST_BIG_ENDIAN); mov[0].dst_type =3D TCG_TYPE_REG; mov[0].src_type =3D TCG_TYPE_REG; - mov[0].src_ext =3D TCG_TARGET_REG_BITS =3D=3D 32 ? MO_32 : MO_64; + mov[0].src_ext =3D MO_64; =20 mov[1].dst =3D ldst->datahi_reg; mov[1].src =3D tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, !HOST_BIG_ENDIAN); mov[1].dst_type =3D TCG_TYPE_REG; mov[1].src_type =3D TCG_TYPE_REG; - mov[1].src_ext =3D TCG_TARGET_REG_BITS =3D=3D 32 ? MO_32 : MO_64; + mov[1].src_ext =3D MO_64; =20 tcg_out_movext2(s, mov, mov + 1, parm->ntmp ? parm->tmp[0] : -1); } @@ -6616,24 +6494,10 @@ static void tcg_out_st_helper_args(TCGContext *s, c= onst TCGLabelQemuLdst *ldst, /* Handle addr argument. */ loc =3D &info->in[next_arg]; tcg_debug_assert(s->addr_type <=3D TCG_TYPE_REG); - if (TCG_TARGET_REG_BITS =3D=3D 32) { - /* - * 32-bit host (and thus 32-bit guest): zero-extend the guest addr= ess - * to 64-bits for the helper by storing the low part. Later, - * after we have processed the register inputs, we will load a - * zero for the high part. - */ - tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN, - TCG_TYPE_I32, TCG_TYPE_I32, + n =3D tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type, ldst->addr_reg, -1); - next_arg +=3D 2; - nmov +=3D 1; - } else { - n =3D tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type, - ldst->addr_reg, -1); - next_arg +=3D n; - nmov +=3D n; - } + next_arg +=3D n; + nmov +=3D n; =20 /* Handle data argument. */ loc =3D &info->in[next_arg]; @@ -6649,7 +6513,6 @@ static void tcg_out_st_helper_args(TCGContext *s, con= st TCGLabelQemuLdst *ldst, break; =20 case TCG_CALL_ARG_BY_REF: - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_debug_assert(data_type =3D=3D TCG_TYPE_I128); tcg_out_st(s, TCG_TYPE_I64, HOST_BIG_ENDIAN ? ldst->datahi_reg : ldst->datalo_reg, @@ -6678,12 +6541,6 @@ static void tcg_out_st_helper_args(TCGContext *s, co= nst TCGLabelQemuLdst *ldst, g_assert_not_reached(); } =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - /* Zero extend the address by loading a zero for the high part. */ - loc =3D &info->in[1 + !HOST_BIG_ENDIAN]; - tcg_out_helper_load_imm(s, loc->arg_slot, TCG_TYPE_I32, 0, parm); - } - tcg_out_helper_load_common_args(s, ldst, parm, info, next_arg); } =20 @@ -6791,7 +6648,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) =20 switch (opc) { case INDEX_op_extrl_i64_i32: - assert(TCG_TARGET_REG_BITS =3D=3D 64); /* * If TCG_TYPE_I32 is represented in some canonical form, * e.g. zero or sign-extended, then emit as a unary op. --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768773979; cv=none; d=zohomail.com; s=zohoarc; b=EAkpw9rJRRS8F2OA80srabrvMr8IbqbeQAyXHWMmuD1xQsQvYwMlr+LwxeE17p2ofx1+XPbMCtXG8l4yBUckjfe4vq1L+g6iDMN1yR1epno+80ZGddERubWd8K5MUrhWQIw96vsn1P3qKxLgAgQH2BRGcIkOP9osrJtjKvnRmg4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768773979; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Jt6epgzk+hjWVFj/7ojbUiaxuIhW/JGBZIUcf+FDUAw=; b=PxUgAY0oqbebQCZugvRvKR38jwbYBCc26b58QNZixZrALKEK2rMi2KK572rhwUW+SutRgTwguezb5tVy1v849zPZUxQxC4yl++J9CEC6iJM2vdlgB2Xz10kuTbygB+jY1cQgMIAr4+OvNOVitncn3mWBLhsiQefd04eMLvUWq+I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768773979312739.1809051116174; Sun, 18 Jan 2026 14:06:19 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhauJ-0005JN-DZ; Sun, 18 Jan 2026 17:06:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhatw-0003bI-0G for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:40 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhatu-0000uv-9l for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:39 -0500 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-2a0a95200e8so23590635ad.0 for ; Sun, 18 Jan 2026 14:05:37 -0800 (PST) Received: from stoup.. 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Sun, 18 Jan 2026 14:05:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 32/54] tcg: Drop TCG_TARGET_REG_BITS tests in tcg-internal.h Date: Mon, 19 Jan 2026 09:03:52 +1100 Message-ID: <20260118220414.8177-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768773980081158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 21 ++------------------- 1 file changed, 2 insertions(+), 19 deletions(-) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index d6a12afe06..2cbfb5d5ca 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -54,31 +54,14 @@ static inline unsigned tcg_call_flags(TCGOp *op) return tcg_call_info(op)->flags; } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 -static inline TCGv_i32 TCGV_LOW(TCGv_i64 t) -{ - return temp_tcgv_i32(tcgv_i64_temp(t) + HOST_BIG_ENDIAN); -} -static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) -{ - return temp_tcgv_i32(tcgv_i64_temp(t) + !HOST_BIG_ENDIAN); -} -#else -TCGv_i32 TCGV_LOW(TCGv_i64) QEMU_ERROR("32-bit code path is reachable"); -TCGv_i32 TCGV_HIGH(TCGv_i64) QEMU_ERROR("32-bit code path is reachable"); -#endif - static inline TCGv_i64 TCGV128_LOW(TCGv_i128 t) { - /* For 32-bit, offset by 2, which may then have TCGV_{LOW,HIGH} applie= d. */ - int o =3D HOST_BIG_ENDIAN ? 64 / TCG_TARGET_REG_BITS : 0; - return temp_tcgv_i64(tcgv_i128_temp(t) + o); + return temp_tcgv_i64(tcgv_i128_temp(t) + HOST_BIG_ENDIAN); } =20 static inline TCGv_i64 TCGV128_HIGH(TCGv_i128 t) { - int o =3D HOST_BIG_ENDIAN ? 0 : 64 / TCG_TARGET_REG_BITS; - return temp_tcgv_i64(tcgv_i128_temp(t) + o); + return temp_tcgv_i64(tcgv_i128_temp(t) + !HOST_BIG_ENDIAN); } =20 bool tcg_target_has_memory_bswap(MemOp memop); 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Sun, 18 Jan 2026 14:05:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 33/54] tcg: Drop TCG_TARGET_REG_BITS test in tcg-has.h Date: Mon, 19 Jan 2026 09:03:53 +1100 Message-ID: <20260118220414.8177-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774050377158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg-has.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/tcg/tcg-has.h b/tcg/tcg-has.h index 2fc0e50d20..27771dc7f0 100644 --- a/tcg/tcg-has.h +++ b/tcg/tcg-has.h @@ -9,11 +9,6 @@ =20 #include "tcg-target-has.h" =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 -/* Turn some undef macros into false macros. */ -#define TCG_TARGET_HAS_extr_i64_i32 0 -#endif - #if !defined(TCG_TARGET_HAS_v64) \ && !defined(TCG_TARGET_HAS_v128) \ && !defined(TCG_TARGET_HAS_v256) --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Sun, 18 Jan 2026 14:05:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 34/54] include/tcg: Drop TCG_TARGET_REG_BITS tests Date: Mon, 19 Jan 2026 09:03:54 +1100 Message-ID: <20260118220414.8177-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774004189158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 9 +++------ include/tcg/tcg-opc.h | 5 +---- include/tcg/tcg.h | 27 ++------------------------- 3 files changed, 6 insertions(+), 35 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 232733cb71..ee379994e7 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -31,8 +31,7 @@ #if TARGET_INSN_START_EXTRA_WORDS =3D=3D 0 static inline void tcg_gen_insn_start(target_ulong pc) { - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, - INSN_START_WORDS * 64 / TCG_TARGET_REG_BITS); + TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS); tcg_set_insn_start_param(op, 0, pc); tcg_set_insn_start_param(op, 1, 0); tcg_set_insn_start_param(op, 2, 0); @@ -40,8 +39,7 @@ static inline void tcg_gen_insn_start(target_ulong pc) #elif TARGET_INSN_START_EXTRA_WORDS =3D=3D 1 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) { - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, - INSN_START_WORDS * 64 / TCG_TARGET_REG_BITS); + TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS); tcg_set_insn_start_param(op, 0, pc); tcg_set_insn_start_param(op, 1, a1); tcg_set_insn_start_param(op, 2, 0); @@ -50,8 +48,7 @@ static inline void tcg_gen_insn_start(target_ulong pc, ta= rget_ulong a1) static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, target_ulong a2) { - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, - INSN_START_WORDS * 64 / TCG_TARGET_REG_BITS); + TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS); tcg_set_insn_start_param(op, 0, pc); tcg_set_insn_start_param(op, 1, a1); tcg_set_insn_start_param(op, 2, a2); diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 28806057c5..61f1c28858 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -109,9 +109,7 @@ DEF(extu_i32_i64, 1, 1, 0, 0) DEF(extrl_i64_i32, 1, 1, 0, 0) DEF(extrh_i64_i32, 1, 1, 0, 0) =20 -#define DATA64_ARGS (TCG_TARGET_REG_BITS =3D=3D 64 ? 1 : 2) - -DEF(insn_start, 0, 0, DATA64_ARGS * INSN_START_WORDS, TCG_OPF_NOT_PRESENT) +DEF(insn_start, 0, 0, INSN_START_WORDS, TCG_OPF_NOT_PRESENT) =20 DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END | TCG_OPF_NOT_PRESE= NT) DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END | TCG_OPF_NOT_PRESE= NT) @@ -184,5 +182,4 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) =20 #include "tcg-target-opc.h.inc" =20 -#undef DATA64_ARGS #undef DEF diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 067150c542..60942ce05c 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -43,19 +43,10 @@ #define CPU_TEMP_BUF_NLONGS 128 #define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 -typedef int32_t tcg_target_long; -typedef uint32_t tcg_target_ulong; -#define TCG_PRIlx PRIx32 -#define TCG_PRIld PRId32 -#elif TCG_TARGET_REG_BITS =3D=3D 64 typedef int64_t tcg_target_long; typedef uint64_t tcg_target_ulong; #define TCG_PRIlx PRIx64 #define TCG_PRIld PRId64 -#else -#error unsupported -#endif =20 #if TCG_TARGET_NB_REGS <=3D 32 typedef uint32_t TCGRegSet; @@ -147,11 +138,7 @@ typedef enum TCGType { #define TCG_TYPE_COUNT (TCG_TYPE_V256 + 1) =20 /* An alias for the size of the host register. */ -#if TCG_TARGET_REG_BITS =3D=3D 32 - TCG_TYPE_REG =3D TCG_TYPE_I32, -#else TCG_TYPE_REG =3D TCG_TYPE_I64, -#endif =20 /* An alias for the size of the native pointer. */ #if UINTPTR_MAX =3D=3D UINT32_MAX @@ -605,23 +592,13 @@ static inline void tcg_set_insn_param(TCGOp *op, unsi= gned arg, TCGArg v) static inline uint64_t tcg_get_insn_start_param(TCGOp *op, unsigned arg) { tcg_debug_assert(arg < INSN_START_WORDS); - if (TCG_TARGET_REG_BITS =3D=3D 64) { - return tcg_get_insn_param(op, arg); - } else { - return deposit64(tcg_get_insn_param(op, arg * 2), 32, 32, - tcg_get_insn_param(op, arg * 2 + 1)); - } + return tcg_get_insn_param(op, arg); } =20 static inline void tcg_set_insn_start_param(TCGOp *op, unsigned arg, uint6= 4_t v) { tcg_debug_assert(arg < INSN_START_WORDS); - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_set_insn_param(op, arg, v); - } else { - tcg_set_insn_param(op, arg * 2, v); - tcg_set_insn_param(op, arg * 2 + 1, v >> 32); - } + tcg_set_insn_param(op, arg, v); } =20 /* The last op that was emitted. */ --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774081; cv=none; d=zohomail.com; s=zohoarc; b=dNxZ9o1p6Ty+g/FGSeLe9ModE8A3i8IPkKx/hSGc9FPKgKRnWPxqAo9HMx/7YZNFw6qQWK+Gr5DYjxYyD3LF8Wjxw7rG0qnlOSTohVOlG+0r8djG5gXS9qdznF3mizMxPs+RV01qtPUqkWmn/9nRiQryvM7cN+/Jd+28DvqSdbU= ARC-Message-Signature: i=1; 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([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7193dbb74sm74402865ad.56.2026.01.18.14.05.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:05:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768773944; x=1769378744; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pUs/qizOln6k9oFq1nxTBHzlXvp7JuDaMx2406hQaG0=; b=lsU9WIb5sc44V97+Nf/b0BZlP/2VKa33FL4nUvVi7iLQfdEPACOBzOXbfPyzprRJyj miGDUX6O23J5r6nS4CYhOiVRJa9Xwdo6/7U7K5UT7DG5gk1iOcpJe9CN1NwAyavuZ0LR 8Xqe87teoOYfcVgMkJrP1ANYkxQ53ljxDvrRGWAgibi2gxpbrhGR3bx4ofZ5i4UV/1S0 JgFhyNfsXsDothshaC1tAFo7YBriivu+qy4rqzmyV6UppWQVpe2X8w0X41eZLGG0FyXh MwPX5I7aiS8z3DKCDK5TeSS39eCh3WptS72KyHWh7wEemRWtbqZaWmO7fkBH7PbeiFV3 96aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768773944; x=1769378744; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=pUs/qizOln6k9oFq1nxTBHzlXvp7JuDaMx2406hQaG0=; b=r4W0SudGCf+XARwIAn6uHyWcHUxe7gRrSRBa6+uTQh9YoxwYMtoOh1EaFExIrfuKf3 l5nlWLL5vBSvYFXOCgaFBeaCtLqrGGkaw+Jxt8VbBKO5etR3+7yZJ2hH2rqZPXCuqIPw WjdUzUHMbL4Z0yyB5bwbvRUgOjquUnWVCoPjYylLiRPE5npJPz9644r040BzjbxjDsUw bHdsk5ir0mIW8czOyViIia90gQm6PF99bcz+SnE8rq8iF7vSl82bZ7ssGoIQ8hzQ5DWy 4WB8t8jyEj603Zhogf6hTKzf5n8mMeBaVDaVc7Yuil41bgI1nqzCXB9EngB1frdpHEQd CwRA== X-Gm-Message-State: AOJu0YyJJ3fWi+v5PjtCmgXcjo/jb2wmaoH4WLXzMcfuHaZgotbdw636 l+iKdfXtNYKEE9tciMHVMC2NvrKth8x3Tgw1ZKWXXdw7Whc4xZ12WA2uHGEYtZlqDN2F7iER+BR /Xov6gY23gA== X-Gm-Gg: AY/fxX7Scv6yg6fJld+4tuPOxXrQo510R8LjdpThXpX8ckteZMlChYzffqk8bF3OdMW aVnZMWHRU7K9ZxIlSrcd3KLjANVLjyHh4gUBTgKZpW+KUqN96SUbASMv9f/Rmr2ZKw+H1xe20Mj RLlE9pVMN3uUsLmc2VSVRydYGlCjhZhkliiUFEjhWtUa3m7kuyjnmfdzxzmr/I7Nj7VBcmIsg9m zU1iOd33HXmDbXS9c6DhxuER8hPFncQZd315g0Siyfu7AJIQOJhC/0rI9WVnfTbuPxi0oYOtKYk fNQFMZ5GSQEFfneuarEk5gvaJnoaw3UAcqJZnolQwCmr28fPkTqw+uOB0ZozXrqciP8iloT+kBm Hmk8EKmbPTk8eZXTLzsBmK3RVNS+TA8yPDiVoUvkOjRnda+q3/CWRowglgCJsYInMAedmoMN7Zn 5q4Gl4g6GThoLYPTnM+A== X-Received: by 2002:a17:902:d2c9:b0:2a0:8be7:e3d0 with SMTP id d9443c01a7336-2a718859fe1mr82746925ad.10.1768773943647; Sun, 18 Jan 2026 14:05:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Thomas Huth , Pierrick Bouvier Subject: [PULL 35/54] target/i386/tcg: Drop TCG_TARGET_REG_BITS test Date: Mon, 19 Jan 2026 09:03:55 +1100 Message-ID: <20260118220414.8177-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774082414158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Thomas Huth Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/i386/tcg/emit.c.inc | 37 +++++++++---------------------------- 1 file changed, 9 insertions(+), 28 deletions(-) diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 41bf047b8d..639a1eb638 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -2094,34 +2094,15 @@ static void gen_IMUL3(DisasContext *s, X86DecodedIn= sn *decode) =20 case MO_32: #ifdef TARGET_X86_64 - if (TCG_TARGET_REG_BITS =3D=3D 64) { - /* - * This produces fewer TCG ops, and better code if flags are n= eeded, - * but it requires a 64-bit multiply even if they are not. Us= e it - * only if the target has 64-bits registers. - * - * s->T0 is already sign-extended. - */ - tcg_gen_ext32s_tl(s->T1, s->T1); - tcg_gen_mul_tl(s->T0, s->T0, s->T1); - /* Compare the full result to the extension of the truncated r= esult. */ - tcg_gen_ext32s_tl(s->T1, s->T0); - cc_src_rhs =3D s->T0; - } else { - /* Variant that only needs a 32-bit widening multiply. */ - TCGv_i32 hi =3D tcg_temp_new_i32(); - TCGv_i32 lo =3D tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(lo, s->T0); - tcg_gen_trunc_tl_i32(hi, s->T1); - tcg_gen_muls2_i32(lo, hi, lo, hi); - tcg_gen_extu_i32_tl(s->T0, lo); - - cc_src_rhs =3D tcg_temp_new(); - tcg_gen_extu_i32_tl(cc_src_rhs, hi); - /* Compare the high part to the sign bit of the truncated resu= lt */ - tcg_gen_sari_i32(lo, lo, 31); - tcg_gen_extu_i32_tl(s->T1, lo); - } + /* + * This produces fewer TCG ops, and better code if flags are neede= d. + * s->T0 is already sign-extended. + */ + tcg_gen_ext32s_tl(s->T1, s->T1); + tcg_gen_mul_tl(s->T0, s->T0, s->T1); + /* Compare the full result to the extension of the truncated resul= t. */ + tcg_gen_ext32s_tl(s->T1, s->T0); + cc_src_rhs =3D s->T0; break; =20 case MO_64: --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768773990; cv=none; d=zohomail.com; s=zohoarc; b=ZQCLoCuMUWHIgsJyEVkgSwXL/ytmSiWW/QXjdakUBrhkyvdwAK/TCMzF5+zFBRzQOzmXjsIPNwv+vWMWx9I2TCFg4R/3DF32e+QKFhSCWb5+7EDYbUsJk4i5bLtGkN2x6VazlOhv3Vy+aaoOUYn3mieyzczqTWRmGxX5uO67xRw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768773990; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=85REHlkWJDtWsilQDfbxqyO96MGCDiDn4G3cKbUWWrA=; b=dP1EHwceHYfLgrwsCmVOvCQPaIX6iwb2EiPzFCeI6jU7X1IjJF4F5zv7KyIHNPtTa1qp6tsVj9O7+bmaRrNVHgOck8JO1im9wbfCK2qO+ndVybVchoNtubMZ5tCfPLFaEbEyjb9cKWo4H0tg1neAhaYSr2wS/yu/ObHn0gTGBh4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768773990124889.1950929202668; Sun, 18 Jan 2026 14:06:30 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhauS-0005tN-1e; Sun, 18 Jan 2026 17:06:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhau6-0004o3-6j for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:50 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhau3-0000xf-N9 for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:49 -0500 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-2a0833b5aeeso37526925ad.1 for ; Sun, 18 Jan 2026 14:05:46 -0800 (PST) Received: from stoup.. ([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7193dbb74sm74402865ad.56.2026.01.18.14.05.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:05:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768773946; x=1769378746; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=85REHlkWJDtWsilQDfbxqyO96MGCDiDn4G3cKbUWWrA=; b=aoWiqvMPahZmYcfY5uWL7HMtIC9A+c5N0VXmi5pwnzVFoWqBKUkvC5kH4ZssFihSk7 tGccM5cXXv7sd05pvqPLnPMxhGG8HMvMmEYley8YNtMmE76sSuop+10uVDSQAvVxzKTX RbDuWG/UrAS/X4lG2qnifkKDJA1CJX6zFYPT/4TUcC7CW6J5ULP8iePoIyMpre7+0pbQ QJ6npJ7Nt0gtSXBlZhW7AjAwUeRXhAtCYy0tQJrx8EoQAlRpSYpq3K2H9WjXt9k9OsnO Z39CnrDywR0uMkJPLtytFcO8yAakjRXtipa9dthPF/L9nQ839D9OKi+tPVWPcfGG8NjT d9+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768773946; x=1769378746; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=85REHlkWJDtWsilQDfbxqyO96MGCDiDn4G3cKbUWWrA=; b=TUf9Gq/DZkH2mOfe44zhNTCXCUH2Bu8Nya+GXuqmF0a8htx0XH3Ac+JfmX172H7Z/l hk2fEiVR61dcwL/jvzbAgnpDbmc2F4KeAIco3CNcyYbnov/6iHkL7zLF66ARcC3IVmFh n7YuDDJv2qa8X7xxGFpoWm9CO/+gGiyqaxWDI9myHQ7E/O5LqBmSnh/FInSXslL5teuC ZTpgimX1cNH2JSGrFdVmfSfqkPqbOvG7OFIg/yOPM7urp4VQ8P9lMAlyk3QApEBkcyj1 h5VW0ZdyoeRYajmM5gmtbsUeyrkj2NFfFJVuLtP//XkonM7ln0MFYkaq5RjityzvevYj 3EHA== X-Gm-Message-State: AOJu0Yz1oRUdQ0vvjbwpuwR7EFj4PECCJW/0LyauoymZL+ArfZEi6zcB 8718ojqqX+VxKNsv3gaLWSlAiQMY8hgCKRhyFl4KIz8tuDAI3GOSYoW9QJGTsh6ZQF1TKOe3bn1 dceAwGuj6Nw== X-Gm-Gg: AY/fxX7+UHI3fGHjn1nIGtmyqPAGWhVw/eHp4DJ+vKReZrOJPQiIHmMOHqys2HR3Qg0 i7kftKDy+KHhYxRluRI7CTUbyiYY8uhTDrl8WHcL4AogfySM6GDA9HUEN2kT1gMeBKjJUKwU/PY fZKBDm+PGvMoA3FgsSXDjUkLTawaTffhfWEiY/kjr7vx3ULWoC8gQqX9Y38V9RNMNKCF53e3reF Jde05cik29Qn5Am+IUtdud6OOnby5yC7nVPkaADGRyWeFPjlzRWUbxontlTj23WXnnNAK1dLYgq gZMnfo3V8QFrBQD3m+//xHXLUakx4YId1sUnCNjeIDVwDY+aEr7JMg9YIr/2wvDv3hQAEllc4QK X5dw3V9Sm9UR2Lk2r/uXmC9MJA2EECeLyurrEozTh3bolXLpnJuOsMGJ6CQAggUottCZ3sUz7PL jzubsioxNIfuO3UqQFrg== X-Received: by 2002:a17:902:d48e:b0:2a5:8ee5:2981 with SMTP id d9443c01a7336-2a7188f954fmr81999215ad.32.1768773945882; Sun, 18 Jan 2026 14:05:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 36/54] target/riscv: Drop TCG_TARGET_REG_BITS test Date: Mon, 19 Jan 2026 09:03:56 +1100 Message-ID: <20260118220414.8177-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768773992102158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 54 ++++++------------------- 1 file changed, 13 insertions(+), 41 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index caefd38216..4df9a40b44 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1181,60 +1181,32 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t = rs1, uint32_t nf, * Update vstart with the number of processed elements. * Use the helper function if either: * - vstart is not 0. - * - the target has 32 bit registers and we are loading/storing 64 bit= long - * elements. This is to ensure that we process every element with a = single - * memory instruction. */ =20 - bool use_helper_fn =3D !(s->vstart_eq_zero) || - (TCG_TARGET_REG_BITS =3D=3D 32 && log2_esz =3D= =3D 3); + bool use_helper_fn =3D !s->vstart_eq_zero; =20 if (!use_helper_fn) { - TCGv addr =3D tcg_temp_new(); uint32_t size =3D s->cfg_ptr->vlenb * nf; TCGv_i64 t8 =3D tcg_temp_new_i64(); - TCGv_i32 t4 =3D tcg_temp_new_i32(); MemOp atomicity =3D MO_ATOM_NONE; if (log2_esz =3D=3D 0) { atomicity =3D MO_ATOM_NONE; } else { atomicity =3D MO_ATOM_IFALIGN_PAIR; } - if (TCG_TARGET_REG_BITS =3D=3D 64) { - for (int i =3D 0; i < size; i +=3D 8) { - addr =3D get_address(s, rs1, i); - if (is_load) { - tcg_gen_qemu_ld_i64(t8, addr, s->mem_idx, - MO_LE | MO_64 | atomicity); - tcg_gen_st_i64(t8, tcg_env, vreg_ofs(s, vd) + i); - } else { - tcg_gen_ld_i64(t8, tcg_env, vreg_ofs(s, vd) + i); - tcg_gen_qemu_st_i64(t8, addr, s->mem_idx, - MO_LE | MO_64 | atomicity); - } - if (i =3D=3D size - 8) { - tcg_gen_movi_tl(cpu_vstart, 0); - } else { - tcg_gen_addi_tl(cpu_vstart, cpu_vstart, 8 >> log2_esz); - } + for (int i =3D 0; i < size; i +=3D 8) { + TCGv addr =3D get_address(s, rs1, i); + if (is_load) { + tcg_gen_qemu_ld_i64(t8, addr, s->mem_idx, MO_LEUQ | atomic= ity); + tcg_gen_st_i64(t8, tcg_env, vreg_ofs(s, vd) + i); + } else { + tcg_gen_ld_i64(t8, tcg_env, vreg_ofs(s, vd) + i); + tcg_gen_qemu_st_i64(t8, addr, s->mem_idx, MO_LEUQ | atomic= ity); } - } else { - for (int i =3D 0; i < size; i +=3D 4) { - addr =3D get_address(s, rs1, i); - if (is_load) { - tcg_gen_qemu_ld_i32(t4, addr, s->mem_idx, - MO_LE | MO_32 | atomicity); - tcg_gen_st_i32(t4, tcg_env, vreg_ofs(s, vd) + i); - } else { - tcg_gen_ld_i32(t4, tcg_env, vreg_ofs(s, vd) + i); - tcg_gen_qemu_st_i32(t4, addr, s->mem_idx, - MO_LE | MO_32 | atomicity); - } - if (i =3D=3D size - 4) { - tcg_gen_movi_tl(cpu_vstart, 0); - } else { - tcg_gen_addi_tl(cpu_vstart, cpu_vstart, 4 >> log2_esz); - } + if (i =3D=3D size - 8) { + tcg_gen_movi_tl(cpu_vstart, 0); + } else { + tcg_gen_addi_tl(cpu_vstart, cpu_vstart, 8 >> log2_esz); } } } else { --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768773995; cv=none; d=zohomail.com; s=zohoarc; b=G/zy+c9NAM/TW6g0O+rhVy2hzrZohwvuA94oOmXDo/Wju4cmHX1IDji4q2tHt5Em0M6ZS/Rdr0wBP7ms10nlaFAAUYjZhid2suLXo9yLFbyn9ZtbtgBx+BemjNX4TgsBPvrV+Sp/48BCWSss5SKNXTS6QUE1Dp9TADVi7rzF2dw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768773995; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dIX8M3PeuiegMB+HRi2DRYnSj2Vd5HpfS+cGE/3s+Sk=; b=hgD/BZ6jA6wyi1ommwhFpL7BOuNmtbgesF2xiEHsayzYhdiZNJEzIu4qrcX6TRfmooTFX8h546UIJKQhJafjYtjjq9M2HypDh2pl0SbQQBJIf2nJIDDKE57f/hrSZMAHGEsammiQiiRJYZQbEHVTR4GsjKH1Z8Ij0Fk9ABYTbBM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768773995972497.30242643291524; Sun, 18 Jan 2026 14:06:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhauU-0006Dt-Cv; Sun, 18 Jan 2026 17:06:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhau7-0004zR-Rh for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:55 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhau5-0000yM-Pd for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:51 -0500 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-2a58f2e514eso22985955ad.3 for ; Sun, 18 Jan 2026 14:05:49 -0800 (PST) Received: from stoup.. ([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7193dbb74sm74402865ad.56.2026.01.18.14.05.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:05:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768773948; x=1769378748; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dIX8M3PeuiegMB+HRi2DRYnSj2Vd5HpfS+cGE/3s+Sk=; b=scKhCtNjmtrz3SyPl3ZY62a3GsniyCqe6rgsT8AKKsxcmwCyOzqGGxgpVZrtdtd+Rd GUzfbw2MFXsKcC//9L6rfuQrFeyckrnIvR2YLpfo8tDXaE4997uuzJ04tdaAzTrkWBVT A0+9gTrzgiWYkVlgZiSpmRRHBGhhXiqHKQJCyP0iToNkwjBTZInvnic5MFpSp/dH2v2G X/fP1bclYxqIU55BVGnzvy7M9dpVUOD4xxw33YyWmgvIXFxBqVa8TV77v+FvqJHOzC3w ceykf/ebXnFZ95f6pVJkJR73AYkdaRcH3QWi1lyXWZ5ApbMY25rcsDVjmi0CIDxxWd2M UDaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768773948; x=1769378748; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=dIX8M3PeuiegMB+HRi2DRYnSj2Vd5HpfS+cGE/3s+Sk=; b=Fh1pJRerQeLLjBYpugEht3/SBVgWGwWr4Zn8nxwArkTlollGQcef2LxKuneXx5N6jG dvQcTz9IuDumHmMQV8FhmodswSl0w+r17N520m8SppDvqWYBaKfnE4ryUTYRRWo5jocI +DmD4C4oDrruKMJS6GjOcozB9acv0LLgYlwqvYIH3kbDlL7MYG8TPa1rYH/O6cIluCZT R4ibsU63ukrrILL1RA+OU4i9rpFw4hQ8GX3OacAq6urDyvTk/O65s0JHTH2g1UkzrWqq xYk86MYRaWWfX6isB9emZQcrt2WSQ4iGXjgd1kK81Ecl+cgV6PTk8cbPxp83fJd9AAJX Kljw== X-Gm-Message-State: AOJu0YwWzeYPe2DGMXDnMdWYfcYoLtiPgwzBGaO5r8Z9IQEu9pcq3Jgz Brw0BxW1LVOlWeg76vLUMmhfI0It0rKJdXW3jqOlTAEQfUSNGd41nDBOA4leKkra5K6/OkBoEw/ m54GAyyL2Sg== X-Gm-Gg: AY/fxX78NXMewXzvGEdNO9Q1S4/+3UBmC7i6nWbo+3EXZcv9Ss23Up3CzWcqf1kqueM IetoEUCsCtnzNvzinpprI20m8e0UrzA++HXhAxierNhFl4mOQQtfV3C/p/ZouuNlkyhHlaF0Otu lolp/+dkCi1nTlDc+mcr7maFz0VYo2Nerzu+4PvC3rri7lmWyJLdwPH5hG73FfNfk0qNUPvKU3+ lpnq+FySrnPZ8nkUXrCpWT6kq0RXWwpkxhtr3dV/TTrU8eIDrgfawXE9gcajlIxkALj72Bta35z uH6KF2vuiVKn+Q3I7tHXRjaWRwUy+8YbtV/I42fWpy8CFgNRsQNx49v72neAdE3QNEC2/0wrjNe UKEPaxHcAmjkqxDB8Nh2sLIH6KYcgwAcuwpVo5MTqqGshfaUg3s1snR38Ynnw1XeetCGhf5YgfF f6gfnhOIUyYEbZ+xS+HthQ9kLQo9t3 X-Received: by 2002:a17:902:ec87:b0:2a0:f0e2:94b7 with SMTP id d9443c01a7336-2a7188fd7f2mr103998115ad.30.1768773948018; Sun, 18 Jan 2026 14:05:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 37/54] accel/tcg/runtime: Remove 64-bit shift helpers Date: Mon, 19 Jan 2026 09:03:57 +1100 Message-ID: <20260118220414.8177-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768773998143158500 Content-Type: text/plain; charset="utf-8" These were only required for some 32-bit hosts. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 4 ---- accel/tcg/tcg-runtime.c | 15 --------------- 2 files changed, 19 deletions(-) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index 8436599b9f..698e9baa29 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -8,10 +8,6 @@ DEF_HELPER_FLAGS_2(rem_i64, TCG_CALL_NO_RWG_SE, s64, s64, = s64) DEF_HELPER_FLAGS_2(divu_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(remu_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64) =20 -DEF_HELPER_FLAGS_2(shl_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_FLAGS_2(shr_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_FLAGS_2(sar_i64, TCG_CALL_NO_RWG_SE, s64, s64, s64) - DEF_HELPER_FLAGS_2(mulsh_i64, TCG_CALL_NO_RWG_SE, s64, s64, s64) DEF_HELPER_FLAGS_2(muluh_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64) =20 diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index fa7ed9739c..f483c9c2ba 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -55,21 +55,6 @@ uint32_t HELPER(remu_i32)(uint32_t arg1, uint32_t arg2) =20 /* 64-bit helpers */ =20 -uint64_t HELPER(shl_i64)(uint64_t arg1, uint64_t arg2) -{ - return arg1 << arg2; -} - -uint64_t HELPER(shr_i64)(uint64_t arg1, uint64_t arg2) -{ - return arg1 >> arg2; -} - -int64_t HELPER(sar_i64)(int64_t arg1, int64_t arg2) -{ - return arg1 >> arg2; -} - int64_t HELPER(div_i64)(int64_t arg1, int64_t arg2) { return arg1 / arg2; --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774102; cv=none; d=zohomail.com; s=zohoarc; b=DgK2u6dwdLFbUrZ8uKzLFd0NpKfQY7Y6nlEEMjJUSpTweun4B7rVx5MiyxvTWYewAuJJjno2c8S8W6yaURKQvcy/UwOvk847utxToHnVQIyME+I67rLdVKNq5yny/Aoh5rhXsVynqVzvz6cFAbg3085VzD/zzzxkx8an/J52Qmk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768774102; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=joRi6369pVbDsKfJdtidvp6zyQujsSJuuqqcthZ9YJA=; b=YmX3vLqBucNgsfxpvZPIdz1ADrkT8Eny+QEcu4iVpdMiKWC16/mB+U+qkEycIF8gILQLkSm0PI6Mqm4NOwLoAUf3ot9Euq//NOUIUZx2bhpCzA5CXraIpgvMy047xu0StDdu05hhO6i1dcW0lv5gXS6OLDchKD/TaMUzrQr1t1Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768774102246278.41211965877244; Sun, 18 Jan 2026 14:08:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhauR-0005tv-QC; Sun, 18 Jan 2026 17:06:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhauB-00054o-GX for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:57 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhau9-0000zM-Al for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:54 -0500 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-29f2676bb21so37329805ad.0 for ; Sun, 18 Jan 2026 14:05:51 -0800 (PST) Received: from stoup.. ([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7193dbb74sm74402865ad.56.2026.01.18.14.05.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:05:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768773951; x=1769378751; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=joRi6369pVbDsKfJdtidvp6zyQujsSJuuqqcthZ9YJA=; b=qI6EjGQZte9u6gbA4X8VfNGsTcWtR1msKWggKEPZb5xAksruv8wjr09Dvf/wwH7qTx oKQAmGb5MroYFRqa8q0+GNiozaEPRPHjgQhhj20UjAThzN6NpKbPGodOCNUxkiNjHcxQ JtWQslBuu+jdd/Z07eBJ0Vb64K8KBN7thnEkQMN6tMWT6Fc/N3v1kesCICzBUT6w3O7i CoFXBMGK7D6uneJqqmWWG4OlNS6tuky2rMl5lab35TaMp3Kxm591h9ZuwvPqp0xVoQUc eY/t6f+yiQ7KpBym3b9b0jLe+NIFX5mkYyKKkyZgXX53LFhYT1iOm4XjDdEr5wez2J2k 9LXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768773951; x=1769378751; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=joRi6369pVbDsKfJdtidvp6zyQujsSJuuqqcthZ9YJA=; b=OIOHDXefr+uPS0m3Lp0BiWr59bmMfgdvzjlCND4q7RC5FKhvYaLbyk3J6NDAr1rVc/ 1Xc7V0bbFp2nSDDRZZh5QlWls459ze4TPfA/ZgkD4143RWHBbp/PNmL/jgV8YoZlCfaN XUAlhhOwfpklrYMVMfmUoZoUEuwtGfmKgtJHTTD/kp/xQxV7K5JjjOosBhl3/fSt/XHE kxgE55QKfs3yTSkShS+GPB25qczyFgaCA6SDsn1PJha884QO7Uzh1mbBX6L82mgw8U4s c0+UoeVFJZk1Gj1dfyDoJsD1RrJ5h37sXbHAE3vpOvjMjluZEmZ6BQ5W+F14Mz2uP/Ye qxBw== X-Gm-Message-State: AOJu0Yxu3jAT8NbVskaDwEyxNeNQwrXkr0HANEsX8NSJxFetL54ksI16 Shki/vbyc/TbmS6w+eOEeKpt/vpUIvmY/zALbLDiZ5ZudQDlyd9Cwi8G1NnZ23LLDkony4SsDcd yd5GClxXr2g== X-Gm-Gg: AY/fxX6oiJVYEPY+vEab4HN+jRdwnGabn+SZMFcDAwAuGXhh7yIR7HCuFwrBjyyHjga 7saF3OKBsXYhXlO90zmYzytbvSVtB3YzGDRS74YjcOqpLbYWAI9PFSdxVS880ycl8mzm58WOniS zNDFZSvbX/cBklemENk7oiB9vEKEmJIHg+No6Mp9514GAHXoAdCcz8c7cDsIPQnXqaWccTHT42a COn5+4k93glVndV18DsCXrXDFwrcKYImLXPUdJ9yfEBTEiAQqzH2eR283nSxsr5Mm58yYjdugPK E+PUoEPJHKtSg+/HhYLR6ngdsubIsydntPOdoxbbhCb21phcWsB9UNQna8mI419Avq+gvFBzQRv QwzPOzsrA+c49R3yTg7TSR2PKx2rQbvA89Vuf1lBRnJylLkzi8xpNxURR5czDf49amnSaFUYOf6 lTvUJz/tHAj33EAG8bow== X-Received: by 2002:a17:902:f788:b0:29e:9387:f2b7 with SMTP id d9443c01a7336-2a7188577d1mr94309825ad.11.1768773950896; Sun, 18 Jan 2026 14:05:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 38/54] accel/tcg/runtime: Remove helper_nonatomic_cmpxchgo Date: Mon, 19 Jan 2026 09:03:58 +1100 Message-ID: <20260118220414.8177-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774102501158500 This were only required for some 32-bit hosts. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 3 --- accel/tcg/atomic_common.c.inc | 20 -------------------- 2 files changed, 23 deletions(-) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index 698e9baa29..dc89155c0f 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -73,9 +73,6 @@ DEF_HELPER_FLAGS_4(atomic_fetch_oro_le, TCG_CALL_NO_WG, i128, env, i64, i128, i32) #endif =20 -DEF_HELPER_FLAGS_5(nonatomic_cmpxchgo, TCG_CALL_NO_WG, - i128, env, i64, i128, i128, i32) - #ifdef CONFIG_ATOMIC64 #define GEN_ATOMIC_HELPERS(NAME) \ DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), b), \ diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc index bca93a0ac4..1ff80d19fe 100644 --- a/accel/tcg/atomic_common.c.inc +++ b/accel/tcg/atomic_common.c.inc @@ -59,26 +59,6 @@ CMPXCHG_HELPER(cmpxchgo_le, Int128) =20 #undef CMPXCHG_HELPER =20 -Int128 HELPER(nonatomic_cmpxchgo)(CPUArchState *env, uint64_t addr, - Int128 cmpv, Int128 newv, uint32_t oi) -{ -#if TCG_TARGET_REG_BITS =3D=3D 32 - uintptr_t ra =3D GETPC(); - Int128 oldv; - - oldv =3D cpu_ld16_mmu(env, addr, oi, ra); - if (int128_eq(oldv, cmpv)) { - cpu_st16_mmu(env, addr, newv, oi, ra); - } else { - /* Even with comparison failure, still need a write cycle. */ - probe_write(env, addr, 16, get_mmuidx(oi), ra); - } - return oldv; -#else - g_assert_not_reached(); -#endif -} - #define ATOMIC_HELPER(OP, TYPE) \ TYPE HELPER(glue(atomic_,OP))(CPUArchState *env, uint64_t addr, \ TYPE val, uint32_t oi) \ --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774180; cv=none; d=zohomail.com; s=zohoarc; b=LypyTRYpFAEYnIAml5auLbZgxOs2JzON8cwO4PsL1nf5Yb+RU5CMXEexZOKdqq45uxKT2QIrs/cHbaCmRz3qAKm8oHyQ7xmsxaXKjCNjViB9l8mWQxbvtSOF82duHCIPjFVSJ+qoVb5mFUuZu5g4ICTupOGGlk73ZZPT6gm2k+U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768774180; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0laMDFdu0GCNRz+fuF/L/mWxDMERFitEw5PSc+47rq0=; b=Co1PKrZqR8AGR7JUbSk5e1gPzTY5JplOiPtLYmihPjKqvheN1KxDgSN1XPsNnDf6qCJQRK3ebe9kpUgzNmWc6r5NMKCRhMzt4MTD0G1JL9+SeE5X4UcSsS3v3a31LeiCcebFqhNzr8QWfeqKGCJ3OM8EvGk/UaNP5RYKlfKrOJY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768774180775461.5472253979033; Sun, 18 Jan 2026 14:09:40 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhauV-0006MB-Cx; Sun, 18 Jan 2026 17:06:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhauD-00057y-9i for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:59 -0500 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhauB-0000zp-7q for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:05:57 -0500 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-2a12ebe4b74so35808595ad.0 for ; Sun, 18 Jan 2026 14:05:54 -0800 (PST) Received: from stoup.. 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 16 ---------------- include/accel/tcg/cpu-ldst-common.h | 9 --------- accel/tcg/cputlb.c | 2 -- accel/tcg/user-exec.c | 2 -- tcg/tcg-op-ldst.c | 17 ++++++----------- accel/tcg/atomic_common.c.inc | 12 ------------ 6 files changed, 6 insertions(+), 52 deletions(-) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index dc89155c0f..0b832176b3 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -48,12 +48,10 @@ DEF_HELPER_FLAGS_5(atomic_cmpxchgl_be, TCG_CALL_NO_WG, i32, env, i64, i32, i32, i32) DEF_HELPER_FLAGS_5(atomic_cmpxchgl_le, TCG_CALL_NO_WG, i32, env, i64, i32, i32, i32) -#ifdef CONFIG_ATOMIC64 DEF_HELPER_FLAGS_5(atomic_cmpxchgq_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i32) DEF_HELPER_FLAGS_5(atomic_cmpxchgq_le, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i32) -#endif #if HAVE_CMPXCHG128 DEF_HELPER_FLAGS_5(atomic_cmpxchgo_be, TCG_CALL_NO_WG, i128, env, i64, i128, i128, i32) @@ -73,7 +71,6 @@ DEF_HELPER_FLAGS_4(atomic_fetch_oro_le, TCG_CALL_NO_WG, i128, env, i64, i128, i32) #endif =20 -#ifdef CONFIG_ATOMIC64 #define GEN_ATOMIC_HELPERS(NAME) \ DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), b), \ TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ @@ -89,19 +86,6 @@ DEF_HELPER_FLAGS_4(atomic_fetch_oro_le, TCG_CALL_NO_WG, TCG_CALL_NO_WG, i64, env, i64, i64, i32) \ DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), q_be), \ TCG_CALL_NO_WG, i64, env, i64, i64, i32) -#else -#define GEN_ATOMIC_HELPERS(NAME) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), b), \ - TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_le), \ - TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_be), \ - TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_le), \ - TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_be), \ - TCG_CALL_NO_WG, i32, env, i64, i32, i32) -#endif /* CONFIG_ATOMIC64 */ =20 GEN_ATOMIC_HELPERS(fetch_add) GEN_ATOMIC_HELPERS(fetch_and) diff --git a/include/accel/tcg/cpu-ldst-common.h b/include/accel/tcg/cpu-ld= st-common.h index 17a3250ded..f12be8cfb7 100644 --- a/include/accel/tcg/cpu-ldst-common.h +++ b/include/accel/tcg/cpu-ldst-common.h @@ -60,7 +60,6 @@ TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \ (CPUArchState *env, vaddr addr, TYPE val, \ MemOpIdx oi, uintptr_t retaddr); =20 -#ifdef CONFIG_ATOMIC64 #define GEN_ATOMIC_HELPER_ALL(NAME) \ GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ @@ -69,14 +68,6 @@ TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \ GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \ GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \ GEN_ATOMIC_HELPER(NAME, uint64_t, q_be) -#else -#define GEN_ATOMIC_HELPER_ALL(NAME) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) -#endif =20 GEN_ATOMIC_HELPER_ALL(fetch_add) GEN_ATOMIC_HELPER_ALL(fetch_sub) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c30073326a..a6774083b0 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2886,10 +2886,8 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, I= nt128 val, #define DATA_SIZE 4 #include "atomic_template.h" =20 -#ifdef CONFIG_ATOMIC64 #define DATA_SIZE 8 #include "atomic_template.h" -#endif =20 #if defined(CONFIG_ATOMIC128) || HAVE_CMPXCHG128 #define DATA_SIZE 16 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 1800dffa63..ddbdc0432d 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1258,10 +1258,8 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr = addr, MemOpIdx oi, #define DATA_SIZE 4 #include "atomic_template.h" =20 -#ifdef CONFIG_ATOMIC64 #define DATA_SIZE 8 #include "atomic_template.h" -#endif =20 #if defined(CONFIG_ATOMIC128) || HAVE_CMPXCHG128 #define DATA_SIZE 16 diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 55bfbf3a20..354d9968f9 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -825,11 +825,6 @@ typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, = TCGv_i64, typedef void (*gen_atomic_op_i128)(TCGv_i128, TCGv_env, TCGv_i64, TCGv_i128, TCGv_i32); =20 -#ifdef CONFIG_ATOMIC64 -# define WITH_ATOMIC64(X) X, -#else -# define WITH_ATOMIC64(X) -#endif #if HAVE_CMPXCHG128 # define WITH_ATOMIC128(X) X, #else @@ -842,8 +837,8 @@ static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP) = + 1] =3D { [MO_16 | MO_BE] =3D gen_helper_atomic_cmpxchgw_be, [MO_32 | MO_LE] =3D gen_helper_atomic_cmpxchgl_le, [MO_32 | MO_BE] =3D gen_helper_atomic_cmpxchgl_be, - WITH_ATOMIC64([MO_64 | MO_LE] =3D gen_helper_atomic_cmpxchgq_le) - WITH_ATOMIC64([MO_64 | MO_BE] =3D gen_helper_atomic_cmpxchgq_be) + [MO_64 | MO_LE] =3D gen_helper_atomic_cmpxchgq_le, + [MO_64 | MO_BE] =3D gen_helper_atomic_cmpxchgq_be, WITH_ATOMIC128([MO_128 | MO_LE] =3D gen_helper_atomic_cmpxchgo_le) WITH_ATOMIC128([MO_128 | MO_BE] =3D gen_helper_atomic_cmpxchgo_be) }; @@ -1235,8 +1230,8 @@ static void * const table_##NAME[(MO_SIZE | MO_BSWAP)= + 1] =3D { \ [MO_16 | MO_BE] =3D gen_helper_atomic_##NAME##w_be, \ [MO_32 | MO_LE] =3D gen_helper_atomic_##NAME##l_le, \ [MO_32 | MO_BE] =3D gen_helper_atomic_##NAME##l_be, \ - WITH_ATOMIC64([MO_64 | MO_LE] =3D gen_helper_atomic_##NAME##q_le) \ - WITH_ATOMIC64([MO_64 | MO_BE] =3D gen_helper_atomic_##NAME##q_be) \ + [MO_64 | MO_LE] =3D gen_helper_atomic_##NAME##q_le, \ + [MO_64 | MO_BE] =3D gen_helper_atomic_##NAME##q_be, \ WITH_ATOMIC128([MO_128 | MO_LE] =3D gen_helper_atomic_##NAME##o_le) \ WITH_ATOMIC128([MO_128 | MO_BE] =3D gen_helper_atomic_##NAME##o_be) \ }; \ @@ -1287,8 +1282,8 @@ static void * const table_##NAME[(MO_SIZE | MO_BSWAP)= + 1] =3D { \ [MO_16 | MO_BE] =3D gen_helper_atomic_##NAME##w_be, \ [MO_32 | MO_LE] =3D gen_helper_atomic_##NAME##l_le, \ [MO_32 | MO_BE] =3D gen_helper_atomic_##NAME##l_be, \ - WITH_ATOMIC64([MO_64 | MO_LE] =3D gen_helper_atomic_##NAME##q_le) \ - WITH_ATOMIC64([MO_64 | MO_BE] =3D gen_helper_atomic_##NAME##q_be) \ + [MO_64 | MO_LE] =3D gen_helper_atomic_##NAME##q_le, \ + [MO_64 | MO_BE] =3D gen_helper_atomic_##NAME##q_be, \ }; \ void tcg_gen_atomic_##NAME##_i32_chk(TCGv_i32 ret, TCGTemp *addr, \ TCGv_i32 val, TCGArg idx, \ diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc index 1ff80d19fe..7d779dd51d 100644 --- a/accel/tcg/atomic_common.c.inc +++ b/accel/tcg/atomic_common.c.inc @@ -46,11 +46,8 @@ CMPXCHG_HELPER(cmpxchgw_be, uint32_t) CMPXCHG_HELPER(cmpxchgw_le, uint32_t) CMPXCHG_HELPER(cmpxchgl_be, uint32_t) CMPXCHG_HELPER(cmpxchgl_le, uint32_t) - -#ifdef CONFIG_ATOMIC64 CMPXCHG_HELPER(cmpxchgq_be, uint64_t) CMPXCHG_HELPER(cmpxchgq_le, uint64_t) -#endif =20 #if HAVE_CMPXCHG128 CMPXCHG_HELPER(cmpxchgo_be, Int128) @@ -64,7 +61,6 @@ CMPXCHG_HELPER(cmpxchgo_le, Int128) TYPE val, uint32_t oi) \ { return glue(glue(cpu_atomic_,OP),_mmu)(env, addr, val, oi, GETPC());= } =20 -#ifdef CONFIG_ATOMIC64 #define GEN_ATOMIC_HELPERS(OP) \ ATOMIC_HELPER(glue(OP,b), uint32_t) \ ATOMIC_HELPER(glue(OP,w_be), uint32_t) \ @@ -73,14 +69,6 @@ CMPXCHG_HELPER(cmpxchgo_le, Int128) ATOMIC_HELPER(glue(OP,l_le), uint32_t) \ ATOMIC_HELPER(glue(OP,q_be), uint64_t) \ ATOMIC_HELPER(glue(OP,q_le), uint64_t) -#else -#define GEN_ATOMIC_HELPERS(OP) \ - ATOMIC_HELPER(glue(OP,b), uint32_t) \ - ATOMIC_HELPER(glue(OP,w_be), uint32_t) \ - ATOMIC_HELPER(glue(OP,w_le), uint32_t) \ - ATOMIC_HELPER(glue(OP,l_be), uint32_t) \ - ATOMIC_HELPER(glue(OP,l_le), uint32_t) -#endif =20 GEN_ATOMIC_HELPERS(fetch_add) GEN_ATOMIC_HELPERS(fetch_and) --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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This allows removal of functions like load_atomic8_or_exit and simplification of load_atom_extract_al8_or_exit to load_atom_extract_al8. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 35 +------- accel/tcg/ldst_atomicity.c.inc | 149 +++++---------------------------- 2 files changed, 24 insertions(+), 160 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a6774083b0..6900a12682 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2080,25 +2080,6 @@ static uint64_t do_ld_parts_beN(MMULookupPageData *p= , uint64_t ret_be) return ret_be; } =20 -/** - * do_ld_parts_be4 - * @p: translation parameters - * @ret_be: accumulated data - * - * As do_ld_bytes_beN, but with one atomic load. - * Four aligned bytes are guaranteed to cover the load. - */ -static uint64_t do_ld_whole_be4(MMULookupPageData *p, uint64_t ret_be) -{ - int o =3D p->addr & 3; - uint32_t x =3D load_atomic4(p->haddr - o); - - x =3D cpu_to_be32(x); - x <<=3D o * 8; - x >>=3D (4 - p->size) * 8; - return (ret_be << (p->size * 8)) | x; -} - /** * do_ld_parts_be8 * @p: translation parameters @@ -2111,7 +2092,7 @@ static uint64_t do_ld_whole_be8(CPUState *cpu, uintpt= r_t ra, MMULookupPageData *p, uint64_t ret_be) { int o =3D p->addr & 7; - uint64_t x =3D load_atomic8_or_exit(cpu, ra, p->haddr - o); + uint64_t x =3D load_atomic8(p->haddr - o); =20 x =3D cpu_to_be64(x); x <<=3D o * 8; @@ -2176,11 +2157,7 @@ static uint64_t do_ld_beN(CPUState *cpu, MMULookupPa= geData *p, if (atom =3D=3D MO_ATOM_IFALIGN_PAIR ? p->size =3D=3D half_size : p->size >=3D half_size) { - if (!HAVE_al8_fast && p->size < 4) { - return do_ld_whole_be4(p, ret_be); - } else { - return do_ld_whole_be8(cpu, ra, p, ret_be); - } + return do_ld_whole_be8(cpu, ra, p, ret_be); } /* fall through */ =20 @@ -2586,13 +2563,7 @@ static uint64_t do_st_leN(CPUState *cpu, MMULookupPa= geData *p, if (atom =3D=3D MO_ATOM_IFALIGN_PAIR ? p->size =3D=3D half_size : p->size >=3D half_size) { - if (!HAVE_al8_fast && p->size <=3D 4) { - return store_whole_le4(p->haddr, p->size, val_le); - } else if (HAVE_al8) { - return store_whole_le8(p->haddr, p->size, val_le); - } else { - cpu_loop_exit_atomic(cpu, ra); - } + return store_whole_le8(p->haddr, p->size, val_le); } /* fall through */ =20 diff --git a/accel/tcg/ldst_atomicity.c.inc b/accel/tcg/ldst_atomicity.c.inc index c735add261..f5b8289009 100644 --- a/accel/tcg/ldst_atomicity.c.inc +++ b/accel/tcg/ldst_atomicity.c.inc @@ -12,13 +12,6 @@ #include "host/load-extract-al16-al8.h.inc" #include "host/store-insert-al16.h.inc" =20 -#ifdef CONFIG_ATOMIC64 -# define HAVE_al8 true -#else -# define HAVE_al8 false -#endif -#define HAVE_al8_fast (ATOMIC_REG_SIZE >=3D 8) - /** * required_atomicity: * @@ -132,44 +125,7 @@ static inline uint32_t load_atomic4(void *pv) static inline uint64_t load_atomic8(void *pv) { uint64_t *p =3D __builtin_assume_aligned(pv, 8); - - qemu_build_assert(HAVE_al8); - return qatomic_read__nocheck(p); -} - -/** - * load_atomic8_or_exit: - * @cpu: generic cpu state - * @ra: host unwind address - * @pv: host address - * - * Atomically load 8 aligned bytes from @pv. - * If this is not possible, longjmp out to restart serially. - */ -static uint64_t load_atomic8_or_exit(CPUState *cpu, uintptr_t ra, void *pv) -{ - if (HAVE_al8) { - return load_atomic8(pv); - } - -#ifdef CONFIG_USER_ONLY - /* - * If the page is not writable, then assume the value is immutable - * and requires no locking. This ignores the case of MAP_SHARED with - * another process, because the fallback start_exclusive solution - * provides no protection across processes. - */ - WITH_MMAP_LOCK_GUARD() { - if (!page_check_range(h2g(pv), 8, PAGE_WRITE_ORG)) { - uint64_t *p =3D __builtin_assume_aligned(pv, 8); - return *p; - } - } -#endif - - /* Ultimate fallback: re-execute in serial context. */ - trace_load_atom8_or_exit_fallback(ra); - cpu_loop_exit_atomic(cpu, ra); + return qatomic_read(p); } =20 /** @@ -264,9 +220,7 @@ static uint64_t load_atom_extract_al8x2(void *pv) } =20 /** - * load_atom_extract_al8_or_exit: - * @cpu: generic cpu state - * @ra: host unwind address + * load_atom_extract_al8 * @pv: host address * @s: object size in bytes, @s <=3D 4. * @@ -275,15 +229,14 @@ static uint64_t load_atom_extract_al8x2(void *pv) * 8-byte load and extract. * The value is returned in the low bits of a uint32_t. */ -static uint32_t load_atom_extract_al8_or_exit(CPUState *cpu, uintptr_t ra, - void *pv, int s) +static uint32_t load_atom_extract_al8(void *pv, int s) { uintptr_t pi =3D (uintptr_t)pv; int o =3D pi & 7; int shr =3D (HOST_BIG_ENDIAN ? 8 - s - o : o) * 8; =20 pv =3D (void *)(pi & ~7); - return load_atomic8_or_exit(cpu, ra, pv) >> shr; + return load_atomic8(pv) >> shr; } =20 /** @@ -297,7 +250,7 @@ static uint32_t load_atom_extract_al8_or_exit(CPUState = *cpu, uintptr_t ra, * and p % 16 + s > 8. I.e. does not cross a 16-byte * boundary, but *does* cross an 8-byte boundary. * This is the slow version, so we must have eliminated - * any faster load_atom_extract_al8_or_exit case. + * any faster load_atom_extract_al8 case. * * If this is not possible, longjmp out to restart serially. */ @@ -374,21 +327,6 @@ static inline uint64_t load_atom_8_by_4(void *pv) } } =20 -/** - * load_atom_8_by_8_or_4: - * @pv: host address - * - * Load 8 bytes from aligned @pv, with at least 4-byte atomicity. - */ -static inline uint64_t load_atom_8_by_8_or_4(void *pv) -{ - if (HAVE_al8_fast) { - return load_atomic8(pv); - } else { - return load_atom_8_by_4(pv); - } -} - /** * load_atom_2: * @p: host address @@ -418,12 +356,8 @@ static uint16_t load_atom_2(CPUState *cpu, uintptr_t r= a, return lduw_he_p(pv); case MO_16: /* The only case remaining is MO_ATOM_WITHIN16. */ - if (!HAVE_al8_fast && (pi & 3) =3D=3D 1) { - /* Big or little endian, we want the middle two bytes. */ - return load_atomic4(pv - 1) >> 8; - } if ((pi & 15) !=3D 7) { - return load_atom_extract_al8_or_exit(cpu, ra, pv, 2); + return load_atom_extract_al8(pv, 2); } return load_atom_extract_al16_or_exit(cpu, ra, pv, 2); default: @@ -468,7 +402,7 @@ static uint32_t load_atom_4(CPUState *cpu, uintptr_t ra, return load_atom_extract_al4x2(pv); case MO_32: if (!(pi & 4)) { - return load_atom_extract_al8_or_exit(cpu, ra, pv, 4); + return load_atom_extract_al8(pv, 4); } return load_atom_extract_al16_or_exit(cpu, ra, pv, 4); default: @@ -493,7 +427,7 @@ static uint64_t load_atom_8(CPUState *cpu, uintptr_t ra, * If the host does not support 8-byte atomics, wait until we have * examined the atomicity parameters below. */ - if (HAVE_al8 && likely((pi & 7) =3D=3D 0)) { + if (likely((pi & 7) =3D=3D 0)) { return load_atomic8(pv); } if (HAVE_ATOMIC128_RO) { @@ -502,30 +436,9 @@ static uint64_t load_atom_8(CPUState *cpu, uintptr_t r= a, =20 atmax =3D required_atomicity(cpu, pi, memop); if (atmax =3D=3D MO_64) { - if (!HAVE_al8 && (pi & 7) =3D=3D 0) { - load_atomic8_or_exit(cpu, ra, pv); - } return load_atom_extract_al16_or_exit(cpu, ra, pv, 8); } - if (HAVE_al8_fast) { - return load_atom_extract_al8x2(pv); - } - switch (atmax) { - case MO_8: - return ldq_he_p(pv); - case MO_16: - return load_atom_8_by_2(pv); - case MO_32: - return load_atom_8_by_4(pv); - case -MO_32: - if (HAVE_al8) { - return load_atom_extract_al8x2(pv); - } - trace_load_atom8_fallback(memop, ra); - cpu_loop_exit_atomic(cpu, ra); - default: - g_assert_not_reached(); - } + return load_atom_extract_al8x2(pv); } =20 /** @@ -565,18 +478,10 @@ static Int128 load_atom_16(CPUState *cpu, uintptr_t r= a, b =3D load_atom_8_by_4(pv + 8); break; case MO_64: - if (!HAVE_al8) { - trace_load_atom16_fallback(memop, ra); - cpu_loop_exit_atomic(cpu, ra); - } a =3D load_atomic8(pv); b =3D load_atomic8(pv + 8); break; case -MO_64: - if (!HAVE_al8) { - trace_load_atom16_fallback(memop, ra); - cpu_loop_exit_atomic(cpu, ra); - } a =3D load_atom_extract_al8x2(pv); b =3D load_atom_extract_al8x2(pv + 8); break; @@ -624,9 +529,7 @@ static inline void store_atomic4(void *pv, uint32_t val) static inline void store_atomic8(void *pv, uint64_t val) { uint64_t *p =3D __builtin_assume_aligned(pv, 8); - - qemu_build_assert(HAVE_al8); - qatomic_set__nocheck(p, val); + qatomic_set(p, val); } =20 /** @@ -688,9 +591,8 @@ static void store_atom_insert_al8(uint64_t *p, uint64_t= val, uint64_t msk) { uint64_t old, new; =20 - qemu_build_assert(HAVE_al8); p =3D __builtin_assume_aligned(p, 8); - old =3D qatomic_read__nocheck(p); + old =3D qatomic_read(p); do { new =3D (old & ~msk) | val; } while (!__atomic_compare_exchange_n(p, &old, new, true, @@ -802,7 +704,6 @@ static uint64_t store_whole_le8(void *pv, int size, uin= t64_t val_le) uint64_t m =3D MAKE_64BIT_MASK(0, sz); uint64_t v; =20 - qemu_build_assert(HAVE_al8); if (HOST_BIG_ENDIAN) { v =3D bswap64(val_le) >> sh; m =3D bswap64(m) >> sh; @@ -887,10 +788,8 @@ static void store_atom_2(CPUState *cpu, uintptr_t ra, store_atom_insert_al4(pv - 1, (uint32_t)val << 8, MAKE_64BIT_MASK(= 8, 16)); return; } else if ((pi & 7) =3D=3D 3) { - if (HAVE_al8) { - store_atom_insert_al8(pv - 3, (uint64_t)val << 24, MAKE_64BIT_= MASK(24, 16)); - return; - } + store_atom_insert_al8(pv - 3, (uint64_t)val << 24, MAKE_64BIT_MASK= (24, 16)); + return; } else if ((pi & 15) =3D=3D 7) { if (HAVE_CMPXCHG128) { Int128 v =3D int128_lshift(int128_make64(val), 56); @@ -957,10 +856,8 @@ static void store_atom_4(CPUState *cpu, uintptr_t ra, return; case MO_32: if ((pi & 7) < 4) { - if (HAVE_al8) { - store_whole_le8(pv, 4, cpu_to_le32(val)); - return; - } + store_whole_le8(pv, 4, cpu_to_le32(val)); + return; } else { if (HAVE_CMPXCHG128) { store_whole_le16(pv, 4, int128_make64(cpu_to_le32(val))); @@ -988,7 +885,7 @@ static void store_atom_8(CPUState *cpu, uintptr_t ra, uintptr_t pi =3D (uintptr_t)pv; int atmax; =20 - if (HAVE_al8 && likely((pi & 7) =3D=3D 0)) { + if (likely((pi & 7) =3D=3D 0)) { store_atomic8(pv, val); return; } @@ -1005,7 +902,7 @@ static void store_atom_8(CPUState *cpu, uintptr_t ra, store_atom_8_by_4(pv, val); return; case -MO_32: - if (HAVE_al8) { + { uint64_t val_le =3D cpu_to_le64(val); int s2 =3D pi & 7; int s1 =3D 8 - s2; @@ -1024,9 +921,8 @@ static void store_atom_8(CPUState *cpu, uintptr_t ra, default: g_assert_not_reached(); } - return; } - break; + return; case MO_64: if (HAVE_CMPXCHG128) { store_whole_le16(pv, 8, int128_make64(cpu_to_le64(val))); @@ -1077,12 +973,9 @@ static void store_atom_16(CPUState *cpu, uintptr_t ra, store_atom_8_by_4(pv + 8, b); return; case MO_64: - if (HAVE_al8) { - store_atomic8(pv, a); - store_atomic8(pv + 8, b); - return; - } - break; + store_atomic8(pv, a); + store_atomic8(pv + 8, b); + return; case -MO_64: if (HAVE_CMPXCHG128) { uint64_t val_le; --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774150; cv=none; d=zohomail.com; s=zohoarc; b=EzoJ83geOXMEyCh7czwu5GQ2/S1xQHuOmebZfJZWjxQiZvAtcEQrPWY5G5GfZUpYvVNsnf5rwkpe4TJPHfzremBSdzLcxwqTML1gS52SwpLNZPuRH+rBrzsXM9xR4zUyCN4G1/tmHhX/eS96CVDX0DOOxcbVFc9p8dBKl+dFReU= ARC-Message-Signature: i=1; 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Sun, 18 Jan 2026 14:09:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 41/54] accel/tcg: Drop CONFIG_ATOMIC64 test from translator.c Date: Mon, 19 Jan 2026 09:04:01 +1100 Message-ID: <20260118220414.8177-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774152637158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/translator.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 034f2f359e..f3eddcbb2e 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -352,15 +352,13 @@ static bool translator_ld(CPUArchState *env, DisasCon= textBase *db, return true; } break; -#ifdef CONFIG_ATOMIC64 case 8: if (QEMU_IS_ALIGNED(pc, 8)) { - uint64_t t =3D qatomic_read__nocheck((uint64_t *)host); + uint64_t t =3D qatomic_read((uint64_t *)host); stq_he_p(dest, t); return true; } break; -#endif } /* Unaligned or partial read from the second page is not atomic. */ memcpy(dest, host, len); --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774150; cv=none; d=zohomail.com; s=zohoarc; b=LDM26LhbCzNbZGYrjmHs0z2zvi1KQkT1KFYjUAA3GStwgqe68Hy0e7flU/JsbYHhTSQk7P3/HOakSrm5DoLBdvaERnKr7ADyZYIlbTFgwmIZ+unsbGjsAK10TLMzk+huyh3Ojixm8obhbyQh7dV3JKIhQhosXKl5oobRIJO1geY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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Sun, 18 Jan 2026 14:09:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 42/54] linux-user/arm: Drop CONFIG_ATOMIC64 test Date: Mon, 19 Jan 2026 09:04:02 +1100 Message-ID: <20260118220414.8177-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774152643158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- linux-user/arm/cpu_loop.c | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-) diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index cd89b7d6f5..40aefc4c1d 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -146,25 +146,8 @@ static void arm_kernel_cmpxchg64_helper(CPUARMState *e= nv) /* Swap if host !=3D guest endianness, for the host cmpxchg below */ oldval =3D tswap64(oldval); newval =3D tswap64(newval); - -#ifdef CONFIG_ATOMIC64 - val =3D qatomic_cmpxchg__nocheck(host_addr, oldval, newval); + val =3D qatomic_cmpxchg(host_addr, oldval, newval); cpsr =3D (val =3D=3D oldval) * CPSR_C; -#else - /* - * This only works between threads, not between processes, but since - * the host has no 64-bit cmpxchg, it is the best that we can do. - */ - start_exclusive(); - val =3D *host_addr; - if (val =3D=3D oldval) { - *host_addr =3D newval; - cpsr =3D CPSR_C; - } else { - cpsr =3D 0; - } - end_exclusive(); -#endif mmap_unlock(); =20 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr); --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774167; cv=none; d=zohomail.com; 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Sun, 18 Jan 2026 14:09:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 43/54] linux-user/hppa: Drop CONFIG_ATOMIC64 test Date: Mon, 19 Jan 2026 09:04:03 +1100 Message-ID: <20260118220414.8177-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774168771158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- linux-user/hppa/cpu_loop.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 356cb48acc..e5c0f52d94 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -83,20 +83,8 @@ static abi_ulong hppa_lws(CPUHPPAState *env) uint64_t o64, n64, r64; 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Sun, 18 Jan 2026 14:09:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 44/54] target/arm: Drop CONFIG_ATOMIC64 tests Date: Mon, 19 Jan 2026 09:04:04 +1100 Message-ID: <20260118220414.8177-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774198798158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/ptw.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a986dc66f6..8b8dc09e72 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -757,20 +757,12 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Trans= late *ptw, =20 if (likely(host)) { /* Page tables are in RAM, and we have the host address. */ -#ifdef CONFIG_ATOMIC64 - data =3D qatomic_read__nocheck((uint64_t *)host); + data =3D qatomic_read((uint64_t *)host); if (ptw->out_be) { data =3D be64_to_cpu(data); } else { data =3D le64_to_cpu(data); } -#else - if (ptw->out_be) { - data =3D ldq_be_p(host); - } else { - data =3D ldq_le_p(host); - } -#endif } else { /* Page tables are in MMIO. */ MemTxAttrs attrs =3D { @@ -798,7 +790,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t= old_val, uint64_t new_val, S1Translate *ptw, ARMMMUFaultInfo *fi) { -#if defined(CONFIG_ATOMIC64) && defined(CONFIG_TCG) +#ifdef CONFIG_TCG uint64_t cur_val; void *host =3D ptw->out_host; =20 @@ -903,17 +895,17 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64= _t old_val, if (ptw->out_be) { old_val =3D cpu_to_be64(old_val); new_val =3D cpu_to_be64(new_val); - cur_val =3D qatomic_cmpxchg__nocheck((uint64_t *)host, old_val, ne= w_val); + cur_val =3D qatomic_cmpxchg((uint64_t *)host, old_val, new_val); cur_val =3D be64_to_cpu(cur_val); } else { old_val =3D cpu_to_le64(old_val); new_val =3D cpu_to_le64(new_val); - cur_val =3D qatomic_cmpxchg__nocheck((uint64_t *)host, old_val, ne= w_val); + cur_val =3D qatomic_cmpxchg((uint64_t *)host, old_val, new_val); cur_val =3D le64_to_cpu(cur_val); } return cur_val; #else - /* AArch32 does not have FEAT_HADFS; non-TCG guests only use debug-mod= e. */ + /* Non-TCG guests only use debug-mode. */ g_assert_not_reached(); #endif } --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774197; cv=none; d=zohomail.com; s=zohoarc; b=N4mWjSVlC9ZN4EFg49d68QO7HOOYw2g7N8HzFhWwkDQ14UfF5x5SMyocPcLI2e/6/EhLxNINLMxOhPbx/JbT7WT9O6q6AZ4e568bo+9nyjWc4/8ahm1rx9umbxMA4Q9WU7igTYjw89YHhFMCr7qbWEcskVPOHLsc2xJsKPPvPfI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768774197; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Sun, 18 Jan 2026 14:09:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 45/54] target/hppa: Drop CONFIG_ATOMIC64 test Date: Mon, 19 Jan 2026 09:04:05 +1100 Message-ID: <20260118220414.8177-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774198781158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/hppa/op_helper.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 65faf03cd0..f961046e4c 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -74,7 +74,6 @@ static void atomic_store_mask64(CPUHPPAState *env, target= _ulong addr, uint64_t val, uint64_t mask, int size, uintptr_t ra) { -#ifdef CONFIG_ATOMIC64 int mmu_idx =3D cpu_mmu_index(env_cpu(env), 0); uint64_t old, new, cmp, *haddr; void *vaddr; @@ -88,15 +87,12 @@ static void atomic_store_mask64(CPUHPPAState *env, targ= et_ulong addr, old =3D *haddr; while (1) { new =3D be32_to_cpu((cpu_to_be32(old) & ~mask) | (val & mask)); - cmp =3D qatomic_cmpxchg__nocheck(haddr, old, new); + cmp =3D qatomic_cmpxchg(haddr, old, new); if (cmp =3D=3D old) { return; } old =3D cmp; } -#else - cpu_loop_exit_atomic(env_cpu(env), ra); -#endif } =20 static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ulong v= al, --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774204; cv=none; d=zohomail.com; s=zohoarc; b=GxRMXTWVa+CiE6I2DsLyHQ+wH0qzYbtXeCTmTXv9TXu67j9M5Nv45fKAPetaN4QCy58rySe3ch2Nx/e78OGjspHrQNTKTuP0Pw42GPlonwpdIf6cEKDVrQjFRH9pBYr7RucefyXIxWdNhelNBmXL3X/d/aEtO9vqTm6twbQFjkw= ARC-Message-Signature: i=1; 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Sun, 18 Jan 2026 14:09:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 46/54] target/m68k: Drop CONFIG_ATOMIC64 tests Date: Mon, 19 Jan 2026 09:04:06 +1100 Message-ID: <20260118220414.8177-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774206811158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/m68k/op_helper.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index a27e2bcfbc..f7df83c850 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -816,14 +816,11 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs= , uint32_t a1, uint32_t a2, uint32_t u2 =3D env->dregs[Du2]; uint32_t l1, l2; uintptr_t ra =3D GETPC(); -#if defined(CONFIG_ATOMIC64) int mmu_idx =3D cpu_mmu_index(env_cpu(env), 0); MemOpIdx oi =3D make_memop_idx(MO_BEUQ, mmu_idx); -#endif =20 if (parallel) { /* We're executing in a parallel context -- must be atomic. */ -#ifdef CONFIG_ATOMIC64 uint64_t c, u, l; if ((a1 & 7) =3D=3D 0 && a2 =3D=3D a1 + 4) { c =3D deposit64(c2, 32, 32, c1); @@ -837,9 +834,7 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs, = uint32_t a1, uint32_t a2, l =3D cpu_atomic_cmpxchgq_be_mmu(env, a2, c, u, oi, ra); l2 =3D l >> 32; l1 =3D l; - } else -#endif - { + } else { /* Tell the main loop we need to serialize this insn. */ cpu_loop_exit_atomic(env_cpu(env), ra); } --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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0 : fc + 2 > max) || (HAVE_ATOMIC128_RW ? 0 : sc > max)) { cpu_loop_exit_atomic(env_cpu(env), ra); @@ -1856,12 +1854,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t= r3, uint64_t a1, uint64_t ov; =20 if (parallel) { -#ifdef CONFIG_ATOMIC64 ov =3D cpu_atomic_cmpxchgq_be_mmu(env, a1, cv, nv, oi8, ra= ); -#else - /* Note that we asserted !parallel above. */ - g_assert_not_reached(); -#endif } else { ov =3D cpu_ldq_mmu(env, a1, oi8, ra); cpu_stq_mmu(env, a1, (ov =3D=3D cv ? nv : ov), oi8, ra); --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774186; cv=none; d=zohomail.com; s=zohoarc; b=cbgEPPkON48eh2A9aAptz+EnsFbnrTn4Q7C9qz9kbj7ZjGOb8My1GdZ91eyCqOG94fv1ZrSrGEKcD5xeUwMvfalrR6LDAS7ZjXjBstdMDBaJMSF3VkOWrHxjY7nV3hh93tvZ4rtC/oZhm/n2Rioht/eDrsp5VueD0WHAIPp162o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768774186; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3agDLlzr0Vtwe03Q0XoUK7yGFQ6c06YyHNp7mf4+w4w=; b=JvUDKrIwNpEtHxB8cr8nhzgvHAWDZ/yH14KevEQeX4ZvgD7CX4yRBrzpdnwr7aNlKfdb1F+btvQ+uF7ffP89QQeG4G/SzE/r6X7raHpOn2XbhL4/ltFsAHYfrvnPaH49aZ0UOIH9qqRtjU8OxUhbnuZWaa8x2OnF60EmylA4dl8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768774186281279.41328045515934; Sun, 18 Jan 2026 14:09:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhaxd-0000oC-Mk; Sun, 18 Jan 2026 17:09:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhaxT-0000EN-3r for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:09:19 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhaxR-0001dT-NG for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:09:18 -0500 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-2a0c09bb78cso27711075ad.0 for ; Sun, 18 Jan 2026 14:09:17 -0800 (PST) Received: from stoup.. ([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7190ab921sm73298205ad.8.2026.01.18.14.09.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:09:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768774156; x=1769378956; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3agDLlzr0Vtwe03Q0XoUK7yGFQ6c06YyHNp7mf4+w4w=; b=pBxiu2TyGqVMslBxChp7GSqvuS0pJFUFzWaoclxkG1Bi3LFZqgBLwv+ySwUaD3ggyO jsnd/dWFjxsuFLQOAu/ZuHqr5djEQjf41NORelDZfz/JwZ6OmE/wS0/iuSHehU2h2dCY i8KJsLGE53LAaEE0cytRyqR/eN/rU3UvYQXEcEsoquh9PY1L4UPZoGFYh2BnC6byvtkZ a7g/l+05PL02QHqj/kYZXPccWCPWDqSIWaOo9hxzxqpWLlypVnPFBHQH6gpWKrkmuv2j CRH1PLkK+BqjW8uW8EYD9+fiTLZ3KhQ6dus9JPq4cGuA4gEZ991ha3Eixznw8E4NTnR3 N+ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768774156; x=1769378956; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=3agDLlzr0Vtwe03Q0XoUK7yGFQ6c06YyHNp7mf4+w4w=; b=ob+zzdjVLtxB0WBFx1jbLK16v8l0Uaa/5jDZvpJCxrVrV6kOHzcC1dlS4N6SjqM1FS RTWlmlHw2yVyAAp4vfaozQJ6ZQvctccNgvs8oPrdLMP4C43BK3sja+k/RC8QejeKYwTU 5c75Xr41R/Mpot8vYC77rqlit3b/u7zzNFKJf5T107pTgDEROAYEBpc/eYYO2FsIiCLI t8woajEhbc5iQ8Y9w4GG7enusVVIlOEhY9hQAQXVqWtZLre8skSn2BYkO4PS7KBINY2Y xJbxNfG0vuyIQKY28dwk2or9P2IywuBi1aNuN6lVT93+K+aBd2YomKY5d8IuEF9Rd2un yXVQ== X-Gm-Message-State: AOJu0YyF22uSs7PYxJXAUCw1zDRJF9tNs35U51/UxvReWGenfDNBoepX 6KfIDhmnWEDda11b9OlgcrsW/pYDH6h8jfEZ3tJ/1nRwvB2xOiLLykEzY9ZmwGGYyRVc00hG06S dWZimFTHkJg== X-Gm-Gg: AY/fxX4QlrrszFBUWToJn3iKaW2UAB5wwUs8TEUKIeeEePn2UT4ISjS7N6Wptkfafur YdHpOy/ckYXNU3YcRqqHkhBV5+ddg/d5acSIdFI9B0vOqT1z1nD5THEkvn4RbPymCKGI/WgahTh AZ15gMLVcfH76sRQB4Y9W2tESTEMFtX8J3MKpSrUo0NU1wBXv8j6syDjNEHd9XZrkaY/32AmG6D YaRoNBieiBcwNxeWhTDaLfDT3zeo7EfYZI5eQt8fEs19k70zC1RyhoK+cNAkpDNDxg+/M/gMMNK JRr1SGmpl6+7uwU44G0i2exM2UpJOwg/K4Ke/xs7lGq/LNcQwWNA/mpqRC5GhJljvR3HOHm73r+ qKnumcSAeEyr/NUgManggb1iZa0Xg/B3VS+Dn6G6Bk7UvIbJBGDMTD+LcIMYuJnYbxPlYS3Lb8y as9bhkCa+VF9ZJn5kXcg== X-Received: by 2002:a17:902:f650:b0:2a3:ccfc:4de5 with SMTP id d9443c01a7336-2a700978f8bmr133427955ad.5.1768774156272; Sun, 18 Jan 2026 14:09:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 48/54] target/s390x: Simplify atomicity check in do_csst Date: Mon, 19 Jan 2026 09:04:08 +1100 Message-ID: <20260118220414.8177-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774186755158500 Content-Type: text/plain; charset="utf-8" We should have used MO_{32,64} from the start, rather than raw integer constants. However, now that the CONFIG_ATOMIC64 test has been removed, we can remove the 'max' variable and simplify the two blocks. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 0b8b6d3bbb..2a79a789f6 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1813,13 +1813,10 @@ static uint32_t do_csst(CPUS390XState *env, uint32_= t r3, uint64_t a1, * restart early if we can't support either operation that is supposed * to be atomic. */ - if (parallel) { - uint32_t max =3D 2; - max =3D 3; - if ((HAVE_CMPXCHG128 ? 0 : fc + 2 > max) || - (HAVE_ATOMIC128_RW ? 0 : sc > max)) { - cpu_loop_exit_atomic(env_cpu(env), ra); - } + if (parallel && + ((!HAVE_CMPXCHG128 && fc + 2 > MO_64) || + (!HAVE_ATOMIC128_RW && sc > MO_64))) { + cpu_loop_exit_atomic(env_cpu(env), ra); } =20 /* --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774189; cv=none; d=zohomail.com; s=zohoarc; b=fZJgqVT1aJ93WfHIFg0H3LBWO0rvglxVKXbXkJCLuCHi+cywaQfx1NGZGeg23wlA0pkEN5OOUJBDQsJVKUujFXJtYFuP4H+e+j8FFPgZn71D2wpTQ0BdV09Fkt2YW4yLn1oSGRgmOjjFH+8uo8Y04fdKWkKMjtvcdQgTssvVNQ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768774189; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Cmt/DkSN995wvdP0a06/sQl06r6QbkCd5PkO/R0OVlU=; b=KmZekvfjqcGuZPKvjdZ5GOcjD/WS2VxTIDl11KlN8FvC49u413q5+E2jVxX8yQrAD9yCmqa1bx+f7Gtl2RLmkTa3bhGVFQlHqsSElVkksVYJtLAwqut8YLu1Ly05sEj+f9t/5epzF0cHguZnj+JsSLdXsCRICoJRsWkD9cxyDtw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768774189435940.9611373889177; Sun, 18 Jan 2026 14:09:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhaxf-00016R-RE; Sun, 18 Jan 2026 17:09:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhaxW-0000WC-Ve for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:09:24 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhaxU-0001dr-Fz for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:09:22 -0500 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-29f1bc40b35so38117935ad.2 for ; Sun, 18 Jan 2026 14:09:19 -0800 (PST) Received: from stoup.. ([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7190ab921sm73298205ad.8.2026.01.18.14.09.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:09:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768774159; x=1769378959; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Cmt/DkSN995wvdP0a06/sQl06r6QbkCd5PkO/R0OVlU=; b=NEFG7HtB/KLo1XfzJTwh/7lTIThctWvOlzgSQH+4bSf8Vhb7e84NhO4O2NqnHqQDbi 7NUOiP/6B9ryktqGf+pqUs7axeLORpqIwByc/azVt/8HYAMPoQlBRxjhvKzUQS3jmO6i 49lWwNGFCvtMWm8KMptjSMi4G94bhS9J8JiOYoe+/1qzSGDJGdCKo7KExwFh7iKk6BK9 Kwk2xSXG+WoKLdNMmzlaFn8qJjeInArrUQ3lf8sn8K4AGS4AmZJhIyoQUzfJ5NG7OTPG jD/lwLc1EvhWY/FoXds0WmW8+3SH6eB4HiwXP4f5TSMV2/xHmjhKcY+r48L2IdNJCJAG shTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768774159; x=1769378959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Cmt/DkSN995wvdP0a06/sQl06r6QbkCd5PkO/R0OVlU=; b=SGz8C2sIQekDMJdTlofNdf90sgKPW1prj1M9gTFraBsdXDL6zFfum2HnJcats9JLuE n+pOxiFeREpzIVYIgRrF5V4YQtkQ4/HNcIOwVpkmaxXBecjhnckG+sOl3/PMUFYmF5eF JYVgJr57J/9O4lGUnrY541yqI818hGdz9V5KAanh8m62ARFFk6CSHVgRh86MUsTLo88j XFx05Pv1ZLuQTLSspGVrf6wUh+DVVTjZ6THVnu1KL0t+qU0jPKJT1EVc01kBezsDCE4k CQ+L5QtIfZRSIIZCkJIMBhi6H4TuUu4sl4Jz2vs/oaDpfWAVPJY1tuNMznRE+wnI9dR7 qFhg== X-Gm-Message-State: AOJu0YwR/V2M1CMO0ibj7RyutuJ9Ku7wQ0tEicHIiaBlPZPHHZ7N8fm7 eJBD0/kMuHtKQFexoLXBRn5V513AG+810wfRbvvxgA6BsoN6a242MKbJH7H618q/bJUoxR7GX8a NSCKCGNMxBw== X-Gm-Gg: AY/fxX5w3HWIFytqqcIZs5zj8fE2BTrbMs2Caw9IdxvS3pbv0xP/g3RI+mdElYznYQB yGAxfv0fsjAC0mXVkLFdBwE34qwr8lYq/0j8CUXq+j/syDlnlSdYKrYlQOhRibHlTxiH6PhvfEH RhbNk1nmOUj50AAIeGs+9ovAO+wXr+fj50lHbnQJPmZerWz3d3GzHRaoJYMKZoVZ4uuhYtQG7Pr c6h+tMxnxS5OwkZALZEEL7lvta9039BN0GrBq2dgb7kSBKk60BudKWegsgJJ6//wBkwBh1r8Sw4 LYGxVLoMnlOsJHnQ9/jdFGqA2NSaPkcawGJXMnaBTxqqCiS7bbpd5lXziyr6LcoTdjn8MVPB7c3 6UwSLqzKxphL76iefK7bqPaxKvYfLmEV5mirolo5ab/egelAS/Vn0umHXex7qyzPcCabB4RHwrv 7BfexgvGX4d5s82KL4Mw== X-Received: by 2002:a17:902:ce0a:b0:2a3:e7b6:ab53 with SMTP id d9443c01a7336-2a717554c25mr93866155ad.22.1768774158905; Sun, 18 Jan 2026 14:09:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 49/54] migration: Drop use of Stat64 Date: Mon, 19 Jan 2026 09:04:09 +1100 Message-ID: <20260118220414.8177-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774190916158500 The Stat64 structure is an aid for 32-bit hosts, and is no longer required. Use plain 64-bit types. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- migration/migration-stats.h | 36 ++++++++++++++++------------------- migration/cpu-throttle.c | 4 ++-- migration/migration-stats.c | 16 ++++++++-------- migration/migration.c | 24 +++++++++++------------ migration/multifd-nocomp.c | 2 +- migration/multifd-zero-page.c | 4 ++-- migration/multifd.c | 12 ++++-------- migration/qemu-file.c | 6 +++--- migration/ram.c | 30 ++++++++++++++--------------- migration/rdma.c | 8 ++++---- 10 files changed, 67 insertions(+), 75 deletions(-) diff --git a/migration/migration-stats.h b/migration/migration-stats.h index 05290ade76..c0f50144c9 100644 --- a/migration/migration-stats.h +++ b/migration/migration-stats.h @@ -13,8 +13,6 @@ #ifndef QEMU_MIGRATION_STATS_H #define QEMU_MIGRATION_STATS_H =20 -#include "qemu/stats64.h" - /* * Amount of time to allocate to each "chunk" of bandwidth-throttled * data. @@ -29,9 +27,7 @@ =20 /* * These are the ram migration statistic counters. It is loosely - * based on MigrationStats. We change to Stat64 any counter that - * needs to be updated using atomic ops (can be accessed by more than - * one thread). + * based on MigrationStats. */ typedef struct { /* @@ -41,66 +37,66 @@ typedef struct { * since last iteration, not counting what the guest has dirtied * since we synchronized bitmaps. */ - Stat64 dirty_bytes_last_sync; + uint64_t dirty_bytes_last_sync; /* * Number of pages dirtied per second. */ - Stat64 dirty_pages_rate; + uint64_t dirty_pages_rate; /* * Number of times we have synchronized guest bitmaps. */ - Stat64 dirty_sync_count; + uint64_t dirty_sync_count; /* * Number of times zero copy failed to send any page using zero * copy. */ - Stat64 dirty_sync_missed_zero_copy; + uint64_t dirty_sync_missed_zero_copy; /* * Number of bytes sent at migration completion stage while the * guest is stopped. */ - Stat64 downtime_bytes; + uint64_t downtime_bytes; /* * Number of bytes sent through multifd channels. */ - Stat64 multifd_bytes; + uint64_t multifd_bytes; /* * Number of pages transferred that were not full of zeros. */ - Stat64 normal_pages; + uint64_t normal_pages; /* * Number of bytes sent during postcopy. */ - Stat64 postcopy_bytes; + uint64_t postcopy_bytes; /* * Number of postcopy page faults that we have handled during * postcopy stage. */ - Stat64 postcopy_requests; + uint64_t postcopy_requests; /* * Number of bytes sent during precopy stage. */ - Stat64 precopy_bytes; + uint64_t precopy_bytes; /* * Number of bytes transferred with QEMUFile. */ - Stat64 qemu_file_transferred; + uint64_t qemu_file_transferred; /* * Amount of transferred data at the start of current cycle. */ - Stat64 rate_limit_start; + uint64_t rate_limit_start; /* * Maximum amount of data we can send in a cycle. */ - Stat64 rate_limit_max; + uint64_t rate_limit_max; /* * Number of bytes sent through RDMA. */ - Stat64 rdma_bytes; + uint64_t rdma_bytes; /* * Number of pages transferred that were full of zeros. */ - Stat64 zero_pages; + uint64_t zero_pages; } MigrationAtomicStats; =20 extern MigrationAtomicStats mig_stats; diff --git a/migration/cpu-throttle.c b/migration/cpu-throttle.c index 0642e6bdea..3b4d4aea52 100644 --- a/migration/cpu-throttle.c +++ b/migration/cpu-throttle.c @@ -134,7 +134,7 @@ int cpu_throttle_get_percentage(void) =20 void cpu_throttle_dirty_sync_timer_tick(void *opaque) { - uint64_t sync_cnt =3D stat64_get(&mig_stats.dirty_sync_count); + uint64_t sync_cnt =3D qatomic_read(&mig_stats.dirty_sync_count); =20 /* * The first iteration copies all memory anyhow and has no @@ -153,7 +153,7 @@ void cpu_throttle_dirty_sync_timer_tick(void *opaque) } =20 end: - throttle_dirty_sync_count_prev =3D stat64_get(&mig_stats.dirty_sync_co= unt); + throttle_dirty_sync_count_prev =3D qatomic_read(&mig_stats.dirty_sync_= count); =20 timer_mod(throttle_dirty_sync_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL_RT) + diff --git a/migration/migration-stats.c b/migration/migration-stats.c index f690b98a03..3f17b6ac5c 100644 --- a/migration/migration-stats.c +++ b/migration/migration-stats.c @@ -11,7 +11,7 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/stats64.h" +#include "qemu/atomic.h" #include "qemu-file.h" #include "trace.h" #include "migration-stats.h" @@ -29,7 +29,7 @@ bool migration_rate_exceeded(QEMUFile *f) return false; } =20 - uint64_t rate_limit_start =3D stat64_get(&mig_stats.rate_limit_start); + uint64_t rate_limit_start =3D qatomic_read(&mig_stats.rate_limit_start= ); uint64_t rate_limit_current =3D migration_transferred_bytes(); uint64_t rate_limit_used =3D rate_limit_current - rate_limit_start; =20 @@ -41,7 +41,7 @@ bool migration_rate_exceeded(QEMUFile *f) =20 uint64_t migration_rate_get(void) { - return stat64_get(&mig_stats.rate_limit_max); + return qatomic_read(&mig_stats.rate_limit_max); } =20 #define XFER_LIMIT_RATIO (1000 / BUFFER_DELAY) @@ -51,19 +51,19 @@ void migration_rate_set(uint64_t limit) /* * 'limit' is per second. But we check it each BUFFER_DELAY milliseco= nds. */ - stat64_set(&mig_stats.rate_limit_max, limit / XFER_LIMIT_RATIO); + qatomic_set(&mig_stats.rate_limit_max, limit / XFER_LIMIT_RATIO); } =20 void migration_rate_reset(void) { - stat64_set(&mig_stats.rate_limit_start, migration_transferred_bytes()); + qatomic_set(&mig_stats.rate_limit_start, migration_transferred_bytes()= ); } =20 uint64_t migration_transferred_bytes(void) { - uint64_t multifd =3D stat64_get(&mig_stats.multifd_bytes); - uint64_t rdma =3D stat64_get(&mig_stats.rdma_bytes); - uint64_t qemu_file =3D stat64_get(&mig_stats.qemu_file_transferred); + uint64_t multifd =3D qatomic_read(&mig_stats.multifd_bytes); + uint64_t rdma =3D qatomic_read(&mig_stats.rdma_bytes); + uint64_t qemu_file =3D qatomic_read(&mig_stats.qemu_file_transferred); =20 trace_migration_transferred_bytes(qemu_file, multifd, rdma); return qemu_file + multifd + rdma; diff --git a/migration/migration.c b/migration/migration.c index 1c34d8d432..1bcde301f7 100644 --- a/migration/migration.c +++ b/migration/migration.c @@ -1266,22 +1266,22 @@ static void populate_ram_info(MigrationInfo *info, = MigrationState *s) info->ram =3D g_malloc0(sizeof(*info->ram)); info->ram->transferred =3D migration_transferred_bytes(); info->ram->total =3D ram_bytes_total(); - info->ram->duplicate =3D stat64_get(&mig_stats.zero_pages); - info->ram->normal =3D stat64_get(&mig_stats.normal_pages); + info->ram->duplicate =3D qatomic_read(&mig_stats.zero_pages); + info->ram->normal =3D qatomic_read(&mig_stats.normal_pages); info->ram->normal_bytes =3D info->ram->normal * page_size; info->ram->mbps =3D s->mbps; info->ram->dirty_sync_count =3D - stat64_get(&mig_stats.dirty_sync_count); + qatomic_read(&mig_stats.dirty_sync_count); info->ram->dirty_sync_missed_zero_copy =3D - stat64_get(&mig_stats.dirty_sync_missed_zero_copy); + qatomic_read(&mig_stats.dirty_sync_missed_zero_copy); info->ram->postcopy_requests =3D - stat64_get(&mig_stats.postcopy_requests); + qatomic_read(&mig_stats.postcopy_requests); info->ram->page_size =3D page_size; - info->ram->multifd_bytes =3D stat64_get(&mig_stats.multifd_bytes); + info->ram->multifd_bytes =3D qatomic_read(&mig_stats.multifd_bytes); info->ram->pages_per_second =3D s->pages_per_second; - info->ram->precopy_bytes =3D stat64_get(&mig_stats.precopy_bytes); - info->ram->downtime_bytes =3D stat64_get(&mig_stats.downtime_bytes); - info->ram->postcopy_bytes =3D stat64_get(&mig_stats.postcopy_bytes); + info->ram->precopy_bytes =3D qatomic_read(&mig_stats.precopy_bytes); + info->ram->downtime_bytes =3D qatomic_read(&mig_stats.downtime_bytes); + info->ram->postcopy_bytes =3D qatomic_read(&mig_stats.postcopy_bytes); =20 if (migrate_xbzrle()) { info->xbzrle_cache =3D g_malloc0(sizeof(*info->xbzrle_cache)); @@ -1302,7 +1302,7 @@ static void populate_ram_info(MigrationInfo *info, Mi= grationState *s) if (s->state !=3D MIGRATION_STATUS_COMPLETED) { info->ram->remaining =3D ram_bytes_remaining(); info->ram->dirty_pages_rate =3D - stat64_get(&mig_stats.dirty_pages_rate); + qatomic_read(&mig_stats.dirty_pages_rate); } =20 if (migrate_dirty_limit() && dirtylimit_in_service()) { @@ -3420,10 +3420,10 @@ static void migration_update_counters(MigrationStat= e *s, * if we haven't sent anything, we don't want to * recalculate. 10000 is a small enough number for our purposes */ - if (stat64_get(&mig_stats.dirty_pages_rate) && + if (qatomic_read(&mig_stats.dirty_pages_rate) && transferred > 10000) { s->expected_downtime =3D - stat64_get(&mig_stats.dirty_bytes_last_sync) / expected_bw_per= _ms; + qatomic_read(&mig_stats.dirty_bytes_last_sync) / expected_bw_p= er_ms; } =20 migration_rate_reset(); diff --git a/migration/multifd-nocomp.c b/migration/multifd-nocomp.c index b48eae3d86..9be79b3b8e 100644 --- a/migration/multifd-nocomp.c +++ b/migration/multifd-nocomp.c @@ -141,7 +141,7 @@ static int multifd_nocomp_send_prepare(MultiFDSendParam= s *p, Error **errp) return -1; } =20 - stat64_add(&mig_stats.multifd_bytes, p->packet_len); + qatomic_add(&mig_stats.multifd_bytes, p->packet_len); } =20 return 0; diff --git a/migration/multifd-zero-page.c b/migration/multifd-zero-page.c index 4cde868159..00c330416a 100644 --- a/migration/multifd-zero-page.c +++ b/migration/multifd-zero-page.c @@ -77,8 +77,8 @@ void multifd_send_zero_page_detect(MultiFDSendParams *p) pages->normal_num =3D i; =20 out: - stat64_add(&mig_stats.normal_pages, pages->normal_num); - stat64_add(&mig_stats.zero_pages, pages->num - pages->normal_num); + qatomic_add(&mig_stats.normal_pages, pages->normal_num); + qatomic_add(&mig_stats.zero_pages, pages->num - pages->normal_num); } =20 void multifd_recv_zero_page_process(MultiFDRecvParams *p) diff --git a/migration/multifd.c b/migration/multifd.c index bf6da85af8..c9d4a67a46 100644 --- a/migration/multifd.c +++ b/migration/multifd.c @@ -58,10 +58,6 @@ struct { * operations on both 32bit / 64 bits hosts. It means on 32bit systems * multifd will overflow the packet_num easier, but that should be * fine. - * - * Another option is to use QEMU's Stat64 then it'll be 64 bits on all - * hosts, however so far it does not support atomic fetch_add() yet. - * Make it easy for now. */ uintptr_t packet_num; /* @@ -174,7 +170,7 @@ static int multifd_send_initial_packet(MultiFDSendParam= s *p, Error **errp) if (ret !=3D 0) { return -1; } - stat64_add(&mig_stats.multifd_bytes, size); + qatomic_add(&mig_stats.multifd_bytes, size); return 0; } =20 @@ -607,7 +603,7 @@ static int multifd_zero_copy_flush(QIOChannel *c) return -1; } if (ret =3D=3D 1) { - stat64_add(&mig_stats.dirty_sync_missed_zero_copy, 1); + qatomic_add(&mig_stats.dirty_sync_missed_zero_copy, 1); } =20 return ret; @@ -735,7 +731,7 @@ static void *multifd_send_thread(void *opaque) break; } =20 - stat64_add(&mig_stats.multifd_bytes, total_size); + qatomic_add(&mig_stats.multifd_bytes, total_size); =20 p->next_packet_size =3D 0; multifd_send_data_clear(p->data); @@ -766,7 +762,7 @@ static void *multifd_send_thread(void *opaque) break; } /* p->next_packet_size will always be zero for a SYNC pack= et */ - stat64_add(&mig_stats.multifd_bytes, p->packet_len); + qatomic_add(&mig_stats.multifd_bytes, p->packet_len); } =20 qatomic_set(&p->pending_sync, MULTIFD_SYNC_NONE); diff --git a/migration/qemu-file.c b/migration/qemu-file.c index 4b5a409a80..8d82d94416 100644 --- a/migration/qemu-file.c +++ b/migration/qemu-file.c @@ -295,7 +295,7 @@ int qemu_fflush(QEMUFile *f) qemu_file_set_error_obj(f, -EIO, local_error); } else { uint64_t size =3D iov_size(f->iov, f->iovcnt); - stat64_add(&mig_stats.qemu_file_transferred, size); + qatomic_add(&mig_stats.qemu_file_transferred, size); } =20 qemu_iovec_release_ram(f); @@ -552,7 +552,7 @@ void qemu_put_buffer_at(QEMUFile *f, const uint8_t *buf= , size_t buflen, return; } =20 - stat64_add(&mig_stats.qemu_file_transferred, buflen); + qatomic_add(&mig_stats.qemu_file_transferred, buflen); } =20 =20 @@ -785,7 +785,7 @@ int coroutine_mixed_fn qemu_get_byte(QEMUFile *f) =20 uint64_t qemu_file_transferred(QEMUFile *f) { - uint64_t ret =3D stat64_get(&mig_stats.qemu_file_transferred); + uint64_t ret =3D qatomic_read(&mig_stats.qemu_file_transferred); int i; =20 g_assert(qemu_file_is_writable(f)); diff --git a/migration/ram.c b/migration/ram.c index 04958c5603..fc7ece2c1a 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -479,11 +479,11 @@ uint64_t ram_bytes_remaining(void) void ram_transferred_add(uint64_t bytes) { if (runstate_is_running()) { - stat64_add(&mig_stats.precopy_bytes, bytes); + qatomic_add(&mig_stats.precopy_bytes, bytes); } else if (migration_in_postcopy()) { - stat64_add(&mig_stats.postcopy_bytes, bytes); + qatomic_add(&mig_stats.postcopy_bytes, bytes); } else { - stat64_add(&mig_stats.downtime_bytes, bytes); + qatomic_add(&mig_stats.downtime_bytes, bytes); } } =20 @@ -605,7 +605,7 @@ static void xbzrle_cache_zero_page(ram_addr_t current_a= ddr) /* We don't care if this fails to allocate a new cache page * as long as it updated an old one */ cache_insert(XBZRLE.cache, current_addr, XBZRLE.zero_target_page, - stat64_get(&mig_stats.dirty_sync_count)); + qatomic_read(&mig_stats.dirty_sync_count)); } =20 #define ENCODING_FLAG_XBZRLE 0x1 @@ -631,7 +631,7 @@ static int save_xbzrle_page(RAMState *rs, PageSearchSta= tus *pss, int encoded_len =3D 0, bytes_xbzrle; uint8_t *prev_cached_page; QEMUFile *file =3D pss->pss_channel; - uint64_t generation =3D stat64_get(&mig_stats.dirty_sync_count); + uint64_t generation =3D qatomic_read(&mig_stats.dirty_sync_count); =20 if (!cache_is_cached(XBZRLE.cache, current_addr, generation)) { xbzrle_counters.cache_miss++; @@ -1035,9 +1035,9 @@ uint64_t ram_pagesize_summary(void) =20 uint64_t ram_get_total_transferred_pages(void) { - return stat64_get(&mig_stats.normal_pages) + - stat64_get(&mig_stats.zero_pages) + - xbzrle_counters.pages; + return (qatomic_read(&mig_stats.normal_pages) + + qatomic_read(&mig_stats.zero_pages) + + xbzrle_counters.pages); } =20 static void migration_update_rates(RAMState *rs, int64_t end_time) @@ -1045,7 +1045,7 @@ static void migration_update_rates(RAMState *rs, int6= 4_t end_time) uint64_t page_count =3D rs->target_page_count - rs->target_page_count_= prev; =20 /* calculate period counters */ - stat64_set(&mig_stats.dirty_pages_rate, + qatomic_set(&mig_stats.dirty_pages_rate, rs->num_dirty_pages_period * 1000 / (end_time - rs->time_last_bitmap_sync)); =20 @@ -1136,7 +1136,7 @@ static void migration_bitmap_sync(RAMState *rs, bool = last_stage) RAMBlock *block; int64_t end_time; =20 - stat64_add(&mig_stats.dirty_sync_count, 1); + qatomic_add(&mig_stats.dirty_sync_count, 1); =20 if (!rs->time_last_bitmap_sync) { rs->time_last_bitmap_sync =3D qemu_clock_get_ms(QEMU_CLOCK_REALTIM= E); @@ -1150,7 +1150,7 @@ static void migration_bitmap_sync(RAMState *rs, bool = last_stage) RAMBLOCK_FOREACH_NOT_IGNORED(block) { ramblock_sync_dirty_bitmap(rs, block); } - stat64_set(&mig_stats.dirty_bytes_last_sync, ram_bytes_remaini= ng()); + qatomic_set(&mig_stats.dirty_bytes_last_sync, ram_bytes_remain= ing()); } } =20 @@ -1173,7 +1173,7 @@ static void migration_bitmap_sync(RAMState *rs, bool = last_stage) rs->bytes_xfer_prev =3D migration_transferred_bytes(); } if (migrate_events()) { - uint64_t generation =3D stat64_get(&mig_stats.dirty_sync_count); + uint64_t generation =3D qatomic_read(&mig_stats.dirty_sync_count); qapi_event_send_migration_pass(generation); } } @@ -1232,7 +1232,7 @@ static int save_zero_page(RAMState *rs, PageSearchSta= tus *pss, return 0; } =20 - stat64_add(&mig_stats.zero_pages, 1); + qatomic_add(&mig_stats.zero_pages, 1); =20 if (migrate_mapped_ram()) { /* zero pages are not transferred with mapped-ram */ @@ -1291,7 +1291,7 @@ static int save_normal_page(PageSearchStatus *pss, RA= MBlock *block, } } ram_transferred_add(TARGET_PAGE_SIZE); - stat64_add(&mig_stats.normal_pages, 1); + qatomic_add(&mig_stats.normal_pages, 1); return 1; } =20 @@ -1943,7 +1943,7 @@ int ram_save_queue_pages(const char *rbname, ram_addr= _t start, ram_addr_t len, RAMBlock *ramblock; RAMState *rs =3D ram_state; =20 - stat64_add(&mig_stats.postcopy_requests, 1); + qatomic_add(&mig_stats.postcopy_requests, 1); RCU_READ_LOCK_GUARD(); =20 if (!rbname) { diff --git a/migration/rdma.c b/migration/rdma.c index 9e301cf917..cced173379 100644 --- a/migration/rdma.c +++ b/migration/rdma.c @@ -1936,8 +1936,8 @@ retry: * would think that head.len would be the more similar * thing to a correct value. */ - stat64_add(&mig_stats.zero_pages, - sge.length / qemu_target_page_size()); + qatomic_add(&mig_stats.zero_pages, + sge.length / qemu_target_page_size()); return 1; } =20 @@ -2045,7 +2045,7 @@ retry: } =20 set_bit(chunk, block->transit_bitmap); - stat64_add(&mig_stats.normal_pages, sge.length / qemu_target_page_size= ()); + qatomic_add(&mig_stats.normal_pages, sge.length / qemu_target_page_siz= e()); /* * We are adding to transferred the amount of data written, but no * overhead at all. I will assume that RDMA is magicaly and don't @@ -2055,7 +2055,7 @@ retry: * sizeof(send_wr) + sge.length * but this being RDMA, who knows. */ - stat64_add(&mig_stats.rdma_bytes, sge.length); + qatomic_add(&mig_stats.rdma_bytes, sge.length); ram_transferred_add(sge.length); rdma->total_writes++; =20 --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774182; cv=none; d=zohomail.com; s=zohoarc; b=BaK8y2r+jU/2xnX9ACK4ML8HPL8qg/w6rB5nX8LRPTbj5aBFxwhMAKC00XgW2nqxRYODpP2kkPCeE+cbm8GSlAfNqjUnzyHieSwI10vK6YSV5JjdirRJ1LajprTEYBSVjf/kWHWE0S6PJVhnBE7onL0Owv9Sy/hliE4xsYIsSek= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768774182; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0b6Gm0w9KlLs51qj052MnIFfJ9dUHou4Uw1pKozVZqU=; b=QKN5BCvHYlt6TP/D42GxZ7jBZI8yugsUqtPAgOEXfLQX3vOu3gxeK0WTcFr382EQ2Yk7+pCxlJDKpnllnps32PNajYz/zmhqnkIyvMKutiVGBIp9J4cnxmLl4lbYYompXxSteySemawiQtp77D3fZhsxlSNm8uaUj1de+DHeGaY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768774182282687.8810871951918; Sun, 18 Jan 2026 14:09:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhaxg-0001A0-Dv; Sun, 18 Jan 2026 17:09:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhaxY-0000WR-3j for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:09:24 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhaxW-0001e6-Ef for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:09:23 -0500 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-2a12ebe4b74so35821345ad.0 for ; Sun, 18 Jan 2026 14:09:21 -0800 (PST) Received: from stoup.. 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Use plain 64-bit types. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/block/block_int-common.h | 3 +-- block/io.c | 10 +++++++++- block/qapi.c | 2 +- 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/include/block/block_int-common.h b/include/block/block_int-com= mon.h index 6d0898e53d..9324af903d 100644 --- a/include/block/block_int-common.h +++ b/include/block/block_int-common.h @@ -30,7 +30,6 @@ #include "qemu/aiocb.h" #include "qemu/iov.h" #include "qemu/rcu.h" -#include "qemu/stats64.h" =20 #define BLOCK_FLAG_LAZY_REFCOUNTS 8 =20 @@ -1246,7 +1245,7 @@ struct BlockDriverState { QLIST_HEAD(, BdrvDirtyBitmap) dirty_bitmaps; =20 /* Offset after the highest byte written to */ - Stat64 wr_highest_offset; + uint64_t wr_highest_offset; =20 /* * If true, copy read backing sectors into image. Can be >1 if more diff --git a/block/io.c b/block/io.c index cace297f22..e8fb4ede4d 100644 --- a/block/io.c +++ b/block/io.c @@ -39,6 +39,7 @@ #include "qemu/main-loop.h" #include "system/replay.h" #include "qemu/units.h" +#include "qemu/atomic.h" =20 /* Maximum bounce buffer for copy-on-read and write zeroes, in bytes */ #define MAX_BOUNCE_BUFFER (32768 << BDRV_SECTOR_BITS) @@ -2044,7 +2045,14 @@ bdrv_co_write_req_finish(BdrvChild *child, int64_t o= ffset, int64_t bytes, if (req->bytes) { switch (req->type) { case BDRV_TRACKED_WRITE: - stat64_max(&bs->wr_highest_offset, offset + bytes); + { + uint64_t new =3D offset + bytes; + uint64_t old =3D qatomic_read(&bs->wr_highest_offset); + + while (old < new) { + old =3D qatomic_cmpxchg(&bs->wr_highest_offset, old, n= ew); + } + } /* fall through, to set dirty bits */ case BDRV_TRACKED_DISCARD: bdrv_set_dirty(bs, offset, bytes); diff --git a/block/qapi.c b/block/qapi.c index 9f5771e019..27e0ac6a32 100644 --- a/block/qapi.c +++ b/block/qapi.c @@ -651,7 +651,7 @@ bdrv_query_bds_stats(BlockDriverState *bs, bool blk_lev= el) s->node_name =3D g_strdup(bdrv_get_node_name(bs)); } =20 - s->stats->wr_highest_offset =3D stat64_get(&bs->wr_highest_offset); + s->stats->wr_highest_offset =3D qatomic_read(&bs->wr_highest_offset); =20 s->driver_specific =3D bdrv_get_specific_stats(bs); =20 --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774210; cv=none; d=zohomail.com; s=zohoarc; b=mXx84u/MYfLhf2iqxiFkobVkt9PQ7AFCZD2Lj8NsbUJWafuv7FEOVi3AXneXhyOr9StqY5aJyi0Wvlz7IUgxPj5fLN/BsKwaN2H4AH8fopvsqP16wCxOqBGJi94at3EDPS9jk5/FRsXqt0/2f5EmSUkzz8D/lChSPnEQaB4ATyM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768774210; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=lL29N2VWw0Lqbbdj3QFDL4vdVxUWKQ/hHfpVJMWA/Kc=; b=nXCTF677TcpWAbtpC1ji8XrgcBA3vl/GNt+hNYtHFkZ2qsiaGbf7XxTI6e+Gs1NvMYe9ZOFsACsdzXKLVwJWh48Jv92WO+nuOZhQd/ja9fQZQFPl9JBbLr9iHn0CdGak1E7f0wwC91S3BpZfgTy2fDuWl4cKRXKqkZepAOlkyJE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768774210176164.9703999650585; Sun, 18 Jan 2026 14:10:10 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhaxi-0001NV-D2; Sun, 18 Jan 2026 17:09:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhaxc-0000iT-Jc for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:09:28 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhaxZ-0001ed-5J for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:09:27 -0500 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-2a09d981507so26997055ad.1 for ; Sun, 18 Jan 2026 14:09:24 -0800 (PST) Received: from stoup.. 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/qemu/stats64.h | 199 ----------------------------------------- util/stats64.c | 148 ------------------------------ util/meson.build | 1 - 3 files changed, 348 deletions(-) delete mode 100644 include/qemu/stats64.h delete mode 100644 util/stats64.c diff --git a/include/qemu/stats64.h b/include/qemu/stats64.h deleted file mode 100644 index 99b5cb724a..0000000000 --- a/include/qemu/stats64.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Atomic operations on 64-bit quantities. - * - * Copyright (C) 2017 Red Hat, Inc. - * - * Author: Paolo Bonzini - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - */ - -#ifndef QEMU_STATS64_H -#define QEMU_STATS64_H - -#include "qemu/atomic.h" - -/* This provides atomic operations on 64-bit type, using a reader-writer - * spinlock on architectures that do not have 64-bit accesses. Even on - * those architectures, it tries hard not to take the lock. - */ - -typedef struct Stat64 { -#ifdef CONFIG_ATOMIC64 - aligned_uint64_t value; -#else - uint32_t low, high; - uint32_t lock; -#endif -} Stat64; - -#ifdef CONFIG_ATOMIC64 -static inline void stat64_init(Stat64 *s, uint64_t value) -{ - /* This is not guaranteed to be atomic! */ - *s =3D (Stat64) { value }; -} - -static inline uint64_t stat64_get(const Stat64 *s) -{ - return qatomic_read__nocheck(&s->value); -} - -static inline void stat64_set(Stat64 *s, uint64_t value) -{ - qatomic_set__nocheck(&s->value, value); -} - -static inline void stat64_add(Stat64 *s, uint64_t value) -{ - qatomic_add(&s->value, value); -} - -static inline void stat64_min(Stat64 *s, uint64_t value) -{ - uint64_t orig =3D qatomic_read__nocheck(&s->value); - while (orig > value) { - orig =3D qatomic_cmpxchg__nocheck(&s->value, orig, value); - } -} - -static inline void stat64_max(Stat64 *s, uint64_t value) -{ - uint64_t orig =3D qatomic_read__nocheck(&s->value); - while (orig < value) { - orig =3D qatomic_cmpxchg__nocheck(&s->value, orig, value); - } -} -#else -uint64_t stat64_get(const Stat64 *s); -void stat64_set(Stat64 *s, uint64_t value); -bool stat64_min_slow(Stat64 *s, uint64_t value); -bool stat64_max_slow(Stat64 *s, uint64_t value); -bool stat64_add32_carry(Stat64 *s, uint32_t low, uint32_t high); - -static inline void stat64_init(Stat64 *s, uint64_t value) -{ - /* This is not guaranteed to be atomic! */ - *s =3D (Stat64) { .low =3D value, .high =3D value >> 32, .lock =3D 0 }; -} - -static inline void stat64_add(Stat64 *s, uint64_t value) -{ - uint32_t low, high; - high =3D value >> 32; - low =3D (uint32_t) value; - if (!low) { - if (high) { - qatomic_add(&s->high, high); - } - return; - } - - for (;;) { - uint32_t orig =3D s->low; - uint32_t result =3D orig + low; - uint32_t old; - - if (result < low || high) { - /* If the high part is affected, take the lock. */ - if (stat64_add32_carry(s, low, high)) { - return; - } - continue; - } - - /* No carry, try with a 32-bit cmpxchg. The result is independent= of - * the high 32 bits, so it can race just fine with stat64_add32_ca= rry - * and even stat64_get! - */ - old =3D qatomic_cmpxchg(&s->low, orig, result); - if (orig =3D=3D old) { - return; - } - } -} - -static inline void stat64_min(Stat64 *s, uint64_t value) -{ - uint32_t low, high; - uint32_t orig_low, orig_high; - - high =3D value >> 32; - low =3D (uint32_t) value; - do { - orig_high =3D qatomic_read(&s->high); - if (orig_high < high) { - return; - } - - if (orig_high =3D=3D high) { - /* High 32 bits are equal. Read low after high, otherwise we - * can get a false positive (e.g. 0x1235,0x0000 changes to - * 0x1234,0x8000 and we read it as 0x1234,0x0000). Pairs with - * the write barrier in stat64_min_slow. - */ - smp_rmb(); - orig_low =3D qatomic_read(&s->low); - if (orig_low <=3D low) { - return; - } - - /* See if we were lucky and a writer raced against us. The - * barrier is theoretically unnecessary, but if we remove it - * we may miss being lucky. - */ - smp_rmb(); - orig_high =3D qatomic_read(&s->high); - if (orig_high < high) { - return; - } - } - - /* If the value changes in any way, we have to take the lock. */ - } while (!stat64_min_slow(s, value)); -} - -static inline void stat64_max(Stat64 *s, uint64_t value) -{ - uint32_t low, high; - uint32_t orig_low, orig_high; - - high =3D value >> 32; - low =3D (uint32_t) value; - do { - orig_high =3D qatomic_read(&s->high); - if (orig_high > high) { - return; - } - - if (orig_high =3D=3D high) { - /* High 32 bits are equal. Read low after high, otherwise we - * can get a false positive (e.g. 0x1234,0x8000 changes to - * 0x1235,0x0000 and we read it as 0x1235,0x8000). Pairs with - * the write barrier in stat64_max_slow. - */ - smp_rmb(); - orig_low =3D qatomic_read(&s->low); - if (orig_low >=3D low) { - return; - } - - /* See if we were lucky and a writer raced against us. The - * barrier is theoretically unnecessary, but if we remove it - * we may miss being lucky. - */ - smp_rmb(); - orig_high =3D qatomic_read(&s->high); - if (orig_high > high) { - return; - } - } - - /* If the value changes in any way, we have to take the lock. */ - } while (!stat64_max_slow(s, value)); -} - -#endif - -#endif diff --git a/util/stats64.c b/util/stats64.c deleted file mode 100644 index 09736014ec..0000000000 --- a/util/stats64.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Atomic operations on 64-bit quantities. - * - * Copyright (C) 2017 Red Hat, Inc. - * - * Author: Paolo Bonzini - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - */ - -#include "qemu/osdep.h" -#include "qemu/atomic.h" -#include "qemu/stats64.h" -#include "qemu/processor.h" - -#ifndef CONFIG_ATOMIC64 -static inline void stat64_rdlock(Stat64 *s) -{ - /* Keep out incoming writers to avoid them starving us. */ - qatomic_add(&s->lock, 2); - - /* If there is a concurrent writer, wait for it. */ - while (qatomic_read(&s->lock) & 1) { - cpu_relax(); - } -} - -static inline void stat64_rdunlock(Stat64 *s) -{ - qatomic_sub(&s->lock, 2); -} - -static inline bool stat64_wrtrylock(Stat64 *s) -{ - return qatomic_cmpxchg(&s->lock, 0, 1) =3D=3D 0; -} - -static inline void stat64_wrunlock(Stat64 *s) -{ - qatomic_dec(&s->lock); -} - -uint64_t stat64_get(const Stat64 *s) -{ - uint32_t high, low; - - stat64_rdlock((Stat64 *)s); - - /* 64-bit writes always take the lock, so we can read in - * any order. - */ - high =3D qatomic_read(&s->high); - low =3D qatomic_read(&s->low); - stat64_rdunlock((Stat64 *)s); - - return ((uint64_t)high << 32) | low; -} - -void stat64_set(Stat64 *s, uint64_t val) -{ - while (!stat64_wrtrylock(s)) { - cpu_relax(); - } - - qatomic_set(&s->high, val >> 32); - qatomic_set(&s->low, val); - stat64_wrunlock(s); -} - -bool stat64_add32_carry(Stat64 *s, uint32_t low, uint32_t high) -{ - uint32_t old; - - if (!stat64_wrtrylock(s)) { - cpu_relax(); - return false; - } - - /* 64-bit reads always take the lock, so they don't care about the - * order of our update. By updating s->low first, we can check - * whether we have to carry into s->high. - */ - old =3D qatomic_fetch_add(&s->low, low); - high +=3D (old + low) < old; - qatomic_add(&s->high, high); - stat64_wrunlock(s); - return true; -} - -bool stat64_min_slow(Stat64 *s, uint64_t value) -{ - uint32_t high, low; - uint64_t orig; - - if (!stat64_wrtrylock(s)) { - cpu_relax(); - return false; - } - - high =3D qatomic_read(&s->high); - low =3D qatomic_read(&s->low); - - orig =3D ((uint64_t)high << 32) | low; - if (value < orig) { - /* We have to set low before high, just like stat64_min reads - * high before low. The value may become higher temporarily, but - * stat64_get does not notice (it takes the lock) and the only ill - * effect on stat64_min is that the slow path may be triggered - * unnecessarily. - */ - qatomic_set(&s->low, (uint32_t)value); - smp_wmb(); - qatomic_set(&s->high, value >> 32); - } - stat64_wrunlock(s); - return true; -} - -bool stat64_max_slow(Stat64 *s, uint64_t value) -{ - uint32_t high, low; - uint64_t orig; - - if (!stat64_wrtrylock(s)) { - cpu_relax(); - return false; - } - - high =3D qatomic_read(&s->high); - low =3D qatomic_read(&s->low); - - orig =3D ((uint64_t)high << 32) | low; - if (value > orig) { - /* We have to set low before high, just like stat64_max reads - * high before low. The value may become lower temporarily, but - * stat64_get does not notice (it takes the lock) and the only ill - * effect on stat64_max is that the slow path may be triggered - * unnecessarily. - */ - qatomic_set(&s->low, (uint32_t)value); - smp_wmb(); - qatomic_set(&s->high, value >> 32); - } - stat64_wrunlock(s); - return true; -} -#endif diff --git a/util/meson.build b/util/meson.build index 35029380a3..d7d6b213f6 100644 --- a/util/meson.build +++ b/util/meson.build @@ -59,7 +59,6 @@ util_ss.add(files('qht.c')) util_ss.add(files('qsp.c')) util_ss.add(files('range.c')) util_ss.add(files('reserved-region.c')) -util_ss.add(files('stats64.c')) util_ss.add(files('systemd.c')) util_ss.add(files('transactions.c')) util_ss.add(files('guest-random.c')) --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774176; cv=none; d=zohomail.com; s=zohoarc; b=B/FMYpjMiuBd5FKUjg3t21TQtFb3LJsORLNwa/I0DfRT3PtoA8vM2m9JM3fUHJ/2irixDzAvBZGYseDAVhYwpWDvZloN+bnZGIhL9nYrlzmKnnUZUuztkIUHB8UIONgTSAz+qpEVrm49O6VXCU7pLFWae6ms3tnSCHWwcc4Fp3k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768774176; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mEULzlPw6xjPe+4/C4phqMCxelohiweTDlicKl24zKE=; b=lYhsEca8rChdpMVvy9UtQrd4DQTwse1yZp1toKmpvhfDAitpeqTp2J6TkWRE71Y2SyU9sfzd+vy0hgIxdFGHYrrupMLzor7q/Q9IDFe6njHcp821IRcL2ZlOC2J5WMvk/bBulvnVHV40OY5clBfdpMRWalQk09J+l2U6EWcsmKQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768774176736485.49938623067453; Sun, 18 Jan 2026 14:09:36 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhaxg-0001Fj-VJ; Sun, 18 Jan 2026 17:09:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhaxe-0000xP-H5 for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:09:30 -0500 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhaxc-0001fN-Ah for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:09:30 -0500 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-29f30233d8aso24804855ad.0 for ; Sun, 18 Jan 2026 14:09:27 -0800 (PST) Received: from stoup.. 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/qemu/atomic.h | 22 ---------- accel/qtest/qtest.c | 4 +- accel/tcg/icount-common.c | 25 ++++++----- system/dirtylimit.c | 2 +- tests/unit/test-rcu-list.c | 17 ++++---- util/atomic64.c | 85 -------------------------------------- util/cacheflush.c | 2 - util/qsp.c | 8 ++-- util/meson.build | 3 -- 9 files changed, 27 insertions(+), 141 deletions(-) delete mode 100644 util/atomic64.c diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h index c39dc99f2f..27d98014d4 100644 --- a/include/qemu/atomic.h +++ b/include/qemu/atomic.h @@ -247,26 +247,4 @@ typedef int64_t aligned_int64_t __attribute__((aligned(8))); typedef uint64_t aligned_uint64_t __attribute__((aligned(8))); =20 -#ifdef CONFIG_ATOMIC64 -/* Use __nocheck because sizeof(void *) might be < sizeof(u64) */ -#define qatomic_read_i64(P) \ - _Generic(*(P), int64_t: qatomic_read__nocheck(P)) -#define qatomic_read_u64(P) \ - _Generic(*(P), uint64_t: qatomic_read__nocheck(P)) -#define qatomic_set_i64(P, V) \ - _Generic(*(P), int64_t: qatomic_set__nocheck(P, V)) -#define qatomic_set_u64(P, V) \ - _Generic(*(P), uint64_t: qatomic_set__nocheck(P, V)) - -static inline void qatomic64_init(void) -{ -} -#else /* !CONFIG_ATOMIC64 */ -int64_t qatomic_read_i64(const int64_t *ptr); -uint64_t qatomic_read_u64(const uint64_t *ptr); -void qatomic_set_i64(int64_t *ptr, int64_t val); -void qatomic_set_u64(uint64_t *ptr, uint64_t val); -void qatomic64_init(void); -#endif /* !CONFIG_ATOMIC64 */ - #endif /* QEMU_ATOMIC_H */ diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c index 1d4337d698..bb1491d93b 100644 --- a/accel/qtest/qtest.c +++ b/accel/qtest/qtest.c @@ -31,12 +31,12 @@ static int64_t qtest_clock_counter; =20 static int64_t qtest_get_virtual_clock(void) { - return qatomic_read_i64(&qtest_clock_counter); + return qatomic_read(&qtest_clock_counter); } =20 static void qtest_set_virtual_clock(int64_t count) { - qatomic_set_i64(&qtest_clock_counter, count); + qatomic_set(&qtest_clock_counter, count); } =20 static int qtest_init_accel(AccelState *as, MachineState *ms) diff --git a/accel/tcg/icount-common.c b/accel/tcg/icount-common.c index d6471174a3..b1b6c005fe 100644 --- a/accel/tcg/icount-common.c +++ b/accel/tcg/icount-common.c @@ -86,8 +86,8 @@ static void icount_update_locked(CPUState *cpu) int64_t executed =3D icount_get_executed(cpu); cpu->icount_budget -=3D executed; =20 - qatomic_set_i64(&timers_state.qemu_icount, - timers_state.qemu_icount + executed); + qatomic_set(&timers_state.qemu_icount, + timers_state.qemu_icount + executed); } =20 /* @@ -116,15 +116,14 @@ static int64_t icount_get_raw_locked(void) /* Take into account what has run */ icount_update_locked(cpu); } - /* The read is protected by the seqlock, but needs atomic64 to avoid U= B */ - return qatomic_read_i64(&timers_state.qemu_icount); + /* The read is protected by the seqlock, but needs atomic to avoid UB = */ + return qatomic_read(&timers_state.qemu_icount); } =20 static int64_t icount_get_locked(void) { int64_t icount =3D icount_get_raw_locked(); - return qatomic_read_i64(&timers_state.qemu_icount_bias) + - icount_to_ns(icount); + return qatomic_read(&timers_state.qemu_icount_bias) + icount_to_ns(ico= unt); } =20 int64_t icount_get_raw(void) @@ -201,9 +200,9 @@ static void icount_adjust(void) timers_state.icount_time_shift + 1); } timers_state.last_delta =3D delta; - qatomic_set_i64(&timers_state.qemu_icount_bias, - cur_icount - (timers_state.qemu_icount - << timers_state.icount_time_shift)); + qatomic_set(&timers_state.qemu_icount_bias, + cur_icount - (timers_state.qemu_icount + << timers_state.icount_time_shift)); seqlock_write_unlock(&timers_state.vm_clock_seqlock, &timers_state.vm_clock_lock); } @@ -269,8 +268,8 @@ static void icount_warp_rt(void) } warp_delta =3D MIN(warp_delta, delta); } - qatomic_set_i64(&timers_state.qemu_icount_bias, - timers_state.qemu_icount_bias + warp_delta); + qatomic_set(&timers_state.qemu_icount_bias, + timers_state.qemu_icount_bias + warp_delta); } timers_state.vm_clock_warp_start =3D -1; seqlock_write_unlock(&timers_state.vm_clock_seqlock, @@ -361,8 +360,8 @@ void icount_start_warp_timer(void) */ seqlock_write_lock(&timers_state.vm_clock_seqlock, &timers_state.vm_clock_lock); - qatomic_set_i64(&timers_state.qemu_icount_bias, - timers_state.qemu_icount_bias + deadline); + qatomic_set(&timers_state.qemu_icount_bias, + timers_state.qemu_icount_bias + deadline); seqlock_write_unlock(&timers_state.vm_clock_seqlock, &timers_state.vm_clock_lock); qemu_clock_notify(QEMU_CLOCK_VIRTUAL); diff --git a/system/dirtylimit.c b/system/dirtylimit.c index a0c327533c..50fa67f3d6 100644 --- a/system/dirtylimit.c +++ b/system/dirtylimit.c @@ -123,7 +123,7 @@ static void *vcpu_dirty_rate_stat_thread(void *opaque) int64_t vcpu_dirty_rate_get(int cpu_index) { DirtyRateVcpu *rates =3D vcpu_dirty_rate_stat->stat.rates; - return qatomic_read_i64(&rates[cpu_index].dirty_rate); + return qatomic_read(&rates[cpu_index].dirty_rate); } =20 void vcpu_dirty_rate_stat_start(void) diff --git a/tests/unit/test-rcu-list.c b/tests/unit/test-rcu-list.c index 8f0adb8b00..8dde3e61a8 100644 --- a/tests/unit/test-rcu-list.c +++ b/tests/unit/test-rcu-list.c @@ -105,7 +105,7 @@ static void reclaim_list_el(struct rcu_head *prcu) struct list_element *el =3D container_of(prcu, struct list_element, rc= u); g_free(el); /* Accessed only from call_rcu thread. */ - qatomic_set_i64(&n_reclaims, n_reclaims + 1); + qatomic_set(&n_reclaims, n_reclaims + 1); } =20 #if TEST_LIST_TYPE =3D=3D 1 @@ -247,7 +247,7 @@ static void *rcu_q_updater(void *arg) qemu_mutex_lock(&counts_mutex); n_nodes +=3D n_nodes_local; n_updates +=3D n_updates_local; - qatomic_set_i64(&n_nodes_removed, n_nodes_removed + n_removed_local); + qatomic_set(&n_nodes_removed, n_nodes_removed + n_removed_local); qemu_mutex_unlock(&counts_mutex); return NULL; } @@ -301,23 +301,22 @@ static void rcu_qtest(const char *test, int duration,= int nreaders) n_removed_local++; } qemu_mutex_lock(&counts_mutex); - qatomic_set_i64(&n_nodes_removed, n_nodes_removed + n_removed_local); + qatomic_set(&n_nodes_removed, n_nodes_removed + n_removed_local); qemu_mutex_unlock(&counts_mutex); synchronize_rcu(); - while (qatomic_read_i64(&n_nodes_removed) > - qatomic_read_i64(&n_reclaims)) { + while (qatomic_read(&n_nodes_removed) > qatomic_read(&n_reclaims)) { g_usleep(100); synchronize_rcu(); } if (g_test_in_charge) { - g_assert_cmpint(qatomic_read_i64(&n_nodes_removed), =3D=3D, - qatomic_read_i64(&n_reclaims)); + g_assert_cmpint(qatomic_read(&n_nodes_removed), =3D=3D, + qatomic_read(&n_reclaims)); } else { printf("%s: %d readers; 1 updater; nodes read: " \ "%lld, nodes removed: %"PRIi64"; nodes reclaimed: %"PRIi64"= \n", test, nthreadsrunning - 1, n_reads, - qatomic_read_i64(&n_nodes_removed), - qatomic_read_i64(&n_reclaims)); + qatomic_read(&n_nodes_removed), + qatomic_read(&n_reclaims)); exit(0); } } diff --git a/util/atomic64.c b/util/atomic64.c deleted file mode 100644 index c20d071d8e..0000000000 --- a/util/atomic64.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (C) 2018, Emilio G. Cota - * - * License: GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ -#include "qemu/osdep.h" -#include "qemu/atomic.h" -#include "qemu/thread.h" -#include "qemu/cacheinfo.h" -#include "qemu/memalign.h" - -#ifdef CONFIG_ATOMIC64 -#error This file must only be compiled if !CONFIG_ATOMIC64 -#endif - -/* - * When !CONFIG_ATOMIC64, we serialize both reads and writes with spinlock= s. - * We use an array of spinlocks, with padding computed at run-time based on - * the host's dcache line size. - * We point to the array with a void * to simplify the padding's computati= on. - * Each spinlock is located every lock_size bytes. - */ -static void *lock_array; -static size_t lock_size; - -/* - * Systems without CONFIG_ATOMIC64 are unlikely to have many cores, so we = use a - * small array of locks. - */ -#define NR_LOCKS 16 - -static QemuSpin *addr_to_lock(const void *addr) -{ - uintptr_t a =3D (uintptr_t)addr; - uintptr_t idx; - - idx =3D a >> qemu_dcache_linesize_log; - idx ^=3D (idx >> 8) ^ (idx >> 16); - idx &=3D NR_LOCKS - 1; - return lock_array + idx * lock_size; -} - -#define GEN_READ(name, type) \ - type name(const type *ptr) \ - { \ - QemuSpin *lock =3D addr_to_lock(ptr); \ - type ret; \ - \ - qemu_spin_lock(lock); \ - ret =3D *ptr; \ - qemu_spin_unlock(lock); \ - return ret; \ - } - -GEN_READ(qatomic_read_i64, int64_t) -GEN_READ(qatomic_read_u64, uint64_t) -#undef GEN_READ - -#define GEN_SET(name, type) \ - void name(type *ptr, type val) \ - { \ - QemuSpin *lock =3D addr_to_lock(ptr); \ - \ - qemu_spin_lock(lock); \ - *ptr =3D val; \ - qemu_spin_unlock(lock); \ - } - -GEN_SET(qatomic_set_i64, int64_t) -GEN_SET(qatomic_set_u64, uint64_t) -#undef GEN_SET - -void qatomic64_init(void) -{ - int i; - - lock_size =3D ROUND_UP(sizeof(QemuSpin), qemu_dcache_linesize); - lock_array =3D qemu_memalign(qemu_dcache_linesize, lock_size * NR_LOCK= S); - for (i =3D 0; i < NR_LOCKS; i++) { - QemuSpin *lock =3D lock_array + i * lock_size; - - qemu_spin_init(lock); - } -} diff --git a/util/cacheflush.c b/util/cacheflush.c index 99221a409f..c043c5f881 100644 --- a/util/cacheflush.c +++ b/util/cacheflush.c @@ -216,8 +216,6 @@ static void __attribute__((constructor)) init_cache_inf= o(void) qemu_icache_linesize_log =3D ctz32(isize); qemu_dcache_linesize =3D dsize; qemu_dcache_linesize_log =3D ctz32(dsize); - - qatomic64_init(); } =20 =20 diff --git a/util/qsp.c b/util/qsp.c index 6b783e2e7f..382e4397e2 100644 --- a/util/qsp.c +++ b/util/qsp.c @@ -346,9 +346,9 @@ static QSPEntry *qsp_entry_get(const void *obj, const c= har *file, int line, */ static inline void do_qsp_entry_record(QSPEntry *e, int64_t delta, bool ac= q) { - qatomic_set_u64(&e->ns, e->ns + delta); + qatomic_set(&e->ns, e->ns + delta); if (acq) { - qatomic_set_u64(&e->n_acqs, e->n_acqs + 1); + qatomic_set(&e->n_acqs, e->n_acqs + 1); } } =20 @@ -538,8 +538,8 @@ static void qsp_aggregate(void *p, uint32_t h, void *up) * The entry is in the global hash table; read from it atomically (as = in * "read once"). */ - agg->ns +=3D qatomic_read_u64(&e->ns); - agg->n_acqs +=3D qatomic_read_u64(&e->n_acqs); + agg->ns +=3D qatomic_read(&e->ns); + agg->n_acqs +=3D qatomic_read(&e->n_acqs); } =20 static void qsp_iter_diff(void *p, uint32_t hash, void *htp) diff --git a/util/meson.build b/util/meson.build index d7d6b213f6..59e835a8d3 100644 --- a/util/meson.build +++ b/util/meson.build @@ -1,8 +1,5 @@ util_ss.add(files('osdep.c', 'cutils.c', 'unicode.c', 'qemu-timer-common.c= ')) util_ss.add(files('thread-context.c'), numa) -if not config_host_data.get('CONFIG_ATOMIC64') - util_ss.add(files('atomic64.c')) -endif if host_os !=3D 'windows' util_ss.add(files('aio-posix.c')) util_ss.add(files('fdmon-poll.c')) --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7190ab921sm73298205ad.8.2026.01.18.14.09.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:09:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768774168; x=1769378968; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YwA+XxyWFDkORFNBlQmOw9xYRUenABDhu5WGq8pWY6s=; b=Zfg0cMHa1yPi2CTMgdR2jOx0X2nSPWRCIXGVoRisxmdot/U6fZR2ExWu6MPJ3LDLpn ViddAcTzRmjHGzUG/5Dr/7pcmVDtebPr5iC9+AxzQ4+XEJ/rVsvV3WGqKsDOZaoefPcB bX6HRpR+v2ZSRckhn7arOgHGVO+U9CNjkECOKJbAFrq+hYdkdsiNjdOJVPsr/UrHYbYU iiAhkkLdnVwZwxMCdLTPq8Fw3xNQHgsHIWdt29gtpOO5H/o0DVEFq1KLE2VUvECC7es1 BvhAIP1H8TeK5ZHM5cXbAVrAsHhxDVrNIgD4in1RYlAFYMX4dcWOJH5Z3k7hOb3+FGI+ Ia2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768774168; x=1769378968; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=YwA+XxyWFDkORFNBlQmOw9xYRUenABDhu5WGq8pWY6s=; b=jK3IsNpX68z8nIWuJCe6jjsvrTIO8DiQmB5ISSM6D2PGRItyIWmZqFUDTRb1CTrVKE FHKrm3ecQKYj2dMBEkLieXDtgt57tc5MnHty97z7/cY6UKyD2drC0KCrzW82aZuD2NXx Yx3U+AkRr6MOAdxEeRSpOfQQPPDWrrGbNrVwKXFhmVu7fSG9f1nAxK5sB1/pTaEPP5Om /GSydwkObqGYdnL+BrqG+cQkfGzJt8m3bDkH4PMz+XCfu/IC5UVw/N11+1UsQX/NXXCU 0cOi99QdFw/tr+fuZ+2b4j/MOweijBi120fliNFJ0I8k19KIsHySHCUhIAD1fAlTjdvT qg9w== X-Gm-Message-State: AOJu0YyVod1XqPbNGEslXbYq8lvcEW4G2odhPWsanTM320+EsLQkaRiE 1UXgt754Wg9EgHOPygUuOgvYH92ag2oG2WQqeAfs2kAki2HPUdIWdoXVZKLqDgUGfUYzr+SLjxp xg21J8JYhuw== X-Gm-Gg: AY/fxX5nFRqX7x2X/zvh7KjTkT62Jqa5YD8CXqds0bqpJhoRJt5tyxV4tZlmoTVpxuK uwS3fqtZGH2Tjc9w4a9tiCyfELRGODY3w6EtZXVCGcpbOddsy273HApSNkyW0cIiLQVtYrYuTzR XG0tGDTnv/FMSumSI75y248gGUxQwWcDoSR8VrHlnE+qiB1LC8d4VWls2022XWDfABT5rQwIM+0 W6KLMEqABhe/Z8hO2UjxfCsw7aQt6XQhsCAjBFZkVVrlEd/4URmcljUX2pJJ/PIXSoX2fL1xYFb t4XYXyajrSY+5HEsEsk/L3Q3YTnmw+CMNry92edFlgk9piS/ZQw+rhrdUuNu/Ddj0wt1mBaTp2X kCr8oTliTvPnso6aGZV4vUMJvDbqO0pgETs/EMyOdFcsZyb8EZKY+5YdRJi4IvoKrs0e4a0yVZ4 w7ehkrqjTPsT+xmNcla0SjelrkLdpZ X-Received: by 2002:a17:903:41c7:b0:297:f8d9:aad7 with SMTP id d9443c01a7336-2a7177dfcb2mr83654925ad.50.1768774168266; Sun, 18 Jan 2026 14:09:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 53/54] meson: Remove CONFIG_ATOMIC64 Date: Mon, 19 Jan 2026 09:04:13 +1100 Message-ID: <20260118220414.8177-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774206815158500 Content-Type: text/plain; charset="utf-8" This config is no longer used. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- meson.build | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/meson.build b/meson.build index 0189d8fd44..3108f01e88 100644 --- a/meson.build +++ b/meson.build @@ -2939,22 +2939,6 @@ config_host_data.set('HAVE_BROKEN_SIZE_MAX', not cc.= compiles(''' return printf("%zu", SIZE_MAX); }''', args: ['-Werror'])) =20 -# See if 64-bit atomic operations are supported. -# Note that without __atomic builtins, we can only -# assume atomic loads/stores max at pointer size. -config_host_data.set('CONFIG_ATOMIC64', cc.links(''' - #include - int main(void) - { - uint64_t x =3D 0, y =3D 0; - y =3D __atomic_load_n(&x, __ATOMIC_RELAXED); - __atomic_store_n(&x, y, __ATOMIC_RELAXED); - __atomic_compare_exchange_n(&x, &y, x, 0, __ATOMIC_RELAXED, __ATOMIC_R= ELAXED); - __atomic_exchange_n(&x, y, __ATOMIC_RELAXED); - __atomic_fetch_add(&x, y, __ATOMIC_RELAXED); - return 0; - }''', args: qemu_isa_flags)) - # has_int128_type is set to false on Emscripten to avoid errors by libffi # during runtime. has_int128_type =3D host_os !=3D 'emscripten' and cc.compiles(''' --=20 2.43.0 From nobody Sat Feb 7 04:55:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768774194; cv=none; d=zohomail.com; s=zohoarc; b=clRQQ1l0DpC5i5/DFzMx9UI1ProI8egV0goXjCKaUmv5lxCaAjHTUSBY70tPVqXdflKf5lX/nNt0Vr0j1bAeRhI+IAfYakdGcEajmJCJkTSws4HMWisUrD31qkwEyuHOKo5NzSGaA4W4dHC+N9GcNc9Ch5rwfmCXj6kYZfsd9Ac= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768774194; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VnCVV9AnEgawNA+fiIe+uEXCZKJSFhPJndsOefTu71g=; b=JCWSFmS085CDxx3rv3f6goaI+0iUcPNkAPnnzTHYbmJr7v11ALvez4FEO/NqtW+y1oIwNtcKuKGsZ9TuBx2WAnQHKLu3UwIOMAozKUIG+luPBcnj7Qto6/6SeEa0MTAAwf2KX40dLmXBGY+1q0adWyXpLbO3395gDSoc5YazLpQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768774194387561.1916032229061; Sun, 18 Jan 2026 14:09:54 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vhaxk-0001bc-Js; Sun, 18 Jan 2026 17:09:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vhaxi-0001MH-2N for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:09:34 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vhaxg-0001gC-5V for qemu-devel@nongnu.org; Sun, 18 Jan 2026 17:09:33 -0500 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-2a0833b5aeeso37543665ad.1 for ; Sun, 18 Jan 2026 14:09:31 -0800 (PST) Received: from stoup.. ([180.233.125.201]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7190ab921sm73298205ad.8.2026.01.18.14.09.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jan 2026 14:09:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768774171; x=1769378971; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VnCVV9AnEgawNA+fiIe+uEXCZKJSFhPJndsOefTu71g=; b=nYpprE9xQYkq3l3Amy2P21fGeiHWahqg3XLCvfqPfxFfW3S24pQbtZ72nBZzkkIMqW uIC8hogQc7b93vtjuo3yYwsYOzvqCJr5ljacLyd1OrOvObfR+/W91RlfevT64LxKEQOw Bwu4tDyRMod/+wCyMPV8naIz24wdTgTau01nmJhyLZX9deOFrMUwK2uvDN3Kq+0Awlw6 rCiywKbWkFbhEd2DleEy5ZoBmQrAnXh/qPDXuoy19HxhMF2KBjefr4GUtKRWGSvww/Uj YkJROWeB0C5PhQV/pKWROL5sb3Xnlxn051XGgyNsfMBVzciYDCF+vx6zoeTniHlHtMPO n0eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768774171; x=1769378971; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=VnCVV9AnEgawNA+fiIe+uEXCZKJSFhPJndsOefTu71g=; b=iytQoEl1YYiyxOVJjyXgTWCsuLyU6cs++RMD8z5OskLNdTsGhEMCrmpsJODYpX5PYU TX3PZIl8RkrbEotNAeqfNokduQY0glifTSXTRYinoZgCjnwjoSGIbIlNTL4YI7CbQchg C3nha4RcgxWVtCfb1BwGPibI5sfEZVPjLKth0ac1YJO29wA3cg47RYye+MnXfBOcnOlq jPNJxqryvvw9U6nhQtMCFlAKPNle8vQJLlzKGl7glGMbzGEDKNvrtWduUDhSW6BZ6/IP rR+ELQ94pFqeL8bL7x/ONjVuXGnRtzTYbkSIiYSkb17G+FfC/rDogfUvaQecv4Rp4ebV 02pA== X-Gm-Message-State: AOJu0YwNfvhXCZD0zRvupZsFi+Uqzjs3AS+2JUQYIoHsbEdNrYvshN+D m4LoPB9Whqtd1LWmhEu59ZNjvoVLQlyl2F51rXRFPGQ5RxsukDtqBTZFr2+F1HMDaC2k3DGLP5Q lW3oYoBsR8g== X-Gm-Gg: AY/fxX6GnMwNKUnDhxGcpTP79dwYBrOSKEhkNvrTUG2tI1qqkPREft5YR8mUacFubYn z84MfRyl47i2cUO9o+vyDlfBINJ3nG1bHLaecYRc3oWwkqPHFNFlPyjZX2ioNH3+y9BW1/T2OXb sFzXUEgZ8DzX6DIbkB8MVTa+/5lzqDtTbHxf/TqfCUeBU+HpvQOaxP4495VLCuLKjmIY03drGrE cS1khVHkmZXhB7zcJiejSX4JneKoMWK1pnm4WIdv0Yr5dr9znN7VR75Xlf8Z7AJQAegsE39NLfo PmNGDJKuKoimTKtinWbCcJQaoTJ60Mf/m0g7QHIJBdGEg7FNHCNt7mTWIgAp64Q+AmpooATq6XW PPMb8/6VKpEAfD9hV3TgC9OUEtEMDzBtm1RXFLXwgBm3cvNSJ4eBGrvUUTv56hdN/fH5cZfmRRz ND1rQvF4b6VIgYGAwwUA== X-Received: by 2002:a17:903:2f4c:b0:2a0:a8c2:be5d with SMTP id d9443c01a7336-2a7188583d4mr76683165ad.5.1768774170634; Sun, 18 Jan 2026 14:09:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 54/54] include/qemu/atomic: Drop aligned_{u}int64_t Date: Mon, 19 Jan 2026 09:04:14 +1100 Message-ID: <20260118220414.8177-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260118220414.8177-1-richard.henderson@linaro.org> References: <20260118220414.8177-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768774194809158500 As we no longer support i386 as a host architecture, this abstraction is no longer required. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 4 ++-- include/qemu/atomic.h | 13 ------------- include/system/cpu-timers-internal.h | 2 +- linux-user/hppa/cpu_loop.c | 2 +- util/qsp.c | 4 ++-- 5 files changed, 6 insertions(+), 19 deletions(-) diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index ae5203b439..f7924078f7 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -27,8 +27,8 @@ # define SHIFT 4 #elif DATA_SIZE =3D=3D 8 # define SUFFIX q -# define DATA_TYPE aligned_uint64_t -# define SDATA_TYPE aligned_int64_t +# define DATA_TYPE uint64_t +# define SDATA_TYPE int64_t # define BSWAP bswap64 # define SHIFT 3 #elif DATA_SIZE =3D=3D 4 diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h index 27d98014d4..dc9290084b 100644 --- a/include/qemu/atomic.h +++ b/include/qemu/atomic.h @@ -234,17 +234,4 @@ _oldn; \ }) =20 -/* - * Abstractions to access atomically (i.e. "once") i64/u64 variables. - * - * The i386 abi is odd in that by default members are only aligned to - * 4 bytes, which means that 8-byte types can wind up mis-aligned. - * Clang will then warn about this, and emit a call into libatomic. - * - * Use of these types in structures when they will be used with atomic - * operations can avoid this. - */ -typedef int64_t aligned_int64_t __attribute__((aligned(8))); -typedef uint64_t aligned_uint64_t __attribute__((aligned(8))); - #endif /* QEMU_ATOMIC_H */ diff --git a/include/system/cpu-timers-internal.h b/include/system/cpu-time= rs-internal.h index 94bb7394c5..8c262ce139 100644 --- a/include/system/cpu-timers-internal.h +++ b/include/system/cpu-timers-internal.h @@ -47,7 +47,7 @@ typedef struct TimersState { int64_t last_delta; =20 /* Compensate for varying guest execution speed. */ - aligned_int64_t qemu_icount_bias; + int64_t qemu_icount_bias; =20 int64_t vm_clock_warp_start; int64_t cpu_clock_offset; diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index e5c0f52d94..972e85c487 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -83,7 +83,7 @@ static abi_ulong hppa_lws(CPUHPPAState *env) uint64_t o64, n64, r64; o64 =3D *(uint64_t *)g2h(cs, old); n64 =3D *(uint64_t *)g2h(cs, new); - r64 =3D qatomic_cmpxchg((aligned_uint64_t *)g2h(cs, addr),= o64, n64); + r64 =3D qatomic_cmpxchg((uint64_t *)g2h(cs, addr), o64, n6= 4); ret =3D r64 !=3D o64; } break; diff --git a/util/qsp.c b/util/qsp.c index 382e4397e2..55477ae025 100644 --- a/util/qsp.c +++ b/util/qsp.c @@ -83,8 +83,8 @@ typedef struct QSPCallSite QSPCallSite; struct QSPEntry { void *thread_ptr; const QSPCallSite *callsite; - aligned_uint64_t n_acqs; - aligned_uint64_t ns; + uint64_t n_acqs; + uint64_t ns; unsigned int n_objs; /* count of coalesced objs; only used for reporti= ng */ }; typedef struct QSPEntry QSPEntry; --=20 2.43.0