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Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/hvf/hvf.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index fcb7fa3b30c..9ce720793d8 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -200,6 +200,9 @@ void hvf_arm_init_debug(void) #define SYSREG_PMCEID0_EL0 SYSREG(3, 3, 9, 12, 6) #define SYSREG_PMCEID1_EL0 SYSREG(3, 3, 9, 12, 7) #define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0) + +#define SYSREG_CNTV_CTL_EL0 SYSREG(3, 3, 14, 3, 1) +#define SYSREG_CNTV_CVAL_EL0 SYSREG(3, 3, 14, 3, 2) #define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7) =20 #define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 12, 8, 4) @@ -502,6 +505,7 @@ int hvf_arch_get_registers(CPUState *cpu) uint64_t val; hv_simd_fp_uchar16_t fpval; int i, n; + bool b; =20 for (i =3D 0; i < ARRAY_SIZE(hvf_reg_match); i++) { ret =3D hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val= ); @@ -631,6 +635,16 @@ int hvf_arch_get_registers(CPUState *cpu) =20 aarch64_restore_sp(env, arm_current_el(env)); =20 + ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CVAL_EL0, = &val); + assert_hvf_ok(ret); + b =3D hvf_sysreg_write_cp(cpu, "VTimer", SYSREG_CNTV_CVAL_EL0, val); + assert(b); + + ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &= val); + assert_hvf_ok(ret); + b =3D hvf_sysreg_write_cp(cpu, "VTimer", SYSREG_CNTV_CTL_EL0, val); + assert(b); + return 0; } =20 @@ -642,6 +656,7 @@ int hvf_arch_put_registers(CPUState *cpu) uint64_t val; hv_simd_fp_uchar16_t fpval; int i, n; + bool b; =20 for (i =3D 0; i < ARRAY_SIZE(hvf_reg_match); i++) { val =3D *(uint64_t *)((void *)env + hvf_reg_match[i].offset); @@ -756,6 +771,16 @@ int hvf_arch_put_registers(CPUState *cpu) ret =3D hv_vcpu_set_vtimer_offset(cpu->accel->fd, hvf_state->vtimer_of= fset); assert_hvf_ok(ret); =20 + b =3D hvf_sysreg_read_cp(cpu, "VTimer", SYSREG_CNTV_CVAL_EL0, &val); + assert(b); + ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CVAL_EL0, = val); + assert_hvf_ok(ret); + + b =3D hvf_sysreg_read_cp(cpu, "VTimer", SYSREG_CNTV_CTL_EL0, &val); + assert(b); + ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, v= al); + assert_hvf_ok(ret); + return 0; } =20 --=20 2.52.0