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a="69131168" X-IronPort-AV: E=Sophos;i="6.21,232,1763452800"; d="scan'208";a="69131168" X-CSE-ConnectionGUID: sJNxcObPTb+uadIIa0gWYQ== X-CSE-MsgGUID: YfzqnsF3R/yLt9eB/BipSA== X-ExtLoop1: 1 From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: xiaoyao.li@intel.com, Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH 5/7] target/i386: Save/Restore DS based PEBS specfic MSRs Date: Fri, 16 Jan 2026 17:10:51 -0800 Message-ID: <20260117011053.80723-6-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260117011053.80723-1-zide.chen@intel.com> References: <20260117011053.80723-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.18; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1768612756446158500 Content-Type: text/plain; charset="utf-8" From: Dapeng Mi DS-based PEBS introduces three MSRs: MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, and MSR_IA32_PEBS_ENABLE. Save and restore these MSRs when legacy DS PEBS is enabled. Signed-off-by: Dapeng Mi Signed-off-by: Zide Chen --- target/i386/cpu.h | 9 +++++++++ target/i386/kvm/kvm.c | 25 +++++++++++++++++++++++++ target/i386/machine.c | 27 ++++++++++++++++++++++++++- 3 files changed, 60 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e7cf4a7bd594..dc5b477be283 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -422,6 +422,7 @@ typedef enum X86Seg { #define MSR_IA32_PERF_CAPABILITIES 0x345 #define PERF_CAP_LBR_FMT 0x3f #define PERF_CAP_FULL_WRITE (1U << 13) +#define PERF_CAP_PEBS_BASELINE (1U << 14) =20 #define MSR_IA32_TSX_CTRL 0x122 #define MSR_IA32_TSCDEADLINE 0x6e0 @@ -512,6 +513,11 @@ typedef enum X86Seg { #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 =20 +/* Legacy DS based PEBS MSRs */ +#define MSR_IA32_PEBS_ENABLE 0x3f1 +#define MSR_PEBS_DATA_CFG 0x3f2 +#define MSR_IA32_DS_AREA 0x600 + #define MSR_MC0_CTL 0x400 #define MSR_MC0_STATUS 0x401 #define MSR_MC0_ADDR 0x402 @@ -2089,6 +2095,9 @@ typedef struct CPUArchState { uint64_t msr_fixed_ctr_ctrl; uint64_t msr_global_ctrl; uint64_t msr_global_status; + uint64_t msr_ds_area; + uint64_t msr_pebs_data_cfg; + uint64_t msr_pebs_enable; uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; uint64_t msr_gp_counters[MAX_GP_COUNTERS]; uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 530f50e4b218..80974114a173 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4061,6 +4061,15 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState lev= el) kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); } =20 + if (env->features[FEAT_1_EDX] & CPUID_DTS) { + kvm_msr_entry_add(cpu, MSR_IA32_DS_AREA, env->msr_ds_area); + } + + if (env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_PEBS_BASE= LINE) { + kvm_msr_entry_add(cpu, MSR_IA32_PEBS_ENABLE, env->msr_pebs= _enable); + kvm_msr_entry_add(cpu, MSR_PEBS_DATA_CFG, env->msr_pebs_da= ta_cfg); + } + /* Set the counter values. */ for (i =3D 0; i < num_architectural_pmu_fixed_counters; i++) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, @@ -4606,6 +4615,13 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, perf_cntr_base + i, 0); kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0); } + if (env->features[FEAT_1_EDX] & CPUID_DTS) { + kvm_msr_entry_add(cpu, MSR_IA32_DS_AREA, 0); + } + if (env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_PEBS_BASELINE= ) { + kvm_msr_entry_add(cpu, MSR_IA32_PEBS_ENABLE, 0); + kvm_msr_entry_add(cpu, MSR_PEBS_DATA_CFG, 0); + } } =20 if (env->mcg_cap) { @@ -4938,6 +4954,15 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] =3D msrs[i].data; break; + case MSR_IA32_DS_AREA: + env->msr_ds_area =3D msrs[i].data; + break; + case MSR_PEBS_DATA_CFG: + env->msr_pebs_data_cfg =3D msrs[i].data; + break; + case MSR_IA32_PEBS_ENABLE: + env->msr_pebs_enable =3D msrs[i].data; + break; case HV_X64_MSR_HYPERCALL: env->msr_hv_hypercall =3D msrs[i].data; break; diff --git a/target/i386/machine.c b/target/i386/machine.c index 7d08a05835fc..7f45db1247b1 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -659,6 +659,27 @@ static const VMStateDescription vmstate_msr_ia32_featu= re_control =3D { } }; =20 +static bool ds_pebs_enabled(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return (env->msr_ds_area || env->msr_pebs_enable || + env->msr_pebs_data_cfg); +} + +static const VMStateDescription vmstate_msr_ds_pebs =3D { + .name =3D "cpu/msr_ds_pebs", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D ds_pebs_enabled, + .fields =3D (const VMStateField[]){ + VMSTATE_UINT64(env.msr_ds_area, X86CPU), + VMSTATE_UINT64(env.msr_pebs_data_cfg, X86CPU), + VMSTATE_UINT64(env.msr_pebs_enable, X86CPU), + VMSTATE_END_OF_LIST()} +}; + static bool pmu_enable_needed(void *opaque) { X86CPU *cpu =3D opaque; @@ -697,7 +718,11 @@ static const VMStateDescription vmstate_msr_architectu= ral_pmu =3D { VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS), VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS), VMSTATE_END_OF_LIST() - } + }, + .subsections =3D (const VMStateDescription * const []) { + &vmstate_msr_ds_pebs, + NULL, + }, }; =20 static bool mpx_needed(void *opaque) --=20 2.52.0