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a="69131148" X-IronPort-AV: E=Sophos;i="6.21,232,1763452800"; d="scan'208";a="69131148" X-CSE-ConnectionGUID: 3gTCIqKOQNaUvL1gCEEEKw== X-CSE-MsgGUID: do0kuAd5TgW1OmLmWJblrA== X-ExtLoop1: 1 From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: xiaoyao.li@intel.com, Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH 1/7] target/i386: Disable unsupported BTS for guest Date: Fri, 16 Jan 2026 17:10:47 -0800 Message-ID: <20260117011053.80723-2-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260117011053.80723-1-zide.chen@intel.com> References: <20260117011053.80723-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.18; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1768612850119158500 Content-Type: text/plain; charset="utf-8" BTS (Branch Trace Store), enumerated by IA32_MISC_ENABLE.BTS_UNAVAILABLE (bit 11), is deprecated and has been superseded by LBR and Intel PT. KVM yields control of the above mentioned bit to userspace since KVM commit 9fc222967a39 ("KVM: x86: Give host userspace full control of MSR_IA32_MISC_ENABLES"). However, QEMU does not set this bit, which allows guests to write the BTS and BTINT bits in IA32_DEBUGCTL. Since KVM doesn't support BTS, this may lead to unexpected MSR access errors. Setting this bit does not introduce migration compatibility issues, so the VMState version_id is not bumped. Signed-off-by: Zide Chen --- target/i386/cpu.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 2bbc977d9088..f2b79a8bf1dc 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -474,7 +474,10 @@ typedef enum X86Seg { =20 #define MSR_IA32_MISC_ENABLE 0x1a0 /* Indicates good rep/movs microcode on some processors: */ -#define MSR_IA32_MISC_ENABLE_DEFAULT 1 +#define MSR_IA32_MISC_ENABLE_FASTSTRING 1 +#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) +#define MSR_IA32_MISC_ENABLE_DEFAULT (MSR_IA32_MISC_ENABLE_FASTSTRIN= G |\ + MSR_IA32_MISC_ENABLE_BTS_UNAVA= IL) #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) =20 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) --=20 2.52.0