From nobody Sat Feb 7 07:25:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1768612849; cv=none; d=zohomail.com; s=zohoarc; b=UaUSQEvUug5frEemhCrM72xaI38djjxqzfVxBsEHXdrZvlz4Iid4cvLpnSFXIOuqZTePZ344c5Ar9fG67HSi48xC1ECEQibKAan6j/scjcIFSSnGBKiyHRHiZGW46uBRnD1EX7ucLsPfQ8+Luy5MUYDhi5PXlBIJ0C6sbACflXc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768612849; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=z9S46PtZnAO6KFNd/0DX4VdtEdcGxL9T/HiFuBpkSHk=; b=oF39HGIYK4qXPQVc4kWTSshBtgg4IiVUMRCZRIlD7/AZ6OdVNsw/CLtCPaZNIortkhuRw5d1QgbpIpMDpdzlmwmf/FRhmks/te7vMxAnltNlUY8tplot6DvPjd6phH8iXqs0TMN2TtZbcxPUz7q2Zdma0SQp2n9n/+1GBZf//2E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176861284986050.21807739963424; Fri, 16 Jan 2026 17:20:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vguxL-0004pl-Cd; Fri, 16 Jan 2026 20:18:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vguxC-0004mW-1l for qemu-devel@nongnu.org; Fri, 16 Jan 2026 20:18:14 -0500 Received: from mgamail.intel.com ([192.198.163.18]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vgux9-00078g-Ct for qemu-devel@nongnu.org; Fri, 16 Jan 2026 20:18:13 -0500 Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jan 2026 17:18:07 -0800 Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jan 2026 17:18:07 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768612691; x=1800148691; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1YGD2m13b08g6ocSDICUbrUDqi3sC1hiqJxS0srsQNg=; b=A0o6oCaAH6prttYWJ3HETH2xgnay/Twx9zemHsHPy6QYJpEPm2eRypLT Hr/73OcWlTQcs7Ohrar7r+RFkzg2SnJz4htr9WkgBTcxapjO/KrHHyduW 3OZqD4pCP7CNprEhbNvHzKTh6IkGJNVqg+ojHsHEdZ7A+AIE0dvyPoOiL o7E6DbxJR8K6KneYXOK7Oxb1O4sHjxMUEwFJZ5zjrQdBVAHrkAoDnvw5q d5UHhXoAY/MEtIOntmp1gargmOnI8qeDXTYwZuDdieorqpGjTvaZ34DZt RHGsZ6k4OlS5WJzuucGbh5sTuPYZmlboqQsU93/h6iYfk4uB2oPYDPr/e w==; X-CSE-ConnectionGUID: 6pd8hLkyT7CkNXI8msao6A== X-CSE-MsgGUID: dX12aJjvR3ajdX4frCFKvQ== X-IronPort-AV: E=McAfee;i="6800,10657,11673"; a="69131148" X-IronPort-AV: E=Sophos;i="6.21,232,1763452800"; d="scan'208";a="69131148" X-CSE-ConnectionGUID: 3gTCIqKOQNaUvL1gCEEEKw== X-CSE-MsgGUID: do0kuAd5TgW1OmLmWJblrA== X-ExtLoop1: 1 From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: xiaoyao.li@intel.com, Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH 1/7] target/i386: Disable unsupported BTS for guest Date: Fri, 16 Jan 2026 17:10:47 -0800 Message-ID: <20260117011053.80723-2-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260117011053.80723-1-zide.chen@intel.com> References: <20260117011053.80723-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.18; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1768612850119158500 Content-Type: text/plain; charset="utf-8" BTS (Branch Trace Store), enumerated by IA32_MISC_ENABLE.BTS_UNAVAILABLE (bit 11), is deprecated and has been superseded by LBR and Intel PT. KVM yields control of the above mentioned bit to userspace since KVM commit 9fc222967a39 ("KVM: x86: Give host userspace full control of MSR_IA32_MISC_ENABLES"). However, QEMU does not set this bit, which allows guests to write the BTS and BTINT bits in IA32_DEBUGCTL. Since KVM doesn't support BTS, this may lead to unexpected MSR access errors. Setting this bit does not introduce migration compatibility issues, so the VMState version_id is not bumped. Signed-off-by: Zide Chen --- target/i386/cpu.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 2bbc977d9088..f2b79a8bf1dc 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -474,7 +474,10 @@ typedef enum X86Seg { =20 #define MSR_IA32_MISC_ENABLE 0x1a0 /* Indicates good rep/movs microcode on some processors: */ -#define MSR_IA32_MISC_ENABLE_DEFAULT 1 +#define MSR_IA32_MISC_ENABLE_FASTSTRING 1 +#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) +#define MSR_IA32_MISC_ENABLE_DEFAULT (MSR_IA32_MISC_ENABLE_FASTSTRIN= G |\ + MSR_IA32_MISC_ENABLE_BTS_UNAVA= IL) #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) =20 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) --=20 2.52.0 From nobody Sat Feb 7 07:25:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1768612803; cv=none; d=zohomail.com; s=zohoarc; b=eWEzA4+g51cU2rquOwA8BpzIi3zaWlT+UnzmJsASAl0blmLDEOsXS+I1NycQ9bsHdk8Re0NTPLuQ3Qfb7qRHv7yW+MFoDUZkZ2af9UCHzCgGAXnxmNS86Q0WZu3zSmCG7VSiIk9R/1rfku6v0HDif+piQ/8L09MXe97tFzCOzyM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768612803; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3mYvNFnWDBchWfQzbWxVQT8eZvlX5XBMaB47Dzcp9nM=; b=DrHsKuL8R9j+xJfnSOZjmf6ZoEWzHXUW9u6EtPPXS7+VykuJSg9eSWIkIJ81z/xYOISM7OthGWPM4RALS5FzAMjG9Pnoc526LB2rGEpCBf2v0YBizBGeKCm+nsM3NuLvDhJ0X8sLFVM3dJ1BxNlVnZmJm7OjnvEk3QB6yflL9zw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768612803808158.31446636999635; Fri, 16 Jan 2026 17:20:03 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vguxL-0004qD-UX; Fri, 16 Jan 2026 20:18:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vguxD-0004mi-PX for qemu-devel@nongnu.org; Fri, 16 Jan 2026 20:18:16 -0500 Received: from mgamail.intel.com ([192.198.163.18]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vguxC-00077n-2B for qemu-devel@nongnu.org; Fri, 16 Jan 2026 20:18:15 -0500 Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jan 2026 17:18:08 -0800 Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jan 2026 17:18:07 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768612694; x=1800148694; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WVJQSNpNKHu3X0iUjOMBxv0QHS5KDEf9o+KQJ8gyVAQ=; b=gVZJ8uMqShYL/INe6YTbv/boC7zvTxcBIA8/0+G6G90Py+6i1tJ2zxF/ 7s3oUnXhCP/t8syEjg3Hu1gPy33LTt5uR07NM8/47J+lCdgTRM23zRRDe iC09f85kGoF61YpnR6Xzkirwj/kCV2uPRWLqOBS/8uSUOxFOKmMtVcvvI Q6F0CdnJvfowu+YLcRJaWRZYYlOc+F7OHTf3dJdm32WkgjXzWeOkMWGri 7mQnBQiv5egHK/oRIWhMzhe5wfNdzvECFBjR6RewaVPIN0H7XaMYTGQfO /8nTA3pCNYhbf2bN3wn94adfvWBdczHau6jUwBSsdLgPAn3O/WeYCSuua w==; X-CSE-ConnectionGUID: a0PLjm+BRhumKkzimtDJ8A== X-CSE-MsgGUID: LjP/hSMqRAO7vpySNOCAKw== X-IronPort-AV: E=McAfee;i="6800,10657,11673"; a="69131153" X-IronPort-AV: E=Sophos;i="6.21,232,1763452800"; d="scan'208";a="69131153" X-CSE-ConnectionGUID: /+z504YORU+VnwiO6lsoeA== X-CSE-MsgGUID: UW7hqU9YRR2jgIAvFDbxCg== X-ExtLoop1: 1 From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: xiaoyao.li@intel.com, Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH 2/7] target/i386: Don't save/restore PERF_GLOBAL_OVF_CTRL MSR Date: Fri, 16 Jan 2026 17:10:48 -0800 Message-ID: <20260117011053.80723-3-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260117011053.80723-1-zide.chen@intel.com> References: <20260117011053.80723-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.18; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1768612805977158500 Content-Type: text/plain; charset="utf-8" From: Dapeng Mi MSR_CORE_PERF_GLOBAL_OVF_CTRL is a write-only MSR and reads always return zero. Saving and restoring this MSR is therefore unnecessary. Replace VMSTATE_UINT64 with VMSTATE_UNUSED in the VMStateDescription to ignore env.msr_global_ovf_ctrl during migration. This avoids the need to bump version_id and does not introduce any migration incompatibility. Signed-off-by: Dapeng Mi Signed-off-by: Zide Chen --- target/i386/cpu.h | 1 - target/i386/kvm/kvm.c | 6 ------ target/i386/machine.c | 4 ++-- 3 files changed, 2 insertions(+), 9 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index f2b79a8bf1dc..0b480c631ed0 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2086,7 +2086,6 @@ typedef struct CPUArchState { uint64_t msr_fixed_ctr_ctrl; uint64_t msr_global_ctrl; uint64_t msr_global_status; - uint64_t msr_global_ovf_ctrl; uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; uint64_t msr_gp_counters[MAX_GP_COUNTERS]; uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 7b9b740a8e5a..cffbc90d1c50 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4069,8 +4069,6 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState leve= l) if (has_architectural_pmu_version > 1) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, env->msr_global_status); - kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, - env->msr_global_ovf_ctrl); =20 /* Now start the PMU. */ kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, @@ -4588,7 +4586,6 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0); - kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0); } for (i =3D 0; i < num_architectural_pmu_fixed_counters; i++) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0); @@ -4917,9 +4914,6 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_CORE_PERF_GLOBAL_STATUS: env->msr_global_status =3D msrs[i].data; break; - case MSR_CORE_PERF_GLOBAL_OVF_CTRL: - env->msr_global_ovf_ctrl =3D msrs[i].data; - break; case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_F= IXED_COUNTERS - 1: env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] =3D = msrs[i].data; break; diff --git a/target/i386/machine.c b/target/i386/machine.c index c9139612813b..1125c8a64ec5 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -666,7 +666,7 @@ static bool pmu_enable_needed(void *opaque) int i; =20 if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl || - env->msr_global_status || env->msr_global_ovf_ctrl) { + env->msr_global_status) { return true; } for (i =3D 0; i < MAX_FIXED_COUNTERS; i++) { @@ -692,7 +692,7 @@ static const VMStateDescription vmstate_msr_architectur= al_pmu =3D { VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU), VMSTATE_UINT64(env.msr_global_ctrl, X86CPU), VMSTATE_UINT64(env.msr_global_status, X86CPU), - VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU), + VMSTATE_UNUSED(sizeof(uint64_t)), VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COU= NTERS), VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS), VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS), --=20 2.52.0 From nobody Sat Feb 7 07:25:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1768612789; cv=none; d=zohomail.com; s=zohoarc; b=i+lxCDRm6tIM8mQDrc6txTQmZ/T2aovMnVDRJtR+u2/uvgFS05rBlYFy0rnuCe8CdX9kzZ4OfVRV8TWdqBW+TJaI5R8Z7UWtja1jMDaCU5dtWd/K84GAKjk1IU3mqL4KQPs6+7O+9EjH9zatM1Hke5ELviD/KpKIEek8ftmX6YI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768612789; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7oxrrQFB/0zilwHTZs5FT7jUIlVd5eAlfyZPM9mvX48=; b=SXDEhRzh7PlHQN7Eke3Iac2kUNL2x0h/bg2RL6MqMLrr6/gMp3pNzY6M3ukgnd1RCgUwcDaFhLPLnJWgAwZcnP35sbGt+vL4E0+RqzUtYLmJm2c7gtrQh0d/KvAybvmWdyoKKAyJu2TvHMMPmk5s/3dHF+zzjPEzzZl+q1UQ2Lg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768612789780748.2576451568593; Fri, 16 Jan 2026 17:19:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vguxL-0004pZ-99; Fri, 16 Jan 2026 20:18:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vguxD-0004mh-MW for qemu-devel@nongnu.org; Fri, 16 Jan 2026 20:18:16 -0500 Received: from mgamail.intel.com ([192.198.163.18]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vguxC-00078g-21 for qemu-devel@nongnu.org; Fri, 16 Jan 2026 20:18:15 -0500 Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jan 2026 17:18:08 -0800 Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jan 2026 17:18:08 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768612694; x=1800148694; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3LAfenVCwIiuUdSFycJUlecFg2V/epsiKiOvzm0Dv2A=; b=bhI1WyUl/LsRt0UFaptF6A3Kq2mTIWaDcRJ3kDLCprR3B9h1eddi4RGk dbWvVu82Qo2zrsOSL57ITRnu8rDFHX7+LbzOXWlSHt5rHuJXBtlOIiiA8 21MT6vMotFEXxmdFvlOT6UPn1baXEAT271DH07wtQnUzTctQ+O+A+BDcl l3dEuWr4cbEplsu7r4q85B8YFNKVv3IUOONPSrLJz3Cf+5zDghIvm0adK 94P8lLIxNnKRUdnq2GtAPPun6NUE0FaX2fs7X5pFNtV7vt1rAgIyoUoxE CotqaDcP3Qr0F177ZEFgnKGvwkuc4KevALroxeCxJmGGeBr0IbpMydCln w==; X-CSE-ConnectionGUID: x7QdWVY0Rd+ToIG8AksmTQ== X-CSE-MsgGUID: hFVGpvDNQ8yrnCtEBIDJBw== X-IronPort-AV: E=McAfee;i="6800,10657,11673"; a="69131158" X-IronPort-AV: E=Sophos;i="6.21,232,1763452800"; d="scan'208";a="69131158" X-CSE-ConnectionGUID: WaqVDCyhRT6p/C0Bu1/fMg== X-CSE-MsgGUID: JwpHhkpKTA6xms5V78cFUA== X-ExtLoop1: 1 From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: xiaoyao.li@intel.com, Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH 3/7] target/i386: Gate enable_pmu on kvm_enabled() Date: Fri, 16 Jan 2026 17:10:49 -0800 Message-ID: <20260117011053.80723-4-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260117011053.80723-1-zide.chen@intel.com> References: <20260117011053.80723-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.18; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1768612792085158500 Content-Type: text/plain; charset="utf-8" Guest PMU support requires KVM. Clear cpu->enable_pmu when KVM is not enabled, so PMU-related code can rely solely on cpu->enable_pmu. This reduces duplication and avoids bugs where one of the checks is missed. For example, cpu_x86_cpuid() enables CPUID.0AH when cpu->enable_pmu is set but does not check kvm_enabled(). This is implicitly fixed by this patch: if (cpu->enable_pmu) { x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); } Also fix two places that check kvm_enabled() but not cpu->enable_pmu. Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi --- target/i386/cpu.c | 9 ++++++--- target/i386/kvm/kvm.c | 4 ++-- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 37803cd72490..f1ac98970d3e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8671,7 +8671,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *ecx =3D 0; *edx =3D 0; if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || - !kvm_enabled()) { + !cpu->enable_pmu) { break; } =20 @@ -9018,7 +9018,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, case 0x80000022: *eax =3D *ebx =3D *ecx =3D *edx =3D 0; /* AMD Extended Performance Monitoring and Debug */ - if (kvm_enabled() && cpu->enable_pmu && + if (cpu->enable_pmu && (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFM= ON_V2)) { *eax |=3D CPUID_8000_0022_EAX_PERFMON_V2; *ebx |=3D kvm_arch_get_supported_cpuid(cs->kvm_state, index, c= ount, @@ -9642,7 +9642,7 @@ static bool x86_cpu_filter_features(X86CPU *cpu, bool= verbose) * are advertised by cpu_x86_cpuid(). Keep these two in sync. */ if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && - kvm_enabled()) { + cpu->enable_pmu) { x86_cpu_get_supported_cpuid(0x14, 0, &eax_0, &ebx_0, &ecx_0, &edx_0); x86_cpu_get_supported_cpuid(0x14, 1, @@ -9790,6 +9790,9 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) Error *local_err =3D NULL; unsigned requested_lbr_fmt; =20 + if (!kvm_enabled()) + cpu->enable_pmu =3D false; + #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) /* Use pc-relative instructions in system-mode */ tcg_cflags_set(cs, CF_PCREL); diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index cffbc90d1c50..e81fa46ed66c 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4222,7 +4222,7 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState leve= l) env->msr_xfd_err); } =20 - if (kvm_enabled() && cpu->enable_pmu && + if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { uint64_t depth; int ret; @@ -4698,7 +4698,7 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0); } =20 - if (kvm_enabled() && cpu->enable_pmu && + if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { uint64_t depth; =20 --=20 2.52.0 From nobody Sat Feb 7 07:25:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1768612843; cv=none; d=zohomail.com; s=zohoarc; b=FRGUNq+pP1XzloJblXicjTjSR8u8ll+P+e8JLOzfmoNnA0IYj5k1ApVTuWuM19alm6QmfO70VUXmBRBBopN/MRTiPZ8WmBr6aYap7+8/RzIkqVL8FOXVro0ebUH8IfFPYbTbPhoH6nSAEKQFB8nZVwq3Ag5M4jA+N+IzTsNFFNI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768612843; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CgV7UBumZMu+U4gCAUG0XgkdAqVxbfd7Mv4jQrTWNrI=; b=YsDXHDw+D1zDxws4S8M5MXB8hqL9Kub7dGr3UieWl389njNi8ZuuOWCe/Kod7lMdZE56kdFLjvlr/GMgWOW+66lz4F0D4OVtjAUDiAh/uYdfABlNluzaz2Q7NwzeFtgpQhFnsuTnKm+yraHlExwEnfUqrRKLodPspRXylMgWxA8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTP id 1768612842827102.47645385567444; Fri, 16 Jan 2026 17:20:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vguxM-0004qS-Da; Fri, 16 Jan 2026 20:18:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vguxE-0004mk-5e for qemu-devel@nongnu.org; Fri, 16 Jan 2026 20:18:16 -0500 Received: from mgamail.intel.com ([192.198.163.18]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vguxC-0007Aa-Fc for qemu-devel@nongnu.org; Fri, 16 Jan 2026 20:18:15 -0500 Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jan 2026 17:18:08 -0800 Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jan 2026 17:18:08 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768612695; x=1800148695; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0EHb9zhaCZcf7BErUyjTZ5rV4RNsDDaKZWDuBspJf60=; b=V5El7gmY5lZ6ZgMvmAURYm0HhJvgIyOe+klb8egMS5f+I2iU8NCF/wy1 447WQKNjPXNjWTdR6cFe2iDcsPz7fgCbPk77bWyTWF6KIi4MSTvbSKEoS e/cMIdniSwvbgVhTBcmniI4DWTPYDDdTzyPS+UFK4PCaVKtrVsNnYCsHX 2Y5UMLSo78efqFZzn41u1F2Tzty5t8RC/LbaOSpOXkNPexO9sHTyVbTRz reT8T9vBXasFfvcS7vK4Jyy7DepkgTC9EvA5oA8LTxgCCR9tCLPebCeRP 7vzO/q4102IUG0eJ1Bj5Z1lBJqjhgNC2VQM93EedUMezvm2MesPYLPiOJ Q==; X-CSE-ConnectionGUID: Hh0vng1FR7yfRbPQ0Q3Cdg== X-CSE-MsgGUID: 6U1zHtkRTV2UKqxCUmJiTg== X-IronPort-AV: E=McAfee;i="6800,10657,11673"; a="69131163" X-IronPort-AV: E=Sophos;i="6.21,232,1763452800"; d="scan'208";a="69131163" X-CSE-ConnectionGUID: mNuTuSRfQAWCK/ad0cnTvQ== X-CSE-MsgGUID: uPiptIIgRwyNypKjc59FXQ== X-ExtLoop1: 1 From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: xiaoyao.li@intel.com, Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH 4/7] target/i386: Support full-width writes for perf counters Date: Fri, 16 Jan 2026 17:10:50 -0800 Message-ID: <20260117011053.80723-5-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260117011053.80723-1-zide.chen@intel.com> References: <20260117011053.80723-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.18; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1768612844105158500 Content-Type: text/plain; charset="utf-8" From: Dapeng Mi If IA32_PERF_CAPABILITIES.FW_WRITE (bit 13) is set, each general- purpose counter IA32_PMCi (starting at 0xc1) is accompanied by a corresponding alias MSR starting at 0x4c1 (IA32_A_PMC0), which are 64-bit wide. The legacy IA32_PMCi MSRs are not full-width and their effective width is determined by CPUID.0AH:EAX[23:16]. Since these two sets of MSRs are aliases, when IA32_A_PMCi is supported it is safe to use it for save/restore instead of the legacy MSRs, regardless of whether the hypervisor uses the legacy or the 64-bit counterpart. Full-width write is a user-visible feature and can be disabled individually. Reduce MAX_GP_COUNTERS from 18 to 15 to avoid conflicts between the full-width MSR range and MSR_MCG_EXT_CTL. Current CPUs support at most 10 general-purpose counters, so 15 is sufficient for now and leaves room for future expansion. Bump minimum_version_id to avoid migration from older QEMU, as this may otherwise cause VMState overflow. This also requires bumping version_id, which prevents migration to older QEMU as well. Signed-off-by: Dapeng Mi Signed-off-by: Zide Chen --- target/i386/cpu.h | 5 ++++- target/i386/kvm/kvm.c | 19 +++++++++++++++++-- target/i386/machine.c | 4 ++-- 3 files changed, 23 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0b480c631ed0..e7cf4a7bd594 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -421,6 +421,7 @@ typedef enum X86Seg { =20 #define MSR_IA32_PERF_CAPABILITIES 0x345 #define PERF_CAP_LBR_FMT 0x3f +#define PERF_CAP_FULL_WRITE (1U << 13) =20 #define MSR_IA32_TSX_CTRL 0x122 #define MSR_IA32_TSCDEADLINE 0x6e0 @@ -448,6 +449,8 @@ typedef enum X86Seg { #define MSR_IA32_SGXLEPUBKEYHASH3 0x8f =20 #define MSR_P6_PERFCTR0 0xc1 +/* Alternative perfctr range with full access. */ +#define MSR_IA32_PMC0 0x4c1 =20 #define MSR_IA32_SMBASE 0x9e #define MSR_SMI_COUNT 0x34 @@ -1740,7 +1743,7 @@ typedef struct { #endif =20 #define MAX_FIXED_COUNTERS 3 -#define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) +#define MAX_GP_COUNTERS 15 =20 #define NB_OPMASK_REGS 8 =20 diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index e81fa46ed66c..530f50e4b218 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4049,6 +4049,12 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState lev= el) } =20 if (has_architectural_pmu_version > 0) { + uint32_t perf_cntr_base =3D MSR_P6_PERFCTR0; + + if (env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_FULL_WRIT= E) { + perf_cntr_base =3D MSR_IA32_PMC0; + } + if (has_architectural_pmu_version > 1) { /* Stop the counter. */ kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); @@ -4061,7 +4067,7 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState leve= l) env->msr_fixed_counters[i]); } for (i =3D 0; i < num_architectural_pmu_gp_counters; i++) { - kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, + kvm_msr_entry_add(cpu, perf_cntr_base + i, env->msr_gp_counters[i]); kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, env->msr_gp_evtsel[i]); @@ -4582,6 +4588,12 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1); } if (has_architectural_pmu_version > 0) { + uint32_t perf_cntr_base =3D MSR_P6_PERFCTR0; + + if (env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_FULL_WRITE) { + perf_cntr_base =3D MSR_IA32_PMC0; + } + if (has_architectural_pmu_version > 1) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); @@ -4591,7 +4603,7 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0); } for (i =3D 0; i < num_architectural_pmu_gp_counters; i++) { - kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0); + kvm_msr_entry_add(cpu, perf_cntr_base + i, 0); kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0); } } @@ -4920,6 +4932,9 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1: env->msr_gp_counters[index - MSR_P6_PERFCTR0] =3D msrs[i].data; break; + case MSR_IA32_PMC0 ... MSR_IA32_PMC0 + MAX_GP_COUNTERS - 1: + env->msr_gp_counters[index - MSR_IA32_PMC0] =3D msrs[i].data; + break; case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] =3D msrs[i].data; break; diff --git a/target/i386/machine.c b/target/i386/machine.c index 1125c8a64ec5..7d08a05835fc 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -685,8 +685,8 @@ static bool pmu_enable_needed(void *opaque) =20 static const VMStateDescription vmstate_msr_architectural_pmu =3D { .name =3D "cpu/msr_architectural_pmu", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .needed =3D pmu_enable_needed, .fields =3D (const VMStateField[]) { VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU), --=20 2.52.0 From nobody Sat Feb 7 07:25:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1768612754; cv=none; d=zohomail.com; s=zohoarc; b=Z8jMAZYKiNIAnPHk9302suFWlpopUx4vdPHgq962PDdyGC4ulj3LECZXWhrARK7DuDV5HFW3XEgd36/pnrY6WV66gtmpnVjBe4Wj3Nvu+neES181AwgiY4shgNW+5aprigNZoxHRTjr/831Lib4HkDSfk6/4N5IK7dIDl1tr6Ok= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768612754; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ngQf/Sb6ploSLuWu7RcolQcQZozb23YTI9136J38NqQ=; b=K2IT/fC1C9f6sK0Qgp2P4ZDsaCwENfrFSggvTHSgbELobj3pkr97aG/t1twJA4r/ZJV5yB8jQZZe7ULwMjDV4yf8LkgvIoZGwAINf2x5IyWTw3DBUETxidCVLeTqZ1T1xViPJEMRdUwQgyghDaYS8pD3uf/H30xZ1g+++SAVhmk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768612754005604.8803307243817; Fri, 16 Jan 2026 17:19:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vguxO-0004sJ-Sk; Fri, 16 Jan 2026 20:18:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vguxF-0004nI-Qs for qemu-devel@nongnu.org; Fri, 16 Jan 2026 20:18:18 -0500 Received: from mgamail.intel.com ([192.198.163.18]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vguxE-00078g-19 for qemu-devel@nongnu.org; Fri, 16 Jan 2026 20:18:17 -0500 Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jan 2026 17:18:09 -0800 Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jan 2026 17:18:08 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768612696; x=1800148696; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5SM+V/i5RlkKEUO9iOkuBJwBqiK8SuXbIsYPBKq/HyY=; b=i+aQ28ga9XPA23pbaQ2eFa4QwQCUs1etNoK9h4WJaNEdsCFKnITkyNmB VjlNkRYUbaRyZHO3fOyRMFbWXSeG5ryNT51+CFDNBFZG97joF2D47uPhh 2vPS5jwj/5JuGG6uFC13aCsl2+t9x2CDiRy5MD1xuTHvhpJtEFvkWR5ZK xatCy+7XJwMsqYRfyRucU6jBHz1wGUOc2oWfQMFqYyi5E8GPbFZQm83+X Gf4ApQIad+9v/BLjS5bLU0hWQ0vlXmP3xKmyybh2yNUDgVkD6IdWC0qLv 0MSIF2F3SuB9vrWggtqrGMQlzWeacUOiD4MfvXn9ckyYqMmcLjc0LAExd Q==; X-CSE-ConnectionGUID: jDk76PZlTZmSfJQYf6po1g== X-CSE-MsgGUID: OR08xBtGQx6ufw0ri1wAxw== X-IronPort-AV: E=McAfee;i="6800,10657,11673"; a="69131168" X-IronPort-AV: E=Sophos;i="6.21,232,1763452800"; d="scan'208";a="69131168" X-CSE-ConnectionGUID: sJNxcObPTb+uadIIa0gWYQ== X-CSE-MsgGUID: YfzqnsF3R/yLt9eB/BipSA== X-ExtLoop1: 1 From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: xiaoyao.li@intel.com, Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH 5/7] target/i386: Save/Restore DS based PEBS specfic MSRs Date: Fri, 16 Jan 2026 17:10:51 -0800 Message-ID: <20260117011053.80723-6-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260117011053.80723-1-zide.chen@intel.com> References: <20260117011053.80723-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.18; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1768612756446158500 Content-Type: text/plain; charset="utf-8" From: Dapeng Mi DS-based PEBS introduces three MSRs: MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, and MSR_IA32_PEBS_ENABLE. Save and restore these MSRs when legacy DS PEBS is enabled. Signed-off-by: Dapeng Mi Signed-off-by: Zide Chen --- target/i386/cpu.h | 9 +++++++++ target/i386/kvm/kvm.c | 25 +++++++++++++++++++++++++ target/i386/machine.c | 27 ++++++++++++++++++++++++++- 3 files changed, 60 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e7cf4a7bd594..dc5b477be283 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -422,6 +422,7 @@ typedef enum X86Seg { #define MSR_IA32_PERF_CAPABILITIES 0x345 #define PERF_CAP_LBR_FMT 0x3f #define PERF_CAP_FULL_WRITE (1U << 13) +#define PERF_CAP_PEBS_BASELINE (1U << 14) =20 #define MSR_IA32_TSX_CTRL 0x122 #define MSR_IA32_TSCDEADLINE 0x6e0 @@ -512,6 +513,11 @@ typedef enum X86Seg { #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 =20 +/* Legacy DS based PEBS MSRs */ +#define MSR_IA32_PEBS_ENABLE 0x3f1 +#define MSR_PEBS_DATA_CFG 0x3f2 +#define MSR_IA32_DS_AREA 0x600 + #define MSR_MC0_CTL 0x400 #define MSR_MC0_STATUS 0x401 #define MSR_MC0_ADDR 0x402 @@ -2089,6 +2095,9 @@ typedef struct CPUArchState { uint64_t msr_fixed_ctr_ctrl; uint64_t msr_global_ctrl; uint64_t msr_global_status; + uint64_t msr_ds_area; + uint64_t msr_pebs_data_cfg; + uint64_t msr_pebs_enable; uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; uint64_t msr_gp_counters[MAX_GP_COUNTERS]; uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 530f50e4b218..80974114a173 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4061,6 +4061,15 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState lev= el) kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); } =20 + if (env->features[FEAT_1_EDX] & CPUID_DTS) { + kvm_msr_entry_add(cpu, MSR_IA32_DS_AREA, env->msr_ds_area); + } + + if (env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_PEBS_BASE= LINE) { + kvm_msr_entry_add(cpu, MSR_IA32_PEBS_ENABLE, env->msr_pebs= _enable); + kvm_msr_entry_add(cpu, MSR_PEBS_DATA_CFG, env->msr_pebs_da= ta_cfg); + } + /* Set the counter values. */ for (i =3D 0; i < num_architectural_pmu_fixed_counters; i++) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, @@ -4606,6 +4615,13 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, perf_cntr_base + i, 0); kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0); } + if (env->features[FEAT_1_EDX] & CPUID_DTS) { + kvm_msr_entry_add(cpu, MSR_IA32_DS_AREA, 0); + } + if (env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_PEBS_BASELINE= ) { + kvm_msr_entry_add(cpu, MSR_IA32_PEBS_ENABLE, 0); + kvm_msr_entry_add(cpu, MSR_PEBS_DATA_CFG, 0); + } } =20 if (env->mcg_cap) { @@ -4938,6 +4954,15 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] =3D msrs[i].data; break; + case MSR_IA32_DS_AREA: + env->msr_ds_area =3D msrs[i].data; + break; + case MSR_PEBS_DATA_CFG: + env->msr_pebs_data_cfg =3D msrs[i].data; + break; + case MSR_IA32_PEBS_ENABLE: + env->msr_pebs_enable =3D msrs[i].data; + break; case HV_X64_MSR_HYPERCALL: env->msr_hv_hypercall =3D msrs[i].data; break; diff --git a/target/i386/machine.c b/target/i386/machine.c index 7d08a05835fc..7f45db1247b1 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -659,6 +659,27 @@ static const VMStateDescription vmstate_msr_ia32_featu= re_control =3D { } }; =20 +static bool ds_pebs_enabled(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return (env->msr_ds_area || env->msr_pebs_enable || + env->msr_pebs_data_cfg); +} + +static const VMStateDescription vmstate_msr_ds_pebs =3D { + .name =3D "cpu/msr_ds_pebs", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D ds_pebs_enabled, + .fields =3D (const VMStateField[]){ + VMSTATE_UINT64(env.msr_ds_area, X86CPU), + VMSTATE_UINT64(env.msr_pebs_data_cfg, X86CPU), + VMSTATE_UINT64(env.msr_pebs_enable, X86CPU), + VMSTATE_END_OF_LIST()} +}; + static bool pmu_enable_needed(void *opaque) { X86CPU *cpu =3D opaque; @@ -697,7 +718,11 @@ static const VMStateDescription vmstate_msr_architectu= ral_pmu =3D { VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS), VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS), VMSTATE_END_OF_LIST() - } + }, + .subsections =3D (const VMStateDescription * const []) { + &vmstate_msr_ds_pebs, + NULL, + }, }; =20 static bool mpx_needed(void *opaque) --=20 2.52.0 From nobody Sat Feb 7 07:25:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1768612754; cv=none; d=zohomail.com; s=zohoarc; b=L5sXC3ZZYJEQkHWq5f87jvXrB+st0Xac6lRXc1nRU4p4oW08bRkYmfcehfNtP879igo0wcY/tgQOMioJw3yGeumHawB6zWn3epVCUFeYR/gp1hIGDvPCXOMnD54nUxpD+ReAE2AVtKI39ocmo8W2o6tdQCFY7V3nmbCdKPfPGyU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768612754; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=KD2Ixxok2eOedty/KqJEB70kdO5HPgHKpgT0RK+fk+4=; b=Sc7WCtHFIAp71gPbCBa2rypOZ5s8pl8pIYkuKAIp7SluO5j2/gDOVxa1yZbcVfYvszJ5oGz4GXy/FrqATwJG1MBpk57pWwq59AOSCkElASh9XUz4EkTA8wW19Yx3AQuxuxq3sXbav7MgBK4SBa/ozQMXBKe8Vkd0JJAHR0kwj5U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176861275487035.34046104070546; Fri, 16 Jan 2026 17:19:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vguxK-0004oF-QB; Fri, 16 Jan 2026 20:18:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vguxF-0004nH-Mw for qemu-devel@nongnu.org; Fri, 16 Jan 2026 20:18:18 -0500 Received: from mgamail.intel.com ([192.198.163.18]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vguxE-00077n-3l for qemu-devel@nongnu.org; Fri, 16 Jan 2026 20:18:17 -0500 Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jan 2026 17:18:09 -0800 Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jan 2026 17:18:09 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768612696; x=1800148696; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2R2pFzeaXsFhmsgZPzDgKDW8nxLi3n1LYVYLNZ0AwJ8=; b=F90M5TVI/kqWpE0Spk4okwIz70pQsebQUGye7q8oJFMChkofZeoD5A1C M2pF4DQ1e+au1ycndm4SrPJPoqZtLwp6JhGyfspTIxIg2zVqqkyPfAJmr Ct1FBXBiNenPU3Gml7hWqOq3gOgqwMEy8OrepUsBQ0fueAnh2xDGYXkFt pmv+4J+s5QA+oYsWZy1t0c4cMmUH4sjN9JFrSVODVE1L0PXRAG3pN42vV 57GeI4DA0gRZh9BCE1nuLD65wAjav2NS+QN/y6RcL7KSFw8wHh8oW2Owb 7qwcY1tBnJYpo4q4R4Nzu72kwst9WHTfJaUuX7JcI3As3YQL+RztQh6I2 Q==; X-CSE-ConnectionGUID: 3gCf3/5rQLKXfmdegZvD0w== X-CSE-MsgGUID: dscpg8Q0TtCpIYegZjNVUQ== X-IronPort-AV: E=McAfee;i="6800,10657,11673"; a="69131173" X-IronPort-AV: E=Sophos;i="6.21,232,1763452800"; d="scan'208";a="69131173" X-CSE-ConnectionGUID: BTMa7AWnQjGZUDSRdc2D5Q== X-CSE-MsgGUID: ycrDxFSbRPaAZpXUWTRNtg== X-ExtLoop1: 1 From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: xiaoyao.li@intel.com, Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH 6/7] target/i386: Make some PEBS features user-visible Date: Fri, 16 Jan 2026 17:10:52 -0800 Message-ID: <20260117011053.80723-7-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260117011053.80723-1-zide.chen@intel.com> References: <20260117011053.80723-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.18; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1768612756521158500 Content-Type: text/plain; charset="utf-8" Populate selected PEBS feature names in FEAT_PERF_CAPABILITIES to make the corresponding bits user-visible CPU feature knobs, allowing them to be explicitly enabled or disabled via -cpu +/-. Once named, these bits become part of the guest CPU configuration contract. If a VM is configured with such a feature enabled, migration to a destination that does not support the feature may fail, as the destination cannot honor the guest-visible CPU model. The PEBS_FMT bits are intentionally not exposed. They are not meaningful as user-visible features, and QEMU registers CPU features as boolean QOM properties, which makes them unsuitable for representing and checking numeric capabilities. Co-developed-by: Dapeng Mi Signed-off-by: Dapeng Mi Signed-off-by: Zide Chen --- target/i386/cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f1ac98970d3e..fc6a64287415 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1618,10 +1618,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = =3D { .type =3D MSR_FEATURE_WORD, .feat_names =3D { NULL, NULL, NULL, NULL, + NULL, NULL, "pebs-trap", "pebs-arch-reg" NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, "full-width-write", NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, "full-width-write", "pebs-baseline", NULL, + NULL, "pebs-timing-info", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, --=20 2.52.0 From nobody Sat Feb 7 07:25:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1768612777; cv=none; d=zohomail.com; s=zohoarc; b=VyguUpI4NzeEGxANzZ4a/RsM0QoItrsN86KwxUEqy8DliO+mcerMAiEtPi7PPVhpOyS1lBspTMBMBavyC6iOAuK4oRDYG9oz9+/VFr/tM/E70m1x/0VVgpoWPEPvGcR26kS+sy9fCsEhZH4j+MrGG5TDZI1O8WoYMfcTGOWkROc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768612777; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=W1s/10cczLw5B6UN4eE1zNTQSQxJKa2Zbq660IIeG8k=; b=WJ2nGmF+rH3TJkTbZpyoVnohUDJw0nxddZrA1ARRYMXBRv/Imulb4a/dfpQW0wHbgB4NNPY44Cy9eNXNB9BTCCIkjMwtySYF1BSc73tXS52xQaIekJuz+rj/o3ACASNcPVSgeyMryxdsNHeMc4RRqkMDxNgVm+Q8YF85Bd8KJXI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768612777098382.658895545777; Fri, 16 Jan 2026 17:19:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vguxM-0004r4-TZ; Fri, 16 Jan 2026 20:18:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vguxG-0004nM-H0 for qemu-devel@nongnu.org; Fri, 16 Jan 2026 20:18:18 -0500 Received: from mgamail.intel.com ([192.198.163.18]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vguxE-0007Aa-G8 for qemu-devel@nongnu.org; Fri, 16 Jan 2026 20:18:18 -0500 Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jan 2026 17:18:09 -0800 Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jan 2026 17:18:09 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768612697; x=1800148697; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vEIyTu/kBF1eBSOMPe+vyM/W3HEARflxO8H2okHBMss=; b=gUaru1mk1ObuwWV9KEv6KcZBg8BMRSp/EJE5fVn0LD00NlLr7lFZzCaZ VyNSfa/koxNYGhxT7ordg1xIohAbodLq7MydaC9e8pv5je+1mrIjyOPRG Baz99SKYlziA/UJH5ZJKq6ZTIpTXGKufOMZ3quD/HEQTk7G6brn50I60z CZFTAc1xw4pRTrHQ77U+kQ2wf6s9mnjYTHjLiM1z2gdpuuwPs80+pryMd sAt7w4I+YDIjQuOjvnQC7mFvrPVkuCpssw7O6lTg5TnKgEc8bKgSaiCcQ Jtib29xPMyda46k9EyYx77EI+H1+EOuLH7iF/cbo5QVlu0bQp8be7cPND g==; X-CSE-ConnectionGUID: G85Ul2awQFOx1TaWIQbvdw== X-CSE-MsgGUID: U8JZRFGNQTiQ/FNRR5WMAA== X-IronPort-AV: E=McAfee;i="6800,10657,11673"; a="69131178" X-IronPort-AV: E=Sophos;i="6.21,232,1763452800"; d="scan'208";a="69131178" X-CSE-ConnectionGUID: BuQ5J8yQQzOdwChrgS8B7A== X-CSE-MsgGUID: UnawozAMSbyGCXagXYsYAQ== X-ExtLoop1: 1 From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: xiaoyao.li@intel.com, Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH 7/7] target/i386: Increase MSR_BUF_SIZE and split KVM_[GET/SET]_MSRS calls Date: Fri, 16 Jan 2026 17:10:53 -0800 Message-ID: <20260117011053.80723-8-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260117011053.80723-1-zide.chen@intel.com> References: <20260117011053.80723-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.18; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1768612779953158500 Content-Type: text/plain; charset="utf-8" Newer Intel server CPUs support a large number of PMU MSRs. Currently, QEMU allocates cpu->kvm_msr_buf as a single-page buffer, which is not sufficient to hold all possible MSRs. Increase MSR_BUF_SIZE to 8192 bytes, providing space for up to 511 MSRs. This is sufficient even for the theoretical worst case, such as architectural LBR with a depth of 64. KVM_[GET/SET]_MSRS is limited to 255 MSRs per call. Raising this limit to 511 would require changes in KVM and would introduce backward compatibility issues. Instead, split requests into multiple KVM_[GET/SET]_MSRS calls when the number of MSRs exceeds the API limit. Signed-off-by: Zide Chen --- target/i386/kvm/kvm.c | 109 +++++++++++++++++++++++++++++++++++------- 1 file changed, 92 insertions(+), 17 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 80974114a173..a72e4d60dfa2 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -98,9 +98,12 @@ #define KVM_APIC_BUS_CYCLE_NS 1 #define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS) =20 -/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus - * 255 kvm_msr_entry structs */ -#define MSR_BUF_SIZE 4096 +/* A 8192-byte buffer can hold the 8-byte kvm_msrs header, plus + * 511 kvm_msr_entry structs */ +#define MSR_BUF_SIZE 8192 + +/* Maximum number of MSRs in one single KVM_[GET/SET]_MSRS call. */ +#define KVM_MAX_IO_MSRS 255 =20 typedef bool QEMURDMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t *val); typedef bool QEMUWRMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t val); @@ -3878,23 +3881,102 @@ static void kvm_msr_entry_add_perf(X86CPU *cpu, Fe= atureWordArray f) } } =20 -static int kvm_buf_set_msrs(X86CPU *cpu) +static int __kvm_buf_set_msrs(X86CPU *cpu, struct kvm_msrs *msrs) { - int ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); + int ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, msrs); if (ret < 0) { return ret; } =20 - if (ret < cpu->kvm_msr_buf->nmsrs) { - struct kvm_msr_entry *e =3D &cpu->kvm_msr_buf->entries[ret]; + if (ret < msrs->nmsrs) { + struct kvm_msr_entry *e =3D &msrs->entries[ret]; error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx6= 4, (uint32_t)e->index, (uint64_t)e->data); } =20 - assert(ret =3D=3D cpu->kvm_msr_buf->nmsrs); + assert(ret =3D=3D msrs->nmsrs); + return ret; +} + +static int __kvm_buf_get_msrs(X86CPU *cpu, struct kvm_msrs *msrs) +{ + int ret; + + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, msrs); + if (ret < 0) { + return ret; + } + + if (ret < msrs->nmsrs) { + struct kvm_msr_entry *e =3D &msrs->entries[ret]; + error_report("error: failed to get MSR 0x%" PRIx32, + (uint32_t)e->index); + } + + assert(ret =3D=3D msrs->nmsrs); + return ret; +} + +static int kvm_buf_set_or_get_msrs(X86CPU *cpu, bool is_write) +{ + struct kvm_msr_entry *entries =3D cpu->kvm_msr_buf->entries; + struct kvm_msrs *buf =3D NULL; + int current, remaining, ret =3D 0; + size_t buf_size; + + buf_size =3D KVM_MAX_IO_MSRS * sizeof(struct kvm_msr_entry) + + sizeof(struct kvm_msrs); + buf =3D g_malloc(buf_size); + + remaining =3D cpu->kvm_msr_buf->nmsrs; + current =3D 0; + while (remaining) { + size_t size; + + memset(buf, 0, buf_size); + + if (remaining > KVM_MAX_IO_MSRS) { + buf->nmsrs =3D KVM_MAX_IO_MSRS; + } else { + buf->nmsrs =3D remaining; + } + + size =3D buf->nmsrs * sizeof(entries[0]); + memcpy(buf->entries, &entries[current], size); + + if (is_write) { + ret =3D __kvm_buf_set_msrs(cpu, buf); + } else { + ret =3D __kvm_buf_get_msrs(cpu, buf); + } + + if (ret < 0) { + goto out; + } + + if (!is_write) + memcpy(&entries[current], buf->entries, size); + + current +=3D buf->nmsrs; + remaining -=3D buf->nmsrs; + } + +out: + g_free(buf); + return ret < 0 ? ret : cpu->kvm_msr_buf->nmsrs; +} + +static int kvm_buf_set_msrs(X86CPU *cpu) +{ + kvm_buf_set_or_get_msrs(cpu, true); return 0; } =20 +static int kvm_buf_get_msrs(X86CPU *cpu) +{ + return kvm_buf_set_or_get_msrs(cpu, false); +} + static void kvm_init_msrs(X86CPU *cpu) { CPUX86State *env =3D &cpu->env; @@ -3928,7 +4010,7 @@ static void kvm_init_msrs(X86CPU *cpu) if (has_msr_ucode_rev) { kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev); } - assert(kvm_buf_set_msrs(cpu) =3D=3D 0); + kvm_buf_set_msrs(cpu); } =20 static int kvm_put_msrs(X86CPU *cpu, KvmPutState level) @@ -4762,18 +4844,11 @@ static int kvm_get_msrs(X86CPU *cpu) } } =20 - ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf); + ret =3D kvm_buf_get_msrs(cpu); if (ret < 0) { return ret; } =20 - if (ret < cpu->kvm_msr_buf->nmsrs) { - struct kvm_msr_entry *e =3D &cpu->kvm_msr_buf->entries[ret]; - error_report("error: failed to get MSR 0x%" PRIx32, - (uint32_t)e->index); - } - - assert(ret =3D=3D cpu->kvm_msr_buf->nmsrs); /* * MTRR masks: Each mask consists of 5 parts * a 10..0: must be zero --=20 2.52.0