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Thu, 15 Jan 2026 19:35:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: ktokunaga.mail@gmail.com, berrange@redhat.com, pierrick.bouvier@linaro.org, thuth@redhat.com, pbonzini@redhat.com, philmd@linaro.org Subject: [PATCH v2 34/58] tcg: Drop TCG_TARGET_REG_BITS tests in tcg-op-ldst.c Date: Fri, 16 Jan 2026 14:32:40 +1100 Message-ID: <20260116033305.51162-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260116033305.51162-1-richard.henderson@linaro.org> References: <20260116033305.51162-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768534633800158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg-op-ldst.c | 113 +++++++++++----------------------------------- 1 file changed, 27 insertions(+), 86 deletions(-) diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 7716c3ad7c..55bfbf3a20 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -106,24 +106,12 @@ static void gen_ldst2(TCGOpcode opc, TCGType type, TC= GTemp *vl, TCGTemp *vh, =20 static void gen_ld_i64(TCGv_i64 v, TCGTemp *addr, MemOpIdx oi) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - gen_ldst2(INDEX_op_qemu_ld2, TCG_TYPE_I64, - tcgv_i32_temp(TCGV_LOW(v)), tcgv_i32_temp(TCGV_HIGH(v)), - addr, oi); - } else { - gen_ldst1(INDEX_op_qemu_ld, TCG_TYPE_I64, tcgv_i64_temp(v), addr, = oi); - } + gen_ldst1(INDEX_op_qemu_ld, TCG_TYPE_I64, tcgv_i64_temp(v), addr, oi); } =20 static void gen_st_i64(TCGv_i64 v, TCGTemp *addr, MemOpIdx oi) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - gen_ldst2(INDEX_op_qemu_st2, TCG_TYPE_I64, - tcgv_i32_temp(TCGV_LOW(v)), tcgv_i32_temp(TCGV_HIGH(v)), - addr, oi); - } else { - gen_ldst1(INDEX_op_qemu_st, TCG_TYPE_I64, tcgv_i64_temp(v), addr, = oi); - } + gen_ldst1(INDEX_op_qemu_st, TCG_TYPE_I64, tcgv_i64_temp(v), addr, oi); } =20 static void tcg_gen_req_mo(TCGBar type) @@ -143,7 +131,7 @@ static TCGTemp *tci_extend_addr(TCGTemp *addr) * Compare to the extension performed by tcg_out_{ld,st}_helper_args * for native code generation. */ - if (TCG_TARGET_REG_BITS =3D=3D 64 && tcg_ctx->addr_type =3D=3D TCG_TYP= E_I32) { + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { TCGv_i64 temp =3D tcg_temp_ebb_new_i64(); tcg_gen_extu_i32_i64(temp, temp_tcgv_i32(addr)); return tcgv_i64_temp(temp); @@ -356,16 +344,6 @@ static void tcg_gen_qemu_ld_i64_int(TCGv_i64 val, TCGT= emp *addr, TCGv_i64 copy_addr; TCGTemp *addr_new; =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { - tcg_gen_qemu_ld_i32_int(TCGV_LOW(val), addr, idx, memop); - if (memop & MO_SIGN) { - tcg_gen_sari_i32(TCGV_HIGH(val), TCGV_LOW(val), 31); - } else { - tcg_gen_movi_i32(TCGV_HIGH(val), 0); - } - return; - } - tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); orig_memop =3D memop =3D tcg_canonicalize_memop(memop, 1, 0); orig_oi =3D oi =3D make_memop_idx(memop, idx); @@ -421,11 +399,6 @@ static void tcg_gen_qemu_st_i64_int(TCGv_i64 val, TCGT= emp *addr, MemOpIdx orig_oi, oi; TCGTemp *addr_new; =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { - tcg_gen_qemu_st_i32_int(TCGV_LOW(val), addr, idx, memop); - return; - } - tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop =3D tcg_canonicalize_memop(memop, 1, 1); orig_oi =3D oi =3D make_memop_idx(memop, idx); @@ -577,7 +550,7 @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCG= Temp *addr, orig_oi =3D make_memop_idx(memop, idx); =20 /* TODO: For now, force 32-bit hosts to use the helper. */ - if (TCG_TARGET_HAS_qemu_ldst_i128 && TCG_TARGET_REG_BITS =3D=3D 64) { + if (TCG_TARGET_HAS_qemu_ldst_i128) { TCGv_i64 lo, hi; bool need_bswap =3D false; MemOpIdx oi =3D orig_oi; @@ -691,7 +664,7 @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCG= Temp *addr, =20 /* TODO: For now, force 32-bit hosts to use the helper. */ =20 - if (TCG_TARGET_HAS_qemu_ldst_i128 && TCG_TARGET_REG_BITS =3D=3D 64) { + if (TCG_TARGET_HAS_qemu_ldst_i128) { TCGv_i64 lo, hi; MemOpIdx oi =3D orig_oi; bool need_bswap =3D false; @@ -950,17 +923,6 @@ static void tcg_gen_nonatomic_cmpxchg_i64_int(TCGv_i64= retv, TCGTemp *addr, { TCGv_i64 t1, t2; =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { - tcg_gen_nonatomic_cmpxchg_i32_int(TCGV_LOW(retv), addr, TCGV_LOW(c= mpv), - TCGV_LOW(newv), idx, memop); - if (memop & MO_SIGN) { - tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); - } else { - tcg_gen_movi_i32(TCGV_HIGH(retv), 0); - } - return; - } - t1 =3D tcg_temp_ebb_new_i64(); t2 =3D tcg_temp_ebb_new_i64(); =20 @@ -1019,17 +981,6 @@ static void tcg_gen_atomic_cmpxchg_i64_int(TCGv_i64 r= etv, TCGTemp *addr, * is removed. */ tcg_gen_movi_i64(retv, 0); - return; - } - - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_atomic_cmpxchg_i32_int(TCGV_LOW(retv), addr, TCGV_LOW(cmpv= ), - TCGV_LOW(newv), idx, memop); - if (memop & MO_SIGN) { - tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); - } else { - tcg_gen_movi_i32(TCGV_HIGH(retv), 0); - } } else { TCGv_i32 c32 =3D tcg_temp_ebb_new_i32(); TCGv_i32 n32 =3D tcg_temp_ebb_new_i32(); @@ -1064,43 +1015,33 @@ static void tcg_gen_nonatomic_cmpxchg_i128_int(TCGv= _i128 retv, TCGTemp *addr, TCGv_i128 cmpv, TCGv_i128 n= ewv, TCGArg idx, MemOp memop) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - /* Inline expansion below is simply too large for 32-bit hosts. */ - MemOpIdx oi =3D make_memop_idx(memop, idx); - TCGv_i64 a64 =3D maybe_extend_addr64(addr); + TCGv_i128 oldv =3D tcg_temp_ebb_new_i128(); + TCGv_i128 tmpv =3D tcg_temp_ebb_new_i128(); + TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); + TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); + TCGv_i64 z =3D tcg_constant_i64(0); =20 - gen_helper_nonatomic_cmpxchgo(retv, tcg_env, a64, cmpv, newv, - tcg_constant_i32(oi)); - maybe_free_addr64(a64); - } else { - TCGv_i128 oldv =3D tcg_temp_ebb_new_i128(); - TCGv_i128 tmpv =3D tcg_temp_ebb_new_i128(); - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 z =3D tcg_constant_i64(0); + tcg_gen_qemu_ld_i128_int(oldv, addr, idx, memop); =20 - tcg_gen_qemu_ld_i128_int(oldv, addr, idx, memop); + /* Compare i128 */ + tcg_gen_xor_i64(t0, TCGV128_LOW(oldv), TCGV128_LOW(cmpv)); + tcg_gen_xor_i64(t1, TCGV128_HIGH(oldv), TCGV128_HIGH(cmpv)); + tcg_gen_or_i64(t0, t0, t1); =20 - /* Compare i128 */ - tcg_gen_xor_i64(t0, TCGV128_LOW(oldv), TCGV128_LOW(cmpv)); - tcg_gen_xor_i64(t1, TCGV128_HIGH(oldv), TCGV128_HIGH(cmpv)); - tcg_gen_or_i64(t0, t0, t1); + /* tmpv =3D equal ? newv : oldv */ + tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_LOW(tmpv), t0, z, + TCGV128_LOW(newv), TCGV128_LOW(oldv)); + tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_HIGH(tmpv), t0, z, + TCGV128_HIGH(newv), TCGV128_HIGH(oldv)); =20 - /* tmpv =3D equal ? newv : oldv */ - tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_LOW(tmpv), t0, z, - TCGV128_LOW(newv), TCGV128_LOW(oldv)); - tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_HIGH(tmpv), t0, z, - TCGV128_HIGH(newv), TCGV128_HIGH(oldv)); + /* Unconditional writeback. */ + tcg_gen_qemu_st_i128_int(tmpv, addr, idx, memop); + tcg_gen_mov_i128(retv, oldv); =20 - /* Unconditional writeback. */ - tcg_gen_qemu_st_i128_int(tmpv, addr, idx, memop); - tcg_gen_mov_i128(retv, oldv); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i128(tmpv); - tcg_temp_free_i128(oldv); - } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i128(tmpv); + tcg_temp_free_i128(oldv); } =20 void tcg_gen_nonatomic_cmpxchg_i128_chk(TCGv_i128 retv, TCGTemp *addr, --=20 2.43.0