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Thu, 15 Jan 2026 19:35:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: ktokunaga.mail@gmail.com, berrange@redhat.com, pierrick.bouvier@linaro.org, thuth@redhat.com, pbonzini@redhat.com, philmd@linaro.org Subject: [PATCH v2 33/58] tcg: Drop TCG_TARGET_REG_BITS tests in tcg-op-gvec.c Date: Fri, 16 Jan 2026 14:32:39 +1100 Message-ID: <20260116033305.51162-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260116033305.51162-1-richard.henderson@linaro.org> References: <20260116033305.51162-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768534611783158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.c | 49 +++++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 25 deletions(-) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 2cfc7e9409..bc323e2500 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -586,12 +586,11 @@ static void do_dup(unsigned vece, TCGv_ptr dbase, uin= t32_t dofs, } } =20 - /* Implement inline with a vector type, if possible. - * Prefer integer when 64-bit host and no variable dup. + /* + * Implement inline with a vector type, if possible; + * prefer_i64 with 64-bit variable dup. */ - type =3D choose_vector_type(NULL, vece, oprsz, - (TCG_TARGET_REG_BITS =3D=3D 64 && in_32 =3D= =3D NULL - && (in_64 =3D=3D NULL || vece =3D=3D MO_64)= )); + type =3D choose_vector_type(NULL, vece, oprsz, vece =3D=3D MO_64 && in= _64); if (type !=3D 0) { TCGv_vec t_vec =3D tcg_temp_new_vec(type); =20 @@ -612,11 +611,11 @@ static void do_dup(unsigned vece, TCGv_ptr dbase, uin= t32_t dofs, t_32 =3D NULL; =20 if (in_32) { - /* We are given a 32-bit variable input. For a 64-bit host, - use a 64-bit operation unless the 32-bit operation would - be simple enough. */ - if (TCG_TARGET_REG_BITS =3D=3D 64 - && (vece !=3D MO_32 || !check_size_impl(oprsz, 4))) { + /* + * We are given a 32-bit variable input. Use a 64-bit operati= on + * unless the 32-bit operation would be simple enough. + */ + if (vece !=3D MO_32 || !check_size_impl(oprsz, 4)) { t_64 =3D tcg_temp_ebb_new_i64(); tcg_gen_extu_i32_i64(t_64, in_32); tcg_gen_dup_i64(vece, t_64, t_64); @@ -629,14 +628,16 @@ static void do_dup(unsigned vece, TCGv_ptr dbase, uin= t32_t dofs, t_64 =3D tcg_temp_ebb_new_i64(); tcg_gen_dup_i64(vece, t_64, in_64); } else { - /* We are given a constant input. */ - /* For 64-bit hosts, use 64-bit constants for "simple" constan= ts - or when we'd need too many 32-bit stores, or when a 64-bit - constant is really required. */ + /* + * We are given a constant input. + * Use 64-bit constants for "simple" constants or when we'd + * need too many 32-bit stores, or when a 64-bit constant + * is really required. + */ if (vece =3D=3D MO_64 - || (TCG_TARGET_REG_BITS =3D=3D 64 - && (in_c =3D=3D 0 || in_c =3D=3D -1 - || !check_size_impl(oprsz, 4)))) { + || in_c =3D=3D 0 + || in_c =3D=3D -1 + || !check_size_impl(oprsz, 4)) { t_64 =3D tcg_constant_i64(in_c); } else { t_32 =3D tcg_constant_i32(in_c); @@ -3872,12 +3873,11 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, = uint32_t dofs, } =20 /* - * Implement inline with a vector type, if possible. - * Prefer integer when 64-bit host and 64-bit comparison. + * Implement inline with a vector type, if possible; + * prefer_i64 for a 64-bit comparison. */ hold_list =3D tcg_swap_vecop_list(cmp_list); - type =3D choose_vector_type(cmp_list, vece, oprsz, - TCG_TARGET_REG_BITS =3D=3D 64 && vece =3D=3D= MO_64); + type =3D choose_vector_type(cmp_list, vece, oprsz, vece =3D=3D MO_64); switch (type) { case TCG_TYPE_V256: /* Recall that ARM SVE allows vector sizes that are not a @@ -3992,11 +3992,10 @@ void tcg_gen_gvec_cmps(TCGCond cond, unsigned vece,= uint32_t dofs, } =20 /* - * Implement inline with a vector type, if possible. - * Prefer integer when 64-bit host and 64-bit comparison. + * Implement inline with a vector type, if possible; + * prefer_i64 for a 64-bit comparison. */ - type =3D choose_vector_type(cmp_list, vece, oprsz, - TCG_TARGET_REG_BITS =3D=3D 64 && vece =3D=3D= MO_64); + type =3D choose_vector_type(cmp_list, vece, oprsz, vece =3D=3D MO_64); if (type !=3D 0) { const TCGOpcode *hold_list =3D tcg_swap_vecop_list(cmp_list); TCGv_vec t_vec =3D tcg_temp_new_vec(type); --=20 2.43.0