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[2001:8b0:1d0:0:428d:5cff:fe57:1f7f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4356996cecasm514207f8f.26.2026.01.15.10.55.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 10:55:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768503312; x=1769108112; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=dFDbbBRCQ6aEWxiWdS+TlHvgeoAjTJihJKhODkPXEig=; b=tDo/pOn9LjzTBysfcSn5Nn/2Vf6xqgjk0cr9ocbmizezB6yK442cQt6pIQZXPvLHOY NQpCyrkJWdehzXlETpLpPqOb2CMnRaXhz+werThltktVToc2ePZOOZHMrVvjU9WpKPPF vz0Remufz2jTaqOVQT2FcagzjWarxtmmpo2MrZXlT4b0pspqYxWc3bQM33oUsUP4E4Ir 5aG/PEQGpN14POonr/lEYWBH2XLiinYHsAFynKQsVcBgRYMFRG1NmdRlLGbUSWHlBtJo Kf+TArecXwE4YLKw/PHvxrpQiNcV+ymsd4GDCc+zzwQ4LxZZooYrC+hrVUdeAJAE6QUT xZlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768503312; x=1769108112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=dFDbbBRCQ6aEWxiWdS+TlHvgeoAjTJihJKhODkPXEig=; b=Zb7RDZkreALnTAMJzMCavIFrAGDTHrsG0qzqjoPT6LENEi/eoZPvc4Oe+3c9bl1b95 tzxYDxMJZKxbT56aMBsVKrGSs2bDk/Ab+WUDJoztSowu8yTL6fIOnW+lgSWbZeJdgrti OMWIIJXQDtf4wdpD4rgDb4CIsQlntz4w3WmvLug2yCsSc+jlywmActTJfQVfV36KcQsw 7wraUY83qi6pg5NNoAHqCyLpRdfnPU/ebj6LcXCIdZjoPbgaQtcZqiXGhZtthoYV9sLv VgrtAxISP1hpc6dhHFOBe7jAnlFiDNSAcGdcydDgC8lgO3iFe/LauI6VAoiMKgURNm5X Zs8A== X-Gm-Message-State: AOJu0YxhQPJcfRPld/x/TgsZE2sY/jOFMHbmg+xSNs8bJN5zc4VTQkHb oL7oNMSFlCznUPTTeR/bwWYboPUV+R1h5RDIa6bHU72p/XRKSFXZ0qz126NPCRiPKFZ10dQ6tNk LcwT/ X-Gm-Gg: AY/fxX5m9wNXAZsFB3UN+O4gHaP5Tl7NDBVFiU6lsyvt2Kiy5nKQeiqJU15B1aSGEkO bwjwQ31ieT8bJzWzT1SXIa0ZNsM+Sk3dWuW6GE8vOc2UcaQOemZ6YXWRfEoyYeHmgmDKRVwBFvb +fCJyAUxxWhsB1F3g/FHn+QTipISl2klJhtLVmRHWvRlSXL6kh/95dFbR9nf6JiEQwJAQpfwS99 NNn0ghKKUrhPPhhB6HBRnm/4/QvoLzllM6DImj3ROkTYmEse9nq1QlKNz5UZPjIVEvi57ADMr8Y mt+dU0Gkv/AMYpenxm1Xv7u+VH1OniuBbo1nAT9jbVv3/sK+zxGRwqmltwxLI3lRNje3R9VSHN7 j/TbK+kdcxdfLRSznfyTnHb7hUrJK3yI8cNpk64aVYgtMnFligNbRkOlkUBNrau0CyNK8wHSujM YrioqCGK4Q3cRkGEgfTJbFMse0zl2PxP6y0/ZoMTp2zsyTHCG1042G9KL9m0NULjDSYQTe9iJ0j mXPcjKLEJYgVO3UazghLnw9rDR1W2QQFhC1nyzkzGYVxQ== X-Received: by 2002:a05:600c:4584:b0:47b:deb9:15fb with SMTP id 5b1f17b1804b1-4801e350af0mr7788195e9.33.1768503312031; Thu, 15 Jan 2026 10:55:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/25] target/arm: Allow writes to FNG1, FNG0, A2 Date: Thu, 15 Jan 2026 18:54:45 +0000 Message-ID: <20260115185508.786428-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260115185508.786428-1-peter.maydell@linaro.org> References: <20260115185508.786428-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768503363368158500 Content-Type: text/plain; charset="utf-8" From: Jim MacArthur This just allows read/write of three feature bits. ASID is still ignored. Any writes to TTBR0_EL0 and TTBR1_EL0, including changing the ASID, will still cause a complete flush of the TLB. Signed-off-by: Jim MacArthur Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 7 +++++++ target/arm/helper.c | 28 ++++++++++++++++++++++------ target/arm/internals.h | 5 +++++ 3 files changed, 34 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index c86a4e667d..a7ca410dcb 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -346,6 +346,8 @@ FIELD(ID_AA64MMFR3, SDERR, 52, 4) FIELD(ID_AA64MMFR3, ADERR, 56, 4) FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) =20 +FIELD(ID_AA64MMFR4, ASID2, 8, 4) + FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) FIELD(ID_AA64DFR0, TRACEVER, 4, 4) FIELD(ID_AA64DFR0, PMUVER, 8, 4) @@ -1369,6 +1371,11 @@ static inline bool isar_feature_aa64_aie(const ARMIS= ARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR3, AIE) !=3D 0; } =20 +static inline bool isar_feature_aa64_asid2(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR4, ASID2) !=3D 0; +} + static inline bool isar_feature_aa64_mec(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index a7239ff25b..1ee721ac7b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -428,6 +428,15 @@ int alle1_tlbmask(CPUARMState *env) ARMMMUIdxBit_Stage2_S); } =20 +int alle2_tlbmask(void) +{ + return (ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_2_GCS | + ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E20_0_GCS); +} + static const ARMCPRegInfo cp_reginfo[] =3D { /* * Define the secure and non-secure FCSE identifier CP registers @@ -2802,12 +2811,7 @@ static void vmsa_tcr_ttbr_el2_write(CPUARMState *env= , const ARMCPRegInfo *ri, */ if (extract64(raw_read(env, ri) ^ value, 48, 16) && (arm_hcr_el2_eff(env) & HCR_E2H)) { - uint16_t mask =3D ARMMMUIdxBit_E20_2 | - ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E20_2_GCS | - ARMMMUIdxBit_E20_0 | - ARMMMUIdxBit_E20_0_GCS; - tlb_flush_by_mmuidx(env_cpu(env), mask); + tlb_flush_by_mmuidx(env_cpu(env), alle2_tlbmask()); } raw_write(env, ri, value); } @@ -6102,6 +6106,12 @@ static void tcr2_el1_write(CPUARMState *env, const A= RMCPRegInfo *ri, if (cpu_isar_feature(aa64_aie, cpu)) { valid_mask |=3D TCR2_AIE; } + if (cpu_isar_feature(aa64_asid2, cpu)) { + valid_mask |=3D TCR2_FNG1 | TCR2_FNG0 | TCR2_A2; + if (((raw_read(env, ri) ^ value) & TCR2_A2) !=3D 0) { + tlb_flush_by_mmuidx(CPU(cpu), alle1_tlbmask(env)); + } + } value &=3D valid_mask; raw_write(env, ri, value); } @@ -6121,6 +6131,12 @@ static void tcr2_el2_write(CPUARMState *env, const A= RMCPRegInfo *ri, if (cpu_isar_feature(aa64_mec, cpu)) { valid_mask |=3D TCR2_AMEC0 | TCR2_AMEC1; } + if (cpu_isar_feature(aa64_asid2, cpu)) { + valid_mask |=3D TCR2_FNG1 | TCR2_FNG0 | TCR2_A2; + if (((raw_read(env, ri) ^ value) & TCR2_A2) !=3D 0) { + tlb_flush_by_mmuidx(CPU(cpu), alle2_tlbmask()); + } + } value &=3D valid_mask; raw_write(env, ri, value); } diff --git a/target/arm/internals.h b/target/arm/internals.h index 440072d820..f7b641342a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1892,6 +1892,11 @@ uint64_t gt_direct_access_timer_offset(CPUARMState *= env, int timeridx); * all EL1" scope; this covers stage 1 and stage 2. */ int alle1_tlbmask(CPUARMState *env); +/* + * Return mask of ARMMMUIdxBit values corresponding to an "invalidate + * all EL2&0" scope. + */ +int alle2_tlbmask(void); =20 /* Set the float_status behaviour to match the Arm defaults */ void arm_set_default_fp_behaviours(float_status *s); --=20 2.47.3