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Thu, 15 Jan 2026 10:55:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/25] hw/arm/raspi: remove duplicate include Date: Thu, 15 Jan 2026 18:54:43 +0000 Message-ID: <20260115185508.786428-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260115185508.786428-1-peter.maydell@linaro.org> References: <20260115185508.786428-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768503392706158500 Content-Type: text/plain; charset="utf-8" From: Osama Abdelkader hw/arm/boot.h is included twice Signed-off-by: Osama Abdelkader Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/raspi.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 1276bb4df4..00e4a10466 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -24,7 +24,6 @@ #include "qemu/error-report.h" #include "hw/core/boards.h" #include "hw/core/loader.h" -#include "hw/arm/boot.h" #include "hw/arm/machines-qom.h" #include "qom/object.h" =20 --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768503347; cv=none; d=zohomail.com; s=zohoarc; b=XNlMSMmQitWxSeGrlUGDrN++tJezUsrKuMX5NqYsUt1TAoah4BZowu60elfebtK6AP3spS3/6bjeGKvAhU0Ufuwg1hsC+bW4owSzC0w9cSX6vKSeTnwzl/Sn+1DNclTCRHce7RDEmdPy1TSeUqB+gMtaNuctPLpq2VWSxdc1sf8= ARC-Message-Signature: i=1; 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Thu, 15 Jan 2026 10:55:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/25] target/arm: Enable ID_AA64MMFR4_EL1 register Date: Thu, 15 Jan 2026 18:54:44 +0000 Message-ID: <20260115185508.786428-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260115185508.786428-1-peter.maydell@linaro.org> References: <20260115185508.786428-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768503348743158500 From: Jim MacArthur Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Gustavo Romero Signed-off-by: Jim MacArthur [PMM: add entry to v8_user_idregs[] list also] Signed-off-by: Peter Maydell --- target/arm/cpu-sysregs.h.inc | 1 + target/arm/helper.c | 6 ++++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index 2bb2861c62..2ba49d8478 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -14,6 +14,7 @@ DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0) DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2) DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3) +DEF(ID_AA64MMFR4_EL1, 3, 0, 0, 7, 4) DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2) diff --git a/target/arm/helper.c b/target/arm/helper.c index 263ca29d92..a7239ff25b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6566,11 +6566,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR3) }, - { .name =3D "ID_AA64MMFR4_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + { .name =3D "ID_AA64MMFR4_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR4) }, { .name =3D "ID_AA64MMFR5_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -6706,6 +6706,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .exported_bits =3D R_ID_AA64MMFR2_AT_MASK }, { .name =3D "ID_AA64MMFR3_EL1", .exported_bits =3D 0 }, + { .name =3D "ID_AA64MMFR4_EL1", + .exported_bits =3D 0 }, { .name =3D "ID_AA64MMFR*_EL1_RESERVED", .is_glob =3D true }, { .name =3D "ID_AA64DFR0_EL1", --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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ASID is still ignored. Any writes to TTBR0_EL0 and TTBR1_EL0, including changing the ASID, will still cause a complete flush of the TLB. Signed-off-by: Jim MacArthur Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 7 +++++++ target/arm/helper.c | 28 ++++++++++++++++++++++------ target/arm/internals.h | 5 +++++ 3 files changed, 34 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index c86a4e667d..a7ca410dcb 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -346,6 +346,8 @@ FIELD(ID_AA64MMFR3, SDERR, 52, 4) FIELD(ID_AA64MMFR3, ADERR, 56, 4) FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) =20 +FIELD(ID_AA64MMFR4, ASID2, 8, 4) + FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) FIELD(ID_AA64DFR0, TRACEVER, 4, 4) FIELD(ID_AA64DFR0, PMUVER, 8, 4) @@ -1369,6 +1371,11 @@ static inline bool isar_feature_aa64_aie(const ARMIS= ARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR3, AIE) !=3D 0; } =20 +static inline bool isar_feature_aa64_asid2(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR4, ASID2) !=3D 0; +} + static inline bool isar_feature_aa64_mec(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index a7239ff25b..1ee721ac7b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -428,6 +428,15 @@ int alle1_tlbmask(CPUARMState *env) ARMMMUIdxBit_Stage2_S); } =20 +int alle2_tlbmask(void) +{ + return (ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_2_GCS | + ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E20_0_GCS); +} + static const ARMCPRegInfo cp_reginfo[] =3D { /* * Define the secure and non-secure FCSE identifier CP registers @@ -2802,12 +2811,7 @@ static void vmsa_tcr_ttbr_el2_write(CPUARMState *env= , const ARMCPRegInfo *ri, */ if (extract64(raw_read(env, ri) ^ value, 48, 16) && (arm_hcr_el2_eff(env) & HCR_E2H)) { - uint16_t mask =3D ARMMMUIdxBit_E20_2 | - ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E20_2_GCS | - ARMMMUIdxBit_E20_0 | - ARMMMUIdxBit_E20_0_GCS; - tlb_flush_by_mmuidx(env_cpu(env), mask); + tlb_flush_by_mmuidx(env_cpu(env), alle2_tlbmask()); } raw_write(env, ri, value); } @@ -6102,6 +6106,12 @@ static void tcr2_el1_write(CPUARMState *env, const A= RMCPRegInfo *ri, if (cpu_isar_feature(aa64_aie, cpu)) { valid_mask |=3D TCR2_AIE; } + if (cpu_isar_feature(aa64_asid2, cpu)) { + valid_mask |=3D TCR2_FNG1 | TCR2_FNG0 | TCR2_A2; + if (((raw_read(env, ri) ^ value) & TCR2_A2) !=3D 0) { + tlb_flush_by_mmuidx(CPU(cpu), alle1_tlbmask(env)); + } + } value &=3D valid_mask; raw_write(env, ri, value); } @@ -6121,6 +6131,12 @@ static void tcr2_el2_write(CPUARMState *env, const A= RMCPRegInfo *ri, if (cpu_isar_feature(aa64_mec, cpu)) { valid_mask |=3D TCR2_AMEC0 | TCR2_AMEC1; } + if (cpu_isar_feature(aa64_asid2, cpu)) { + valid_mask |=3D TCR2_FNG1 | TCR2_FNG0 | TCR2_A2; + if (((raw_read(env, ri) ^ value) & TCR2_A2) !=3D 0) { + tlb_flush_by_mmuidx(CPU(cpu), alle2_tlbmask()); + } + } value &=3D valid_mask; raw_write(env, ri, value); } diff --git a/target/arm/internals.h b/target/arm/internals.h index 440072d820..f7b641342a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1892,6 +1892,11 @@ uint64_t gt_direct_access_timer_offset(CPUARMState *= env, int timeridx); * all EL1" scope; this covers stage 1 and stage 2. */ int alle1_tlbmask(CPUARMState *env); +/* + * Return mask of ARMMMUIdxBit values corresponding to an "invalidate + * all EL2&0" scope. + */ +int alle2_tlbmask(void); =20 /* Set the float_status behaviour to match the Arm defaults */ void arm_set_default_fp_behaviours(float_status *s); --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768503344; cv=none; d=zohomail.com; s=zohoarc; b=JrrSrLAoWkKV656zrvySZiQaiBT9Ducm3EblZergHyP+RIs7IYi4p6M4O9kg7cPoT3lCOfeIM3QefRTssJaqzL4aJT45kMOzqzhnLUZg9Y6Vc3JVARz0ZtT/4bn9ffu0jk1k1YXnlgmMeR+7QHdWD+tV9bPpR8vO77VRzfQ+n20= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768503344; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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Thu, 15 Jan 2026 10:55:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/25] target/arm/tcg/cpu64.c: Enable ASID2 for cpu_max Date: Thu, 15 Jan 2026 18:54:46 +0000 Message-ID: <20260115185508.786428-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260115185508.786428-1-peter.maydell@linaro.org> References: <20260115185508.786428-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768503346704158500 Content-Type: text/plain; charset="utf-8" From: Jim MacArthur docs/system/arm/emulation.rst: Add ASID2 Reviewed-by: Gustavo Romero Signed-off-by: Jim MacArthur Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 31a5878a8f..3f30ea5a30 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -24,6 +24,7 @@ the following architecture extensions: - FEAT_AIE (Memory Attribute Index Enhancement) - FEAT_Armv9_Crypto (Armv9 Cryptographic Extension) - FEAT_ASID16 (16 bit ASID) +- FEAT_ASID2 (Concurrent use of two ASIDs) - FEAT_ATS1A (Address Translation operations that ignore stage 1 permissio= ns) - FEAT_BBM at level 2 (Translation table break-before-make levels) - FEAT_BF16 (AArch64 BFloat16 instructions) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 917db5bb09..611838171b 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1334,6 +1334,10 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR3, AIE, 1); /* FEAT_AIE */ SET_IDREG(isar, ID_AA64MMFR3, t); =20 + t =3D GET_IDREG(isar, ID_AA64MMFR4); + t =3D FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* FEAT_ASID2 */ + SET_IDREG(isar, ID_AA64MMFR4, t); + t =3D GET_IDREG(isar, ID_AA64ZFR0); t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* FEAT_SVE2p1 */ t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768503349; cv=none; d=zohomail.com; s=zohoarc; b=Cc5HSXLpHFUfjixXt+vbDCVHgRwBsOUd5mlOOcoh1LaoS6JK5llH7vyV8RCaVEbAcHQIXp5Qge2nuLm8t30J/OK+oFBHL8mfncfE+xMwq6rL5L+pFdb1x6tfTgU0x/ClJUUp7dTfrcSgP7ICcWPBQV8RAP/LsL/oooX7/rFPuuU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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If not present, check these read as RES0. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Jim MacArthur Signed-off-by: Peter Maydell --- tests/tcg/aarch64/system/asid2.c | 76 ++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 tests/tcg/aarch64/system/asid2.c diff --git a/tests/tcg/aarch64/system/asid2.c b/tests/tcg/aarch64/system/as= id2.c new file mode 100644 index 0000000000..7d5466af34 --- /dev/null +++ b/tests/tcg/aarch64/system/asid2.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * + * ASID2 Feature presence and enabled TCR2_EL1 bits test + * + * Copyright (c) 2025 Linaro Ltd + * + */ + +#include +#include + +#define ID_AA64MMFR3_EL1 "S3_0_C0_C7_3" +#define ID_AA64MMFR4_EL1 "S3_0_C0_C7_4" +#define TCR2_EL1 "S3_0_C2_C0_3" + +int main() +{ + /* + * Test for presence of ASID2 and three feature bits enabled by it: + * https://developer.arm.com/documentation/109697/2025_09/Feature-desc= riptions/The-Armv9-5-architecture-extension + * Bits added are FNG1, FNG0, and A2. These should be RES0 if A2 is + * not enabled and read as the written value if A2 is enabled. + */ + + uint64_t out; + uint64_t idreg3; + uint64_t idreg4; + int tcr2_present; + int asid2_present; + + /* Mask is FNG1, FNG0, and A2 */ + const uint64_t feature_mask =3D (1ULL << 18 | 1ULL << 17 | 1ULL << 16); + const uint64_t in =3D feature_mask; + + asm("mrs %[idreg3], " ID_AA64MMFR3_EL1 "\n\t" + : [idreg3] "=3Dr" (idreg3)); + + tcr2_present =3D ((idreg3 & 0xF) !=3D 0); + + if (!tcr2_present) { + ml_printf("TCR2 is not present, cannot perform test"); + return 0; + } + + asm("mrs %[idreg4], " ID_AA64MMFR4_EL1 "\n\t" + : [idreg4] "=3Dr" (idreg4)); + + asid2_present =3D ((idreg4 & 0xF00) !=3D 0); + + asm("msr " TCR2_EL1 ", %[x0]\n\t" + "mrs %[x1], " TCR2_EL1 "\n\t" + : [x1] "=3Dr" (out) + : [x0] "r" (in)); + + if (asid2_present) { + if ((out & feature_mask) =3D=3D in) { + ml_printf("OK\n"); + return 0; + } else { + ml_printf("FAIL: ASID2 present, but read value %lx !=3D " + "written value %lx\n", + out & feature_mask, in); + return 1; + } + } else { + if (out =3D=3D 0) { + ml_printf("TCR2_EL1 reads as RES0 as expected\n"); + return 0; + } else { + ml_printf("FAIL: ASID2, missing but read value %lx !=3D 0\n", + out & feature_mask, in); + return 1; + } + } +} --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768503352; cv=none; d=zohomail.com; s=zohoarc; b=MUs5FljHL/fhnOKDF2j5kA8UE8B1pQ/zRWvLFPOEPPO7NFfHSTZ/+Ls2SFbj06c8hbBjxwue89kCkZHIlxSBX1X964Q2ufPiuEOPwAneJUphQ819xPm5slH+4lIktWlTvEcEU1VFEisuLgE8jUlDVxj8AmZQLHB7mAJaHwY1OIY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768503352; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Zqq8lC3PTzkCbrFHvPVa1u+gK2upzDKe386+6s++ORg=; b=cgDbtkDNMlKoml6ly1l0ZJPUpr6VuXta5FSWw2D3AuWO4spUecxRRs1+UfkiHnBm7sI6ijdI7I88d7H62lWqexi3+F/TXcR8+/MLtOqTO6J3Qq7cDpik6GUkLSpsNSPg/chhbtwLIUvn6AMVRS2MQr9uuHqqOHxhr8796P1kb0Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768503352785286.03933874929317; Thu, 15 Jan 2026 10:55:52 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vgSVY-0000sj-H5; Thu, 15 Jan 2026 13:55:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vgSV6-0000dK-TL for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:22 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vgSV3-0005sv-Ev for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:19 -0500 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-42fbc305882so614536f8f.0 for ; Thu, 15 Jan 2026 10:55:15 -0800 (PST) Received: from mnementh.archaic.org.uk (f.7.f.1.7.5.e.f.f.f.c.5.d.8.2.4.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. 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Signed-off-by: julia Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20251217-cmsdk-uart-disabled-warning2-v1-1-847de48840bc@trainwi= t.ch Signed-off-by: Peter Maydell --- hw/char/cmsdk-apb-uart.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/char/cmsdk-apb-uart.c b/hw/char/cmsdk-apb-uart.c index bf891081dc..edb80f6181 100644 --- a/hw/char/cmsdk-apb-uart.c +++ b/hw/char/cmsdk-apb-uart.c @@ -159,6 +159,10 @@ static uint64_t uart_read(void *opaque, hwaddr offset,= unsigned size) switch (offset) { case A_DATA: r =3D s->rxbuf; + if (!(s->ctrl & R_CTRL_RX_EN_MASK)) { + qemu_log_mask(LOG_GUEST_ERROR, + "CMSDK APB UART: receive data read with Rx disab= led\n"); + } s->state &=3D ~R_STATE_RXFULL_MASK; cmsdk_apb_uart_update(s); qemu_chr_fe_accept_input(&s->chr); @@ -248,6 +252,10 @@ static void uart_write(void *opaque, hwaddr offset, ui= nt64_t value, switch (offset) { case A_DATA: s->txbuf =3D value; + if (!(s->ctrl & R_CTRL_TX_EN_MASK)) { + qemu_log_mask(LOG_GUEST_ERROR, + "CMSDK APB UART: transmit data write with Tx dis= abled\n"); + } if (s->state & R_STATE_TXFULL_MASK) { /* Buffer already full -- note the overrun and let the * existing pending transmit callback handle the new char. --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768503383; cv=none; d=zohomail.com; s=zohoarc; b=ZxjO/pVFds63TX3xKZ907zbCghS1LZiZQrgX7shfwexk3i/9LWfLyugNeiLrQjAzAWzssLnJ9eCuIcDWP9nsjFAVXdcQZS9qn1Lud2BcOkuGX0aOAmF1Hy81rj0PfFtlARKoJZOoCTdSZDM7EsKJCuNA0ew3uFULD69NqUjRqdY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768503383; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Tw/4WFwwimCPloBHy1pZS+5uugfLv7VltlAhw1gKOiY=; b=FsNvUSo2K16pebq81k1Cm/XHbrmb1G/5HkPmpapaJaGKi7d6yAqGmg9PS2QJ3gEod9RZ5e8AJMWGOCdL2GVFqBastMBsNosVE0eM/RN0dVcDJJXHJCB34GS/CRM2otTcbEXq8idL9zHLporZo3ehNFmx5JFBIlNfGlpNX6Ia4L0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768503383985554.4539798031612; Thu, 15 Jan 2026 10:56:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vgSVf-00019b-TX; Thu, 15 Jan 2026 13:55:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vgSV7-0000dQ-05 for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:22 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vgSV4-0005t4-7w for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:19 -0500 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-43277900fb4so1099657f8f.1 for ; Thu, 15 Jan 2026 10:55:17 -0800 (PST) Received: from mnementh.archaic.org.uk (f.7.f.1.7.5.e.f.f.f.c.5.d.8.2.4.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0:0:428d:5cff:fe57:1f7f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4356996cecasm514207f8f.26.2026.01.15.10.55.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 10:55:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768503316; x=1769108116; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Tw/4WFwwimCPloBHy1pZS+5uugfLv7VltlAhw1gKOiY=; b=mVjq/mMzZzKnL+gCHJhAOzMZI72QjEJT/6kBm8uAtxa2A5zhcExr1xHWfJcnsc882A rqzhpmIMWUSEviBJVk041t6X75HP1emOqSGp3lVi53i12fe9T4B19yfIN3Qm2SvGhx41 M5MG8vG948SArPRyuPgIj7kaLmWQht1tNWEK5uWYqtJGshAqDsOFu6xbFc1VKGU2CCqQ OI/XKSFs0/T39bQV8jFmwgsvKCzGsd3EWyCgBj1DFXNVn5B/1gM4CklMvJvCLhIFyUtS HUoL1VJMpr4eOx1dJeFyz7r3Ysmfx/I2DFvYCGUeZj9HXM3IRVxvOtR9zzL0xqAQsHD/ SvkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768503316; x=1769108116; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Tw/4WFwwimCPloBHy1pZS+5uugfLv7VltlAhw1gKOiY=; b=LO/un/x9RVgfQCKhH/jUKLiDLwlbSfflvM+uzcbmHrEBmeULTuLuhUoP9o8WWYEKVi droEX3XbHFvlAcad3lH+upY4pqJcHqRwRbPj158itFpZ0ia3dvZzJR0hSy6jtE18KxMV mxZtODRGU1hP+C7Wzwm1noQuifo/ffI6bJx7YCYXV/L85FhVhkWv+xQTnlu6tlNbLjrz owpai98PCH7BlmcYW/P17jy/b4jlDpEbL98x59Ofe8/LJPtkEOMkFu0lXQFahDOpe4av O7Z0RarIB4XcGeeKRKrt/vAYIg11KAQ808y3G81ymuTZCYw7AKrEkMZ/E/NC2Ly027PF Xxyg== X-Gm-Message-State: AOJu0Yx2nePmPQi2VqIAMMMfGpxgByEb3P/w2Rh7yYOwsHt+hfSjvPmX Kyq3CZhGn3GsGXLE3EM2Ipo55rGowHrXlM2kHoLOBjj4IT5LV6WEt7/5N3/YVtLCaT0kQPBh/5s uDAoQ X-Gm-Gg: AY/fxX7YzALggbHEjPGcK8DKsGztDNsYujC+60R7B3wRYDgApVP9Wr1PVrmlZnKWgUJ p/EZIm3yhqI16uKG9Kncoo7hHPzCPeYj06y2/Fzl+nBW0RknkfplYW2s2SWjioASSxFgvHSkVyM RmEB8yEO0JS6lSRh9qf/obp1wTyx211zSFOlwiefVnn86t/7jri6CIIp18uAuqg1xYsSX/VjdSa ZMRR3cJuc1CUBnstRRujfWU+2pJC9BgAz7Qq9fiw+nrrnEmkBKXbufRe4qpUxXVtnzu7j8dZp7r Rmu+2KPlDHV/98fuW6BRd1YatAYixbVHOYvxaL/Ta1ZkdWR3pVP7UWceLS7DKC20G6kIqHTfBL3 az7iETaTrHfSekR6Ju7H2DkvP3rxi3IdAH9kMODXNuO8MwPDJ0t3Qz/QXbu3nz3k3kUWGz3sVSD LWzyPTSsW32CxbzMGpw76p/7N6h53qjyQpJHdjtUPV0Yee3tUAVrgy5InD3xvv7j/XSIIE/gs1T nLWksXeyH0T87vrvnDsqpKgrzzBeXWp4kUv1yL5GqOkynsoevf24kiZ X-Received: by 2002:a5d:5f51:0:b0:430:fd0e:a502 with SMTP id ffacd0b85a97d-434df0ed345mr5126340f8f.22.1768503316040; Thu, 15 Jan 2026 10:55:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/25] hw/arm: Re-enable the MAX78000FTHR machine in qemu-system-arm/aarch64 Date: Thu, 15 Jan 2026 18:54:49 +0000 Message-ID: <20260115185508.786428-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260115185508.786428-1-peter.maydell@linaro.org> References: <20260115185508.786428-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768503384669158500 From: Philippe Mathieu-Daud=C3=A9 Unfortunately while rebasing the series registering the ARM/Aarch64 machine interfaces and getting it merged as commit 38c5ab40031 ("hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries") we missed the recent addition of the MAX78000FTHR machine in commit 51eb283dd0e. Correct that. The effect is that the machine was accidentally disabled. Cc: qemu-stable@nongnu.org Reported-by: Thomas Huth Tested-by: Thomas Huth Tested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20251218214306.63667-1-philmd@linaro.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3248 Fixes: 38c5ab40031 ("hw/arm: Filter machine types for single binary") Signed-off-by: Peter Maydell --- hw/arm/max78000fthr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/max78000fthr.c b/hw/arm/max78000fthr.c index ed50bb9197..530ca9dd96 100644 --- a/hw/arm/max78000fthr.c +++ b/hw/arm/max78000fthr.c @@ -12,6 +12,7 @@ #include "hw/core/qdev-properties.h" #include "hw/core/qdev-clock.h" #include "qemu/error-report.h" +#include "hw/arm/machines-qom.h" #include "hw/arm/max78000_soc.h" #include "hw/arm/boot.h" =20 @@ -47,4 +48,4 @@ static void max78000_machine_init(MachineClass *mc) mc->valid_cpu_types =3D valid_cpu_types; } =20 -DEFINE_MACHINE("max78000fthr", max78000_machine_init) +DEFINE_MACHINE_ARM("max78000fthr", max78000_machine_init) --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768503356; cv=none; d=zohomail.com; s=zohoarc; b=AXCqpFim/WkkAfZr54Ht1+9o65MAc9gAKvsahBkf36S6g86WADj1GJPqwEhFcEhOQz8fJJ1GHer8SMANsb9hbJc7twQwbi+FePRueDLkzEtMKMObOnuzVT5lTqh03CvgAKgNDUUTstm5r2j0wzqy1NdJoTzslhY958DPjQnv14c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768503356; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=AEo8xACRrqFksaTq19NMJKvtuBauiXQ84oXtSBtjaLQ=; b=WDsBOHhBWtZoiowwp8FJX3GIIn2lDxELLDCTiHQzDeCkNa8t/3Puon6OVlLA+eFtWUO8O4FfQGsPRNukgFCVTOf5+OsgFPo2R7gUHsHVWyiu48bRudU+7LBUeeKsKBHRIzzqsULaPgKOid1T5wTlngt/qCndyI9UqCijM/3y/a0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768503356499398.4314320864329; Thu, 15 Jan 2026 10:55:56 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vgSVb-00016H-P3; Thu, 15 Jan 2026 13:55:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vgSV8-0000ds-3x for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:24 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vgSV4-0005tE-Gk for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:21 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-47f3b7ef761so7223705e9.0 for ; Thu, 15 Jan 2026 10:55:18 -0800 (PST) Received: from mnementh.archaic.org.uk (f.7.f.1.7.5.e.f.f.f.c.5.d.8.2.4.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. 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This prevented common, target-agnostic code like the SMMU model from using these definitions without triggering "cpu.h included from common code" errors. To resolve this, this commit introduces a new, lightweight header, include/hw/arm/arm-security.h, which is safe for inclusion by common code. The following change was made: - The ARMSecuritySpace enum and the arm_space_is_secure() and arm_secure_to_space() helpers have been moved from target/arm/cpu.h to the new hw/arm/arm-security.h header. This refactoring decouples the security state definitions from the core CPU implementation, allowing common hardware models to correctly handle security states without pulling in heavyweight, target-specific headers. Signed-off-by: Tao Tang Reviewed-by: Eric Auger Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20251216000122.763264-2-pierrick.bouvier@linaro.org Link: https://lists.nongnu.org/archive/html/qemu-arm/2025-09/msg01288.html Signed-off-by: Pierrick Bouvier Signed-off-by: Peter Maydell --- include/hw/arm/arm-security.h | 37 +++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 25 +---------------------- 2 files changed, 38 insertions(+), 24 deletions(-) create mode 100644 include/hw/arm/arm-security.h diff --git a/include/hw/arm/arm-security.h b/include/hw/arm/arm-security.h new file mode 100644 index 0000000000..196cddd14c --- /dev/null +++ b/include/hw/arm/arm-security.h @@ -0,0 +1,37 @@ +/* + * ARM security space helpers + * + * Provide ARMSecuritySpace and helpers for code that is not tied to CPU. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ARM_ARM_SECURITY_H +#define HW_ARM_ARM_SECURITY_H + +/* + * ARM v9 security states. + * The ordering of the enumeration corresponds to the low 2 bits + * of the GPI value, and (except for Root) the concat of NSE:NS. + */ + + typedef enum ARMSecuritySpace { + ARMSS_Secure =3D 0, + ARMSS_NonSecure =3D 1, + ARMSS_Root =3D 2, + ARMSS_Realm =3D 3, +} ARMSecuritySpace; + +/* Return true if @space is secure, in the pre-v9 sense. */ +static inline bool arm_space_is_secure(ARMSecuritySpace space) +{ + return space =3D=3D ARMSS_Secure || space =3D=3D ARMSS_Root; +} + +/* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ +static inline ARMSecuritySpace arm_secure_to_space(bool secure) +{ + return secure ? ARMSS_Secure : ARMSS_NonSecure; +} + +#endif /* HW_ARM_ARM_SECURITY_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9579d43ba3..992dff41c3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -31,6 +31,7 @@ #include "exec/page-protection.h" #include "qapi/qapi-types-common.h" #include "target/arm/multiprocessing.h" +#include "hw/arm/arm-security.h" #include "target/arm/gtimer.h" #include "target/arm/cpu-sysregs.h" #include "target/arm/mmuidx.h" @@ -2102,30 +2103,6 @@ static inline int arm_feature(CPUARMState *env, int = feature) =20 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); =20 -/* - * ARM v9 security states. - * The ordering of the enumeration corresponds to the low 2 bits - * of the GPI value, and (except for Root) the concat of NSE:NS. - */ - -typedef enum ARMSecuritySpace { - ARMSS_Secure =3D 0, - ARMSS_NonSecure =3D 1, - ARMSS_Root =3D 2, - ARMSS_Realm =3D 3, -} ARMSecuritySpace; - -/* Return true if @space is secure, in the pre-v9 sense. */ -static inline bool arm_space_is_secure(ARMSecuritySpace space) -{ - return space =3D=3D ARMSS_Secure || space =3D=3D ARMSS_Root; -} - -/* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ -static inline ARMSecuritySpace arm_secure_to_space(bool secure) -{ - return secure ? ARMSS_Secure : ARMSS_NonSecure; -} =20 #if !defined(CONFIG_USER_ONLY) /** --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768503427; cv=none; d=zohomail.com; s=zohoarc; b=nx0OPxz234FmkdA4PVcczd4PPTlYxPeU44k8NCfj7pz4FJMjrxNR6fSf4RAYn2YXiDqMFce0WVU1Neo+1kXTILFAPkzoa2twN11GKcZAh86ty352jzc/QRjGuISJ/WwFHA3qsvopmoMRfO5ZdIC7JPTJJklSHhYOdRqD02bWvzU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768503427; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=cetP1J1aWKEi9nsVT6d4hD/J2+TMx9aoQKwyU7+I/5k=; b=jDPJjtgdP5dEQd3RQZslfrpLrOWeb//rfdLlkVuK2fdwEeayOeJRky7reYBEuWa6RZU/xSSao8XxI04ihoH6sb5xLc2ewjrI92pQVXxrz3lKz8TRM/yT46+Wry41vgK74pmv0dMYUS9s06VpPBld/6sVRUbAsIPkbSkACICumIk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768503427929534.1106602501028; Thu, 15 Jan 2026 10:57:07 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vgSVz-00024U-Pk; Thu, 15 Jan 2026 13:56:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vgSV8-0000dt-Im for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:22 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vgSV6-0005tZ-Os for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:22 -0500 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-42fb0fc5aa4so1004818f8f.1 for ; Thu, 15 Jan 2026 10:55:19 -0800 (PST) Received: from mnementh.archaic.org.uk (f.7.f.1.7.5.e.f.f.f.c.5.d.8.2.4.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. 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Signed-off-by: Pierrick Bouvier Reviewed-by: Richard Henderson Message-id: 20251216000122.763264-3-pierrick.bouvier@linaro.org [PMM: avoid local vars in middle of block] Signed-off-by: Peter Maydell --- target/arm/cpu.h | 34 +++++++++++++++++++++++++++++ target/arm/ptw.c | 57 ++++++++++++++++++++++++++++++------------------ 2 files changed, 70 insertions(+), 21 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 992dff41c3..2f124d1b15 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1216,6 +1216,40 @@ void arm_v7m_cpu_do_interrupt(CPUState *cpu); =20 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); + +typedef struct ARMGranuleProtectionConfig { + /* GPCCR_EL3 */ + uint64_t gpccr; + /* GPTBR_EL3 */ + uint64_t gptbr; + /* ID_AA64MMFR0_EL1.PARange */ + uint8_t parange; + /* FEAT_SEL2 */ + bool support_sel2; + /* Address space to access Granule Protection Table */ + AddressSpace *gpt_as; +} ARMGranuleProtectionConfig; + +/** + * arm_granule_protection_check + * @config: granule protection configuration + * @paddress: address accessed + * @pspace: physical address space accessed + * @ss: security state for access + * @fi: fault information in case a fault is detected + * + * Checks if @paddress can be accessed in physical adress space @pspace + * for @ss secure state, following granule protection setup with @config. + * If a fault is detected, @fi is set accordingly. + * See GranuleProtectionCheck() in A-profile manual. + * + * Returns: true if access is authorized, else false. + */ +bool arm_granule_protection_check(ARMGranuleProtectionConfig config, + uint64_t paddress, + ARMSecuritySpace pspace, + ARMSecuritySpace ss, + ARMMMUFaultInfo *fi); #endif /* !CONFIG_USER_ONLY */ =20 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 2e6b149b2d..a986dc66f6 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -330,26 +330,26 @@ static bool regime_translation_disabled(CPUARMState *= env, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; } =20 -static bool granule_protection_check(CPUARMState *env, uint64_t paddress, - ARMSecuritySpace pspace, - ARMSecuritySpace ss, - ARMMMUFaultInfo *fi) +bool arm_granule_protection_check(ARMGranuleProtectionConfig config, + uint64_t paddress, + ARMSecuritySpace pspace, + ARMSecuritySpace ss, + ARMMMUFaultInfo *fi) { MemTxAttrs attrs =3D { .secure =3D true, .space =3D ARMSS_Root, }; - ARMCPU *cpu =3D env_archcpu(env); - uint64_t gpccr =3D env->cp15.gpccr_el3; + const uint64_t gpccr =3D config.gpccr; unsigned pps, pgs, l0gptsz, level =3D 0; uint64_t tableaddr, pps_mask, align, entry, index; - AddressSpace *as; MemTxResult result; int gpi; =20 - if (!FIELD_EX64(gpccr, GPCCR, GPC)) { - return true; - } + /* + * We assume Granule Protection Check is enabled when + * calling this function (GPCCR.GPC =3D=3D 1). + */ =20 /* * GPC Priority 1 (R_GMGRR): @@ -362,7 +362,7 @@ static bool granule_protection_check(CPUARMState *env, = uint64_t paddress, * physical address size is invalid. */ pps =3D FIELD_EX64(gpccr, GPCCR, PPS); - if (pps > FIELD_EX64_IDREG(&cpu->isar, ID_AA64MMFR0, PARANGE)) { + if (pps > config.parange) { goto fault_walk; } pps =3D pamax_map[pps]; @@ -432,7 +432,7 @@ static bool granule_protection_check(CPUARMState *env, = uint64_t paddress, } =20 /* GPC Priority 4: the base address of GPTBR_EL3 exceeds PPS. */ - tableaddr =3D env->cp15.gptbr_el3 << 12; + tableaddr =3D config.gptbr << 12; if (tableaddr & ~pps_mask) { goto fault_size; } @@ -446,12 +446,10 @@ static bool granule_protection_check(CPUARMState *env= , uint64_t paddress, align =3D MAKE_64BIT_MASK(0, align); tableaddr &=3D ~align; =20 - as =3D arm_addressspace(env_cpu(env), attrs); - /* Level 0 lookup. */ index =3D extract64(paddress, l0gptsz, pps - l0gptsz); tableaddr +=3D index * 8; - entry =3D address_space_ldq_le(as, tableaddr, attrs, &result); + entry =3D address_space_ldq_le(config.gpt_as, tableaddr, attrs, &resul= t); if (result !=3D MEMTX_OK) { goto fault_eabt; } @@ -479,7 +477,7 @@ static bool granule_protection_check(CPUARMState *env, = uint64_t paddress, level =3D 1; index =3D extract64(paddress, pgs + 4, l0gptsz - pgs - 4); tableaddr +=3D index * 8; - entry =3D address_space_ldq_le(as, tableaddr, attrs, &result); + entry =3D address_space_ldq_le(config.gpt_as, tableaddr, attrs, &resul= t); if (result !=3D MEMTX_OK) { goto fault_eabt; } @@ -513,7 +511,7 @@ static bool granule_protection_check(CPUARMState *env, = uint64_t paddress, case 0b1111: /* all access */ return true; case 0b1000: /* secure */ - if (!cpu_isar_feature(aa64_sel2, cpu)) { + if (!config.support_sel2) { goto fault_walk; } /* fall through */ @@ -3786,11 +3784,28 @@ static bool get_phys_addr_gpc(CPUARMState *env, S1T= ranslate *ptw, memop, result, fi)) { return true; } - if (!granule_protection_check(env, result->f.phys_addr, - result->f.attrs.space, ptw->in_space, fi= )) { - fi->type =3D ARMFault_GPCFOnOutput; - return true; + + if (FIELD_EX64(env->cp15.gpccr_el3, GPCCR, GPC)) { + ARMCPU *cpu =3D env_archcpu(env); + MemTxAttrs attrs =3D { + .secure =3D true, + .space =3D ARMSS_Root, + }; + struct ARMGranuleProtectionConfig config =3D { + .gpccr =3D env->cp15.gpccr_el3, + .gptbr =3D env->cp15.gptbr_el3, + .parange =3D FIELD_EX64_IDREG(&cpu->isar, ID_AA64MMFR0, PARANG= E), + .support_sel2 =3D cpu_isar_feature(aa64_sel2, cpu), + .gpt_as =3D arm_addressspace(env_cpu(env), attrs) + }; + if (!arm_granule_protection_check(config, result->f.phys_addr, + result->f.attrs.space, ptw->in_s= pace, + fi)) { + fi->type =3D ARMFault_GPCFOnOutput; + return true; + } } + return false; } =20 --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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The second is wrong because the offset is an offset into the device but we use it as an absolute physical address, so we will access whatever is at low memory. That happens to be the boot ROM, so we will ignore a write and return random garbage on a read. This bug has been present since 2011, when we did the conversions to the MemoryRegion APIs, which involved changing all devices from working with absolute physical addresses to working with offsets within their MemoryRegions. We must have missed updating these functions. Replace the uses of these functions in omap_mmc.c with an open-coded call to qemu_log_mask() and RAZ/WI behaviour. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/sd/omap_mmc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c index 020429aa4f..d779506131 100644 --- a/hw/sd/omap_mmc.c +++ b/hw/sd/omap_mmc.c @@ -335,7 +335,9 @@ static uint64_t omap_mmc_read(void *opaque, hwaddr offs= et, unsigned size) OMAPMMCState *s =3D opaque; =20 if (size !=3D 2) { - return omap_badwidth_read16(opaque, offset); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, offset, size); + return 0; } =20 switch (offset) { @@ -428,7 +430,8 @@ static void omap_mmc_write(void *opaque, hwaddr offset, OMAPMMCState *s =3D opaque; =20 if (size !=3D 2) { - omap_badwidth_write16(opaque, offset, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, offset, size); return; } =20 --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768503454; cv=none; d=zohomail.com; s=zohoarc; b=F0RNFTMxbEO0QrmK/HiDGTY9VjL86AKSfdy5NnI3hHJPkPAaVasrM0WwxC8kHT+zZBJTFGLgktzynfXYRFeW2FM2k95YDjYxn9qt2JIDtBJYfBi6uje3b7Ntb8JwkWkm4+v2LKcgPd8NcbcaDwQwaaolhs0NkWIjGw4MF+Rhmd4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768503454; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=t1p81LYxQD9tgjtY4PEPaGrAv8vSY3A/eQhUlZgUjX8=; b=heNTypzU6tT82dVHpgzB8v5ePBrO3pWYWMCT+BciiP5heCPhw+qfib3VXCh8eUgMPt9+muhDf7CguEzv6v9anhvi3vZmkUxIWnHtifYr2MGP4dtPxjHSEGJPRbCyWyEeClDL1J+5LW5jIUKveUHQNjQQAuROs/oKS5jfCtyxlzE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768503454113891.61501228775; Thu, 15 Jan 2026 10:57:34 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vgSW1-0002Fo-EY; Thu, 15 Jan 2026 13:56:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vgSVE-0000fu-Nc for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:30 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vgSV7-0005tt-Tx for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:23 -0500 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-432755545fcso788121f8f.1 for ; Thu, 15 Jan 2026 10:55:20 -0800 (PST) Received: from mnementh.archaic.org.uk (f.7.f.1.7.5.e.f.f.f.c.5.d.8.2.4.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0:0:428d:5cff:fe57:1f7f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4356996cecasm514207f8f.26.2026.01.15.10.55.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 10:55:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768503320; x=1769108120; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=t1p81LYxQD9tgjtY4PEPaGrAv8vSY3A/eQhUlZgUjX8=; b=JFPZ91arEhIrKMtCm2GBxBNleHnd+vc0eqYZ0Qz3KlszENxrg6KhGmTk/Oq0q/0Olz 95uiUwtI4Php2KWimuMKgI7tiYcCSP/Ie6IYNqMZBChI3RBv3LJ013dNXUB0FM0F4Zxw sUV1WmOfEPbDfmWnh3mgw5sBVaeScHAzDVm26478iq4YmhP18EJIvE4eFGVDqZuBdVeN QYV/o67wuB5bzfI+6uaueRnmNAvYBN1psUoKcuUEH/dRIhkHUcNFy5tATjc1aVjqDpfw N1iPOgIdWw6E74riyj2N0IIkYCiKatiH8wYdl9IWPBqAB32rw77mmNd60RGxpwQ3Bp78 sCoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768503320; x=1769108120; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=t1p81LYxQD9tgjtY4PEPaGrAv8vSY3A/eQhUlZgUjX8=; b=lA/5LbUg0IewidF/iVZ9dZKN3QNiQL/vdcPmjUqTDiYyXdY3ERi3PzfzF21SdvvNLP /jV7GzxcSP5d514SChrYXmjocqlYKRB1W2YanxamBq7y1uR53lTDtPwqmiJoCkO/Od62 Fn8YJyIZafXDJomAH/Wf6/mgU5iyAALUUX8gT//x3gZmrRigY3Z0FnSPhwUrEpDg57mo 8YnjC40Qp3/8XkjNgdOxNk+/xIRWeav/BGLrTjeZ05ffKjJL/2I0npSrgfoZTli/3fU8 +atl6KmEibWkwpBr7OiYoty0umLMw2ClM3vvlDgheD6MJMIzYee2siO7p7RN+0zGBj+S dfyg== X-Gm-Message-State: AOJu0YxZq4Nka7ee5xIEY0KAHlKr0rLPF7P3MGGvHnWf/2CvcrN/4LS6 X4nJOvWMT2f6Sla79acGeCRPtzbbZ7nrJ/oK6HCEQnQ4fnOj4LK8V1/80P/K3+cKDv3Whr1NGcy H0xZb X-Gm-Gg: AY/fxX4l44duW3zKfQ/SyjZ2352Vn4wUOgJ64Y4WHHCU1TSl0kTvQuj+/wL0UGPfV+q Df9v8zzHyGX55YXnJGtGiTruhaM9ZWRwX/tUQYvzMsBGk1au7Ob4tMbY+d3gDMOZAs/OwQDZv3T PrEl8BMPLoMcoxhL+IzVJdzmFQcUka3BrR3Yf1lGvn8OZvjZ0YN54wtfoTMLQbWfYccgr/Qy/38 xqsCOjx+s/nsjKXPRM9H0LQQ5xc/blhDZxht0ml/tDcG3Dk/bhE3Tdir1kJDwjoChCdIX9j6uE1 E0gn5NnfA2SBbDi7ujCPXkBSyRU98wQWTi6VBdf17fjj0BkLABd2YHoe7Kmk4uX2fhmukdKPpVI OWPzhVDPjJ+95dfP7YHJ4ErzWLr2Rljll1PafElyIWsliAhbNkvSvOHE7p3RmGMpX78Pkne/ome 1B9sV0nbPhxvhZHwgwnec9a7oKB8IuRv+T52cctY0ADmEzS9yhfFjusCW29qZukKtscUeS44UGh AVVP5nLZmL8QjgnIhA/GCGlmMlT4hjPyvX0y+G1i2bkng== X-Received: by 2002:a05:6000:4287:b0:432:84ef:756c with SMTP id ffacd0b85a97d-43569bc7422mr418068f8f.50.1768503319835; Thu, 15 Jan 2026 10:55:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/25] hw/i2c/omap_i2c: Remove omap_badwidth_* calls Date: Thu, 15 Jan 2026 18:54:53 +0000 Message-ID: <20260115185508.786428-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260115185508.786428-1-peter.maydell@linaro.org> References: <20260115185508.786428-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768503455040158500 The omap_badwidth_read* and omap_badwidth_write* functions are used by various OMAP devices when the guest makes an access to registers with an invalid width; they do two things: - log a GUEST_ERROR for the access - call cpu_physical_memory_read() or cpu_physical_memory_write() with the offset they are passed in The first of these produces an unhelpful log message because the function name that is printed is that of the omap-badwidth_* function, not that of the read or write function of the device that called it; this means you can't tell what device is involved. The second is wrong because the offset is an offset into the device but we use it as an absolute physical address, so we will access whatever is at low memory. That happens to be the boot ROM, so we will ignore a write and return random garbage on a read. This bug has been present since 2011, when we did the conversions to the MemoryRegion APIs, which involved changing all devices from working with absolute physical addresses to working with offsets within their MemoryRegions. We must have missed updating these functions. Replace the uses of these functions in omap_i2c.c with an open-coded call to qemu_log_mask() and RAZ/WI behaviour. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/i2c/omap_i2c.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c index e0798f2c8a..d6e28a1a89 100644 --- a/hw/i2c/omap_i2c.c +++ b/hw/i2c/omap_i2c.c @@ -441,7 +441,9 @@ static uint64_t omap_i2c_readfn(void *opaque, hwaddr ad= dr, case 2: return omap_i2c_read(opaque, addr); default: - return omap_badwidth_read16(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } } =20 @@ -457,7 +459,8 @@ static void omap_i2c_writefn(void *opaque, hwaddr addr, omap_i2c_write(opaque, addr, value); break; default: - omap_badwidth_write16(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); break; } } --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768503368; cv=none; d=zohomail.com; s=zohoarc; b=K/VPqskhs0JKfm5/chtwc4BBJB81uPYUcMew3QouYeC6Qa73Kn1DLHY1HjL0o7/+LwDAMYWx/dTCtavLQID0KktUNgtRvu5qhIUnKjB0bqohEPSAP/fgyr0GzURwL+Ym7lKjKJhzMrTmnZap9NpN8SCftQZbxkRLgxkk2PltEh0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768503368; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=rzXa0m3nz1cG2gDO1gPqQo6PFYCv0OqwAEN4mWq3o0A=; b=gf9z19DHiEjcxiVq1Slf2aqQIQVzzgGncYSXJXbOiZEwBFijlr6Xm8e0erv4SNJHvF8xXIQ3HYP8CxrAnkDfz4rU6+73SD6e2ke4rfGTLoASGZGykjKSqvANAP7SLPL1qaLO2QQBXJeJtt/Via/e6LhAzvPinKlz9xMwW1qGij0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768503368414976.8179744296011; Thu, 15 Jan 2026 10:56:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vgSVg-00019l-WE; Thu, 15 Jan 2026 13:55:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vgSVE-0000ft-NR for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:30 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vgSV8-0005uJ-8I for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:23 -0500 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-430f57cd471so755922f8f.0 for ; Thu, 15 Jan 2026 10:55:21 -0800 (PST) Received: from mnementh.archaic.org.uk (f.7.f.1.7.5.e.f.f.f.c.5.d.8.2.4.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0:0:428d:5cff:fe57:1f7f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4356996cecasm514207f8f.26.2026.01.15.10.55.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 10:55:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768503321; x=1769108121; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=rzXa0m3nz1cG2gDO1gPqQo6PFYCv0OqwAEN4mWq3o0A=; b=vgYk4lTacgAGuyC+YEg5Mij697vbqQ7VQpmktwAxjNm9XhDHz4b+JDq14YDOGn3W0C a0/99ealgX6Ayw2OWg/YvjUfp0eJ838Ot4Umxa/9DmdNL4IOWkzrewq5aeZ/oa0bEhri R1J196q3a4a230rg3IcDA+S3deA6ZkSgQMiw6Uo739xCj6+Q19OFmUX0g2t2ceSmC3BG 80vcbtxLy3pebtIorMdznmgxPwUAaUqhiAMNevRnhZMAWxa2TJCRWGe/UiLu2xxWPFFm td+bmpYv57wlWTqXffBgigAACEYoMi1pYPLK4FQ3pwzeSuDzL3UmI7TEhhIOQEIQu/aO R1ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768503321; x=1769108121; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=rzXa0m3nz1cG2gDO1gPqQo6PFYCv0OqwAEN4mWq3o0A=; b=gBeINk6NlXUlsQg3plVyuHtHaXZbciHSfkUjBIsd94G6hw1umZvAmAVJqOw3KgFFqs UqsiAeWwccpl5tcj2T6LYy2ILo7agRylcmfvRVS+8Ne+5eGLoauTWH1uAKYAAPJtnPPG mBzwlVZJCkJjJiAnqIYPNMwaWtR0zUoRIbOgWJqqUYiCpMXgctPwUXlE3JCm9Qj9wkn/ 5xuKGylpmsVwFSnbyz2e9A8Aqnvl++N+gugfkTRrZu6ROqlbMfT+GrVwgnL2IIJTUP2D Ta8JZdi3idnNnQYTJX//fXGfH0PY+jzTToJl+8H30GyV0PxBXl28KKoXFtIEtiPA8vOT 4Sng== X-Gm-Message-State: AOJu0Yxdfj9F38OhMkfIQZSnSpivAOo+gQl4+L528leQ5AotgQGE8u+g 60QnkC9W1Ryvcf595O8UzAIRwJoijUP9C27LCuhwzCaTbZLe9nlwuKxr2CZI9xZMiNAbsGBxfia r0qMk X-Gm-Gg: AY/fxX7vfnQlZ+pQZjSj6QuXfzPKfjAVrom0VjP1vzAO8Z/R7Ls5dYwgDLDaJAEQqH9 vUkxZKwrmr8dTVgL0FgROAtcupuZVpQgnl9ThoMMwpRbm9r9jixpamMT0Fh0I9y0nHstHQtBfJB fCIztE37ZKFc3mm6BozkRoovL2y+stga1TjYVIyJypJo0hpnk4COk85Biz/Cgi1AcdRCeGEV8m/ hvAEDxS2Cj5i2Nd3vPMVL1vsGRQCQgc7OthSb1YY2gsyyhUOc6Q6xFpSiOC/r2bplv5KexjhKlA KmK6PgK/2wihSpZcGYIN/QvLMwvXs8ZOO27OifpHdbLg8AXHhM99VqiKmDPMfIvz98LrXyCHtWM 10uZbEke15bMjh7rMOeiamt6DMDS+uMctdgNMH/yFGSocS2/+W8NCT5+FIpzr3jTEkMLEmGF1L1 kh4tYZnqicsg4A6lV0wvbkEhNMpyu8VJq62olMgsNnGsFvz26eD7Sxk5qepkwoGhYuOmEYlzEdg jGlMsGZwfTitQfIXp7VRNuT0iVEbSwXTXzfcXtlTDUjuw== X-Received: by 2002:a5d:5886:0:b0:430:ff0c:35fb with SMTP id ffacd0b85a97d-4356a05c404mr359020f8f.52.1768503320720; Thu, 15 Jan 2026 10:55:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/25] hw/gpio/omap_gpio: Remove omap_badwidth_* calls Date: Thu, 15 Jan 2026 18:54:54 +0000 Message-ID: <20260115185508.786428-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260115185508.786428-1-peter.maydell@linaro.org> References: <20260115185508.786428-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768503370759158500 The omap_badwidth_read* and omap_badwidth_write* functions are used by various OMAP devices when the guest makes an access to registers with an invalid width; they do two things: - log a GUEST_ERROR for the access - call cpu_physical_memory_read() or cpu_physical_memory_write() with the offset they are passed in The first of these produces an unhelpful log message because the function name that is printed is that of the omap-badwidth_* function, not that of the read or write function of the device that called it; this means you can't tell what device is involved. The second is wrong because the offset is an offset into the device but we use it as an absolute physical address, so we will access whatever is at low memory. That happens to be the boot ROM, so we will ignore a write and return random garbage on a read. This bug has been present since 2011, when we did the conversions to the MemoryRegion APIs, which involved changing all devices from working with absolute physical addresses to working with offsets within their MemoryRegions. We must have missed updating these functions. Replace the uses of these functions in omap_gpio.c with an open-coded call to qemu_log_mask() and RAZ/WI behaviour. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/gpio/omap_gpio.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c index f7619260ca..ee3ddb09e3 100644 --- a/hw/gpio/omap_gpio.c +++ b/hw/gpio/omap_gpio.c @@ -76,7 +76,9 @@ static uint64_t omap_gpio_read(void *opaque, hwaddr addr, int offset =3D addr & OMAP_MPUI_REG_MASK; =20 if (size !=3D 2) { - return omap_badwidth_read16(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (offset) { @@ -116,7 +118,8 @@ static void omap_gpio_write(void *opaque, hwaddr addr, int ln; =20 if (size !=3D 2) { - omap_badwidth_write16(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768503388; cv=none; d=zohomail.com; s=zohoarc; b=Rw6x/Usvru3QJa5nfQbHZJc3oSSk40aFK99VxvLf2KIpHvkBFG8yg3w2eYCHRBqF2Y9+Yy8eDJJA+VhbZiwGRKq9uaAWD/JZ8bRg7PBrlgdHWkkPQAhj9F4Wjhlm7xmbFB9Szg7qEg2m3uiHczuwX4NisT1BdQuaFlBG0HGn7lQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768503388; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=JihJ9EjtCmXQJXv06egkSfCreOQAD+ZK24B5aK3jXDQ=; b=Iyg7ZgtjxyH98FdBT/L1ac1g/2zuRWsV03qdTnGpxTFYr6yUFEEi7U4iqi2l2L2DTxi/fnE66rVTLS1Mjlc84kAMcZjVTwV4/f/2uvHTwzL/mqJG+B3RHinJBf0+gfy5sQKcfu0UW1ZyIvbFxP1hnMUTkyhyO6NJoaYJaGmR3Ww= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17685033888721002.8271073037954; Thu, 15 Jan 2026 10:56:28 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vgSVk-0001F5-Au; Thu, 15 Jan 2026 13:56:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vgSVN-0000hw-45 for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:39 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vgSVC-0005uW-U9 for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:29 -0500 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-42fed090e5fso668888f8f.1 for ; Thu, 15 Jan 2026 10:55:22 -0800 (PST) Received: from mnementh.archaic.org.uk (f.7.f.1.7.5.e.f.f.f.c.5.d.8.2.4.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0:0:428d:5cff:fe57:1f7f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4356996cecasm514207f8f.26.2026.01.15.10.55.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 10:55:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768503321; x=1769108121; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=JihJ9EjtCmXQJXv06egkSfCreOQAD+ZK24B5aK3jXDQ=; b=ncESgrMWVCqILhiJsTxkWVMOcUjbPquYn85HggJO4joFZ97tzf8T3I4lRGSL5e8cy2 QHe+scKKY2OdNZaLhJ2CzYaOmBAKV8cKflH37VSBTicJctGQiypi0ILSqivMb0e/YgSL Ad1/lAEdZlaS1G2dWeSS/s14iaKFy6O4ozQsP0k7mwvvDyGjNARZyOlfgA/1k1X5R8MU l0tDwanaysGVNsgvcmCB2MSKam8WOqw1PKaAvFhxbf+5Q75MXm+nhhHZYFoalOBcJLjn pOwcP/2T44bUkIEUTTmLVZFeN3ozxV6YgUwHnjDX0lWrn9feOakvh8Uf5EufTWOa1DZT 0eZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768503321; x=1769108121; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=JihJ9EjtCmXQJXv06egkSfCreOQAD+ZK24B5aK3jXDQ=; b=fnGvzArQf1hROsDhKZEFqcS0GTxQgxSkimnTDC2J11mqTTFParQR3WZHfwGlbo9y9h zUlZKhWZ1w4LdPfLddFWTiovjjQfoue5piEVQUa2cAb/uBxAFuIAvAlSN+NaZq1EWh3d EIu8ZewOovApM4fmbuqKC45Aojaa6hxturPR57yQjmQO5YzPz1wv+FLFyfY+VC057D+H LASv34WRXY6GLHtIz6FJTvkICELiPqIXVnkfnCVq1f6Tme3vNF8kUUnxOQMX6vJ11Cg5 T6G5DqArkzi902IDDShTTHM7N6SdxCGpXuBSNLJuzopADwtH0n37sF24muglPRGbqqwh fzyA== X-Gm-Message-State: AOJu0Yzd5gLBIpgU9Ag2L8C1iWzmHr/3xQsT6A17YEy1ixt3/lzGrJRK 1QsvF8SMYjosK+Ww3lILEFJNKU9Rx2q3SmXx8ZdXYT4TMo3zaC6bTArfx3f67LeKYvmObbKR8Nt 1O8oP X-Gm-Gg: AY/fxX7UzRbbtEKo+M4YHR5/ButS0OekHqkZHUJJYhsTXEH9AygifP759l2LxK/+GlS 8GvX/pJI5VYiavDiCNvhusYR6v1MfSXoCiN4XPORzdbDMZfxzmOxnr6sFOcphuPgjuDY1iLAwG3 XTUQ1ckkNeR1c/ftY14SHxIDDXwfzhDWizVn8eBLP4ksTYn0aNXDc7cpQxEWYYWFQr5/LoYHueV gR7N4BRbmiyN8rgTJsq8D3sEWLvMePx3gt6vE2Lut84s46esQ2hhgukQoPW4Es2B5Md9/gFFs67 F3nPLBT0PRCvW77Aot11+SwmQAmwpp0qz2IgkmsopCEGkC+4+JJKLHVFZ1r6LPZvIG6lXqkPLEK SQhIQzUYKISO3SPsYPzieEMqlrsBHN3wAY2wsU3j6BJ1+d4Wrf6ixFXzATC4HaHKaefdoJ4BeWc Xq/ICg25XXvxZ+h4k1SNTYXBWUe2QpHGOa+v47Ofwk+DtH2pUi3QFDUuUG13+96lB+7JLxQGMRO aWfeph7GHJn+tXA0Jn8XkMI/cAsPaYmvLsqIkK5ihXiag== X-Received: by 2002:a05:6000:2910:b0:42f:b0ab:7b48 with SMTP id ffacd0b85a97d-43569979c52mr465136f8f.1.1768503321525; Thu, 15 Jan 2026 10:55:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/25] hw/dma/omap_dma: Remove omap_badwidth_* calls Date: Thu, 15 Jan 2026 18:54:55 +0000 Message-ID: <20260115185508.786428-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260115185508.786428-1-peter.maydell@linaro.org> References: <20260115185508.786428-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768503390743158500 The omap_badwidth_read* and omap_badwidth_write* functions are used by various OMAP devices when the guest makes an access to registers with an invalid width; they do two things: - log a GUEST_ERROR for the access - call cpu_physical_memory_read() or cpu_physical_memory_write() with the offset they are passed in The first of these produces an unhelpful log message because the function name that is printed is that of the omap-badwidth_* function, not that of the read or write function of the device that called it; this means you can't tell what device is involved. The second is wrong because the offset is an offset into the device but we use it as an absolute physical address, so we will access whatever is at low memory. That happens to be the boot ROM, so we will ignore a write and return random garbage on a read. This bug has been present since 2011, when we did the conversions to the MemoryRegion APIs, which involved changing all devices from working with absolute physical addresses to working with offsets within their MemoryRegions. We must have missed updating these functions. Replace the uses of these functions in omap_dma.c with an open-coded call to qemu_log_mask() and RAZ/WI behaviour. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/dma/omap_dma.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c index 963ce6fd10..784a3a4f7f 100644 --- a/hw/dma/omap_dma.c +++ b/hw/dma/omap_dma.c @@ -1455,7 +1455,9 @@ static uint64_t omap_dma_read(void *opaque, hwaddr ad= dr, unsigned size) uint16_t ret; =20 if (size !=3D 2) { - return omap_badwidth_read16(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (addr) { @@ -1502,7 +1504,8 @@ static void omap_dma_write(void *opaque, hwaddr addr, int reg, ch; =20 if (size !=3D 2) { - omap_badwidth_write16(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768503390; cv=none; d=zohomail.com; s=zohoarc; b=XB7IzOt7NS16b/8SEA+KwLKhZVoKJgFGHOHvrl6LZivu8uYJXuODr7QR+5PLfNJ6VbuyDK/v4VV/ZhTHcyJvvWQoSKWSxrhJahHFhkHUqzx1ArxbzerdgrQ6QX9OypnufNl9MnuFlCQ8rV4MZGg2K4+vanzziXTlcoBvMIP1moU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768503390; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ROW5G0LmCLnFSQU2/Ic6aBsvPza1+GU/DMA6doQA0/I=; b=S7UcnsE5gt7X61t12zQw1Hcuq9BDmYJxhrXwxJELaqNFR7+DNf+GuDj3wGt91GCl3suSkyoqpcyLenjEF285Vb91t8rPP6cAFD001wQSSdnC1qkXRUBaaj/T+YZNsLSuX22IaIOgrf6seMNya15bfxQv/0LaAWdFAl0J2OvIWdc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768503390968177.16948362789424; Thu, 15 Jan 2026 10:56:30 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vgSVx-0001hS-Pq; Thu, 15 Jan 2026 13:56:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vgSVQ-0000jG-Eu for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:41 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vgSVN-0005um-TV for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:40 -0500 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-42fbad1fa90so1178094f8f.0 for ; Thu, 15 Jan 2026 10:55:23 -0800 (PST) Received: from mnementh.archaic.org.uk (f.7.f.1.7.5.e.f.f.f.c.5.d.8.2.4.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0:0:428d:5cff:fe57:1f7f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4356996cecasm514207f8f.26.2026.01.15.10.55.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 10:55:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768503322; x=1769108122; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ROW5G0LmCLnFSQU2/Ic6aBsvPza1+GU/DMA6doQA0/I=; b=lwbbcBlFkQx7Lc3qxkmbhf3bTx9oqCuxzbA+/kTiQkuOA+Th/kgKA6SffWwjaA0fwG fN0XbX3H2XEUIl2XuEtMNBp1QB6MmVlhCqO8fj/A/gSn8M8htiDYDvQ2fAgZSq1basIT 8Um/s3zfuGl8vHPKvzuPnqwF7WjllySmaAd0zrEfZdCK7EZ3PJufO3c5Mt2U7Sldlv6W bslTwKJzJ6JgF14yD3QPaXNSGLdzLhKLwFgp1/cG9pIxmOyq+Uhk7+N+obfC/vQ/TFEZ 3ATlSBvngcvGT/9HbkBJZmUDhCh/ReH5PeH5SvfnBjB8sf2Z8gd64q0Yb+6d3/JjUMb/ fTug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768503322; x=1769108122; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ROW5G0LmCLnFSQU2/Ic6aBsvPza1+GU/DMA6doQA0/I=; b=rVRfUpfowC5Ci7RJ8LXAnrXUfj6yKQ28Mng+2+e6km1dDIMDnDuUBK3eFngzJxmvNj qKQ+NpYDtc1aLxtz3ctAqcC2+/vE0R6NigZls4Cpp91E9E1W0IeQn6MqexzudXgpet5I HWd0AJgqwDa0JHAPSZFqJm/c5XnyW6gwu+95u09BSebbMGjiM6oyDiNC+n6SKzYjSiM9 6dPOd+ftaZF8JTwsyYtUMamSC1M/7HNkp94/Fjrpv0COSHEtXzbtdpBnUEZVGVBjlLuf Etv9TF4jENLtC4UEsF7iyMcsKeLBNYQGRxJWbrgTzzf0DnA/A9pAMxMXWJLmf8ZWqol0 85OQ== X-Gm-Message-State: AOJu0YzGq+FoHqwj9rm+GE7TXstkKHq8nrys15bLam92CzV177BrNbig YO47gD7E7A5X8JHpZzdrhd3zRH6+KTymMxwiYJZmuecyny1Lz0IQINPCmuIiPbq9Yhx23KfbyZq jVWMM X-Gm-Gg: AY/fxX5jUl9i/viXXdox0wty+F5ZnDeYvq9G0u5vrAPr2JgzC30qLUQCo/kMW6NmkW8 A9avcP3doGyudkWZSDjVTGiDWpJzMvh53nE/nAdz36C7NggmSp14F98ogpl9NGIOcFvPlJZq9td bnYq4RER/+2syr/EMMxu3C87rjwWlhM3dShTfJO/QOxegVALQcp+wRyQ53vhf87u0Y1WxZEE8uv F/+HL/2I/4BBiopoBlfanr+F78Pebt6W3qRSO6ZNkuZwwsanJx2dZTUb0WPJ86AGY2wBmKvHZBn BMmR1ElI/uNgrtWxVS8CNEQlPLIdste60akSfihadPusMPBecmG9dbSr6fr7ajtrkaaqQE0i5ID Nvc7zLftF33YjU4ABsaT90VIHJyZGHXltn43huXZj6sNdEZfWEZL2ZwrSDlFKMiqc7Z4fkn++7s JbqxcmsZ5FlQwZ3CVdLyKeQ4QVBFgEQebtruXoYJfp6k1v3O64GrEUKvbQABJF7UV4aQkGiDBZa TkbmQNIe8zJqD+C9JsWV1X6W8jhm7q+f8MJPIn3BcdCUc+YLUih/DDd X-Received: by 2002:a05:6000:22c9:b0:431:855:c791 with SMTP id ffacd0b85a97d-4356997f5e5mr458936f8f.3.1768503322381; Thu, 15 Jan 2026 10:55:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/25] hw/arm/omap1: Remove omap_badwidth_read* calls Date: Thu, 15 Jan 2026 18:54:56 +0000 Message-ID: <20260115185508.786428-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260115185508.786428-1-peter.maydell@linaro.org> References: <20260115185508.786428-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768503392849158500 The omap_badwidth_read* and omap_badwidth_write* functions are used by various OMAP devices when the guest makes an access to registers with an invalid width; they do two things: - log a GUEST_ERROR for the access - call cpu_physical_memory_read() or cpu_physical_memory_write() with the offset they are passed in The first of these produces an unhelpful log message because the function name that is printed is that of the omap-badwidth_* function, not that of the read or write function of the device that called it; this means you can't tell what device is involved. The second is wrong because the offset is an offset into the device but we use it as an absolute physical address, so we will access whatever is at low memory. That happens to be the boot ROM, so we will ignore a write and return random garbage on a read. This bug has been present since 2011, when we did the conversions to the MemoryRegion APIs, which involved changing all devices from working with absolute physical addresses to working with offsets within their MemoryRegions. We must have missed updating these functions. Replace the uses of the omap_badwidth_read* functions in omap1.c with an open-coded call to qemu_log_mask() and RAZ/WI behaviour. We do just the reads here because there are a lot of callsites in omap1.c; the writes will be done in the next commit. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/omap1.c | 80 +++++++++++++++++++++++++++++++++++++------------- 1 file changed, 60 insertions(+), 20 deletions(-) diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index 9ca8eecfa0..742ee48fcf 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -209,7 +209,9 @@ static uint64_t omap_mpu_timer_read(void *opaque, hwadd= r addr, struct omap_mpu_timer_s *s =3D opaque; =20 if (size !=3D 4) { - return omap_badwidth_read32(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (addr) { @@ -315,7 +317,9 @@ static uint64_t omap_wd_timer_read(void *opaque, hwaddr= addr, struct omap_watchdog_timer_s *s =3D opaque; =20 if (size !=3D 2) { - return omap_badwidth_read16(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (addr) { @@ -439,7 +443,9 @@ static uint64_t omap_os_timer_read(void *opaque, hwaddr= addr, int offset =3D addr & OMAP_MPUI_REG_MASK; =20 if (size !=3D 4) { - return omap_badwidth_read32(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (offset) { @@ -540,7 +546,9 @@ static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr = addr, uint16_t ret; =20 if (size !=3D 2) { - return omap_badwidth_read16(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (addr) { @@ -772,7 +780,9 @@ static uint64_t omap_pin_cfg_read(void *opaque, hwaddr = addr, struct omap_mpu_state_s *s =3D opaque; =20 if (size !=3D 4) { - return omap_badwidth_read32(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (addr) { @@ -995,7 +1005,9 @@ static uint64_t omap_id_read(void *opaque, hwaddr addr, struct omap_mpu_state_s *s =3D opaque; =20 if (size !=3D 4) { - return omap_badwidth_read32(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (addr) { @@ -1077,7 +1089,9 @@ static uint64_t omap_mpui_read(void *opaque, hwaddr a= ddr, struct omap_mpu_state_s *s =3D opaque; =20 if (size !=3D 4) { - return omap_badwidth_read32(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (addr) { @@ -1175,7 +1189,9 @@ static uint64_t omap_tipb_bridge_read(void *opaque, h= waddr addr, struct omap_tipb_bridge_s *s =3D opaque; =20 if (size < 2) { - return omap_badwidth_read16(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (addr) { @@ -1277,7 +1293,9 @@ static uint64_t omap_tcmi_read(void *opaque, hwaddr a= ddr, uint32_t ret; =20 if (size !=3D 4) { - return omap_badwidth_read32(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (addr) { @@ -1391,7 +1409,9 @@ static uint64_t omap_dpll_read(void *opaque, hwaddr a= ddr, struct dpll_ctl_s *s =3D opaque; =20 if (size !=3D 2) { - return omap_badwidth_read16(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 if (addr =3D=3D 0x00) /* CTL_REG */ @@ -1471,7 +1491,9 @@ static uint64_t omap_clkm_read(void *opaque, hwaddr a= ddr, struct omap_mpu_state_s *s =3D opaque; =20 if (size !=3D 2) { - return omap_badwidth_read16(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (addr) { @@ -1764,7 +1786,9 @@ static uint64_t omap_clkdsp_read(void *opaque, hwaddr= addr, CPUState *cpu =3D CPU(s->cpu); =20 if (size !=3D 2) { - return omap_badwidth_read16(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (addr) { @@ -1956,7 +1980,9 @@ static uint64_t omap_mpuio_read(void *opaque, hwaddr = addr, uint16_t ret; =20 if (size !=3D 2) { - return omap_badwidth_read16(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (offset) { @@ -2206,7 +2232,9 @@ static uint64_t omap_uwire_read(void *opaque, hwaddr = addr, unsigned size) int offset =3D addr & OMAP_MPUI_REG_MASK; =20 if (size !=3D 2) { - return omap_badwidth_read16(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (offset) { @@ -2347,7 +2375,9 @@ static uint64_t omap_pwl_read(void *opaque, hwaddr ad= dr, unsigned size) int offset =3D addr & OMAP_MPUI_REG_MASK; =20 if (size !=3D 1) { - return omap_badwidth_read8(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (offset) { @@ -2440,7 +2470,9 @@ static uint64_t omap_pwt_read(void *opaque, hwaddr ad= dr, unsigned size) int offset =3D addr & OMAP_MPUI_REG_MASK; =20 if (size !=3D 1) { - return omap_badwidth_read8(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (offset) { @@ -2574,7 +2606,9 @@ static uint64_t omap_rtc_read(void *opaque, hwaddr ad= dr, unsigned size) uint8_t i; =20 if (size !=3D 1) { - return omap_badwidth_read8(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (offset) { @@ -3118,7 +3152,9 @@ static uint64_t omap_mcbsp_read(void *opaque, hwaddr = addr, uint16_t ret; =20 if (size !=3D 2) { - return omap_badwidth_read16(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (offset) { @@ -3547,7 +3583,9 @@ static uint64_t omap_lpg_read(void *opaque, hwaddr ad= dr, unsigned size) int offset =3D addr & OMAP_MPUI_REG_MASK; =20 if (size !=3D 1) { - return omap_badwidth_read8(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 switch (offset) { @@ -3628,7 +3666,9 @@ static uint64_t omap_mpui_io_read(void *opaque, hwadd= r addr, unsigned size) { if (size !=3D 2) { - return omap_badwidth_read16(opaque, addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); + return 0; } =20 if (addr =3D=3D OMAP_MPUI_BASE) /* CMR */ --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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We can delete a FIXME comment about an infinite loop, because that only looped infinitely back before 2011 when the device was still using absolute physical addresses. Now that we are simply logging the error we can clearly see that there's no loop. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/omap1.c | 64 +++++++++++++++++++++++++++++++++----------------- 1 file changed, 42 insertions(+), 22 deletions(-) diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index 742ee48fcf..b28fbd64fd 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -235,7 +235,8 @@ static void omap_mpu_timer_write(void *opaque, hwaddr a= ddr, struct omap_mpu_timer_s *s =3D opaque; =20 if (size !=3D 4) { - omap_badwidth_write32(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 @@ -344,7 +345,8 @@ static void omap_wd_timer_write(void *opaque, hwaddr ad= dr, struct omap_watchdog_timer_s *s =3D opaque; =20 if (size !=3D 2) { - omap_badwidth_write16(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 @@ -472,7 +474,8 @@ static void omap_os_timer_write(void *opaque, hwaddr ad= dr, int offset =3D addr & OMAP_MPUI_REG_MASK; =20 if (size !=3D 4) { - omap_badwidth_write32(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 @@ -619,7 +622,8 @@ static void omap_ulpd_pm_write(void *opaque, hwaddr add= r, uint16_t diff; =20 if (size !=3D 2) { - omap_badwidth_write16(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 @@ -894,7 +898,8 @@ static void omap_pin_cfg_write(void *opaque, hwaddr add= r, uint32_t diff; =20 if (size !=3D 4) { - omap_badwidth_write32(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 @@ -1052,7 +1057,8 @@ static void omap_id_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { if (size !=3D 4) { - omap_badwidth_write32(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 @@ -1124,7 +1130,8 @@ static void omap_mpui_write(void *opaque, hwaddr addr, struct omap_mpu_state_s *s =3D opaque; =20 if (size !=3D 4) { - omap_badwidth_write32(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 @@ -1221,7 +1228,8 @@ static void omap_tipb_bridge_write(void *opaque, hwad= dr addr, struct omap_tipb_bridge_s *s =3D opaque; =20 if (size < 2) { - omap_badwidth_write16(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 @@ -1332,7 +1340,8 @@ static void omap_tcmi_write(void *opaque, hwaddr addr, struct omap_mpu_state_s *s =3D opaque; =20 if (size !=3D 4) { - omap_badwidth_write32(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 @@ -1430,7 +1439,8 @@ static void omap_dpll_write(void *opaque, hwaddr addr, int div, mult; =20 if (size !=3D 2) { - omap_badwidth_write16(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 @@ -1703,7 +1713,8 @@ static void omap_clkm_write(void *opaque, hwaddr addr, }; =20 if (size !=3D 2) { - omap_badwidth_write16(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 @@ -1833,7 +1844,8 @@ static void omap_clkdsp_write(void *opaque, hwaddr ad= dr, uint16_t diff; =20 if (size !=3D 2) { - omap_badwidth_write16(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 @@ -2043,7 +2055,8 @@ static void omap_mpuio_write(void *opaque, hwaddr add= r, int ln; =20 if (size !=3D 2) { - omap_badwidth_write16(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 @@ -2268,7 +2281,8 @@ static void omap_uwire_write(void *opaque, hwaddr add= r, int offset =3D addr & OMAP_MPUI_REG_MASK; =20 if (size !=3D 2) { - omap_badwidth_write16(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 @@ -2397,7 +2411,8 @@ static void omap_pwl_write(void *opaque, hwaddr addr, int offset =3D addr & OMAP_MPUI_REG_MASK; =20 if (size !=3D 1) { - omap_badwidth_write8(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 @@ -2494,7 +2509,8 @@ static void omap_pwt_write(void *opaque, hwaddr addr, int offset =3D addr & OMAP_MPUI_REG_MASK; =20 if (size !=3D 1) { - omap_badwidth_write8(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 @@ -2691,7 +2707,8 @@ static void omap_rtc_write(void *opaque, hwaddr addr, time_t ti[2]; =20 if (size !=3D 1) { - omap_badwidth_write8(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 @@ -3419,7 +3436,8 @@ static void omap_mcbsp_writew(void *opaque, hwaddr ad= dr, return; } =20 - omap_badwidth_write16(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, 4); } =20 static void omap_mcbsp_write(void *opaque, hwaddr addr, @@ -3433,7 +3451,8 @@ static void omap_mcbsp_write(void *opaque, hwaddr add= r, omap_mcbsp_writew(opaque, addr, value); break; default: - omap_badwidth_write16(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); } } =20 @@ -3607,7 +3626,8 @@ static void omap_lpg_write(void *opaque, hwaddr addr, int offset =3D addr & OMAP_MPUI_REG_MASK; =20 if (size !=3D 1) { - omap_badwidth_write8(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PR= Ix + " with bad width %d\n", __func__, addr, size); return; } =20 @@ -3681,8 +3701,8 @@ static uint64_t omap_mpui_io_read(void *opaque, hwadd= r addr, static void omap_mpui_io_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - /* FIXME: infinite loop */ - omap_badwidth_write16(opaque, addr, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx + " with bad width %d\n", __func__, addr, size); } =20 static const MemoryRegionOps omap_mpui_io_ops =3D { --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768503388; cv=none; d=zohomail.com; s=zohoarc; b=PyYknNUsgTswyVJMG6GRi4XoM5GMpk2s2ETq+DB+fmgxNk383yr0Ono9rkZgKChrZ32ovUK5QN/PZX2Bs4W4hXvTGW+RiLN6UE8DayO8iVFMLZGWEN3UzoWBOL9tVNf1Q58ObvrjkgVGtaCINe1b29X7gf/LEXfem5hhixhgQS4= ARC-Message-Signature: i=1; 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Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/omap1.c | 59 ------------------------------------------- include/hw/arm/omap.h | 10 -------- 2 files changed, 69 deletions(-) diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index b28fbd64fd..47d0f0d736 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -45,65 +45,6 @@ #include "target/arm/cpu-qom.h" #include "trace.h" =20 -static inline void omap_log_badwidth(const char *funcname, hwaddr addr, in= t sz) -{ - qemu_log_mask(LOG_GUEST_ERROR, "%s: %d-bit register %#08" HWADDR_PRIx = "\n", - funcname, 8 * sz, addr); -} - -/* Should signal the TCMI/GPMC */ -uint32_t omap_badwidth_read8(void *opaque, hwaddr addr) -{ - uint8_t ret; - - omap_log_badwidth(__func__, addr, 1); - cpu_physical_memory_read(addr, &ret, 1); - return ret; -} - -void omap_badwidth_write8(void *opaque, hwaddr addr, - uint32_t value) -{ - uint8_t val8 =3D value; - - omap_log_badwidth(__func__, addr, 1); - cpu_physical_memory_write(addr, &val8, 1); -} - -uint32_t omap_badwidth_read16(void *opaque, hwaddr addr) -{ - uint16_t ret; - - omap_log_badwidth(__func__, addr, 2); - cpu_physical_memory_read(addr, &ret, 2); - return ret; -} - -void omap_badwidth_write16(void *opaque, hwaddr addr, - uint32_t value) -{ - uint16_t val16 =3D value; - - omap_log_badwidth(__func__, addr, 2); - cpu_physical_memory_write(addr, &val16, 2); -} - -uint32_t omap_badwidth_read32(void *opaque, hwaddr addr) -{ - uint32_t ret; - - omap_log_badwidth(__func__, addr, 4); - cpu_physical_memory_read(addr, &ret, 4); - return ret; -} - -void omap_badwidth_write32(void *opaque, hwaddr addr, - uint32_t value) -{ - omap_log_badwidth(__func__, addr, 4); - cpu_physical_memory_write(addr, &value, 4); -} - /* MPU OS timers */ struct omap_mpu_timer_s { MemoryRegion iomem; diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index bdb2e887e4..66a435a3d7 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -673,16 +673,6 @@ struct omap_mpu_state_s { struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram, const char *core); =20 -uint32_t omap_badwidth_read8(void *opaque, hwaddr addr); -void omap_badwidth_write8(void *opaque, hwaddr addr, - uint32_t value); -uint32_t omap_badwidth_read16(void *opaque, hwaddr addr); -void omap_badwidth_write16(void *opaque, hwaddr addr, - uint32_t value); -uint32_t omap_badwidth_read32(void *opaque, hwaddr addr); -void omap_badwidth_write32(void *opaque, hwaddr addr, - uint32_t value); - void omap_mpu_wakeup(void *opaque, int irq, int req); =20 #define OMAP_BAD_REG(paddr) \ --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768503376; cv=none; d=zohomail.com; s=zohoarc; b=FfWzwB4/SiGDoc59VsbXaj6x3sucY95ySVgTXMelzQ8z6FT1OfJ5AwW4G2ILhwbqjImgya24/9CxOip3xWUk0bylG0rmSEojOO61KyVkV54TUfOb+9OZL090BN8+v3+MaR/QzJXnEak9Tm2067miXDyL+lIQkHBCM+ZVC+J5YuU= ARC-Message-Signature: i=1; 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Secure support and Granule Protection Check (for RME) for SMMU need to access secure memory. As well, it allows to remove usage of global address_space_memory, allowing different SMMU instances to have a specific view of memory. User creatable SMMU are handled as well for virt machine, by setting the memory properties when device is plugged in. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier Reviewed-by: Eric Auger Message-id: 20260108210453.2280733-1-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- hw/arm/sbsa-ref.c | 16 ++++++++++++---- hw/arm/smmu-common.c | 11 +++++++++++ hw/arm/virt.c | 13 +++++++++++-- include/hw/arm/smmu-common.h | 4 ++++ include/hw/arm/virt.h | 2 ++ 5 files changed, 40 insertions(+), 6 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index d86b470686..52c35e10c2 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -613,7 +613,9 @@ static void create_xhci(const SBSAMachineState *sms) sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, = irq)); } =20 -static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) +static void create_smmu(const SBSAMachineState *sms, PCIBus *bus, + MemoryRegion *sysmem, + MemoryRegion *secure_sysmem) { hwaddr base =3D sbsa_ref_memmap[SBSA_SMMU].base; int irq =3D sbsa_ref_irqmap[SBSA_SMMU]; @@ -625,6 +627,10 @@ static void create_smmu(const SBSAMachineState *sms, P= CIBus *bus) object_property_set_str(OBJECT(dev), "stage", "nested", &error_abort); object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), &error_abort); + object_property_set_link(OBJECT(dev), "memory", OBJECT(sysmem), + &error_abort); + object_property_set_link(OBJECT(dev), "secure-memory", OBJECT(secure_s= ysmem), + &error_abort); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); for (i =3D 0; i < NUM_SMMU_IRQS; i++) { @@ -633,7 +639,9 @@ static void create_smmu(const SBSAMachineState *sms, PC= IBus *bus) } } =20 -static void create_pcie(SBSAMachineState *sms) +static void create_pcie(SBSAMachineState *sms, + MemoryRegion *sysmem, + MemoryRegion *secure_sysmem) { hwaddr base_ecam =3D sbsa_ref_memmap[SBSA_PCIE_ECAM].base; hwaddr size_ecam =3D sbsa_ref_memmap[SBSA_PCIE_ECAM].size; @@ -689,7 +697,7 @@ static void create_pcie(SBSAMachineState *sms) =20 pci_create_simple(pci->bus, -1, "bochs-display"); =20 - create_smmu(sms, pci->bus); + create_smmu(sms, pci->bus, sysmem, secure_sysmem); } =20 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) @@ -825,7 +833,7 @@ static void sbsa_ref_init(MachineState *machine) =20 create_xhci(sms); =20 - create_pcie(sms); + create_pcie(sms, sysmem, secure_sysmem); =20 create_secure_ec(secure_sysmem); =20 diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index e1b77cc55f..cdcfb1343d 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -944,6 +944,13 @@ static void smmu_base_realize(DeviceState *dev, Error = **errp) return; } =20 + g_assert(s->memory); + address_space_init(&s->memory_as, s->memory, "smmu-memory-view"); + if (s->secure_memory) { + address_space_init(&s->secure_memory_as, s->secure_memory, + "smmu-secure-memory-view"); + } + /* * We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based e= xtra * root complexes to be associated with SMMU. @@ -994,6 +1001,10 @@ static const Property smmu_dev_properties[] =3D { DEFINE_PROP_BOOL("smmu_per_bus", SMMUState, smmu_per_bus, false), DEFINE_PROP_LINK("primary-bus", SMMUState, primary_bus, TYPE_PCI_BUS, PCIBus *), + DEFINE_PROP_LINK("memory", SMMUState, memory, + TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_LINK("secure-memory", SMMUState, secure_memory, + TYPE_MEMORY_REGION, MemoryRegion *), }; =20 static void smmu_base_class_init(ObjectClass *klass, const void *data) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9d0568a7d5..4badc1a734 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1514,8 +1514,7 @@ static void create_smmuv3_dev_dtb(VirtMachineState *v= ms, 0x0, vms->iommu_phandle, 0x0, 0x10000); } =20 -static void create_smmu(const VirtMachineState *vms, - PCIBus *bus) +static void create_smmu(const VirtMachineState *vms, PCIBus *bus) { VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); int irq =3D vms->irqmap[VIRT_SMMU]; @@ -1535,6 +1534,10 @@ static void create_smmu(const VirtMachineState *vms, } object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), &error_abort); + object_property_set_link(OBJECT(dev), "memory", OBJECT(vms->sysmem), + &error_abort); + object_property_set_link(OBJECT(dev), "secure-memory", OBJECT(vms->sec= ure_sysmem), + &error_abort); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); for (i =3D 0; i < NUM_SMMU_IRQS; i++) { @@ -1609,6 +1612,7 @@ static void create_pcie(VirtMachineState *vms) memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", ecam_reg, 0, size_ecam); memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias= ); + vms->sysmem =3D get_system_memory(); =20 /* Map the MMIO window into system address space so as to expose * the section of PCI MMIO space which starts at the same base address @@ -2256,6 +2260,7 @@ static void machvirt_init(MachineState *machine) * devices go in at higher priority and take precedence. */ secure_sysmem =3D g_new(MemoryRegion, 1); + vms->secure_sysmem =3D secure_sysmem; memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", UINT64_MAX); memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); @@ -3051,6 +3056,10 @@ static void virt_machine_device_pre_plug_cb(HotplugH= andler *hotplug_dev, } else if (vms->iommu =3D=3D VIRT_IOMMU_NONE) { /* The new SMMUv3 device is specific to the PCI bus */ object_property_set_bool(OBJECT(dev), "smmu_per_bus", true, NU= LL); + object_property_set_link(OBJECT(dev), "memory", + OBJECT(vms->sysmem), NULL); + object_property_set_link(OBJECT(dev), "secure-memory", + OBJECT(vms->secure_sysmem), NULL); } } } diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 48368c8e89..b49b2f27fa 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -162,6 +162,10 @@ struct SMMUState { uint8_t bus_num; PCIBus *primary_bus; bool smmu_per_bus; /* SMMU is specific to the primary_bus */ + MemoryRegion *memory; + AddressSpace memory_as; + MemoryRegion *secure_memory; + AddressSpace secure_memory_as; }; =20 struct SMMUBaseClass { diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 8694aaa4e2..5907d41dbb 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -180,6 +180,8 @@ struct VirtMachineState { bool ns_el2_virt_timer_irq; CXLState cxl_devices_state; bool legacy_smmuv3_present; + MemoryRegion *sysmem; + MemoryRegion *secure_sysmem; }; =20 #define VIRT_ECAM_ID(high) (high ? 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[2001:8b0:1d0:0:428d:5cff:fe57:1f7f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4356996cecasm514207f8f.26.2026.01.15.10.55.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 10:55:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768503326; x=1769108126; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=SO+QQhetqwg3Ke62Uve9EBCMA+Sar8of/HhJLrfwAtQ=; b=NBIxnmi4yRp2hmt8aLnN+c5O6rCv2UAo7KYaG26ksmxbmciyjNgBsBex3uDdVXjW/l KWs3qsp9jqkRhLZPitNkZUd7CaW/D44FPnH8LAB5XXPKMwKQAv6L69Z88eb4kQ9D8qfr SO5KQ7oY+1p5miDHT9QpCkt34JTJSNbXvk6TQGkJz7JfiRkI5S7OpQc/rMPCp/a71Wxx B6SH2AjlVsp0NUCPhwo0Zuss6HOQ5nj6VuHk2gK6w3a+JKThNS0B0ifIce0ZTIODklqX ZdszMutdQz8HUAyBcE3Dd8nO4Ok2+ObgPihs5dRYq5HBnKj9lRSIZ5jYB5CI8dhSsSW4 xfIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768503326; x=1769108126; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=SO+QQhetqwg3Ke62Uve9EBCMA+Sar8of/HhJLrfwAtQ=; b=VX530IJjFg2/El/qsVWMMuHpdUSP28Kk0Y0qc6kHc3mvtNGkhJsHhWgzYcvK/B2ag0 OogV/Hs/9vHVvQr4PnFfsQ5nLFk67Uqr0ZgEo8GAKC7QpLF7w3sd4bfLacgEZUX6CFXZ DLxWEWVj58O9kFTm93LZ8CFI50nhfj72g3lR9WmTs9TNP7rAt7bHdugGj75S1og/sPJ2 ZNsdNLqAmoXUqVaffByvkPTSGmWcIEsvxgBLsCVKEDXiWEk77Ufmr8SJRbR/cpFsWShH 0xVF4/swEfnNpQwrm6UktPb+qK1Z4hmWvkGE4hEMptJgM6No2FBUGGHfPWKu1cEbIqoL wbKQ== X-Gm-Message-State: AOJu0YxJljxnx/t8pSwdVjS8o7hiaHaAN5dFvAUmPUJHqNcorLW+v7Zp QFFNKl6FniQX1BjFsqveoWV4aWjnD+ODx+jx1Gad6aBdx3HJeJ9Mxfl0xGXq36uMpr9j0usgRFy TE95P X-Gm-Gg: AY/fxX4yA7oDCSW7Jsh7cU6xKf6McuQkj+EwDsK1YndWnhghuB+T8Sp9w92YGYFLv1Q CeM6HkiGcbaUrF4wGWoW5bCyYfgOUfMsli8Vz5MEgBJXkSOV9jtB/xJwhtP6KotQYAUv9IAIr9f aTVMS7kqv6DEkpMdu19NsMB9PnjiTW1x5rPSEXO5TlHNFNxyRmFyxOWFTNU5cRU2GHRlAcjEjTC obFk5uBQAzl8fdrf8sSpWxkS4CSm4M8iBud3XPQutzzxrBxPgU5ghFAEqzufAJ2nCZdmeXZCqXS xSfTPrBqo42uLcWhpEvNog59GRM+yjIjNNp0iGqmAdmvoA7acajoqNzsKEaDWiFbwZYczaRa4g0 PUVlE7UYfda/GWV6ix3j44ve0iOUGUfWi373DGUXLEFMIALj07Acwu0mU25AECYIv/XYIlKYlE9 V5mxWXJaw6ao+AaXOBnNm0V+JkZEomK8YaVtsv/2hnhMlAxpy3I/b8nvrx9Mr+v+u59Z259mIS4 33HL6PrKfKCC1nb/ZSFgDilpxUjONYPOFoqljhVKhQzbx4PR9OLavla X-Received: by 2002:a05:6000:4383:b0:42f:bad7:af55 with SMTP id ffacd0b85a97d-43569972e7fmr495371f8f.6.1768503325710; Thu, 15 Jan 2026 10:55:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/25] docs/system/generic-loader: Clarify behaviour of cpu-num Date: Thu, 15 Jan 2026 18:55:00 +0000 Message-ID: <20260115185508.786428-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260115185508.786428-1-peter.maydell@linaro.org> References: <20260115185508.786428-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768503491254158500 The cpu-num suboption to the generic loader has two effects when it is used with -device loader,file=3D: * it specifies which CPU to load the data through * it specifies which CPU gets its PC set to the file's entry point Our documentation is not very clear about what happens if you don't pass this suboption. The default is that we pick the first CPU to load the data, but we don't set the PC for any CPU, so the "If not specified, the default is CPU 0" is confusing: it applies for loading but not for the PC setting. Clarify the text to make it clearer that the option has two effects and the default behaviour is different for the two effects. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --- docs/system/generic-loader.rst | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/docs/system/generic-loader.rst b/docs/system/generic-loader.rst index 4f9fb005f1..3ac39cfbbe 100644 --- a/docs/system/generic-loader.rst +++ b/docs/system/generic-loader.rst @@ -87,12 +87,17 @@ shown below: =20 ```` This specifies the CPU that should be used. This is an - optional argument and will cause the CPU's PC to be set to the - memory address where the raw file is loaded or the entry point - specified in the executable format header. This option should only - be used for the boot image. This will also cause the image to be - written to the specified CPU's address space. If not specified, the - default is CPU 0. + optional argument with two effects: + + * this CPU's address space is used to load the data + * this CPU's PC will be set to the address where the raw file is loaded + or the entry point specified in the executable format header + + If this option is not specified, then the data will be loaded via + the address space of the first CPU, and no CPU will have its PC set. + + Since it sets the starting PC, this option should only be used for the b= oot + image. =20 ```` Setting 'force-raw=3Don' forces the file to be treated as a raw image. --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768503406; cv=none; d=zohomail.com; s=zohoarc; b=Cq5sJ2hmds3EfRhOjoCT7QxTredIWQf0V8/Ie/qGQpqjXQBZhTvbsf81EWVhSwzqIQFfxkZYcQufICYowmnTe9uyCqGjVzfZh5zMFLA6ZXHYnKZFkQGEoK9GeZeFiRN3TvoLD8iOfUPzwbK6QAMP9i0EFPnq8GzYgldACT+BMFs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768503406; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=4gjXCy79pe4NWZapLMTTRsh607ELXIo37IZ3HiA37hQ=; b=VU0UMaxn/jz9cLozUupOaZM8HpJsNp4yCTQEc4CAxfplYz0GcZb8HOi3oD12KvkT6S30gjPQuQM1dc62mLzwRwuyqAiMduy3q8WMA9aaO+aJ3qXId5rCIXIgz6OfDN+kOwhn1BdOkoUeCDm33f/C57hIx1WOLJ/CJBZWXSwPZJM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768503406325865.5732556368471; Thu, 15 Jan 2026 10:56:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vgSVi-0001Da-4V; Thu, 15 Jan 2026 13:55:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vgSVP-0000iC-2F for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:39 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vgSVH-0005vm-9j for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:38 -0500 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-431048c4068so713727f8f.1 for ; Thu, 15 Jan 2026 10:55:27 -0800 (PST) Received: from mnementh.archaic.org.uk (f.7.f.1.7.5.e.f.f.f.c.5.d.8.2.4.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0:0:428d:5cff:fe57:1f7f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4356996cecasm514207f8f.26.2026.01.15.10.55.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 10:55:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768503326; x=1769108126; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4gjXCy79pe4NWZapLMTTRsh607ELXIo37IZ3HiA37hQ=; b=JazjuQWyRkhZm0CNdAH3piTrgnhiN/JwgNlhn1+NED7hWHI8QSlFS1vtBgQ4ih9VJt gfyoMReIBxyTAEJRL+TJEAHc6Bwa2bbpVkLa21OKaHSFJN0n+XDQHnxTcNqsTcjSfQE4 eDkXF728ZmGESlPy7Q/5sczknA6tW8oRiVjKftBLh8/yk3PAf8cOcDBvrGIbpL0zvfgp GZE9TfsXHXPoAtTs12dbqaOImOBTK/eO5usS5T5I51XDtZDp9fgQznYD9/q4derMfNko 7A8ZT3z5qAwG0j6pnzaOc5XMBHPACOiBiBhOzPdipji2YiNCKt4sAgLWLcWtvYz4JJ6I vkLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768503326; x=1769108126; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=4gjXCy79pe4NWZapLMTTRsh607ELXIo37IZ3HiA37hQ=; b=nIE+vV4mZTGz7oP78RzLttMhVmwXXJLwYeatDMxha7VhUNzmDS89ft2OC8iXio6V9M LIQkc08KIYN5FtlGGEMaWnbPMOQ25hE+Rs52YckR5scBrO8zcZkQIFkHDAaftRY1vSxq 93FwxewcRlrMZEVmX12QfV6b3XsQfCUYk3cMbutMsgbl+Qr83/UivsFhiY+ywz2ZbaYH vbzrDnBH61O1oZg4Z9UIp6/O476OD+rBEIV13fgo4/WEZyyPH0aX7RgfBrM0KNBr/ZGa BCo9epvMvtQkjcyohIP7CMX0vFfLmAuZ+BgQgqskY/s7ou06Q49BkFWqqWdnivKkiVdT dIGw== X-Gm-Message-State: AOJu0YxI7XaLfDOWnRJvT1+IzVf50kvy1QxeC4mEBhrvU204TEIu5VPa G7Ka38fRe1PWm9mwrnWF0OlrAUUzoPd61j4eirikJtDPUgDp7lAcqR1760DKyjSL173Mqy2oRVb /nMG1 X-Gm-Gg: AY/fxX6Czc5rgW9VxSloPkngYZV1jTgFM/jhNEAYiOP3iNMjflp4Dhxp6V5ambBSTSz wd7KNecn2IK1p+23tVtT4xZqBMgwkxwvM35K5iV3W471NDsg+ES6ZmQj5qiUc0o4Pr9T37j4i/u TrGy3gNy2OgChfr2qZvD8rSbrHrT1J3mNh4Ja+aAjDAM+A5WgECIiYM7+fwAbJbNv9I5jIFdOGY jer6c4EazjxO7HSvTovh4UWHmoGQR0qh6gxCAd2cYTgXgZL5If3WxPRnMLrlz6pWMj2szhxcHLD ClOwGzp0LNOTOWHZCUtKlIgoZ3j8DCFTmBGWFZpUTPjOB4aSV62VVof0e8q6Hs9pjfw5cA4OSZz hXqv5EODtjm+UGj+rx7MzjTHu+iQp2DOxsnjJcEScWzLkqZ0iYXSyPwGqyk2c1vV5d7hSTkK3xr ZuG6P9QkZ1NFZUbZVsWDJViF8Cj87IDJTZ8OE6ky2eg0PRzgWGrpinlzvYoRIlLOtRG6GfqyrTe OXwKd7W56jsL6bTEexiQVz4qWoemQSxbnnTeYowT0e2EA== X-Received: by 2002:a05:6000:288c:b0:432:c03e:a78e with SMTP id ffacd0b85a97d-434df116480mr5396491f8f.27.1768503326534; Thu, 15 Jan 2026 10:55:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/25] docs/system/generic-loader: Don't mention QemuOpts implementation detail Date: Thu, 15 Jan 2026 18:55:01 +0000 Message-ID: <20260115185508.786428-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260115185508.786428-1-peter.maydell@linaro.org> References: <20260115185508.786428-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768503406844158500 We currently say "All values are parsed using the standard QemuOpts parsing". This doesn't tell the user anything useful because we don't mention QemuOpts anywhere else in the docs. What we're really trying to tell the user is what we mention afterwards: that the values are decimal, and you need an 0x prefix for hex. How we achieve it is an implementation detail the user doesn't need to know. Drop the explicit mention of QemuOpts; this in passing removes a typo "QemuOps" that we made in one place. Put the informative note more closely associated with the suboption which is the one that users might most reasonably assume to default to hex. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --- docs/system/generic-loader.rst | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/docs/system/generic-loader.rst b/docs/system/generic-loader.rst index 3ac39cfbbe..d5416711e9 100644 --- a/docs/system/generic-loader.rst +++ b/docs/system/generic-loader.rst @@ -21,6 +21,10 @@ can be done by following the syntax below:: ```` The address to store the data in. =20 + Note that as usual with QEMU numeric option values, the default is to + treat the argument as decimal. To specify a value in hex, prefix it + with '0x'. + ```` The value to be written to the address. The maximum size of the data is 8 bytes. @@ -37,10 +41,6 @@ can be done by following the syntax below:: The number of the CPU's address space where the data should be loaded. If not specified the address space of the first CPU is used. =20 -All values are parsed using the standard QemuOps parsing. This allows the = user -to specify any values in any format supported. By default the values -will be parsed as decimal. To use hex values the user should prefix the nu= mber -with a '0x'. =20 An example of loading value 0x8000000e to address 0xfd1a0104 is:: =20 @@ -57,14 +57,13 @@ can be done by following the syntax below:: ```` The value to use as the CPU's PC. =20 + Note that as usual with QEMU numeric option values, the default is to + treat the argument as decimal. To specify a value in hex, prefix it + with '0x'. + ```` The number of the CPU whose PC should be set to the specified value. =20 -All values are parsed using the standard QemuOpts parsing. This allows the= user -to specify any values in any format supported. By default the values -will be parsed as decimal. To use hex values the user should prefix the nu= mber -with a '0x'. - An example of setting CPU 0's PC to 0x8000 is:: =20 -device loader,addr=3D0x8000,cpu-num=3D0 @@ -85,6 +84,10 @@ shown below: The memory address where the file should be loaded. This is required for raw images and ignored for non-raw files. =20 + Note that as usual with QEMU numeric option values, the default is to + treat the argument as decimal. To specify a value in hex, prefix it + with '0x'. + ```` This specifies the CPU that should be used. This is an optional argument with two effects: @@ -104,10 +107,6 @@ shown below: This can be used to load supported executable formats as if they were raw. =20 -All values are parsed using the standard QemuOpts parsing. This allows the= user -to specify any values in any format supported. By default the values -will be parsed as decimal. To use hex values the user should prefix the nu= mber -with a '0x'. =20 An example of loading an ELF file which CPU0 will boot is shown below:: =20 --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768503535; cv=none; d=zohomail.com; s=zohoarc; b=EpusdImxgW+vV9noy+whHnWZH+uQuYvSO9CQIBau0nRPnmGZ1aVc992wwmCpl7BZGZb5pncmIHAyZZ2PVZw+kUcrrx+d7ZXFkG2253Uv851BPS0ty9wpMJ06J+OyxQx+3vWuMDt9Aouanh/msK6YHaEni8IoNG8rvqJPlxvyg1s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768503535; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=DUH5FjK7b2EIsIIQmTzRC8PsiEQGFhbRDC16YQhe6Bo=; b=SsNycc+7yZ0k8JcPriVkxVVd06Q/oA1zFlz4n9PmIi/Wc9iuM8tloVePPNL933C3xd9L9FiRkDe4AJNzs1n7IrxNFuZpXNSsHcAw/IdlgU/joiHEnfOV44/vVG+GvcLs2IP7lIVdSAfNe1sZnrB+ls05TC40w6s22BrTrV+0xJo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768503535177833.3901684065629; Thu, 15 Jan 2026 10:58:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vgSW2-0002PN-Nh; Thu, 15 Jan 2026 13:56:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vgSVQ-0000jF-CA for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:41 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vgSVN-0005w7-VI for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:40 -0500 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-47ee301a06aso11660055e9.0 for ; Thu, 15 Jan 2026 10:55:29 -0800 (PST) Received: from mnementh.archaic.org.uk (f.7.f.1.7.5.e.f.f.f.c.5.d.8.2.4.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0:0:428d:5cff:fe57:1f7f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4356996cecasm514207f8f.26.2026.01.15.10.55.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 10:55:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768503328; x=1769108128; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DUH5FjK7b2EIsIIQmTzRC8PsiEQGFhbRDC16YQhe6Bo=; b=RHJmFFjGOMUoN8xir+PTHuNagJIG4ExpBSq71IqWGKGQm5c+ll71RSKfkk6awXzHPh XOHBWXJqsXFAdMWNB2OucowogKX0ft0BQR59Mwf9XUWpNeCjXaHWav4TZGxATrLH6RSE 8zbdee9eb1N1lItaPF1Vw7p8x2LLoD7VaJ8Xbw7Ja1gBrwiqN048ih789CQk3Pxu+I12 IBPyhSVLIl4kjNDOI7lqfw1Y6kaq/Enzc+GVhCJECAM9gyWxxs1YsPXTh/n31wMxfd3P JOMz0Abwoj5b7oriIgFJ7UoYrUIO/L9l9he26+52oKBWyMC3rJjBiEJXcgK8A6oPHc9a LYWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768503328; x=1769108128; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=DUH5FjK7b2EIsIIQmTzRC8PsiEQGFhbRDC16YQhe6Bo=; b=OcKqFYqVapsSLI60yGvH+34IEkhk1Al54P2zCFrZ+h7I6c3U9WR+TowbPhkw9jVhEQ A7EE54xIdzPER8GvTJnsqk9YTWqOOpVo3meQirrH14tupASJXlo+OphjgiHESzGBKfLH 9iB9vwTpwfP400x1xnXFsJYVXUawOfJR/RZcKhNMgAspDYBcN/KdK8cw+Lt9bQRzuWWd zywnCaXts6UPS5JLHDnoJuWYj6oMHSVU8MdXNcBqIzMWxYe8/I+kOJ2mmK3rpY5MPq2w mjdRv8XmUAHOeLzj+rIrc3BwfkNRJ4CAOtHnkjOGqNWuJ201iMgyomBERPh1k6+qmGeB FGtA== X-Gm-Message-State: AOJu0Yybvdh9hw7POOoovh1M3EbNURDPAQYFU7yzKleE85Y1u10Yq0/c AjVjDLe8Ts0jD2Lfu1CR/AXvAus3YHl9U73TZMuriImaMK0/BAL02O+PMwJcuO3LomMBzlS2P/v kUef4 X-Gm-Gg: AY/fxX52JOhx1m9S/9xdrSQHntpc+RvzcW/Zk9Lfl6PFLNmbkLg0jzKRr4I5zpTzSFZ 7A3FxjQ1GtKLiKZOdfGXFuC0aInfsvPFObt5SA7NkSO7CdJoTLa+9Ragmo1xMRe5qfF1qEmAQr6 FpFwn2xvnism5YMfv90mPONiArdXuYrNcmEpteVIhjhr+k0jBeNCRQh+MYoiAksHe9MPkHAmOTH Ml7HaVti4g15pNB/7f6PPYUQAV9tnhsXmsI8m/q1ZEzUp//lpyAu2rxr0oy0bxHqtFoQtGMGl5m Hhc37EYUF4qDoLT1nQrDb8Chb5ybRDgi515nzPN+Xd5q50n/lxZofAFnHLmlSH6QYorsewwriG6 tToAW915Eig3uFsTdyh4l/9Z5C9DQVDE+W0EUvLMiAE3koIZ+Fh25J44TcQd+40abKLnMkmKWD2 zG4BgfdKS4A9HPMjJVBVw6hb5CYSOtdfXNRyANz9Z6Jw0hEq9MAhcSerUQiOnUPPGvg/AbZw3Vq nHu8BTIHoeOjMq5p9y5wv2ACWY9OnnLyBDFFUR4Iv6HUw== X-Received: by 2002:a05:600c:8710:b0:471:14f5:126f with SMTP id 5b1f17b1804b1-4801eb142famr2253005e9.33.1768503328060; Thu, 15 Jan 2026 10:55:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/25] docs/system/generic-loader: move TODO to source code Date: Thu, 15 Jan 2026 18:55:02 +0000 Message-ID: <20260115185508.786428-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260115185508.786428-1-peter.maydell@linaro.org> References: <20260115185508.786428-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768503537523158500 Currently we have a "Restrictions and ToDos" section at the bottom of the document which notes that there's no way to specify a CPU to load a file through that doesn't also set that CPU's PC. This is written as a developer-facing note. Move this to a TODO comment in the source code, and provide a shorter user-facing statement of the current restriction under the specific sub-option that it applies to. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --- docs/system/generic-loader.rst | 14 +++----------- hw/core/generic-loader.c | 18 ++++++++++++++++++ 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/docs/system/generic-loader.rst b/docs/system/generic-loader.rst index d5416711e9..0df9b66976 100644 --- a/docs/system/generic-loader.rst +++ b/docs/system/generic-loader.rst @@ -99,6 +99,9 @@ shown below: If this option is not specified, then the data will be loaded via the address space of the first CPU, and no CPU will have its PC set. =20 + Note that there is currently no way to specify the address space to + load the data without also causing that CPU's PC to be set. + Since it sets the starting PC, this option should only be used for the b= oot image. =20 @@ -111,14 +114,3 @@ shown below: An example of loading an ELF file which CPU0 will boot is shown below:: =20 -device loader,file=3D./images/boot.elf,cpu-num=3D0 - -Restrictions and ToDos -^^^^^^^^^^^^^^^^^^^^^^ - -At the moment it is just assumed that if you specify a cpu-num then -you want to set the PC as well. This might not always be the case. In -future the internal state 'set_pc' (which exists in the generic loader -now) should be exposed to the user so that they can choose if the PC -is set or not. - - diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c index 24f3908b1c..66a24f7b2a 100644 --- a/hw/core/generic-loader.c +++ b/hw/core/generic-loader.c @@ -30,6 +30,24 @@ * separate backend. */ =20 +/* + * TODO: currently the "load a file" functionality provides no way + * for the user to specify which CPU address space to load the data + * into without also causing that CPU's PC to be set to the start + * address of the file. + * + * We could fix this by having a new suboption set-pc (default: true) + * so the user can say + * -device loader,file=3D,cpu-num=3D + * for the current "use this address space and set the PC" behaviour + * or + * -device loader,file=3D,cpu-num=3D,set-pc=3Doff + * to just pick the address space and not set the PC. + * + * Using set-pc without file=3D should be handled as an error; otherwise + * it can feed through to what we set s->set_pc to. + */ + #include "qemu/osdep.h" #include "system/dma.h" #include "system/reset.h" --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768503508; cv=none; d=zohomail.com; s=zohoarc; b=hpFZp351xFW/6HgIwvKFFZpeAtaooR6vPwXMcQGZP4QUQpJ6ESvVhsdUG5WFFx0gxjs8FneMqrKMfRbj/BiEytIF7X3nu1EeEjMm4zCg6nRIizVrFx0Er3tw29mb4rLD2Je91uxigzkzdoXkyOjQq0h3U4kZ3juP7TS8mrzBXV4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768503508; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=wlp0FvTGz1vaK6cfRoAC6PByfj8iN/GLtX8hRHZ8j8A=; b=L/5LMdmKx7BT6rZ5GVbKhGd59f4NzjeNVEg+be+p3Xr8DfTLD5HdJ6VfydjPB+2DfVCV/dTriVvZ6gPPTJmQjXel3j2zbQ7Hpaz+jTBJrCXG+h2LzCjj/Ysr6S5+UfFjIUP1vHqi68hrHZDvPs23YvxndV9JlfYDOszrGXEIx44= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768503508645808.0263145608378; Thu, 15 Jan 2026 10:58:28 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vgSVy-0001rH-Ik; Thu, 15 Jan 2026 13:56:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vgSVQ-0000jA-3V for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:41 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vgSVN-0005wO-Tp for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:39 -0500 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4801c314c84so5219345e9.0 for ; Thu, 15 Jan 2026 10:55:30 -0800 (PST) Received: from mnementh.archaic.org.uk (f.7.f.1.7.5.e.f.f.f.c.5.d.8.2.4.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. 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Cc: qemu-stable@nongnu.org Signed-off-by: Alex Benn=C3=A9e Reviewed-by: C=C3=A9dric Le Goater Message-id: 20260113135941.3361163-1-alex.bennee@linaro.org Cc: C=C3=A9dric Le Goater Signed-off-by: Peter Maydell --- tests/functional/arm/test_aspeed_rainier.py | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/tests/functional/arm/test_aspeed_rainier.py b/tests/functional= /arm/test_aspeed_rainier.py index 602d6194ac..30827beca3 100755 --- a/tests/functional/arm/test_aspeed_rainier.py +++ b/tests/functional/arm/test_aspeed_rainier.py @@ -9,10 +9,8 @@ =20 class RainierMachine(AspeedTest): =20 - ASSET_RAINIER_EMMC =3D Asset( - ('https://fileserver.linaro.org/s/B6pJTwWEkzSDi36/download/' - 'mmc-p10bmc-20240617.qcow2'), - 'd523fb478d2b84d5adc5658d08502bc64b1486955683814f89c6137518acd90b') + ASSET_RAINIER_EMMC =3D Asset('https://kaod.org/qemu/aspeed/rainier/mmc= -p10bmc-20240617.qcow2', + 'd523fb478d2b84d5adc5658d08502bc64b14869556= 83814f89c6137518acd90b') =20 def test_arm_aspeed_emmc_boot(self): self.set_machine('rainier-bmc') --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768503480; cv=none; d=zohomail.com; s=zohoarc; b=g2G4r35HjhHGzHlmONenYySaA5oTv/ljIKhw+E11GnDGRBXRuMGGu2DvQrN6EnS5xEPHxsChprg4Fup8WO6HT0WiRyfPw/iL54lg49RjLS11gkN7nYpxtlvauWJnxieUCCH2gP5xhZ+G7iAPBO58/sIK4Os+vvfbIIPqibE8Ov4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768503480; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=wA/nEsPqIhwLRmIhUu82koV0Ke+qsz79EcZMSFMqDbo=; b=fBvtyInT/JRdTzx3NMW66pkKbNsj91eHh7hOoRVopBAJ/kHAz1NXwkwL1a6bOqOWMv5vauWv8MDggkosyIXx7lADOOT1miyPY4MUdPZ+vNC2+xiUuGWIu2+h9oBzxTGv3xD9JZRO+KgVPRdvTF6tXGtTvatnsDo4uKyQqUlLIh0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768503480024440.61084138176113; Thu, 15 Jan 2026 10:58:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vgSW0-00025J-6c; Thu, 15 Jan 2026 13:56:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vgSVQ-0000jL-T0 for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:41 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vgSVN-0005wa-VS for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:40 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-42fbc305552so1033235f8f.0 for ; Thu, 15 Jan 2026 10:55:30 -0800 (PST) Received: from mnementh.archaic.org.uk (f.7.f.1.7.5.e.f.f.f.c.5.d.8.2.4.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0:0:428d:5cff:fe57:1f7f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4356996cecasm514207f8f.26.2026.01.15.10.55.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 10:55:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768503330; x=1769108130; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wA/nEsPqIhwLRmIhUu82koV0Ke+qsz79EcZMSFMqDbo=; b=CgYioMqs43yPq6+fZi1B6eABLGW2X/c8Hst7+81Sb3M6AuOt7SSr8w+txAOs+2mula 8Dw2sKzmIfYY9JU6/KPgQnbWjFJA9udg366NvrGYCNugMOADZsZ/qtPceqAHxYEU4azo 7gB68fUxXfuqSYSCeVJoHg05Mp64uMRhqtArHAItltzn2h1HUM/K0ie6CS6847vL8GST Rdq06aOopBiziPXkhk01zbjAY2ylc/CU/XxrnMH6I75s3mHrs2QIJrJ0lHiFJcBWXv7Y O07c0kn6mJPyC9zyI8hYPivgsO7Fm/Mgu2KhLYHH2TxhNISXSxQRq3EMHCDX3eKxkqJ4 k9LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768503330; x=1769108130; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=wA/nEsPqIhwLRmIhUu82koV0Ke+qsz79EcZMSFMqDbo=; b=Z8M0nGxNQpkrfsJl7woTckN0TRbcmF69uYLskmy9Ke/c/EGPm5OJ6bZl9AIxd1kadc feHytCtRDqWuEF40ZYgOBFbByRL4TNNK3mHc1mxshrY5jdhkButD4/JEIbiJEJpWBuML MyAVJTxXPth4BILJpySD9qEOl/Zo+U9hmFnEoZ3PPi2mImYMmjr+tqwZZTEUkXQU8Hlp z4WeSV/i7zTMZsUfe2lp/MEn5kOiFx/RU303/fUvRY9kSDWrWuClI2PIakuooZxTWGp0 j11RpW5QghtpcSQeWd12bTV9vBvXzgVsMHG2I5s5QcxddLhYGnLQzkT3HCfErztgkLaF C0kg== X-Gm-Message-State: AOJu0YzPLb3ulniAPBzzz6P5G7yPIRiimrpWiLvNLBuIi8yzH1+kjCOC sK3tAAZZaZsyg6VHPO7WTQTlXR5LP2UMiPAT/YyrWb8qUAanT62HM6MUUx7jydqazIAaPxf3YkX aRjzE X-Gm-Gg: AY/fxX6T7cV6P7UrR6tVG/wOKvG+S2bPrf6qaNGVgkUIbJwmUIbDoyahC+TTfTMxO+n dduti6xhr+2jHq0Yhqqip0tMLOGy76Mr4iAMZBsQb2S+iiyR9X/V5esGE2xwxq4w+Vb1c9J1+ez Zzhy+P993qDWiLKUNT7AJaCI0hVHkKuj4Kbi5RUH6qcfz09Imk9NQmHXLsoJW+edKGz4QzbK0IW lToyBlAoGzOtcXwQ4x81kf/cIfB+/gs7G+tCDpREqbL8E5RIfIq6AbF210ylmbOZvsfi3LXUKKH Hy+MKCloTDgNDM1vULeV+WtMxGvzxFI34m0ZoOC1AX2oN1+yx6QDFg9ajrzBMxGxfd5qvtQmTHk vVX/qnWh98mfrqK3HttDSPXz4nGRQkGirXqrNaGJSQjFKNZnAAs9uic/YDohldyJAo+wnwcV85U 2qHO3iAS53ew1w/cb8OWXnl/szZLY+Obaavfg3HGwCwQcP8EPtL8ghOG/Qt9PJe/jks0tkcgHXc UyntKiNNQzyLYADRFgDK2fes7Syf/H73SahFcj76ZM59A== X-Received: by 2002:a5d:5889:0:b0:430:ff81:2961 with SMTP id ffacd0b85a97d-4356a082ebfmr310433f8f.51.1768503329649; Thu, 15 Jan 2026 10:55:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/25] target/arm: Don't specify ID_PFR1 accessfn twice Date: Thu, 15 Jan 2026 18:55:04 +0000 Message-ID: <20260115185508.786428-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260115185508.786428-1-peter.maydell@linaro.org> References: <20260115185508.786428-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768503481199158500 In the definition of ID_PFR1 we have an ifdef block; we specify the accessfn once in the common part of the ifdef and once in the not-user-only part, which is redundant but harmless. The accessfn will always return success in user-only mode (because we won't trap to EL2), so specify it only in the not-user-only half of the ifdef, as was probably the intention. This is only cc'd to stable to avoid a textual conflict with the following patch, which is a bug fix. Cc: qemu-stable@nongnu.org Fixes: 0f150c8499e970bd ("target/arm: Constify ID_PFR1 on user emulation") Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20251231170858.254594-2-peter.maydell@linaro.org --- target/arm/helper.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1ee721ac7b..958e8edd34 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6312,7 +6312,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "ID_PFR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, - .accessfn =3D access_aa32_tid3, #ifdef CONFIG_USER_ONLY .type =3D ARM_CP_CONST, .resetvalue =3D GET_IDREG(isar, ID_PFR1), --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768503457; cv=none; d=zohomail.com; s=zohoarc; b=mUKizsE/fsvOyLrJYBR5M9sM52JH+owh5C8rZvSMvMGPweLa4QnZtTtrdSr2EbPViuI3pYlhqvMuNGYK2eiHQN+aRi5GuxWxYuRXvYL/CKC5JQGwo0PYEhDCakfqE0+1piPK8alWxv54LAAshXzNERz5sT6I3N30FYNK7ghBlcw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768503457; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=+qqWyiis4vu13eF2YaYpjfVH8hK5g4ZbYU2p2JdrOWg=; b=oGGpviLVOOdli3NmJOzJ2szw+Cljtcqbczmh4vRSlfXxqCS1Jd82yTGMXuWeZNljrTtLleY4+2QMJIJ5+wWz7cDJX6+blqVRw2vsoZY8YV/JuABynWzROPmRnsd8YCazKDFRo6Oxk5KHFpbpp1jRoag2XWUDV+Y6uoAK7/dMpJk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768503457319403.38276166236665; Thu, 15 Jan 2026 10:57:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vgSVz-00020R-FC; Thu, 15 Jan 2026 13:56:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vgSVS-0000m4-Ki for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:43 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vgSVN-0005wl-UG for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:42 -0500 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-4327790c4e9so882990f8f.2 for ; Thu, 15 Jan 2026 10:55:31 -0800 (PST) Received: from mnementh.archaic.org.uk (f.7.f.1.7.5.e.f.f.f.c.5.d.8.2.4.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. 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Different architecture versions have defined this differently: * v7A has a set of ID regs that definitely must trap: - ID_PFR{0,1}, ID_DFR0, ID_AFR0, ID_MMFR{0,1,2,3}, ID_ISAR{0,1,2,3,4,5}, MVFR{0,1} and somewhat vaguely says that "there is no requirement" to trap for registers that are reserved in the ID reg space (i.e. which RAZ and might be used for new ID regs in future) * v8A adds to this list: - ID_PFR2 and MVFR2 must trap - ID_MMFR4, ID_MMFR5, ID_ISAR6, ID_DFR1 and reserved registers in the ID reg space must trap if FEAT_FGT is implemented, and it is IMPDEF if they trap if FEAT_FGT is not implemented In QEMU we seem to have attempted to implement this distinction (taking the "we do trap" IMPDEF choice if no FEAT_FGT), with access_aa64_tid3() always trapping on TID3 and access_aa32_tid3() trapping only if ARM_FEATURE_V8 is set. However, we didn't apply these to the right set of registers: we use access_aa32_tid3() on all the 32-bit ID registers *except* ID_PFR2, ID_DFR1, ID_MMFR5 and the RES0 space, which means that for a v7 CPU we don't trap on a lot of registers that we should trap on, and we do trap on various things that the v7A Arm ARM says there is "no requirement" to trap on. Straighten this out by naming the access functions more clearly for their purpose, and documenting this: access_v7_tid3() is only for the fixed set of ID registers that v7A traps on HCR.TID3, and access_tid3() is for any others, including the reserved encoding spaces and any new registers we add in future. AArch32 MVFR2 access is handled differently, in check_hcr_el2_trap; there we already do not trap on TID3 on v7A cores (where MVFR2 doesn't exist), because we in the code-generation function we UNDEF if ARM_FEATURE_V8 is not set, without generating code to call check_hcr_el2_trap. This bug was causing a problem for Xen which (after a recent change to Xen) expects to be able to trap ID_PFR0 on a Cortex-A15. The result of these changes is that our v8A behaviour remains the same, and on v7A we now trap the registers the Arm ARM definitely requires us to trap, and don't trap the reserved space that "there is no requirement" to trap. Cc: qemu-stable@nongnu.org Fixes: 6a4ef4e5d1084c ("target/arm: Honor HCR_EL2.TID3 trapping requirement= s") Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20251231170858.254594-3-peter.maydell@linaro.org --- target/arm/helper.c | 146 ++++++++++++++++++++++++-------------------- 1 file changed, 81 insertions(+), 65 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 958e8edd34..3f422f509d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5839,9 +5839,18 @@ static const ARMCPRegInfo ccsidr2_reginfo[] =3D { .readfn =3D ccsidr2_read, .type =3D ARM_CP_NO_RAW }, }; =20 -static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInf= o *ri, - bool isread) +static CPAccessResult access_v7a_tid3(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) { + /* + * Trap on TID3 always. This should be used only for the fixed set of + * registers which are defined to trap on HCR.TID3 in v7A, which is: + * ID_PFR{0,1}, ID_DFR0, ID_AFR0, ID_MMFR{0,1,2,3}, ID_ISAR{0,1,2,3,= 4,5} + * (MVFR0 and MVFR1 also trap in v7A, but this is not handled via + * this accessfn but in check_hcr_el2_trap.) + * Any other registers in the TID3 trap space should use access_tid3(), + * so that they trap on v8 and above, but not on v7. + */ if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) { return CP_ACCESS_TRAP_EL2; } @@ -5849,11 +5858,18 @@ static CPAccessResult access_aa64_tid3(CPUARMState = *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 -static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInf= o *ri, - bool isread) +static CPAccessResult access_tid3(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) { + /* + * Trap on TID3, if we implement at least v8. For v8 and above + * the ID register space is at least IMPDEF permitted to trap, + * and must trap if FEAT_FGT is implemented. We choose to trap + * always. Use this function for any new registers that should + * trap on TID3. + */ if (arm_feature(env, ARM_FEATURE_V8)) { - return access_aa64_tid3(env, ri, isread); + return access_v7a_tid3(env, ri, isread); } =20 return CP_ACCESS_OK; @@ -6303,7 +6319,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "ID_PFR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, + .accessfn =3D access_v7a_tid3, .resetvalue =3D GET_IDREG(isar, ID_PFR0)}, /* * ID_PFR1 is not a plain ARM_CP_CONST because we don't know @@ -6317,7 +6333,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D GET_IDREG(isar, ID_PFR1), #else .type =3D ARM_CP_NO_RAW, - .accessfn =3D access_aa32_tid3, + .accessfn =3D access_v7a_tid3, .readfn =3D id_pfr1_read, .writefn =3D arm_cp_write_ignore #endif @@ -6325,72 +6341,72 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "ID_DFR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, + .accessfn =3D access_v7a_tid3, .resetvalue =3D GET_IDREG(isar, ID_DFR0)}, { .name =3D "ID_AFR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, + .accessfn =3D access_v7a_tid3, .resetvalue =3D GET_IDREG(isar, ID_AFR0)}, { .name =3D "ID_MMFR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, + .accessfn =3D access_v7a_tid3, .resetvalue =3D GET_IDREG(isar, ID_MMFR0)}, { .name =3D "ID_MMFR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, + .accessfn =3D access_v7a_tid3, .resetvalue =3D GET_IDREG(isar, ID_MMFR1)}, { .name =3D "ID_MMFR2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, + .accessfn =3D access_v7a_tid3, .resetvalue =3D GET_IDREG(isar, ID_MMFR2)}, { .name =3D "ID_MMFR3", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, + .accessfn =3D access_v7a_tid3, .resetvalue =3D GET_IDREG(isar, ID_MMFR3)}, { .name =3D "ID_ISAR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, + .accessfn =3D access_v7a_tid3, .resetvalue =3D GET_IDREG(isar, ID_ISAR0)}, { .name =3D "ID_ISAR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, + .accessfn =3D access_v7a_tid3, .resetvalue =3D GET_IDREG(isar, ID_ISAR1)}, { .name =3D "ID_ISAR2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, + .accessfn =3D access_v7a_tid3, .resetvalue =3D GET_IDREG(isar, ID_ISAR2)}, { .name =3D "ID_ISAR3", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, + .accessfn =3D access_v7a_tid3, .resetvalue =3D GET_IDREG(isar, ID_ISAR3) }, { .name =3D "ID_ISAR4", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, + .accessfn =3D access_v7a_tid3, .resetvalue =3D GET_IDREG(isar, ID_ISAR4) }, { .name =3D "ID_ISAR5", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, + .accessfn =3D access_v7a_tid3, .resetvalue =3D GET_IDREG(isar, ID_ISAR5) }, { .name =3D "ID_MMFR4", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_MMFR4)}, { .name =3D "ID_ISAR6", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_ISAR6) }, }; define_arm_cp_regs(cpu, v6_idregs); @@ -6441,7 +6457,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D GET_IDREG(isar, ID_AA64PFR0) #else .type =3D ARM_CP_NO_RAW, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .readfn =3D id_aa64pfr0_read, .writefn =3D arm_cp_write_ignore #endif @@ -6449,172 +6465,172 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "ID_AA64PFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_AA64PFR1)}, { .name =3D "ID_AA64PFR2_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_AA64PFR2)}, { .name =3D "ID_AA64PFR3_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64ZFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_AA64ZFR0)}, { .name =3D "ID_AA64SMFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_AA64SMFR0)}, { .name =3D "ID_AA64PFR6_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64PFR7_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64DFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_AA64DFR0) }, { .name =3D "ID_AA64DFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_AA64DFR1) }, { .name =3D "ID_AA64DFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64DFR3_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64AFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_AA64AFR0) }, { .name =3D "ID_AA64AFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_AA64AFR1) }, { .name =3D "ID_AA64AFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64AFR3_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64ISAR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_AA64ISAR0)}, { .name =3D "ID_AA64ISAR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_AA64ISAR1)}, { .name =3D "ID_AA64ISAR2_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_AA64ISAR2)}, { .name =3D "ID_AA64ISAR3_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64ISAR4_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64ISAR5_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64ISAR6_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64ISAR7_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64MMFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR0)}, { .name =3D "ID_AA64MMFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR1) }, { .name =3D "ID_AA64MMFR2_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR2) }, { .name =3D "ID_AA64MMFR3_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR3) }, { .name =3D "ID_AA64MMFR4_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR4) }, { .name =3D "ID_AA64MMFR5_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64MMFR6_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, { .name =3D "ID_AA64MMFR7_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, { .name =3D "MVFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D cpu->isar.mvfr0 }, { .name =3D "MVFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D cpu->isar.mvfr1 }, { .name =3D "MVFR2_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D cpu->isar.mvfr2 }, /* * "0, c0, c3, {0,1,2}" are the encodings corresponding to @@ -6625,17 +6641,17 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "RES_0_C0_C3_0", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, { .name =3D "RES_0_C0_C3_1", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, { .name =3D "RES_0_C0_C3_2", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, /* * Other encodings in "0, c0, c3, ..." are STATE_BOTH because @@ -6646,27 +6662,27 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "RES_0_C0_C3_3", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, { .name =3D "ID_PFR2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_PFR2)}, { .name =3D "ID_DFR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_DFR1)}, { .name =3D "ID_MMFR5", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D GET_IDREG(isar, ID_MMFR5)}, { .name =3D "RES_0_C0_C3_7", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }, }; #ifdef CONFIG_USER_ONLY @@ -6818,7 +6834,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 0, .crm =3D i, .opc2 =3D= CP_ANY, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, + .accessfn =3D access_tid3, .resetvalue =3D 0 }; define_one_arm_cp_reg(cpu, &v8_aa32_raz_idregs); } --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768503410; cv=none; d=zohomail.com; s=zohoarc; b=Nn7WVpT59Aw9zoaAwCP0pAvROhuto6cI9snI/pFgTPXelcCkmUfZKAakR7R4sjKOHrK0YMivL5hMzRUccjDr0YLUifIE9FWuJ6ChKeGsvqePIofc16u6BwyK5G6+q2CppbBwh755vnK/G9Vi1cRurwZwB0jZ3r2RCc6V07Adpaw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768503410; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ccwGlBepenyCt3hvVIc/HOQFMTjzI66ATiAU+WWKcZY=; b=f2UFsk/8gQ3Q2aNCw3gyJWAGE9dRj+x/fJ/3Tlq3GpDHTZXhymAPqI9KA9hcll21Rpz8Xoff95XdBVWvG/uawERUiLQQI+fhOglfBrgljePvArIHYrki30Qo7cQQHxyKp69xf5DV1pqohQWy0/52YOQOM+718bUEgH29Ctm0ZEs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176850341079552.991288337202946; Thu, 15 Jan 2026 10:56:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vgSVx-0001hK-QI; Thu, 15 Jan 2026 13:56:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vgSVQ-0000jC-5i for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:41 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vgSVN-0005ws-SO for qemu-devel@nongnu.org; Thu, 15 Jan 2026 13:55:39 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-47ee9817a35so7213205e9.1 for ; Thu, 15 Jan 2026 10:55:33 -0800 (PST) Received: from mnementh.archaic.org.uk (f.7.f.1.7.5.e.f.f.f.c.5.d.8.2.4.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. 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We incorrectly use an accessfn for REVIDR and AIDR that only traps on v8A cores. Fix this by collapsing access_aa64_tid1() and access_aa32_tid1() together and never doing a check for v8 vs v7. The accessfn is also used for SMIDR_EL1, which is fine as this register is AArch64 only. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20251231170858.254594-4-peter.maydell@linaro.org --- target/arm/helper.c | 24 +++++++----------------- 1 file changed, 7 insertions(+), 17 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3f422f509d..acfb2cbc31 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -933,8 +933,8 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPR= egInfo *ri) return ret; } =20 -static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInf= o *ri, - bool isread) +static CPAccessResult access_tid1(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) { if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TID1))= { return CP_ACCESS_TRAP_EL2; @@ -943,16 +943,6 @@ static CPAccessResult access_aa64_tid1(CPUARMState *en= v, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 -static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInf= o *ri, - bool isread) -{ - if (arm_feature(env, ARM_FEATURE_V8)) { - return access_aa64_tid1(env, ri, isread); - } - - return CP_ACCESS_OK; -} - static const ARMCPRegInfo v7_cp_reginfo[] =3D { /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ { .name =3D "NOP", .cp =3D 15, .crn =3D 7, .crm =3D 0, .opc1 =3D 0, .o= pc2 =3D 4, @@ -978,7 +968,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { { .name =3D "AIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid1, + .accessfn =3D access_tid1, .fgt =3D FGT_AIDR_EL1, .resetvalue =3D 0 }, /* @@ -5001,7 +4991,7 @@ static const ARMCPRegInfo sme_reginfo[] =3D { .writefn =3D smcr_write, .raw_writefn =3D raw_write }, { .name =3D "SMIDR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 6, - .access =3D PL1_R, .accessfn =3D access_aa64_tid1, + .access =3D PL1_R, .accessfn =3D access_tid1, /* * IMPLEMENTOR =3D 0 (software) * REVISION =3D 0 (implementation defined) @@ -7112,7 +7102,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "REVIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 6, .access =3D PL1_R, - .accessfn =3D access_aa64_tid1, + .accessfn =3D access_tid1, .fgt =3D FGT_REVIDR_EL1, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->revidr }, }; @@ -7136,7 +7126,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "TCMTR", .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .access =3D PL1_R, - .accessfn =3D access_aa32_tid1, + .accessfn =3D access_tid1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; /* TLBTR is specific to VMSA */ @@ -7144,7 +7134,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .name =3D "TLBTR", .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 3, .access =3D PL1_R, - .accessfn =3D access_aa32_tid1, + .accessfn =3D access_tid1, .type =3D ARM_CP_CONST, .resetvalue =3D 0, }; /* MPUIR is specific to PMSA V6+ */ --=20 2.47.3 From nobody Mon Feb 9 09:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20251231170858.254594-5-peter.maydell@linaro.org --- target/arm/helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index acfb2cbc31..dce648b482 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5429,8 +5429,8 @@ static const ARMCPRegInfo dcpodp_reg[] =3D { .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, }; =20 -static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInf= o *ri, - bool isread) +static CPAccessResult access_tid5(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) { if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID5)) { return CP_ACCESS_TRAP_EL2; @@ -7467,7 +7467,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo gmid_reginfo =3D { .name =3D "GMID_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 4, - .access =3D PL1_R, .accessfn =3D access_aa64_tid5, + .access =3D PL1_R, .accessfn =3D access_tid5, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->gm_blocksize, }; define_one_arm_cp_reg(cpu, &gmid_reginfo); --=20 2.47.3