From nobody Mon Feb 9 23:46:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768379758; cv=none; d=zohomail.com; s=zohoarc; b=S5s76eOZjg+QPt9rnS9bY8+yo65OaGg5vkWVYSm6qD5NHdwTkmamy28wBYO86Qn6Fvuqply6N+hsbr5jZhjnNBPW42Z9neabXS8l4UsKtKMLfqaYyz7jRWR9FxRz0oPHETfAFsLtld0jNQJXdxKd19EQr0AdZl3fRCMPg3mmBdU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768379758; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5ZPwJRHQFilEPOEWOmwxWP3sRhP1MADwliPZOkuPvbc=; b=dgqo4uUjZNpM9wvQFKGzp8bO1OxXBsAiQzfVbjXXOPBIc3hWRPyYK3LuE4fp5HNFXkT7OlS1yYC6mALUta4KYbJkeA8k0KYw0MeqA9bXIcTsviI4fSNBRR6JajPSHk4eIsfshlvTE+zKvsyRAjHp2S2dEdlrADmXUuwKp7WC02U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768379758587283.23188567606155; Wed, 14 Jan 2026 00:35:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vfwLq-00006O-Ny; Wed, 14 Jan 2026 03:35:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vfwLh-0008VQ-3M for qemu-devel@nongnu.org; Wed, 14 Jan 2026 03:35:30 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vfwLd-0000Vr-Pt for qemu-devel@nongnu.org; Wed, 14 Jan 2026 03:35:28 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-47ed9b04365so10670385e9.0 for ; Wed, 14 Jan 2026 00:35:24 -0800 (PST) Received: from [127.0.1.1] (ppp-2-86-214-23.home.otenet.gr. [2.86.214.23]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-432bd5df9c5sm50121053f8f.22.2026.01.14.00.35.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 00:35:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768379723; x=1768984523; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=5ZPwJRHQFilEPOEWOmwxWP3sRhP1MADwliPZOkuPvbc=; b=xH5lJZtDQKtykHwnzQH2zj9bEBk6WK1FHzH6Wjav5zpZ9VOBc8n+0zAq6WGboyf42y 7evy+mXeQ1IdNpU3qvtVi4r+DJZrQ0CSF7Sc8pWbQXcl1f5ZTQ6GoL+r9wMiSghL8VEE Gwcj2zmO8orXZc7tyM0pyaWVi5d+pfG9iBAI8aXHZSTRjQzV0UkG5T874yRapRZQR8uW EnmwpG56aApZA14msIzmgKMhcpBe1isTZ2vpoGSdjhKeq59v24g3AMjAR7/7lc9mvlQw 0co0r0pRn1Mw6usA15JpS2hYejaXJkZ54T4iqo1xF/B6HXcEbaiMbbxxlOq49EgIgzWn nyMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768379723; x=1768984523; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=5ZPwJRHQFilEPOEWOmwxWP3sRhP1MADwliPZOkuPvbc=; b=kHHDamStlwTpVwV8lezG0bJolsHu89iM7D3OyKp702ZkXWoBJ4AJfGh8k52HzlZ0T9 y5z6xW6/8wuwNUUtoGuXqqSsb+B13rLDh+Fak0JcFCZs9F5nxJlWq0JKJ6Bx3fG9k0ev m2IgtMl5iRAwZi8gd/+QxuRt2cBEkK4lbrLY+eL0hco5bsm3WMp1rA2tpwJth9icckrj LB79MQVOMshtWyqewRZji+jvjq0+Uf/esTvjrIlV8dvM1xWZd1Gh3NU3a4sAvQ+3n/jy BAj+NbDeMrQBUoemViVvuPw8YR9Z74yv/ly2CjaU0fcSoHCpWIiJLpN4Z7xgvgh55zOr rZLg== X-Gm-Message-State: AOJu0YzJHGAi9mpYwZz4w+c+Bhz67dUwMHmiJwfnSPG6AT8P+CHb8Ltu OIE1en4CGARCxSdUSph5AKc9o8otNGBBkzK4u+Jmdw8E9B7dJ8NNxtV7NJZxzRajPtE= X-Gm-Gg: AY/fxX7a18F8kFVs4X1MbQPpni+XSscoxAJF+HJt6zIJs+lSYF9pUF34V/oHLTj2Sl+ EHHPjLGlghEcYbJI5Kw4hMtPkf2zv0ogUhSlfntOnD4CvPxNL90A7dzll7ZkXVJlt6Zh7ABSl1X 17vh/5g/RjGm1WykOOBAYLNsKtzanplsxp9wH4onH1dv0X7XgKbx9/bxMHjk7QMW/cNscQBXSPn F8z4CdDxBWxdh1IRZ6exOFYYc9S7L10gOfZEXptPelVmyM4Fmk9T6gRVHSc8c0Gg9MHkQRY8IwH J4WOlcFMPRrsAXhFatUx88OdumOq+OvXpTsgF63zBvlupnPs41K+R3EL1+fAeFjINHUzEpZ3RNE EJdv3qYP4PAsdJLjuL2ad2nBCZIxRtlp1iVyPpUGnygMJTy3LGWQ+riQ+5GYqDrSLc50EZVRUc4 HWcoM/c/Mcs4OvaBcPgSWVNDgnGOOyIgYlDPDgfdb+kF+fJwbwMZDnilKdQSGhypjl6niH0azJm HARIF4v5U/MnO/VlECZPznL X-Received: by 2002:a05:600c:470c:b0:47e:e2b0:15ba with SMTP id 5b1f17b1804b1-47ee32e03edmr19647835e9.8.1768379723045; Wed, 14 Jan 2026 00:35:23 -0800 (PST) From: Manos Pitsidianakis Date: Wed, 14 Jan 2026 10:35:03 +0200 Subject: [PATCH 1/2] hvf/arm: handle FEAT_SME2 migration MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260114-sme2-hvf-v1-1-ce9599596736@linaro.org> References: <20260114-sme2-hvf-v1-0-ce9599596736@linaro.org> In-Reply-To: <20260114-sme2-hvf-v1-0-ce9599596736@linaro.org> To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Phil_Mathieu-Daud=C3=A9?= , Alexander Graf , Mads Ynddal , Peter Maydell , qemu-arm@nongnu.org, Manos Pitsidianakis X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=18478; i=manos.pitsidianakis@linaro.org; h=from:subject:message-id; bh=NvcBLupGc8GMVdtjdth8YjCrppGSEu88OnpCqMiQAOw=; b=LS0tLS1CRUdJTiBQR1AgTUVTU0FHRS0tLS0tCgpvd0VCYlFLUy9aQU5Bd0FLQVhjcHgzQi9mZ 25RQWNzbVlnQnBaMVZJbU0zNnpxM2F0RDh3NjNzeWgvdElIanhoCmk5YXFtQ2VHdjJNTnQwU2Jp MXVKQWpNRUFBRUtBQjBXSVFUTVhCdE9SS0JXODRkd0hSQjNLY2R3ZjM0SjBBVUMKYVdkVlNBQUt DUkIzS2Nkd2YzNEowUGtoRC85L00xcmJuOTZOck5rV0RlN3JxWHd5eDRoc1dTc250UFBsYndMcg paZkN1YnNFR3B3anJkSENtWitWbVBXOXRHaGtDOGhmVTh4UTZsSUlIdkl3ZCt4V1NLZHpKTytPe HZ2QnZjMnIxCmlRZGM4Y0k3a2ZGQk5jUmk3anFMMmJqQUk5aG5WYUNMZnQ1eEF4YTkzdGVDeDVj WFdGVEZKTklRRXBac1pzbXQKRGl1TGJ5bGlpN0pSQWZjbmdKaW04UWlESjRjUXZ2anU5OHljVE1 xY2NKQVdVVFZiTFhHNnlWZVVhR2J6dlIwMwptOFhyRGJRZVJ2ZkNVUG1wRlZ3ODdMUHRXSUdCQl QrbWh2d0l0bWRuclg2Z2F6OHdZU0V0Z0dURFNSME1ZTUhwCnhJeEpJT01hRE9OR2ExekxUQ2x3V GcyNlhlMElRR0psM1NoYWtCU2ErMC9iR2VtdTM1QjNnUUZRK3M2MUQvajEKWkllNWtZWWhRM0l6 NitQMmNkUVZDMHo3NVc2WnhHK2NZUnFLZzMvelZIaUgwYmRTMGhpZXRuS3lmZUV6ejFWbwpVRW1 FYWpOcnBYc1A2R29EZS9rdnJ4ZXNzMTlmalk5WWFhYzRLc2lmSWdMakErVFgvUGg4MW8ybFozV1 I3VE05CkFOU3Nsckh5TGVMcWZ1WGUxWFZMTFVDSklyaGhtd0lYSWlhaVgra0NqVUhXamdqWFhHZ 0pLTG1kaGthN3pPeXQKTkdVQjAyZFB2a2ZnclNMdk4zMnlLMm5PMW5yQk5YUnRscUdJSndUMzJN NENwMnN4OW0rWUY1Ym16Z29QOTVkdgoxVk44encwRmIxbElnMkN0N0NTVldHV1FzUXZLcGszcm1 5a1VibFF1MHFvWTRvTnZ3dG9MNEYwZjYxNm1rSGhTClFrbTJSdz09Cj1hc2VvCi0tLS0tRU5EIF BHUCBNRVNTQUdFLS0tLS0K X-Developer-Key: i=manos.pitsidianakis@linaro.org; a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768379760746158500 SME2 support adds the following state for HVF guests: - Vector registers Z0, ... , Z31 (introduced by FEAT_SVE but HVF does not support it) - Predicate registers P0, .., P15 (also FEAT_SVE) - ZA register - ZT0 register - PSTATE.{SM,ZA} bits (SVCR pseudo-register) - SMPRI_EL1 which handles the PE's priority in the SMCU - TPIDR2_EL0 the thread local ID register for SME Signed-off-by: Manos Pitsidianakis Reviewed-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 293 ++++++++++++++++++++++++++++++++++++++++= +++- target/arm/hvf/sysreg.c.inc | 10 ++ target/arm/hvf_arm.h | 46 +++++++ target/arm/machine.c | 2 +- 4 files changed, 348 insertions(+), 3 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index fa26f63a61ad8fc2ffb675bd6d3c7fd21f1a9dae..42547b175c30c01c2b7e060dcc0= 1d1e11efb0d1b 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -397,6 +397,62 @@ static const struct hvf_reg_match hvf_fpreg_match[] = =3D { { HV_SIMD_FP_REG_Q31, offsetof(CPUARMState, vfp.zregs[31]) }, }; =20 +#if HVF_SME2_AVAILABLE +static const struct hvf_reg_match hvf_sme2_zreg_match[] =3D { + { HV_SME_Z_REG_0, offsetof(CPUARMState, vfp.zregs[0]) }, + { HV_SME_Z_REG_1, offsetof(CPUARMState, vfp.zregs[1]) }, + { HV_SME_Z_REG_2, offsetof(CPUARMState, vfp.zregs[2]) }, + { HV_SME_Z_REG_3, offsetof(CPUARMState, vfp.zregs[3]) }, + { HV_SME_Z_REG_4, offsetof(CPUARMState, vfp.zregs[4]) }, + { HV_SME_Z_REG_5, offsetof(CPUARMState, vfp.zregs[5]) }, + { HV_SME_Z_REG_6, offsetof(CPUARMState, vfp.zregs[6]) }, + { HV_SME_Z_REG_7, offsetof(CPUARMState, vfp.zregs[7]) }, + { HV_SME_Z_REG_8, offsetof(CPUARMState, vfp.zregs[8]) }, + { HV_SME_Z_REG_9, offsetof(CPUARMState, vfp.zregs[9]) }, + { HV_SME_Z_REG_10, offsetof(CPUARMState, vfp.zregs[10]) }, + { HV_SME_Z_REG_11, offsetof(CPUARMState, vfp.zregs[11]) }, + { HV_SME_Z_REG_12, offsetof(CPUARMState, vfp.zregs[12]) }, + { HV_SME_Z_REG_13, offsetof(CPUARMState, vfp.zregs[13]) }, + { HV_SME_Z_REG_14, offsetof(CPUARMState, vfp.zregs[14]) }, + { HV_SME_Z_REG_15, offsetof(CPUARMState, vfp.zregs[15]) }, + { HV_SME_Z_REG_16, offsetof(CPUARMState, vfp.zregs[16]) }, + { HV_SME_Z_REG_17, offsetof(CPUARMState, vfp.zregs[17]) }, + { HV_SME_Z_REG_18, offsetof(CPUARMState, vfp.zregs[18]) }, + { HV_SME_Z_REG_19, offsetof(CPUARMState, vfp.zregs[19]) }, + { HV_SME_Z_REG_20, offsetof(CPUARMState, vfp.zregs[20]) }, + { HV_SME_Z_REG_21, offsetof(CPUARMState, vfp.zregs[21]) }, + { HV_SME_Z_REG_22, offsetof(CPUARMState, vfp.zregs[22]) }, + { HV_SME_Z_REG_23, offsetof(CPUARMState, vfp.zregs[23]) }, + { HV_SME_Z_REG_24, offsetof(CPUARMState, vfp.zregs[24]) }, + { HV_SME_Z_REG_25, offsetof(CPUARMState, vfp.zregs[25]) }, + { HV_SME_Z_REG_26, offsetof(CPUARMState, vfp.zregs[26]) }, + { HV_SME_Z_REG_27, offsetof(CPUARMState, vfp.zregs[27]) }, + { HV_SME_Z_REG_28, offsetof(CPUARMState, vfp.zregs[28]) }, + { HV_SME_Z_REG_29, offsetof(CPUARMState, vfp.zregs[29]) }, + { HV_SME_Z_REG_30, offsetof(CPUARMState, vfp.zregs[30]) }, + { HV_SME_Z_REG_31, offsetof(CPUARMState, vfp.zregs[31]) }, +}; + +static const struct hvf_reg_match hvf_sme2_preg_match[] =3D { + { HV_SME_P_REG_0, offsetof(CPUARMState, vfp.pregs[0]) }, + { HV_SME_P_REG_1, offsetof(CPUARMState, vfp.pregs[1]) }, + { HV_SME_P_REG_2, offsetof(CPUARMState, vfp.pregs[2]) }, + { HV_SME_P_REG_3, offsetof(CPUARMState, vfp.pregs[3]) }, + { HV_SME_P_REG_4, offsetof(CPUARMState, vfp.pregs[4]) }, + { HV_SME_P_REG_5, offsetof(CPUARMState, vfp.pregs[5]) }, + { HV_SME_P_REG_6, offsetof(CPUARMState, vfp.pregs[6]) }, + { HV_SME_P_REG_7, offsetof(CPUARMState, vfp.pregs[7]) }, + { HV_SME_P_REG_8, offsetof(CPUARMState, vfp.pregs[8]) }, + { HV_SME_P_REG_9, offsetof(CPUARMState, vfp.pregs[9]) }, + { HV_SME_P_REG_10, offsetof(CPUARMState, vfp.pregs[10]) }, + { HV_SME_P_REG_11, offsetof(CPUARMState, vfp.pregs[11]) }, + { HV_SME_P_REG_12, offsetof(CPUARMState, vfp.pregs[12]) }, + { HV_SME_P_REG_13, offsetof(CPUARMState, vfp.pregs[13]) }, + { HV_SME_P_REG_14, offsetof(CPUARMState, vfp.pregs[14]) }, + { HV_SME_P_REG_15, offsetof(CPUARMState, vfp.pregs[15]) }, +}; +#endif /* HVF_SME2_AVAILABLE */ + /* * QEMU uses KVM system register ids in the migration format. * Conveniently, HVF uses the same encoding of the op* and cr* parameters @@ -408,22 +464,203 @@ static const struct hvf_reg_match hvf_fpreg_match[] = =3D { #define HVF_TO_KVMID(HVF) \ (CP_REG_ARM64 | CP_REG_SIZE_U64 | CP_REG_ARM64_SYSREG | (HVF)) =20 -/* Verify this at compile-time. */ +/* + * Verify this at compile-time. + * + * SME2 registers are guarded by a runtime availability attribute instead = of a + * compile-time def, so verify those at runtime in hvf_arch_init_vcpu() be= low. + */ =20 #define DEF_SYSREG(HVF_ID, ...) \ QEMU_BUILD_BUG_ON(HVF_ID !=3D KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARG= S__))); +#define DEF_SYSREG_15_02(...) =20 #include "sysreg.c.inc" =20 #undef DEF_SYSREG +#undef DEF_SYSREG_15_02 =20 #define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) HVF_ID, +#define DEF_SYSREG_15_02(...) =20 static const hv_sys_reg_t hvf_sreg_list[] =3D { #include "sysreg.c.inc" }; =20 #undef DEF_SYSREG +#undef DEF_SYSREG_15_02 + +#define DEF_SYSREG(...) +#define DEF_SYSREG_15_02(HVF_ID, op0, op1, crn, crm, op2) HVF_ID, + +API_AVAILABLE(macos(15.2)) +static const hv_sys_reg_t hvf_sreg_list_sme2[] =3D { +#include "sysreg.c.inc" +}; + +#undef DEF_SYSREG +#undef DEF_SYSREG_15_02 + +/* + * For FEAT_SME2 migration, we need to store PSTATE.{SM,ZA} bits which are + * accessible with the SVCR pseudo-register. However, in the HVF API this = is + * not exposed as a system-register (i.e. HVF_SYS_REG_SVCR) but a custom + * struct, hv_vcpu_sme_state_t. So we need to define our own KVMID in orde= r to + * store it in cpreg_values and make it migrateable. + */ +#define SVCR KVMID_AA64_SYS_REG64(3, 3, 4, 2, 2) + +#if HVF_SME2_AVAILABLE +API_AVAILABLE(macos(15.2)) +static void hvf_arch_put_sme(CPUState *cpu) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + const size_t svl_bytes =3D hvf_arm_sme2_get_svl(); + const size_t z_size =3D svl_bytes; + const size_t preg_size =3D DIV_ROUND_UP(z_size, 8); + const size_t za_size =3D svl_bytes * svl_bytes; + hv_vcpu_sme_state_t sme_state =3D { 0 }; + hv_return_t ret; + uint64_t svcr; + int n; + + /* + * Set PSTATE.{SM,ZA} bits + */ + svcr =3D arm_cpu->cpreg_values[arm_cpu->cpreg_array_len - 1]; + env->svcr =3D svcr; + + /* + * Construct SVCR (PSTATE.{SM,ZA}) state to pass to HVF: + */ + sme_state.streaming_sve_mode_enabled =3D FIELD_EX64(env->svcr, SVCR, S= M) > 0; + sme_state.za_storage_enabled =3D FIELD_EX64(env->svcr, SVCR, ZA) > 0; + ret =3D hv_vcpu_set_sme_state(cpu->accel->fd, &sme_state); + assert_hvf_ok(ret); + + /* + * We only care about Z/P registers if we're in streaming SVE mode, i.= e. + * PSTATE.SM is set, because only then can instructions that access th= em be + * used. We don't care about the register values otherwise. This is be= cause + * when the processing unit exits/enters this mode, it zeroes out those + * registers. + */ + if (sme_state.streaming_sve_mode_enabled) { + for (n =3D 0; n < ARRAY_SIZE(hvf_sme2_zreg_match); ++n) { + ret =3D hv_vcpu_set_sme_z_reg(cpu->accel->fd, + hvf_sme2_zreg_match[n].reg, + (uint8_t *)&env->vfp.zregs[n].d[0], + z_size); + assert_hvf_ok(ret); + } + + for (n =3D 0; n < ARRAY_SIZE(hvf_sme2_preg_match); ++n) { + ret =3D hv_vcpu_set_sme_p_reg(cpu->accel->fd, + hvf_sme2_preg_match[n].reg, + (uint8_t *)&env->vfp.pregs[n].p[0], + preg_size); + assert_hvf_ok(ret); + } + } + + /* + * If PSTATE.ZA bit is set then ZA and ZT0 are valid, otherwise they a= re + * zeroed out. + */ + if (sme_state.za_storage_enabled) { + hv_sme_zt0_uchar64_t tmp =3D { 0 }; + + memcpy(&tmp, &env->za_state.zt0, 64); + ret =3D hv_vcpu_set_sme_zt0_reg(cpu->accel->fd, &tmp); + assert_hvf_ok(ret); + + ret =3D hv_vcpu_set_sme_za_reg(cpu->accel->fd, + (uint8_t *)&env->za_state.za, + za_size); + assert_hvf_ok(ret); + } + + return; +} + +API_AVAILABLE(macos(15.2)) +static void hvf_arch_get_sme(CPUState *cpu) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + const size_t svl_bytes =3D hvf_arm_sme2_get_svl(); + const size_t z_size =3D svl_bytes; + const size_t preg_size =3D DIV_ROUND_UP(z_size, 8); + const size_t za_size =3D svl_bytes * svl_bytes; + hv_vcpu_sme_state_t sme_state =3D { 0 }; + hv_return_t ret; + uint64_t svcr; + int n; + + /* + * Get SVCR (PSTATE.{SM,ZA}) state from HVF: + */ + ret =3D hv_vcpu_get_sme_state(cpu->accel->fd, &sme_state); + assert_hvf_ok(ret); + + /* + * Set SVCR first because changing it will zero out Z/P regs + */ + svcr =3D + (sme_state.za_storage_enabled ? R_SVCR_ZA_MASK : 0) + | (sme_state.streaming_sve_mode_enabled ? R_SVCR_SM_MASK : 0); + + aarch64_set_svcr(env, svcr, R_SVCR_ZA_MASK | R_SVCR_SM_MASK); + arm_cpu->cpreg_values[arm_cpu->cpreg_array_len - 1] =3D svcr; + + /* + * We only care about Z/P registers if we're in streaming SVE mode, i.= e. + * PSTATE.SM is set, because only then can instructions that access th= em be + * used. We don't care about the register values otherwise. This is be= cause + * when the processing unit exits/enters this mode, it zeroes out those + * registers. + */ + if (sme_state.streaming_sve_mode_enabled) { + for (n =3D 0; n < ARRAY_SIZE(hvf_sme2_zreg_match); ++n) { + ret =3D hv_vcpu_get_sme_z_reg(cpu->accel->fd, + hvf_sme2_zreg_match[n].reg, + (uint8_t *)&env->vfp.zregs[n].d[0], + z_size); + assert_hvf_ok(ret); + } + + for (n =3D 0; n < ARRAY_SIZE(hvf_sme2_preg_match); ++n) { + ret =3D hv_vcpu_get_sme_p_reg(cpu->accel->fd, + hvf_sme2_preg_match[n].reg, + (uint8_t *)&env->vfp.pregs[n].p[0], + preg_size); + assert_hvf_ok(ret); + } + } + + /* + * If PSTATE.ZA bit is set then ZA and ZT0 are valid, otherwise they a= re + * zeroed out. + */ + if (sme_state.za_storage_enabled) { + hv_sme_zt0_uchar64_t tmp =3D { 0 }; + + /* Get ZT0 in a tmp vector, and then copy it to env.za_state.zt0 */ + ret =3D hv_vcpu_get_sme_zt0_reg(cpu->accel->fd, &tmp); + assert_hvf_ok(ret); + + memcpy(&env->za_state.zt0, &tmp, 64); + ret =3D hv_vcpu_get_sme_za_reg(cpu->accel->fd, + (uint8_t *)&env->za_state.za, + za_size); + assert_hvf_ok(ret); + + } + + return; +} +#endif /* HVF_SME2_AVAILABLE */ =20 int hvf_arch_get_registers(CPUState *cpu) { @@ -465,6 +702,10 @@ int hvf_arch_get_registers(CPUState *cpu) uint64_t kvm_id =3D arm_cpu->cpreg_indexes[i]; int hvf_id =3D KVMID_TO_HVF(kvm_id); =20 + if (kvm_id =3D=3D HVF_TO_KVMID(SVCR)) { + continue; + } + if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ switch (hvf_id) { @@ -558,6 +799,13 @@ int hvf_arch_get_registers(CPUState *cpu) =20 arm_cpu->cpreg_values[i] =3D val; } +#if HVF_SME2_AVAILABLE + if (__builtin_available(macOS 15.2, *)) { + if (cpu_isar_feature(aa64_sme, arm_cpu)) { + hvf_arch_get_sme(cpu); + } + } +#endif /* HVF_SME2_AVAILABLE */ assert(write_list_to_cpustate(arm_cpu)); =20 aarch64_restore_sp(env, arm_current_el(env)); @@ -603,6 +851,10 @@ int hvf_arch_put_registers(CPUState *cpu) uint64_t kvm_id =3D arm_cpu->cpreg_indexes[i]; int hvf_id =3D KVMID_TO_HVF(kvm_id); =20 + if (kvm_id =3D=3D HVF_TO_KVMID(SVCR)) { + continue; + } + if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ switch (hvf_id) { @@ -687,6 +939,13 @@ int hvf_arch_put_registers(CPUState *cpu) ret =3D hv_vcpu_set_vtimer_offset(cpu->accel->fd, hvf_state->vtimer_of= fset); assert_hvf_ok(ret); =20 +#if HVF_SME2_AVAILABLE + if (__builtin_available(macOS 15.2, *)) { + if (cpu_isar_feature(aa64_sme, arm_cpu)) { + hvf_arch_put_sme(cpu); + } + } +#endif /* HVF_SME2_AVAILABLE */ return 0; } =20 @@ -909,6 +1168,18 @@ int hvf_arch_init_vcpu(CPUState *cpu) hv_return_t ret; int i; =20 + if (__builtin_available(macOS 15.2, *)) { + sregs_match_len +=3D ARRAY_SIZE(hvf_sreg_list_sme2) + 1; + +#define DEF_SYSREG_15_02(HVF_ID, ...) \ + g_assert(HVF_ID =3D=3D KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARGS= __))); +#define DEF_SYSREG(...) + +#include "sysreg.c.inc" + +#undef DEF_SYSREG +#undef DEF_SYSREG_15_02 + } env->aarch64 =3D true; asm volatile("mrs %0, cntfrq_el0" : "=3Dr"(arm_cpu->gt_cntfrq_hz)); =20 @@ -927,7 +1198,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t)); =20 /* Populate cp list for all known sysregs */ - for (i =3D 0; i < sregs_match_len; i++) { + for (i =3D 0; i < ARRAY_SIZE(hvf_sreg_list); i++) { hv_sys_reg_t hvf_id =3D hvf_sreg_list[i]; uint64_t kvm_id =3D HVF_TO_KVMID(hvf_id); uint32_t key =3D kvm_to_cpreg_id(kvm_id); @@ -938,6 +1209,24 @@ int hvf_arch_init_vcpu(CPUState *cpu) arm_cpu->cpreg_indexes[sregs_cnt++] =3D kvm_id; } } + if (__builtin_available(macOS 15.2, *)) { + for (i =3D 0; i < ARRAY_SIZE(hvf_sreg_list_sme2); i++) { + hv_sys_reg_t hvf_id =3D hvf_sreg_list_sme2[i]; + uint64_t kvm_id =3D HVF_TO_KVMID(hvf_id); + uint32_t key =3D kvm_to_cpreg_id(kvm_id); + const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs= , key); + + if (ri) { + assert(!(ri->type & ARM_CP_NO_RAW)); + arm_cpu->cpreg_indexes[sregs_cnt++] =3D kvm_id; + } + } + /* + * Add SVCR last. It is elsewhere assumed its index is after + * hvf_sreg_list and hvf_sreg_list_sme2. + */ + arm_cpu->cpreg_indexes[sregs_cnt++] =3D HVF_TO_KVMID(SVCR); + } arm_cpu->cpreg_array_len =3D sregs_cnt; arm_cpu->cpreg_vmstate_array_len =3D sregs_cnt; =20 diff --git a/target/arm/hvf/sysreg.c.inc b/target/arm/hvf/sysreg.c.inc index 067a8603fa785593ed0879cea26d036b0ec2823e..fb973ec19b747b445b57d7fc15e= 8d0a05336f941 100644 --- a/target/arm/hvf/sysreg.c.inc +++ b/target/arm/hvf/sysreg.c.inc @@ -145,3 +145,13 @@ DEF_SYSREG(HV_SYS_REG_TPIDRRO_EL0, 3, 3, 13, 0, 3) DEF_SYSREG(HV_SYS_REG_CNTV_CTL_EL0, 3, 3, 14, 3, 1) DEF_SYSREG(HV_SYS_REG_CNTV_CVAL_EL0, 3, 3, 14, 3, 2) DEF_SYSREG(HV_SYS_REG_SP_EL1, 3, 4, 4, 1, 0) + +#if HVF_SME2_AVAILABLE +DEF_SYSREG_15_02(HV_SYS_REG_SMCR_EL1, 3, 0, 1, 2, 6) +DEF_SYSREG_15_02(HV_SYS_REG_SMPRI_EL1, 3, 0, 1, 2, 4) +DEF_SYSREG_15_02(HV_SYS_REG_TPIDR2_EL0, 3, 3, 13, 0, 5) +DEF_SYSREG_15_02(HV_SYS_REG_ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) +DEF_SYSREG_15_02(HV_SYS_REG_ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5) +DEF_SYSREG_15_02(HV_SYS_REG_SMPRI_EL1, 3, 0, 1, 2, 4) +DEF_SYSREG_15_02(HV_SYS_REG_SMCR_EL1, 3, 0, 1, 2, 6) +#endif /* HVF_SME2_AVAILABLE */ diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h index ea82f2691dfcce780d9ab7d580c8a7946e3abaa7..adb282f02d0fc059b6ff0ce5270= ad9f447f37927 100644 --- a/target/arm/hvf_arm.h +++ b/target/arm/hvf_arm.h @@ -13,6 +13,14 @@ =20 #include "target/arm/cpu-qom.h" =20 +#ifdef __MAC_OS_X_VERSION_MAX_ALLOWED + #define HVF_SME2_AVAILABLE (__MAC_OS_X_VERSION_MAX_ALLOWED >=3D 150200) + #include "system/hvf_int.h" +#else + #define HVF_SME2_AVAILABLE 0 +#endif + + /** * hvf_arm_init_debug() - initialize guest debug capabilities * @@ -25,4 +33,42 @@ void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu); uint32_t hvf_arm_get_default_ipa_bit_size(void); uint32_t hvf_arm_get_max_ipa_bit_size(void); =20 +#if HVF_SME2_AVAILABLE +static inline bool hvf_arm_sme2_supported(void) +{ + if (__builtin_available(macOS 15.2, *)) { + size_t svl_bytes; + hv_return_t result =3D hv_sme_config_get_max_svl_bytes(&svl_bytes); + if (result =3D=3D HV_UNSUPPORTED) { + return false; + } + assert_hvf_ok(result); + return svl_bytes > 0; + } else { + return false; + } +} + +static inline uint32_t hvf_arm_sme2_get_svl(void) +{ + if (__builtin_available(macOS 15.2, *)) { + size_t svl_bytes; + hv_return_t result =3D hv_sme_config_get_max_svl_bytes(&svl_bytes); + assert_hvf_ok(result); + return svl_bytes; + } else { + abort(); + } +} +#else /* HVF_SME2_AVAILABLE */ +static inline bool hvf_arm_sme2_supported(void) +{ + return false; +} +static inline uint32_t hvf_arm_sme2_get_svl(void) +{ + abort(); +} +#endif /* HVF_SME2_AVAILABLE */ + #endif diff --git a/target/arm/machine.c b/target/arm/machine.c index 0befdb0b28ad3f45b0bd83575dd9fd4fecaf3db1..7e3339081bf1f9f57bb0514d795= c8a4254975c6a 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -231,7 +231,7 @@ static bool sve_needed(void *opaque) { ARMCPU *cpu =3D opaque; =20 - return cpu_isar_feature(aa64_sve, cpu); + return cpu_isar_feature(aa64_sve, cpu) || cpu_isar_feature(aa64_sme, c= pu); } =20 /* The first two words of each Zreg is stored in VFP state. */ --=20 2.47.3 From nobody Mon Feb 9 23:46:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1768379784; cv=none; d=zohomail.com; s=zohoarc; b=BTgM2AUrDoHWwc72eyMs0T3QgvVyPTiplTAtJqK8+EFOhSGaYAwzTXWJDC79xCV91t8hwB0ja42tZ5vEz0hHTncoHafz/ZMMOTUT0ALBLQyLKP2bZ0GisoFwZ1V/eOyesZ6vAIkArtr+5mg0SxBXWGbn35kUfS6fji4ZLwh8oNI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768379784; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1F8dCjujQUOds7Tjuv0RkAfG1TY3N3l+JRmSQjFDw0k=; b=LEdgtFDMVDG45YbP2vI3mHcFz5gdC3kdNVoPs10KDk70dpvpcJ8Zk7VYT6q/8dVv/jQDFy3giFh15v7Ej9A9zU/ztdvgYAeaQEZG9tyPE8iQ92g85ResWqAEWamCQL4btOEU0nlmtDdhE1ONuNd71eg86ZuMQcb+zuxKGKMDYg0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768379784768254.31760835074522; Wed, 14 Jan 2026 00:36:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vfwLs-000080-Le; Wed, 14 Jan 2026 03:35:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vfwLf-0008VN-W5 for qemu-devel@nongnu.org; Wed, 14 Jan 2026 03:35:28 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vfwLd-0000WD-Pw for qemu-devel@nongnu.org; Wed, 14 Jan 2026 03:35:27 -0500 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-432da746749so2542286f8f.0 for ; Wed, 14 Jan 2026 00:35:25 -0800 (PST) Received: from [127.0.1.1] (ppp-2-86-214-23.home.otenet.gr. [2.86.214.23]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-432bd5df9c5sm50121053f8f.22.2026.01.14.00.35.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 00:35:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768379724; x=1768984524; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1F8dCjujQUOds7Tjuv0RkAfG1TY3N3l+JRmSQjFDw0k=; b=p+bFBDApr7u9l3hmO8ERYGDXvvmngQVBlN3WTpmIEGLy78/d2D3/6at6raRSZC7n4e 2eFstZxoZFkJJhuR0UYG5Ue8MFqe0VkM6Aa0qkWpcwr+NRbbzQ4wfF02ac7JbE23oMmT hqz3R5mYi0Hut6g49mkoRa1azOM4GZcrYfhzJz7m8Fd0aqgTSiPReUpZEWljzlc4X+2v iQOH/L3lq8h6tyCQIFPxTuIM0V4EFRM2NKQ0zvavf1VXOyL6zi8frdQAl8ka+HDUXu8S 71fQApW0LBmQPmskCz6PfiwuZFLKEcmb1iQldbd2y6HbkpEmmjdVK/1ir0ylxDnHQGB9 GF+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768379724; x=1768984524; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=1F8dCjujQUOds7Tjuv0RkAfG1TY3N3l+JRmSQjFDw0k=; b=IH7QmADvSMGhPL0gSNcOE6oltM0s1FfyCm4Y7EpbplqHxcuifRGQSrgDiALwG8vt6V EoA/L8Ee9v588kglygRGueYAQG8bryVtncKTnz89OWe4X+PVIDhAcv4lCQR6g2LSHA02 sQbTesA3Vu0c2XoEw+GvkllgsjlZ56qNsCOUwf73cWee5BDV5hGtuqHaYp6lwt49Z78W 673rmU5s75KVwLdgBbIqZZYa6zCMG8ck/Qz27yscJch82gxPhqc9JW7jjowkFEk8IfRO dBCGMa+YgB0jSGIOV/QT+McrZEqM1w+0ndEHJZEAFt/pVbY+e7lC2pHzluVz/BLNSGy+ peeg== X-Gm-Message-State: AOJu0Yxll70Yzo6scpREskeISqOYf+ldUo3FtWjHCuOGYZUgsl2owbUd LJlvRzCHamzbMwl+Bo/34Qp2kCWGuvqdUZYcW2SYd0COPTvc6o5I7YdaLKTMVbAPZgA= X-Gm-Gg: AY/fxX5SB5m5AK+BWFCQars8N+SOx9yMeuBTk1Qg9tWI+gs9gfBcgrOQOzLL61nlt3/ DQyxN546kuTEjcwwC3YfxjGMHNrtqPWtMO5W4xLjYB4SjfhuPnDy3xB44pvVZ2oyKCYbGuaNfy3 oKpBNC5UtxR0Sq8F3NGoXUkKkZpPDYnnKskZ8BznlDqX8MiW3QVcbgqzAG120GKVscolBli+VyR tvBwHtI1G+mq4m13daHKI0ZWfFQOOQNW+OOKMpa8C19l7ZJpEmextLdrroChyKiZ5jhv1fZy2NU +lPm7o9RoLCZYD/QSnW60B/p2JJ4HT6ZzlbP4bWw2RJfXIC0jGhS3DScXYRiVIrqk2Cg9VCVvqT bNY9pk/VuPQJbX99oK9L3R3NaqH9VREjpeCN2M/XodvhJzbNUUBa6JpG2eFb0I9Bl0jT8JAchty oaLeeLepLNWCCDaBFu483YMOwKxGPsVeTs6rUUmkeKF4rSArd4nmqTyflLU4Zm0cr4MYr3pisa/ YYqL68A080GMR6CPkBvFb92HTtGdBnrjOM= X-Received: by 2002:a05:6000:1acf:b0:432:c17c:3076 with SMTP id ffacd0b85a97d-4342c4ff132mr1841473f8f.14.1768379724282; Wed, 14 Jan 2026 00:35:24 -0800 (PST) From: Manos Pitsidianakis Date: Wed, 14 Jan 2026 10:35:04 +0200 Subject: [PATCH 2/2] hvf/arm: expose FEAT_SME2 to guest if available MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260114-sme2-hvf-v1-2-ce9599596736@linaro.org> References: <20260114-sme2-hvf-v1-0-ce9599596736@linaro.org> In-Reply-To: <20260114-sme2-hvf-v1-0-ce9599596736@linaro.org> To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Phil_Mathieu-Daud=C3=A9?= , Alexander Graf , Mads Ynddal , Peter Maydell , qemu-arm@nongnu.org, Manos Pitsidianakis X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3766; i=manos.pitsidianakis@linaro.org; h=from:subject:message-id; bh=+Ifjo7l7CBODQ3juYZTHP5EYl1Mvfgv3FFkePf3tySo=; b=LS0tLS1CRUdJTiBQR1AgTUVTU0FHRS0tLS0tCgpvd0VCYlFLUy9aQU5Bd0FLQVhjcHgzQi9mZ 25RQWNzbVlnQnBaMVZJaTM0M0FxRzl4YTNrSHlnd0RqbXBHZ3ZPCm1TMEZkc3lIeGpiMWNFcGVt M3FKQWpNRUFBRUtBQjBXSVFUTVhCdE9SS0JXODRkd0hSQjNLY2R3ZjM0SjBBVUMKYVdkVlNBQUt DUkIzS2Nkd2YzNEowTktaRC80OGc4aUdPUy85VlZUTXlwYk1NaDVhd0hYQXJlRWlUS1ZDb0lRSA pEdW1DVCtyOGdhdjlFZklmMStiY2czdmd5MXF2dlBkRXlXV2l0WmkvNU95NXhrWVBQVEtOUEdKe TVBQkVWb0VqCmtDVlJPelZqMTlpRUNLdzZuZzJHRklUWmFFWTY3bnAvOG54cWdVblNiWHZNWjUy WG5WTS9Ud0tLM0FYWC9DcXQKK3dhRnh2RzkxY0RoZlZLbExybnhOeTlLTHIrem4yWFF4K3RMN3F tZ1dYeTY0T2xSRkFSdmRmVUg3bUprVDVwMgorRDFxY0xFbXhUR2FuRkxQZDNvZ25VNHQ2R0FwQk lxQWU2WWhoRkJDOXVVQTlPRzZITFB1M1kwV1MveWpIK2c1CmxINTBlTFczK0J5YzZkTEE1YWhFY mQwMjhsMExoNmJDS2t2RjFqYzB6Q3gxTUVGUkdTeU5HYlRCeW1xbGxvUkoKYitjRmVscUNEU3kx aFVTYzRLS0VoYXhhd0VRejIyVmVIYnNuZzZ2U2dGN2Fxa21hTmpHdm1VOEhwY3hPMVlzNQp0cEs ra3d6L0dPOUVmbktydXBNR3QvaGE0WWZqa0d2cFo0dGVXZ3V6Wk9SSWlhQ0NuaDgwbDRFdmpzZn N0Zjg1CkFpWHhYaXcvd0ZWRmV6eEQ2YVZTSkN3MVhsYndXWEZZZE5HejN5cHUrRnhqMUlhWEkva 0ozOHE1NVlvN2RGQjkKNEIyZ3RKSEk5WDNrV1lNMlRvaDBkM291K3Bjc3F6cGRDcHlqRXBpU3R6 clRLdEdlaXhsTmwxdHBWRE1UNWpjMwpCR3RpcnlaeEJMenYweEFwMGxwSm9GMzhDeTFvRUNzaVd GZ0NIWmN3ZUhWK1RlRzlPRW5ENVdqbmloblZnQnNWCm00SVRxUT09Cj1JNVNDCi0tLS0tRU5EIF BHUCBNRVNTQUdFLS0tLS0K X-Developer-Key: i=manos.pitsidianakis@linaro.org; a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1768379786502158500 Starting from M4 cores and MacOS 15.2 SDK, HVF can virtualise FEAT_SME2. Signed-off-by: Manos Pitsidianakis Reviewed-by: Mohamed Mediouni --- target/arm/cpu.c | 4 +++- target/arm/cpu64.c | 13 ++++++++++++- target/arm/hvf/hvf.c | 25 +++++++++++++------------ 3 files changed, 28 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index caf7980b1fc5244c5c2f130e79ba869456c20c88..7f4ebfdf61217db6075495119c1= b642bc2abf295 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1577,7 +1577,9 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **e= rrp) * assumes it, so if the user asked for sve=3Doff then turn off SM= E also. * (KVM doesn't currently support SME at all.) */ - if (cpu_isar_feature(aa64_sme, cpu) && !cpu_isar_feature(aa64_sve,= cpu)) { + if (!hvf_enabled() + && cpu_isar_feature(aa64_sme, cpu) + && !cpu_isar_feature(aa64_sve, cpu)) { object_property_set_bool(OBJECT(cpu), "sme", false, &error_abo= rt); } =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index bf303813701972648fa6751ffe352ba074ca6442..8dd9eb46c783a799a53891a6dda= d40b930e95eb4 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -329,9 +329,20 @@ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) { uint32_t vq_map =3D cpu->sme_vq.map; uint32_t vq_init =3D cpu->sme_vq.init; - uint32_t vq_supported =3D cpu->sme_vq.supported; + uint32_t vq_supported; uint32_t vq; =20 + if (hvf_enabled()) { + if (hvf_arm_sme2_supported()) { + vq_supported =3D hvf_arm_sme2_get_svl(); + } else { + assert(!cpu_isar_feature(aa64_sme, cpu)); + vq_supported =3D 0; + } + } else { + vq_supported =3D cpu->sme_vq.supported; + } + if (vq_map =3D=3D 0) { if (!cpu_isar_feature(aa64_sme, cpu)) { SET_IDREG(&cpu->isar, ID_AA64SMFR0, 0); diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 42547b175c30c01c2b7e060dcc01d1e11efb0d1b..b51eb9bb6a1b416af3b2cbac1aa= c81457c2b4cb2 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1051,18 +1051,18 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCP= UFeatures *ahcf) =20 clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar); =20 - /* - * Disable SME, which is not properly handled by QEMU hvf yet. - * To allow this through we would need to: - * - make sure that the SME state is correctly handled in the - * get_registers/put_registers functions - * - get the SME-specific CPU properties to work with accelerators - * other than TCG - * - fix any assumptions we made that SME implies SVE (since - * on the M4 there is SME but not SVE) - */ - SET_IDREG(&host_isar, ID_AA64PFR1, - GET_IDREG(&host_isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MASK= ); + if (hvf_arm_sme2_supported()) { + t =3D GET_IDREG(&host_isar, ID_AA64PFR1); + t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 2); /* FEAT_SME2 */ + SET_IDREG(&host_isar, ID_AA64PFR1, t); + + t =3D GET_IDREG(&host_isar, ID_AA64SMFR0); + t =3D FIELD_DP64(t, ID_AA64SMFR0, SMEVER, 1); /* FEAT_SME2 */ + SET_IDREG(&host_isar, ID_AA64SMFR0, t); + } else { + SET_IDREG(&host_isar, ID_AA64PFR1, + GET_IDREG(&host_isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MA= SK); + } =20 ahcf->isar =3D host_isar; =20 @@ -1260,6 +1260,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) arm_cpu->isar.idregs[ID_AA64MMFR0_EL1_IDX]); assert_hvf_ok(ret); =20 + aarch64_add_sme_properties(OBJECT(cpu)); return 0; } =20 --=20 2.47.3