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Tue, 13 Jan 2026 04:55:30 -0800 (PST) From: Vladimir Isaev To: richard.henderson@linaro.org, pbonzini@redhat.com Cc: qemu-devel@nongnu.org, Vladimir Isaev Subject: [PATCH] accel/tcg/cputlb.c: fix unaligned IO region access Date: Tue, 13 Jan 2026 15:54:58 +0300 Message-ID: <20260113125514.111899-1-vvisaev@gmail.com> X-Mailer: git-send-email 2.51.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=vvisaev@gmail.com; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1768309197680158501 Content-Type: text/plain; charset="utf-8" According to comment for full->xlat_section for non-RAM: Otherwise, iotlb contains - a physical section number in the lower TARGET_PAGE_BITS - the offset within section->mr of the page base (I/O, ROMD) with the TARGET_PAGE_BITS masked off. This 'physical section number in the lower TARGET_PAGE_BITS' is true only if memory region is aligned to TARGET_PAGE_BITS. For example for memory region with address 0x1000c220 and size of 2 x 4k pages following sections will be created by flatview_add_to_dispatch= (): flatview_add_to_dispatch section 1: addr: 0x1000c220 offset_within_address_= space 0x1000c220 offset_within_region 0x0 flatview_add_to_dispatch section 2: addr: 0x1000c220 offset_within_address_= space 0x1000d000 offset_within_region 0xde0 flatview_add_to_dispatch section 3: addr: 0x1000c220 offset_within_address_= space 0x1000e000 offset_within_region 0x1de0 So offset_within_region is not aligned to TARGET_PAGE_SIZE. This leads to full->xlat_section & ~TARGET_PAGE_BITS to contain information= not only about section number, but also about offset in the memory region. Fix it by clearing TARGET_PAGE_BITS bits in xlat before adding section and = reapply them in io_prepare(). Signed-off-by: Vladimir Isaev --- accel/tcg/cputlb.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c30073326a..4c0b01b606 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1090,7 +1090,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, } } else { /* I/O or ROMD */ - iotlb =3D memory_region_section_get_iotlb(cpu, section) + xlat; + iotlb =3D memory_region_section_get_iotlb(cpu, section) + (xlat & = TARGET_PAGE_MASK); /* * Writes to romd devices must go through MMIO to enable write. * Reads to romd devices go through the ram_ptr found above, @@ -1277,7 +1277,8 @@ io_prepare(hwaddr *out_offset, CPUState *cpu, hwaddr = xlat, hwaddr mr_offset; =20 section =3D iotlb_to_section(cpu, xlat, attrs); - mr_offset =3D (xlat & TARGET_PAGE_MASK) + addr; + mr_offset =3D (xlat & TARGET_PAGE_MASK) + addr + + (section->offset_within_region & ~TARGET_PAGE_MASK); cpu->mem_io_pc =3D retaddr; if (!cpu->neg.can_do_io) { cpu_io_recompile(cpu, retaddr); --=20 2.51.0