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Tsirkin" , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 18/41] intel_iommu: Replay pasid bindings after context cache invalidation Date: Tue, 13 Jan 2026 10:36:14 +0100 Message-ID: <20260113093637.1549214-19-clg@redhat.com> In-Reply-To: <20260113093637.1549214-1-clg@redhat.com> References: <20260113093637.1549214-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1768297089596158500 From: Yi Liu This replays guest pasid bindings after context cache invalidation. Actually, programmer should issue pasid cache invalidation with proper granularity after issuing context cache invalidation. We see old linux such as 6.7.0-rc2 not following the spec, it sends pasid cache invalidation before context cache invalidation, then QEMU depends on context cache invalidation to get pasid entry and setup binding. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Yi Liu Reviewed-by: Michael S. Tsirkin Link: https://lore.kernel.org/qemu-devel/20260106061304.314546-17-zhenzhong= .duan@intel.com Signed-off-by: C=C3=A9dric Le Goater --- hw/i386/intel_iommu.c | 42 ++++++++++++++++++++++++++++++++++++++++++ hw/i386/trace-events | 1 + 2 files changed, 43 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 3241af811c4313e22864a0c2fbb2d83b89208541..08236b85ee67bdb41fb6a9ccbd6= 0ac164e825064 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -77,6 +77,8 @@ struct vtd_iotlb_key { static void vtd_address_space_refresh_all(IntelIOMMUState *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); static void vtd_replay_pasid_bindings_all(IntelIOMMUState *s); +static void vtd_pasid_cache_sync_locked(gpointer key, gpointer value, + gpointer user_data); =20 static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s) { @@ -2322,6 +2324,37 @@ static void vtd_context_global_invalidate(IntelIOMMU= State *s) * VT-d emulation codes. */ vtd_iommu_replay_all(s); + /* + * Same for pasid cache invalidation, per VT-d spec 6.5.2.1, a global + * context cache invalidation should be followed by global PASID cache + * invalidation. In order to work with guest not following spec, + * handle global PASID cache invalidation here. + */ + vtd_replay_pasid_bindings_all(s); +} + +static void vtd_pasid_cache_devsi(VTDAddressSpace *vtd_as) +{ + IntelIOMMUState *s =3D vtd_as->iommu_state; + PCIBus *bus =3D vtd_as->bus; + uint8_t devfn =3D vtd_as->devfn; + struct vtd_as_key key =3D { + .bus =3D bus, + .devfn =3D devfn, + .pasid =3D vtd_as->pasid, + }; + VTDPASIDCacheInfo pc_info; + + if (!s->fsts || !s->root_scalable || !s->dmar_enabled) { + return; + } + + trace_vtd_pasid_cache_devsi(pci_bus_num(bus), + VTD_PCI_SLOT(devfn), VTD_PCI_FUNC(devfn)); + + /* We fake to be global invalidation just to bypass all checks */ + pc_info.type =3D VTD_INV_DESC_PASIDC_G_GLOBAL; + vtd_pasid_cache_sync_locked(&key, vtd_as, &pc_info); } =20 /* Do a context-cache device-selective invalidation. @@ -2382,6 +2415,15 @@ static void vtd_context_device_invalidate(IntelIOMMU= State *s, * happened. */ vtd_address_space_sync(vtd_as); + /* + * Per spec 6.5.2.1, context flush should be followed by PASID + * cache and iotlb flush. In order to work with a guest which = does + * not follow spec and missed PASID cache flush, e.g., linux + * 6.7.0-rc2, we have vtd_pasid_cache_devsi() to invalidate PA= SID + * cache of passthrough device. Host iommu driver would flush + * piotlb when a pasid unbind is passed down to it. + */ + vtd_pasid_cache_devsi(vtd_as); } } } diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 5a3ee1cf6418ba0713a716266e662ced2e3027f0..5fa5e93b68dcdeed823f99f07fb= 5d55810d3e3a5 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -28,6 +28,7 @@ vtd_pasid_cache_reset(void) "" vtd_inv_desc_pasid_cache_gsi(void) "" vtd_inv_desc_pasid_cache_dsi(uint16_t domain) "Domain selective PC invalid= ation domain 0x%"PRIx16 vtd_inv_desc_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID selec= tive PC invalidation domain 0x%"PRIx16" pasid 0x%"PRIx32 +vtd_pasid_cache_devsi(uint8_t bus, uint8_t dev, uint8_t fn) "Dev selective= PC invalidation dev: %02"PRIx8":%02"PRIx8".%02"PRIx8 vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present" vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8"= devfn %"PRIu8" not present" vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t d= omain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" d= omain 0x%"PRIx16 --=20 2.52.0