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Tsirkin" , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 15/41] intel_iommu_accel: Bind/unbind guest page table to host Date: Tue, 13 Jan 2026 10:36:11 +0100 Message-ID: <20260113093637.1549214-16-clg@redhat.com> In-Reply-To: <20260113093637.1549214-1-clg@redhat.com> References: <20260113093637.1549214-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1768297113734158500 From: Zhenzhong Duan This captures the guest PASID table entry modifications and propagates the changes to host to attach a hwpt with type determined per guest IOMMU PGTT configuration. When PGTT=3DPT, attach PASID_0 to a second stage HWPT(GPA->HPA). When PGTT=3DFST, attach PASID_0 to nested HWPT with nesting parent HWPT coming from VFIO. Co-Authored-by: Yi Liu Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Yi Liu Reviewed-by: Michael S. Tsirkin Link: https://lore.kernel.org/qemu-devel/20260106061304.314546-14-zhenzhong= .duan@intel.com Signed-off-by: C=C3=A9dric Le Goater --- hw/i386/intel_iommu_accel.h | 7 +++ include/hw/i386/intel_iommu.h | 2 + hw/i386/intel_iommu.c | 22 ++++++- hw/i386/intel_iommu_accel.c | 114 ++++++++++++++++++++++++++++++++++ hw/i386/trace-events | 3 + 5 files changed, 145 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index 9558148c517bd9c46e95e49c1884152f6c370799..30696765af61b8864b3577984c5= d9bcd774d4212 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -16,6 +16,7 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp); VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *as); +bool vtd_propagate_guest_pasid(VTDAddressSpace *vtd_as, Error **errp); #else static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, @@ -30,5 +31,11 @@ static inline VTDHostIOMMUDevice *vtd_find_hiod_iommufd(= VTDAddressSpace *as) { return NULL; } + +static inline bool vtd_propagate_guest_pasid(VTDAddressSpace *vtd_as, + Error **errp) +{ + return true; +} #endif #endif diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 401322665ac8e1a25330825b9e506d3942249c92..6c61fd39c7bb737afaca47ef792= 1ee96a9e6e473 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -154,6 +154,8 @@ struct VTDAddressSpace { * with the guest IOMMU pgtables for a device. */ IOVATree *iova_tree; + + uint32_t fs_hwpt_id; }; =20 struct VTDIOTLBEntry { diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 9edd625b1a5d246c311efd510df3967749690c29..f9b80e3257b4e382fd0eb9f946f= 6b6691a3d09ab 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -87,7 +87,11 @@ static void vtd_pasid_cache_reset_locked(IntelIOMMUState= *s) g_hash_table_iter_init(&as_it, s->vtd_address_spaces); while (g_hash_table_iter_next(&as_it, NULL, (void **)&vtd_as)) { VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; - pc_entry->valid =3D false; + if (pc_entry->valid) { + pc_entry->valid =3D false; + /* It's fatal to get failure during reset */ + vtd_propagate_guest_pasid(vtd_as, &error_fatal); + } } } =20 @@ -3073,6 +3077,8 @@ static void vtd_pasid_cache_sync_locked(gpointer key,= gpointer value, VTDPASIDEntry pe; IOMMUNotifier *n; uint16_t did; + const char *err_prefix =3D "Attaching to HWPT failed: "; + Error *local_err =3D NULL; =20 if (vtd_dev_get_pe_from_pasid(vtd_as, &pe)) { if (!pc_entry->valid) { @@ -3093,7 +3099,9 @@ static void vtd_pasid_cache_sync_locked(gpointer key,= gpointer value, vtd_address_space_unmap(vtd_as, n); } vtd_switch_address_space(vtd_as); - return; + + err_prefix =3D "Detaching from HWPT failed: "; + goto do_bind_unbind; } =20 /* @@ -3121,12 +3129,20 @@ static void vtd_pasid_cache_sync_locked(gpointer ke= y, gpointer value, if (!pc_entry->valid) { pc_entry->pasid_entry =3D pe; pc_entry->valid =3D true; - } else if (!vtd_pasid_entry_compare(&pe, &pc_entry->pasid_entry)) { + } else if (vtd_pasid_entry_compare(&pe, &pc_entry->pasid_entry)) { + err_prefix =3D "Replacing HWPT attachment failed: "; + } else { return; } =20 vtd_switch_address_space(vtd_as); vtd_address_space_sync(vtd_as); + +do_bind_unbind: + /* TODO: Fault event injection into guest, report error to QEMU for no= w */ + if (!vtd_propagate_guest_pasid(vtd_as, &local_err)) { + error_reportf_err(local_err, "%s", err_prefix); + } } =20 static void vtd_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc= _info) diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index acc9cad959ef2e00f5b2783ea3975a91493d0521..69f82e8831f5f834126b9aa1550= a6da8f2cc94c5 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -13,6 +13,7 @@ #include "intel_iommu_internal.h" #include "intel_iommu_accel.h" #include "hw/pci/pci_bus.h" +#include "trace.h" =20 bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp) @@ -68,3 +69,116 @@ VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpa= ce *as) } return NULL; } + +static bool vtd_create_fs_hwpt(HostIOMMUDeviceIOMMUFD *idev, + VTDPASIDEntry *pe, uint32_t *fs_hwpt_id, + Error **errp) +{ + struct iommu_hwpt_vtd_s1 vtd =3D {}; + + vtd.flags =3D (VTD_SM_PASID_ENTRY_SRE(pe) ? IOMMU_VTD_S1_SRE : 0) | + (VTD_SM_PASID_ENTRY_WPE(pe) ? IOMMU_VTD_S1_WPE : 0) | + (VTD_SM_PASID_ENTRY_EAFE(pe) ? IOMMU_VTD_S1_EAFE : 0); + vtd.addr_width =3D vtd_pe_get_fs_aw(pe); + vtd.pgtbl_addr =3D (uint64_t)vtd_pe_get_fspt_base(pe); + + return iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, idev->hw= pt_id, + 0, IOMMU_HWPT_DATA_VTD_S1, sizeof(vt= d), + &vtd, fs_hwpt_id, errp); +} + +static void vtd_destroy_old_fs_hwpt(HostIOMMUDeviceIOMMUFD *idev, + VTDAddressSpace *vtd_as) +{ + if (!vtd_as->fs_hwpt_id) { + return; + } + iommufd_backend_free_id(idev->iommufd, vtd_as->fs_hwpt_id); + vtd_as->fs_hwpt_id =3D 0; +} + +static bool vtd_device_attach_iommufd(VTDHostIOMMUDevice *vtd_hiod, + VTDAddressSpace *vtd_as, Error **err= p) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + VTDPASIDEntry *pe =3D &vtd_as->pasid_cache_entry.pasid_entry; + uint32_t hwpt_id =3D idev->hwpt_id; + bool ret; + + /* + * We can get here only if flts=3Don, the supported PGTT is FST or PT. + * Catch invalid PGTT when processing invalidation request to avoid + * attaching to wrong hwpt. + */ + if (!vtd_pe_pgtt_is_fst(pe) && !vtd_pe_pgtt_is_pt(pe)) { + error_setg(errp, "Invalid PGTT type %d", + (uint8_t)VTD_SM_PASID_ENTRY_PGTT(pe)); + return false; + } + + if (vtd_pe_pgtt_is_fst(pe)) { + if (!vtd_create_fs_hwpt(idev, pe, &hwpt_id, errp)) { + return false; + } + } + + ret =3D host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp); + trace_vtd_device_attach_hwpt(idev->devid, vtd_as->pasid, hwpt_id, ret); + if (ret) { + /* Destroy old fs_hwpt if it's a replacement */ + vtd_destroy_old_fs_hwpt(idev, vtd_as); + if (vtd_pe_pgtt_is_fst(pe)) { + vtd_as->fs_hwpt_id =3D hwpt_id; + } + } else if (vtd_pe_pgtt_is_fst(pe)) { + iommufd_backend_free_id(idev->iommufd, hwpt_id); + } + + return ret; +} + +static bool vtd_device_detach_iommufd(VTDHostIOMMUDevice *vtd_hiod, + VTDAddressSpace *vtd_as, Error **err= p) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + IntelIOMMUState *s =3D vtd_as->iommu_state; + uint32_t pasid =3D vtd_as->pasid; + bool ret; + + if (s->dmar_enabled && s->root_scalable) { + ret =3D host_iommu_device_iommufd_detach_hwpt(idev, errp); + trace_vtd_device_detach_hwpt(idev->devid, pasid, ret); + } else { + /* + * If DMAR remapping is disabled or guest switches to legacy mode, + * we fallback to the default HWPT which contains shadow page tabl= e. + * So guest DMA could still work. + */ + ret =3D host_iommu_device_iommufd_attach_hwpt(idev, idev->hwpt_id,= errp); + trace_vtd_device_reattach_def_hwpt(idev->devid, pasid, idev->hwpt_= id, + ret); + } + + if (ret) { + vtd_destroy_old_fs_hwpt(idev, vtd_as); + } + + return ret; +} + +bool vtd_propagate_guest_pasid(VTDAddressSpace *vtd_as, Error **errp) +{ + VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; + VTDHostIOMMUDevice *vtd_hiod =3D vtd_find_hiod_iommufd(vtd_as); + + /* Ignore emulated device or legacy VFIO backed device */ + if (!vtd_as->iommu_state->fsts || !vtd_hiod) { + return true; + } + + if (pc_entry->valid) { + return vtd_device_attach_iommufd(vtd_hiod, vtd_as, errp); + } + + return vtd_device_detach_iommufd(vtd_hiod, vtd_as, errp); +} diff --git a/hw/i386/trace-events b/hw/i386/trace-events index b704f4f90c3db8ac84fb49d98237b60800b792c7..5a3ee1cf6418ba0713a716266e6= 62ced2e3027f0 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -73,6 +73,9 @@ vtd_warn_invalid_qi_tail(uint16_t tail) "tail 0x%"PRIx16 vtd_warn_ir_vector(uint16_t sid, int index, int vec, int target) "sid 0x%"= PRIx16" index %d vec %d (should be: %d)" vtd_warn_ir_trigger(uint16_t sid, int index, int trig, int target) "sid 0x= %"PRIx16" index %d trigger %d (should be: %d)" vtd_reset_exit(void) "" +vtd_device_attach_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwpt_id, = int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" +vtd_device_detach_hwpt(uint32_t dev_id, uint32_t pasid, int ret) "dev_id %= d pasid %d ret: %d" +vtd_device_reattach_def_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwp= t_id, int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" =20 # amd_iommu.c amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at = addr 0x%"PRIx64" + offset 0x%"PRIx32 --=20 2.52.0