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Set it earlier in the AccelOpsClass::cpu_target_realize() handler instead, and assert the value is correct when reaching hvf_arch_init_vcpu(). Fixes: a1477da3dde ("hvf: Add Apple Silicon support") Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Akihiko Odaki --- target/arm/hvf/hvf.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index bf8bed1495d..e4c0d936f1f 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -897,6 +897,13 @@ cleanup: return ret; } =20 +static uint64_t get_cntfrq_el0(void) +{ + uint64_t freq_hz =3D 0; + asm volatile("mrs %0, cntfrq_el0" : "=3Dr"(freq_hz)); + return freq_hz; +} + int hvf_arch_init_vcpu(CPUState *cpu) { ARMCPU *arm_cpu =3D ARM_CPU(cpu); @@ -908,7 +915,9 @@ int hvf_arch_init_vcpu(CPUState *cpu) int i; =20 env->aarch64 =3D true; - asm volatile("mrs %0, cntfrq_el0" : "=3Dr"(arm_cpu->gt_cntfrq_hz)); + + /* system count frequency sanity check */ + assert(arm_cpu->gt_cntfrq_hz =3D=3D get_cntfrq_el0()); =20 /* Allocate enough space for our sysreg sync */ arm_cpu->cpreg_indexes =3D g_renew(uint64_t, arm_cpu->cpreg_indexes, @@ -974,6 +983,15 @@ int hvf_arch_init_vcpu(CPUState *cpu) =20 bool hvf_arch_cpu_realize(CPUState *cs, Error **errp) { + ARMCPU *cpu =3D ARM_CPU(cs); + + /* + * We must set the counter frequency HVF will be using + * early, before arm_cpu_realizefn initializes the timers + * with it. + */ + cpu->gt_cntfrq_hz =3D get_cntfrq_el0(); + return true; } =20 --=20 2.52.0