From nobody Mon Feb 9 19:37:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768220528; cv=none; d=zohomail.com; s=zohoarc; b=l5389Ot96p7imfSSP+wLDaiMZPnalir1Ii1wKerujSKLKS3yyiKDqf7Hiv915iTb8AzowlwtPlwA1lAHSXofM52iRDrwqld3VPf2llnwNxJQPZ+7ksGM9TgGr8tPfOpoePKACQtYeg406dl+5vML1HzOCcKBuL5cxxp3klvOCQc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768220528; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=YDrHHlS00KR9cgLAc08zrXeue6HMnDH9zKMdv1cxuvs=; b=O1bdiqSqAd7myobwalwk34btj20hTwc4vFBh6VQgAz70zcQFOub/hUy40rqN4TQKtX0sy2m876uYTxr91QsKFemP9a1/nMlgelRlGYVbGIWYQEjkFOdpze5QfvfsSPJDfzJTcWjV7WF1GwP0g7zoCed4160xlhRtki9tsphdR0g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768220528562854.1685642032328; Mon, 12 Jan 2026 04:22:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vfGuo-0000G1-GS; Mon, 12 Jan 2026 07:20:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vfGub-0008L9-DF for qemu-devel@nongnu.org; Mon, 12 Jan 2026 07:20:47 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vfGuO-0002jt-Hp for qemu-devel@nongnu.org; Mon, 12 Jan 2026 07:20:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=YDrHHlS00KR9cgLAc08zrXeue6HMnDH9zKMdv1cxuvs=; b=rJpjEtSO4P+ii6c oEGf6yvMgYCUJBLerREllAQLA/oDxeUTF1E7nWZuzjHHAwA3OdWvUi1/p+SMxvS+WHpSipTvXFkp6 /cICTHa/HadCXRVqPOp6PK4S7dK/dJoFL7qsFDOVLM7iEdQRjWUnXqHnauvvXYP/nVI3wCNF/uwXA h0=; Date: Mon, 12 Jan 2026 13:22:45 +0100 Subject: [PATCH v3 4/7] target/loongarch: Introduce loongarch_palen_mask() MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-phys_addr-v3-4-5f90fdb4015f@rev.ng> References: <20260112-phys_addr-v3-0-5f90fdb4015f@rev.ng> In-Reply-To: <20260112-phys_addr-v3-0-5f90fdb4015f@rev.ng> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Anton Johansson , palmer@dabbelt.com, alistair.francis@wdc.com, pbonzini@redhat.com, gaosong@loongson.cn, maobibo@loongson.cn Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_FILL_THIS_FORM_SHORT=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1768220529303158500 In preparation for dropping TARGET_PHYS_ADDR_SPACE_BITS, define a runtime function to construct a mask from the PALEN cpucfg field. The mask is then used when converting from virtual to physical addresses. Signed-off-by: Anton Johansson --- target/loongarch/cpu-mmu.h | 1 + target/loongarch/internals.h | 1 - target/loongarch/cpu_helper.c | 14 +++++++++++--- target/loongarch/tcg/tlb_helper.c | 12 ++++++++---- 4 files changed, 20 insertions(+), 8 deletions(-) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index 2259de9d36..3286accc14 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -98,5 +98,6 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *= context, void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, uint64_t *dir_width, unsigned int level); hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +uint64_t loongarch_palen_mask(CPULoongArchState *env); =20 #endif /* LOONGARCH_CPU_MMU_H */ diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index 8793bd9df6..e01dbed40f 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -13,7 +13,6 @@ #define FCMP_UN 0b0100 /* unordered */ #define FCMP_GT 0b1000 /* fp0 > fp1 */ =20 -#define TARGET_PHYS_MASK MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS) #define TARGET_VIRT_MASK MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS) =20 void loongarch_translate_init(void); diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index a6eba4f416..6497b454a6 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -147,6 +147,7 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext= *context, { CPUState *cs =3D env_cpu(env); target_ulong index =3D 0, phys =3D 0; + uint64_t palen_mask =3D loongarch_palen_mask(env); uint64_t dir_base, dir_width; uint64_t base, pte; int level; @@ -154,13 +155,14 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUConte= xt *context, TLBRet ret; MemTxResult ret1; =20 + address =3D context->addr; if ((address >> 63) & 0x1) { base =3D env->CSR_PGDH; } else { base =3D env->CSR_PGDL; } - base &=3D TARGET_PHYS_MASK; + base &=3D palen_mask; =20 for (level =3D 4; level >=3D 0; level--) { get_dir_base_width(env, &dir_base, &dir_width, level); @@ -181,7 +183,7 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext= *context, break; } else { /* Discard high bits with page directory table */ - base &=3D TARGET_PHYS_MASK; + base &=3D palen_mask; } } } @@ -315,7 +317,7 @@ TLBRet get_physical_address(CPULoongArchState *env, MMU= Context *context, /* Check PG and DA */ address =3D context->addr; if (da & !pg) { - context->physical =3D address & TARGET_PHYS_MASK; + context->physical =3D address & loongarch_palen_mask(env); context->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; context->mmu_index =3D MMU_DA_IDX; return TLBRET_MATCH; @@ -364,3 +366,9 @@ hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, = vaddr addr) } return context.physical; } + +uint64_t loongarch_palen_mask(CPULoongArchState *env) +{ + uint64_t phys_bits =3D FIELD_EX32(env->cpucfg[1], CPUCFG1, PALEN); + return MAKE_64BIT_MASK(0, phys_bits); +} diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 01e0a27f0b..30107f3e3f 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -691,8 +691,10 @@ target_ulong helper_lddir(CPULoongArchState *env, targ= et_ulong base, { CPUState *cs =3D env_cpu(env); target_ulong badvaddr, index, phys; + uint64_t palen_mask =3D loongarch_palen_mask(env); uint64_t dir_base, dir_width; =20 + if (unlikely((level =3D=3D 0) || (level > 4))) { qemu_log_mask(LOG_GUEST_ERROR, "Attepted LDDIR with level %u\n", level); @@ -714,11 +716,11 @@ target_ulong helper_lddir(CPULoongArchState *env, tar= get_ulong base, } =20 badvaddr =3D env->CSR_TLBRBADV; - base =3D base & TARGET_PHYS_MASK; + base =3D base & palen_mask; get_dir_base_width(env, &dir_base, &dir_width, level); index =3D (badvaddr >> dir_base) & ((1 << dir_width) - 1); phys =3D base | index << 3; - return ldq_phys(cs->as, phys) & TARGET_PHYS_MASK; + return ldq_phys(cs->as, phys) & palen_mask; } =20 void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong = odd, @@ -728,9 +730,11 @@ void helper_ldpte(CPULoongArchState *env, target_ulong= base, target_ulong odd, target_ulong phys, tmp0, ptindex, ptoffset0, ptoffset1, badv; uint64_t ptbase =3D FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTBASE); uint64_t ptwidth =3D FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTWIDTH); + uint64_t palen_mask =3D loongarch_palen_mask(env); uint64_t dir_base, dir_width; uint8_t ps; =20 + /* * The parameter "base" has only two types, * one is the page table base address, @@ -738,7 +742,7 @@ void helper_ldpte(CPULoongArchState *env, target_ulong = base, target_ulong odd, * and the other is the huge page entry, * whose bit 6 should be 1. */ - base =3D base & TARGET_PHYS_MASK; + base =3D base & palen_mask; if (FIELD_EX64(base, TLBENTRY, HUGE)) { /* * Gets the huge page level and Gets huge page size. @@ -779,7 +783,7 @@ void helper_ldpte(CPULoongArchState *env, target_ulong = base, target_ulong odd, ptoffset0 =3D ptindex << 3; ptoffset1 =3D (ptindex + 1) << 3; phys =3D base | (odd ? ptoffset1 : ptoffset0); - tmp0 =3D ldq_phys(cs->as, phys) & TARGET_PHYS_MASK; + tmp0 =3D ldq_phys(cs->as, phys) & palen_mask; ps =3D ptbase; } =20 --=20 2.51.0