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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1768220533553158500 In preparation for dropping TARGET_PHYS_ADDR_SPACE_BITS, add a a runtime function to correctly represent the size of the physical address space for EV4-6 based on the current CPU version. Reviewed-by: Richard Henderson Signed-off-by: Anton Johansson --- linux-user/alpha/target_proc.h | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/linux-user/alpha/target_proc.h b/linux-user/alpha/target_proc.h index da437ee0e5..6b491ffa3a 100644 --- a/linux-user/alpha/target_proc.h +++ b/linux-user/alpha/target_proc.h @@ -6,6 +6,27 @@ #ifndef ALPHA_TARGET_PROC_H #define ALPHA_TARGET_PROC_H =20 +#include "qemu/osdep.h" +#include "target/alpha/cpu.h" + +static uint8_t alpha_phys_addr_space_bits(CPUAlphaState *env) +{ + switch (env->implver) { + case IMPLVER_2106x: + /* EV4 */ + return 34; + case IMPLVER_21164: + /* EV5 */ + return 40; + case IMPLVER_21264: + case IMPLVER_21364: + /* EV6 and EV7*/ + return 44; + default: + g_assert_not_reached(); + } +} + static int open_cpuinfo(CPUArchState *cpu_env, int fd) { int max_cpus =3D sysconf(_SC_NPROCESSORS_CONF); @@ -57,7 +78,7 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd) "L1 Dcache\t\t: n/a\n" "L2 cache\t\t: n/a\n" "L3 cache\t\t: n/a\n", - model, TARGET_PAGE_SIZE, TARGET_PHYS_ADDR_SPACE_BITS, + model, TARGET_PAGE_SIZE, alpha_phys_addr_space_bits(cpu_env), max_cpus, num_cpus, cpu_mask); =20 return 0; --=20 2.51.0