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Tsirkin" Subject: [PATCH v7 34/36] hw/pci: Factor out common PASID capability initialization Date: Sun, 11 Jan 2026 19:53:20 +0000 Message-ID: <20260111195508.106943-35-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260111195508.106943-1-skolothumtho@nvidia.com> References: <20260111195508.106943-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4B:EE_|DS5PPF5A66AFD1C:EE_ X-MS-Office365-Filtering-Correlation-Id: d9db3d02-beee-466c-1937-08de514bd6ab X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|376014|7416014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?VNrwEqHVRtJgXK4XwQdPOFs8gHI9C6cCN6rie0hqn2ND+WrLJtdz9VyB0bNl?= =?us-ascii?Q?Xd+N83Cu3pfBWMsSxBvTx4Ca6Ea/vCmB7X6bc1DZjza0UinxBCXaWDR1RRcQ?= =?us-ascii?Q?EeAFg42EyFlRcc0dMI4GtGn0CIh6OyT3hOJ234pDIVeCLzAcoaOTZHexDwIQ?= =?us-ascii?Q?lmVHPsu+LpUq4otvcP9UoZ4SoU3fB6Q1cm39tFQZ91SPgW4Gir0F9XChmOuk?= =?us-ascii?Q?2Ojw/iDhRJDExth1p/d92FCUaYbl2pbC74Lv5nfohaf4++JMX9gfFWlfyozQ?= =?us-ascii?Q?wt1BqL1GDPLcVTgXXLp+ItnjUfAT6CTmHkjdd6KU+MH8/Yy12YniYFH5aqS+?= =?us-ascii?Q?/H0ShhCqcFTsw/q47z8/SG7rzRl4OqEzcYJiwnTNc6OR5/kaG9n+v6oNzdUk?= =?us-ascii?Q?MdfyH2gQstrJkK3J4TQCHZW9+ShxeSIqEmGmLkfKTFnBE6aCaXQDaocca8gP?= =?us-ascii?Q?UsgKs6Ae7EgDc2bpwlvrgvvlN80lLvNT4ThJEFrSovLlUI8cQ5ub9Ka7Bgfh?= =?us-ascii?Q?v4j6Q6ePLe6IiHBQUB4EzX84YLzFaNCWDKwFM7/j7pLggauXHp4kijuWqgoc?= =?us-ascii?Q?98H27K84UYnO9wT6r8qpHBIzFiiSjTb332gtLHnWR9ERtHZD1fUnSBiPXEA9?= =?us-ascii?Q?pRNKxTBjiVp48rvGovlKB3AMnX8kN5WvhTE0D5Mg09EC8QhHn56qEblUZ1pv?= =?us-ascii?Q?PkS8xQOLiKMZ4Al+KeYSP4zI57gg0Y3ySwCiOApYb+h3RorOqjCzW7HEGqK1?= =?us-ascii?Q?t/MPYQ0vnHroZUhXid2n/ic7oFRqczrt8Mt1Okcua1CtWTYzZtxRC8jDTtze?= =?us-ascii?Q?ZB4nxoIoGYfF8S1nvl6vnluUT/8jdXdu/gAD9bauslupIkTSPjzjAppDZh8j?= =?us-ascii?Q?4SoPG9QyTARV0bka5CMQOsS9apvYVA7GTeiWdyX+71wwblYa9Or3hNBZk+gp?= =?us-ascii?Q?Bhj4oGzY5tffCOi4/6E/xToIQGPxUOBgvhZvmEXPAjQ/DILgkRx9wZnP2Tq7?= =?us-ascii?Q?1tygSlYchLcKzcd9DkWH+MXW8zAoKS9R5juLdqrVoEw4HzHc8iDVVN50dgAK?= =?us-ascii?Q?g/a9AYvFh2kmU1KjIYqEQP6O/4NxNFcTlGJaGdYvRsWHD1Cw8BJMZJSBt95I?= =?us-ascii?Q?r/AN8Vo4BlkxECnxNBJLS/CdtFsvS0OxWRRr2aRSIXaBlDpzHY1yKaDC4mX9?= =?us-ascii?Q?byGOfxDJdT++w1Eb6y4Y+7QQhpJIge2HR+xztz4BjTHqbad8cMexnVxd/i4H?= =?us-ascii?Q?eTQUd5YUnKZrtdO+qdu5UtSUaa45Ix4tocj9xYFcdsQoXDR3vjT36cGKX/Eb?= =?us-ascii?Q?zPGcubZmpTUFagwXGyQ1qgpoBqCl9KaaYAaDJp6OoXx3Uma+3GWpF/Wlz4XS?= =?us-ascii?Q?OUSi9EFlo7eX05J4gQtGy7UG6vpioSectjz2Ia87wr1+vy3xpEn6zJhBw4Sv?= =?us-ascii?Q?erJ6UVRUPXudjOuUlW0mFb69Vfcf5pzqyOEsN2sOK6NhR8WRWT7ie1FmBZs3?= =?us-ascii?Q?109yWM2Aty62Ma8pAbZsDpYb1jqvgCvHm9Rm/Ip64rcZcAUy+5XtmeMk15TV?= =?us-ascii?Q?ihL4ODEz+u41BDxiSsE=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(376014)(7416014)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jan 2026 19:58:49.7603 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9db3d02-beee-466c-1937-08de514bd6ab X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPF5A66AFD1C Received-SPF: permerror client-ip=2a01:111:f403:c105::5; envelope-from=skolothumtho@nvidia.com; helo=CH5PR02CU005.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1768161713328158500 Content-Type: text/plain; charset="utf-8" Refactor PCIe PASID capability initialization by moving the common register init into a new helper, pcie_pasid_common_init(). Subsequent patch to synthesize a vPASID will make use of this helper. No functional change intended. Cc: Michael S. Tsirkin Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger Reviewed-by: Jonathan Cameron --- hw/pci/pcie.c | 19 ++++++++++++------- include/hw/pci/pcie.h | 2 ++ 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 8568a062a5..efd5588e96 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -1273,18 +1273,13 @@ void pcie_acs_reset(PCIDevice *dev) } } =20 -/* PASID */ -void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, - bool exec_perm, bool priv_mod) +void pcie_pasid_common_init(PCIDevice *dev, uint16_t offset, + uint8_t pasid_width, bool exec_perm, bool priv= _mod) { static const uint16_t control_reg_rw_mask =3D 0x07; uint16_t capability_reg; =20 assert(pasid_width <=3D PCI_EXT_CAP_PASID_MAX_WIDTH); - - pcie_add_capability(dev, PCI_EXT_CAP_ID_PASID, PCI_PASID_VER, offset, - PCI_EXT_CAP_PASID_SIZEOF); - capability_reg =3D ((uint16_t)pasid_width) << PCI_PASID_CAP_WIDTH_SHIF= T; capability_reg |=3D exec_perm ? PCI_PASID_CAP_EXEC : 0; capability_reg |=3D priv_mod ? PCI_PASID_CAP_PRIV : 0; @@ -1296,6 +1291,16 @@ void pcie_pasid_init(PCIDevice *dev, uint16_t offset= , uint8_t pasid_width, pci_set_word(dev->wmask + offset + PCI_PASID_CTRL, control_reg_rw_mask= ); =20 dev->exp.pasid_cap =3D offset; + +} + +/* PASID */ +void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, + bool exec_perm, bool priv_mod) +{ + pcie_add_capability(dev, PCI_EXT_CAP_ID_PASID, PCI_PASID_VER, offset, + PCI_EXT_CAP_PASID_SIZEOF); + pcie_pasid_common_init(dev, offset, pasid_width, exec_perm, priv_mod); } =20 /* PRI */ diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index d68bfa6257..fc02aeb169 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -155,6 +155,8 @@ void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_de= v, DeviceState *dev, void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp); =20 +void pcie_pasid_common_init(PCIDevice *dev, uint16_t offset, + uint8_t pasid_width, bool exec_perm, bool priv= _mod); void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, bool exec_perm, bool priv_mod); void pcie_pri_init(PCIDevice *dev, uint16_t offset, uint32_t outstanding_p= r_cap, --=20 2.43.0