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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(36860700013)(7416014)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jan 2026 19:58:27.2149 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f3e2f35-9a5d-40e5-8a2d-08de514bc93b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7798 Received-SPF: permerror client-ip=2a01:111:f403:c105::7; envelope-from=skolothumtho@nvidia.com; helo=CH4PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1768162058568158501 QEMU SMMUv3 does not enable ATS (Address Translation Services) by default. When accelerated mode is enabled and the host SMMUv3 supports ATS, it can be useful to report ATS capability to the guest so it can take advantage of it if the device also supports ATS. Note: ATS support cannot be reliably detected from the host SMMUv3 IDR registers alone, as firmware ACPI IORT tables may override them. The user must therefore ensure the support before enabling it. The ATS support enabled here is only relevant for vfio-pci endpoints, as SMMUv3 accelerated mode does not support emulated endpoint devices. QEMU=E2=80=99s SMMUv3 implementation still lacks support for handling ATS translation requests, which would be required for emulated endpoints. Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 3 +++ hw/arm/smmuv3.c | 24 +++++++++++++++++++++++- hw/arm/virt-acpi-build.c | 10 ++++++++-- include/hw/arm/smmuv3.h | 1 + 4 files changed, 35 insertions(+), 3 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index df82f1e32a..a97abc1f79 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -654,6 +654,9 @@ void smmuv3_accel_idr_override(SMMUv3State *s) =20 /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it= */ s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, s->ril); + + /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */ + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, s->ats); } =20 /* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index cb619f19df..ca086ba00a 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1498,13 +1498,27 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Erro= r **errp) */ smmuv3_range_inval(bs, &cmd, SMMU_STAGE_2); break; + case SMMU_CMD_ATC_INV: + { + SMMUDevice *sdev =3D smmu_find_sdev(bs, CMD_SID(&cmd)); + + if (!sdev || !s->ats) { + trace_smmuv3_unhandled_cmd(type); + break; + } + + if (!smmuv3_accel_issue_inv_cmd(s, &cmd, sdev, errp)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + break; + } case SMMU_CMD_TLBI_EL3_ALL: case SMMU_CMD_TLBI_EL3_VA: case SMMU_CMD_TLBI_EL2_ALL: case SMMU_CMD_TLBI_EL2_ASID: case SMMU_CMD_TLBI_EL2_VA: case SMMU_CMD_TLBI_EL2_VAA: - case SMMU_CMD_ATC_INV: case SMMU_CMD_PRI_RESP: case SMMU_CMD_RESUME: case SMMU_CMD_STALL_TERM: @@ -1931,6 +1945,10 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "ril can only be disabled if accel=3Don"); return false; } + if (s->ats) { + error_setg(errp, "ats can only be enabled if accel=3Don"); + return false; + } return true; } =20 @@ -2066,6 +2084,7 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), /* RIL can be turned off for accel cases */ DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), + DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2093,6 +2112,9 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "configured in nested mode for vfio-pci dev assignment"); object_class_property_set_description(klass, "ril", "Disable range invalidation support (for accel=3Don)"); + object_class_property_set_description(klass, "ats", + "Enable/disable ATS support (for accel=3Don). Please ensure host " + "platform has ATS support before enabling this"); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index bb408de43a..60d8fda755 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -346,6 +346,7 @@ typedef struct AcpiIortSMMUv3Dev { /* Offset of the SMMUv3 IORT Node relative to the start of the IORT */ size_t offset; bool accel; + bool ats; } AcpiIortSMMUv3Dev; =20 /* @@ -401,6 +402,7 @@ static int iort_smmuv3_devices(Object *obj, void *opaqu= e) =20 bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort); + sdev.ats =3D object_property_get_bool(obj, "ats", &error_abort); pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); sbdev =3D SYS_BUS_DEVICE(obj); sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); @@ -544,6 +546,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) int i, nb_nodes, rc_mapping_count; AcpiIortSMMUv3Dev *sdev; size_t node_size; + bool ats_needed =3D false; int num_smmus =3D 0; uint32_t id =3D 0; int rc_smmu_idmaps_len =3D 0; @@ -579,6 +582,9 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) /* Calculate RMR nodes required. One per SMMUv3 with accelerated m= ode */ for (i =3D 0; i < num_smmus; i++) { sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + if (sdev->ats) { + ats_needed =3D true; + } if (sdev->accel) { nb_nodes++; } @@ -678,8 +684,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, 0, 2); /* Reserved */ /* Table 15 Memory Access Flags */ build_append_int_noprefix(table_data, 0x3 /* CCA =3D CPM =3D DACS =3D = 1 */, 1); - - build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */ + /* ATS Attribute */ + build_append_int_noprefix(table_data, ats_needed, 4); /* MCFG pci_segment */ build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */ =20 diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 533a2182e8..242d6429ed 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -70,6 +70,7 @@ struct SMMUv3State { uint64_t msi_gpa; Error *migration_blocker; bool ril; + bool ats; }; =20 typedef enum { --=20 2.43.0