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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH v7 16/36] hw/arm/smmuv3-accel: Implement get_msi_direct_gpa callback Date: Sun, 11 Jan 2026 19:53:02 +0000 Message-ID: <20260111195508.106943-17-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260111195508.106943-1-skolothumtho@nvidia.com> References: <20260111195508.106943-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA51:EE_|PH0PR12MB5606:EE_ X-MS-Office365-Filtering-Correlation-Id: 7acafe0f-e8cd-4626-3807-08de514ba0d6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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charset="utf-8" Accelerated SMMUv3 instances rely on the physical SMMUv3 for nested translation (guest Stage-1, host Stage-2). In this mode, the guest Stage-1 tables are programmed directly into hardware, and QEMU must not attempt to walk them for translation, as doing so is not reliably safe. For vfio-pci endpoints behind such a vSMMU, the only translation QEMU needs to perform is for the MSI doorbell used during KVM MSI setup. Implement the callback so that kvm_arch_fixup_msi_route() can retrieve the MSI doorbell GPA directly, instead of attempting a software walk of the guest translation tables. Also introduce an SMMUv3 device property to carry the MSI doorbell GPA. This property will be set by the virt machine in a subsequent patch. Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger --- hw/arm/smmuv3-accel.c | 10 ++++++++++ hw/arm/smmuv3.c | 2 ++ include/hw/arm/smmuv3.h | 1 + 3 files changed, 13 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index c125974d12..c6ee123cdf 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -393,6 +393,15 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bu= s, void *opaque, } } =20 +static uint64_t smmuv3_accel_get_msi_gpa(PCIBus *bus, void *opaque, int de= vfn) +{ + SMMUState *bs =3D opaque; + SMMUv3State *s =3D ARM_SMMUV3(bs); + + g_assert(s->msi_gpa); + return s->msi_gpa; +} + /* * Only allow PCIe bridges, pxb-pcie roots, and GPEX roots so vfio-pci * endpoints can sit downstream. Accelerated SMMUv3 requires a vfio-pci @@ -497,6 +506,7 @@ static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_viommu_flags =3D smmuv3_accel_get_viommu_flags, .set_iommu_device =3D smmuv3_accel_set_iommu_device, .unset_iommu_device =3D smmuv3_accel_unset_iommu_device, + .get_msi_direct_gpa =3D smmuv3_accel_get_msi_gpa, }; =20 /* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 7a32afd800..6ed9914b1e 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1998,6 +1998,8 @@ static const Property smmuv3_properties[] =3D { * Defaults to stage 1 */ DEFINE_PROP_STRING("stage", SMMUv3State, stage), + /* GPA of MSI doorbell, for SMMUv3 accel use. */ + DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), }; =20 static void smmuv3_instance_init(Object *obj) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index e54ece2d38..5616a8a2be 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -67,6 +67,7 @@ struct SMMUv3State { /* SMMU has HW accelerator support for nested S1 + s2 */ bool accel; struct SMMUv3AccelState *s_accel; + uint64_t msi_gpa; }; =20 typedef enum { --=20 2.43.0