From nobody Mon Feb 9 04:45:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1767969987; cv=none; d=zohomail.com; s=zohoarc; b=LGu+VXXdsg+IxmF3EEJWbTD59pvtc7uvBaTKyunz9RK6t8LJWXqaZZH14vtMNcE7KiNF71PU0EZpjKaaF+1i9+SGSpAgfGb1Q9Ujh+v57WusfrW2ioxr0GtQNefi10TaP0Vb6JRDtKUOHfQ+hiSmydr+qbvZF/kb8PK6ni6CQJA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767969987; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=AEd+NBb7RujHEtuucC3WwqG1hwpQUDCv9maQrb3V5CI=; b=QHCtlH9mI2XPKmMb8DDUC6bQ55iiNRMzxS902xiSHqij9fSrLyhpAQpGEDxYWT9jgu+sl6Svr0wa6HOppIFSH+uFUzEeEw4BpmL+wIPFI9L9XOpxszjlr7GYtlsrycCDKi10/Yu+U6QaPnTIrbaII4yccgUGtEwX0FjRlRgXxqU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767969987360235.17667998472314; Fri, 9 Jan 2026 06:46:27 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1veDkL-0004GL-Bo; Fri, 09 Jan 2026 09:45:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1veDkK-0004G2-6O for qemu-devel@nongnu.org; Fri, 09 Jan 2026 09:45:48 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1veDkH-0000xm-TM for qemu-devel@nongnu.org; Fri, 09 Jan 2026 09:45:47 -0500 Received: from mail.maildlp.com (unknown [172.18.224.150]) by frasgout.his.huawei.com (SkyGuard) with ESMTPS id 4dnl1n6zMGzHnGkc; Fri, 9 Jan 2026 22:45:33 +0800 (CST) Received: from dubpeml100005.china.huawei.com (unknown [7.214.146.113]) by mail.maildlp.com (Postfix) with ESMTPS id 3C69C40539; Fri, 9 Jan 2026 22:45:44 +0800 (CST) Received: from SecurePC-101-06.huawei.com (10.122.19.247) by dubpeml100005.china.huawei.com (7.214.146.113) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.36; Fri, 9 Jan 2026 14:45:43 +0000 To: Michael Tsirkin , , Davidlohr Bueso CC: , , Ravi Shankar , Marcel Apfelbaum , Markus Armbruster , Michael Roth Subject: [PATCH qemu v5 1/7] hw/pcie: Support enabling flit mode Date: Fri, 9 Jan 2026 14:45:05 +0000 Message-ID: <20260109144511.557781-2-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20260109144511.557781-1-Jonathan.Cameron@huawei.com> References: <20260109144511.557781-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.19.247] X-ClientProxiedBy: lhrpeml100010.china.huawei.com (7.191.174.197) To dubpeml100005.china.huawei.com (7.214.146.113) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1767969988546158500 Content-Type: text/plain; charset="utf-8" From: Davidlohr Bueso PCIe Flit Mode, introduced with the PCIe 6.0 specification, is a fundamental change in how data is transmitted over the bus to improve transfer rates. It shifts from variable-sized Transaction Layer Packets (TLPs) to fixed 256-byte Flow Control Units (FLITs). As with the link speed and width training, have ad-hoc property for setting the flit mode and allow CXL components to make use of it. For the CXL root port and dsp cases, always report flit mode but the actual value after 'training' will depend on the downstream device configuration. Suggested-by: Jonathan Cameron Tested-by: Dongjoo Seo Signed-off-by: Davidlohr Bueso Signed-off-by: Jonathan Cameron --- v5: (Jonathan) Dropped the gen_pcie_root_port.c support as not needed for this series which is otherwise all about CXL. --- include/hw/cxl/cxl_device.h | 1 + include/hw/pci-bridge/cxl_upstream_port.h | 1 + include/hw/pci/pcie.h | 2 +- include/hw/pci/pcie_port.h | 1 + hw/mem/cxl_type3.c | 6 ++++-- hw/pci-bridge/cxl_downstream.c | 8 +++++--- hw/pci-bridge/cxl_root_port.c | 8 +++++--- hw/pci-bridge/cxl_upstream.c | 16 +++++++++------- hw/pci/pcie.c | 23 +++++++++++++++++++---- 9 files changed, 46 insertions(+), 20 deletions(-) diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 165355baf9da..d2440b0f0f6b 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -598,6 +598,7 @@ struct CXLType3Dev { /* PCIe link characteristics */ PCIExpLinkSpeed speed; PCIExpLinkWidth width; + bool flitmode; =20 /* DOE */ DOECap doe_cdat; diff --git a/include/hw/pci-bridge/cxl_upstream_port.h b/include/hw/pci-bri= dge/cxl_upstream_port.h index f208397ffe96..e3d6a27acc86 100644 --- a/include/hw/pci-bridge/cxl_upstream_port.h +++ b/include/hw/pci-bridge/cxl_upstream_port.h @@ -15,6 +15,7 @@ typedef struct CXLUpstreamPort { =20 PCIExpLinkSpeed speed; PCIExpLinkWidth width; + bool flitmode; =20 DOECap doe_cdat; uint64_t sn; diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index c880ae1e04b2..79808126dc18 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -142,7 +142,7 @@ void pcie_ari_init(PCIDevice *dev, uint16_t offset); void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_n= um); void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned); void pcie_cap_fill_link_ep_usp(PCIDevice *dev, PCIExpLinkWidth width, - PCIExpLinkSpeed speed); + PCIExpLinkSpeed speed, bool flitmode); =20 void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *d= ev, Error **errp); diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 7cd7af8cfa4b..53cd64c5edff 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -58,6 +58,7 @@ struct PCIESlot { =20 PCIExpLinkSpeed speed; PCIExpLinkWidth width; + bool flitmode; =20 /* Disable ACS (really for a pcie_root_port) */ bool disable_acs; diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 6eb20137a04f..f6907fb0c3aa 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -405,7 +405,7 @@ static void build_dvsecs(CXLType3Dev *ct3d) dvsec =3D (uint8_t *)&(CXLDVSECPortFlexBus){ .cap =3D 0x26, /* 68B, IO, Mem, non-MLD */ .ctrl =3D 0x02, /* IO always enabled */ - .status =3D 0x26, /* same as capabilities */ + .status =3D ct3d->flitmode ? 0x6 : 0x26, /* lack = of 68B */ .rcvd_mod_ts_data_phase1 =3D 0xef, /* WTF? */ }; cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE, @@ -1245,7 +1245,8 @@ static void ct3d_reset(DeviceState *dev) uint32_t *reg_state =3D ct3d->cxl_cstate.crb.cache_mem_registers; uint32_t *write_msk =3D ct3d->cxl_cstate.crb.cache_mem_regs_write_mask; =20 - pcie_cap_fill_link_ep_usp(PCI_DEVICE(dev), ct3d->width, ct3d->speed); + pcie_cap_fill_link_ep_usp(PCI_DEVICE(dev), ct3d->width, ct3d->speed, + ct3d->flitmode); cxl_component_register_init_common(reg_state, write_msk, CXL2_TYPE3_DE= VICE); cxl_device_register_init_t3(ct3d, CXL_T3_MSIX_MBOX); =20 @@ -1284,6 +1285,7 @@ static const Property ct3_props[] =3D { speed, PCIE_LINK_SPEED_32), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", CXLType3Dev, width, PCIE_LINK_WIDTH_16), + DEFINE_PROP_BOOL("x-256b-flit", CXLType3Dev, flitmode, false), }; =20 static uint64_t get_lsa_size(CXLType3Dev *ct3d) diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index f7b131e67e8e..64086d8ec2f2 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -94,8 +94,9 @@ static void cxl_dsp_reset(DeviceState *qdev) latch_registers(dsp); } =20 -static void build_dvsecs(CXLComponentState *cxl) +static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) { + PCIESlot *s =3D PCIE_SLOT(d); uint8_t *dvsec; =20 dvsec =3D (uint8_t *)&(CXLDVSECPortExt){ 0 }; @@ -107,7 +108,7 @@ static void build_dvsecs(CXLComponentState *cxl) dvsec =3D (uint8_t *)&(CXLDVSECPortFlexBus){ .cap =3D 0x27, /* Cache, IO, Mem, non-MLD */ .ctrl =3D 0x02, /* IO always enabled */ - .status =3D 0x26, /* same */ + .status =3D s->flitmode ? 0x6 : 0x26, /* lack of = 68B */ .rcvd_mod_ts_data_phase1 =3D 0xef, /* WTF? */ }; cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT, @@ -182,7 +183,7 @@ static void cxl_dsp_realize(PCIDevice *d, Error **errp) =20 cxl_cstate->dvsec_offset =3D CXL_DOWNSTREAM_PORT_DVSEC_OFFSET; cxl_cstate->pdev =3D d; - build_dvsecs(cxl_cstate); + build_dvsecs(d, cxl_cstate); cxl_component_register_block_init(OBJECT(d), cxl_cstate, TYPE_CXL_DSP); pci_register_bar(d, CXL_COMPONENT_REG_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY | @@ -217,6 +218,7 @@ static const Property cxl_dsp_props[] =3D { speed, PCIE_LINK_SPEED_64), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_16), + DEFINE_PROP_BOOL("x-256b-flit", PCIESlot, flitmode, true), }; =20 static void cxl_dsp_class_init(ObjectClass *oc, const void *data) diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 197d3148d201..5641048084a4 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -104,8 +104,9 @@ static void latch_registers(CXLRootPort *crp) cxl_component_register_init_common(reg_state, write_msk, CXL2_ROOT_POR= T); } =20 -static void build_dvsecs(CXLComponentState *cxl) +static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) { + PCIESlot *s =3D PCIE_SLOT(d); uint8_t *dvsec; =20 dvsec =3D (uint8_t *)&(CXLDVSECPortExt){ 0 }; @@ -126,7 +127,7 @@ static void build_dvsecs(CXLComponentState *cxl) dvsec =3D (uint8_t *)&(CXLDVSECPortFlexBus){ .cap =3D 0x26, /* IO, Mem, non-MLD */ .ctrl =3D 0x2, - .status =3D 0x26, /* same */ + .status =3D s->flitmode ? 0x6 : 0x26, /* lack of = 68B */ .rcvd_mod_ts_data_phase1 =3D 0xef, }; cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT, @@ -176,7 +177,7 @@ static void cxl_rp_realize(DeviceState *dev, Error **er= rp) =20 cxl_cstate->dvsec_offset =3D CXL_ROOT_PORT_DVSEC_OFFSET; cxl_cstate->pdev =3D pci_dev; - build_dvsecs(cxl_cstate); + build_dvsecs(pci_dev, cxl_cstate); =20 cxl_component_register_block_init(OBJECT(pci_dev), cxl_cstate, TYPE_CXL_ROOT_PORT); @@ -211,6 +212,7 @@ static const Property gen_rp_props[] =3D { speed, PCIE_LINK_SPEED_64), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_32), + DEFINE_PROP_BOOL("x-256b-flit", PCIESlot, flitmode, true), }; =20 static void cxl_rp_dvsec_write_config(PCIDevice *dev, uint32_t addr, diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index 6d708fadc253..c352d11dc7b7 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -101,28 +101,29 @@ static void cxl_usp_reset(DeviceState *qdev) =20 pci_bridge_reset(qdev); pcie_cap_deverr_reset(d); - pcie_cap_fill_link_ep_usp(d, usp->width, usp->speed); + pcie_cap_fill_link_ep_usp(d, usp->width, usp->speed, usp->flitmode); latch_registers(usp); } =20 -static void build_dvsecs(CXLComponentState *cxl) +static void build_dvsecs(CXLUpstreamPort *usp) { + CXLComponentState *cxl_cstate =3D &usp->cxl_cstate; uint8_t *dvsec; =20 dvsec =3D (uint8_t *)&(CXLDVSECPortExt){ .status =3D 0x1, /* Port Power Management Init Complete */ }; - cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT, + cxl_component_create_dvsec(cxl_cstate, CXL2_UPSTREAM_PORT, EXTENSIONS_PORT_DVSEC_LENGTH, EXTENSIONS_PORT_DVSEC, EXTENSIONS_PORT_DVSEC_REVID, dvsec); dvsec =3D (uint8_t *)&(CXLDVSECPortFlexBus){ .cap =3D 0x27, /* Cache, IO, Mem, non-MLD */ .ctrl =3D 0x27, /* Cache, IO, Mem */ - .status =3D 0x26, /* same */ + .status =3D usp->flitmode ? 0x6 : 0x26, /* lack o= f 68B */ .rcvd_mod_ts_data_phase1 =3D 0xef, /* WTF? */ }; - cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT, + cxl_component_create_dvsec(cxl_cstate, CXL2_UPSTREAM_PORT, PCIE_CXL3_FLEXBUS_PORT_DVSEC_LENGTH, PCIE_FLEXBUS_PORT_DVSEC, PCIE_CXL3_FLEXBUS_PORT_DVSEC_REVID, dvsec); @@ -132,7 +133,7 @@ static void build_dvsecs(CXLComponentState *cxl) .reg0_base_lo =3D RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX, .reg0_base_hi =3D 0, }; - cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT, + cxl_component_create_dvsec(cxl_cstate, CXL2_UPSTREAM_PORT, REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC, REG_LOC_DVSEC_REVID, dvsec); } @@ -327,7 +328,7 @@ static void cxl_usp_realize(PCIDevice *d, Error **errp) } cxl_cstate->dvsec_offset =3D CXL_UPSTREAM_PORT_DVSEC_OFFSET; cxl_cstate->pdev =3D d; - build_dvsecs(cxl_cstate); + build_dvsecs(usp); cxl_component_register_block_init(OBJECT(d), cxl_cstate, TYPE_CXL_USP); pci_register_bar(d, CXL_COMPONENT_REG_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY | @@ -369,6 +370,7 @@ static const Property cxl_upstream_props[] =3D { speed, PCIE_LINK_SPEED_32), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", CXLUpstreamPort, width, PCIE_LINK_WIDTH_16), + DEFINE_PROP_BOOL("x-256b-flit", CXLUpstreamPort, flitmode, false), }; =20 static void cxl_upstream_class_init(ObjectClass *oc, const void *data) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index b302de64191b..1de0b1e4fd08 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -113,7 +113,7 @@ pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t = type, uint8_t version) =20 /* Includes setting the target speed default */ static void pcie_cap_fill_lnk(uint8_t *exp_cap, PCIExpLinkWidth width, - PCIExpLinkSpeed speed) + PCIExpLinkSpeed speed, bool flitmode) { /* Clear and fill LNKCAP from what was configured above */ pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP, @@ -158,10 +158,15 @@ static void pcie_cap_fill_lnk(uint8_t *exp_cap, PCIEx= pLinkWidth width, PCI_EXP_LNKCAP2_SLS_64_0GB); } } + + if (flitmode) { + pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA2, + PCI_EXP_LNKSTA2_FLIT); + } } =20 void pcie_cap_fill_link_ep_usp(PCIDevice *dev, PCIExpLinkWidth width, - PCIExpLinkSpeed speed) + PCIExpLinkSpeed speed, bool flitmode) { uint8_t *exp_cap =3D dev->config + dev->exp.exp_cap; =20 @@ -175,7 +180,7 @@ void pcie_cap_fill_link_ep_usp(PCIDevice *dev, PCIExpLi= nkWidth width, QEMU_PCI_EXP_LNKSTA_NLW(width) | QEMU_PCI_EXP_LNKSTA_CLS(speed)); =20 - pcie_cap_fill_lnk(exp_cap, width, speed); + pcie_cap_fill_lnk(exp_cap, width, speed, flitmode); } =20 static void pcie_cap_fill_slot_lnk(PCIDevice *dev) @@ -212,7 +217,7 @@ static void pcie_cap_fill_slot_lnk(PCIDevice *dev) /* the PCI_EXP_LNKSTA_DLLLA will be set in the hotplug function */ } =20 - pcie_cap_fill_lnk(exp_cap, s->width, s->speed); + pcie_cap_fill_lnk(exp_cap, s->width, s->speed, s->flitmode); } =20 int pcie_cap_init(PCIDevice *dev, uint8_t offset, @@ -1106,6 +1111,8 @@ void pcie_sync_bridge_lnk(PCIDevice *bridge_dev) if (!target || !target->exp.exp_cap) { lnksta =3D lnkcap; } else { + uint16_t lnksta2; + lnksta =3D target->config_read(target, target->exp.exp_cap + PCI_EXP_LNKSTA, sizeof(lnksta)); @@ -1119,6 +1126,14 @@ void pcie_sync_bridge_lnk(PCIDevice *bridge_dev) lnksta &=3D ~PCI_EXP_LNKSTA_CLS; lnksta |=3D lnkcap & PCI_EXP_LNKCAP_SLS; } + + lnksta2 =3D target->config_read(target, + target->exp.exp_cap + PCI_EXP_LNKSTA= 2, + sizeof(lnksta2)); + pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA2, + PCI_EXP_LNKSTA2_FLIT); + pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA2, + lnksta2 & PCI_EXP_LNKSTA2_FLIT); } =20 if (!(lnksta & PCI_EXP_LNKSTA_NLW)) { --=20 2.48.1 From nobody Mon Feb 9 04:45:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1767969989; cv=none; d=zohomail.com; s=zohoarc; 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Fri, 9 Jan 2026 14:46:14 +0000 To: Michael Tsirkin , , Davidlohr Bueso CC: , , Ravi Shankar , Marcel Apfelbaum , Markus Armbruster , Michael Roth Subject: [PATCH qemu v5 2/7] hw/cxl: Refactor component register initialization Date: Fri, 9 Jan 2026 14:45:06 +0000 Message-ID: <20260109144511.557781-3-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20260109144511.557781-1-Jonathan.Cameron@huawei.com> References: <20260109144511.557781-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.19.247] X-ClientProxiedBy: lhrpeml100010.china.huawei.com (7.191.174.197) To dubpeml100005.china.huawei.com (7.214.146.113) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1767969990430158500 Content-Type: text/plain; charset="utf-8" From: Ira Weiny CXL 3.2 8.2.4 Table 8-22 defines which capabilities are mandatory, not permitted, or optional for each type of device. cxl_component_register_init_common() uses a rather odd 'fall through' mechanism to define each component register set. This assumes that any device or capability being added builds on the previous devices capabilities. This is not true as there are mutually exclusive capabilities defined. For example, downstream ports can not have snoop but it can have Back Invalidate capable decoders. Refactor this code to make it easier to add individual capabilities as defined by a device type. Any capability which is not specified by the type is left NULL'ed out which complies with the packed nature of the register array. Update all spec references to 3.2. No functional changes should be seen with this patch. Signed-off-by: Ira Weiny Tested-by: Dongjoo Seo [rebased, no RAS for HBs, r3.2 references] Signed-off-by: Davidlohr Bueso Signed-off-by: Jonathan Cameron --- include/hw/cxl/cxl_component.h | 33 ++++++++++----- hw/cxl/cxl-component-utils.c | 75 +++++++++++----------------------- 2 files changed, 46 insertions(+), 62 deletions(-) diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h index b0f2aa791431..1f167d3ef79b 100644 --- a/include/hw/cxl/cxl_component.h +++ b/include/hw/cxl/cxl_component.h @@ -32,10 +32,20 @@ enum reg_type { }; =20 /* - * Capability registers are defined at the top of the CXL.cache/mem region= and - * are packed. For our purposes we will always define the caps in the same - * order. - * CXL r3.1 Table 8-22: CXL_CAPABILITY_ID Assignment for details. + * CXL r3.2 - 8.2.4 Table 8-22 and 8-23 + * + * Capability registers are defined at the top of the CXL.cache/mem region. + * They are defined to be packed and at variable offsets. However, NULL + * capabilities can be added to the packed array. To facilitate easier ac= cess + * within the QEMU code, define these at specified offsets. Then NULL out= any + * capabilities for devices which don't (or can't) have a particular capab= ility + * (see cxl_component_register_init_common). NULL capabilities are to be + * ignored by software. + * + * 'offsets' are based on index's which can then be used to report the arr= ay + * size in CXL Capability Header Register (index/offset 0). + * + * See CXL r3.2 Table 8-25 for an example of allowing a 'NULL' header. */ =20 /* CXL r3.1 Section 8.2.4.1: CXL Capability Header Register */ @@ -46,16 +56,17 @@ REG32(CXL_CAPABILITY_HEADER, 0) FIELD(CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 20, 4) FIELD(CXL_CAPABILITY_HEADER, ARRAY_SIZE, 24, 8) =20 -#define CXLx_CAPABILITY_HEADER(type, offset) \ - REG32(CXL_##type##_CAPABILITY_HEADER, offset) \ +#define CXLx_CAPABILITY_HEADER(type, idx) \ + enum { CXL_##type##_CAP_HDR_IDX =3D idx }; \ + REG32(CXL_##type##_CAPABILITY_HEADER, (idx * 0x4)) \ FIELD(CXL_##type##_CAPABILITY_HEADER, ID, 0, 16) \ FIELD(CXL_##type##_CAPABILITY_HEADER, VERSION, 16, 4) \ FIELD(CXL_##type##_CAPABILITY_HEADER, PTR, 20, 12) -CXLx_CAPABILITY_HEADER(RAS, 0x4) -CXLx_CAPABILITY_HEADER(LINK, 0x8) -CXLx_CAPABILITY_HEADER(HDM, 0xc) -CXLx_CAPABILITY_HEADER(EXTSEC, 0x10) -CXLx_CAPABILITY_HEADER(SNOOP, 0x14) +CXLx_CAPABILITY_HEADER(RAS, 1) +CXLx_CAPABILITY_HEADER(LINK, 2) +CXLx_CAPABILITY_HEADER(HDM, 3) +CXLx_CAPABILITY_HEADER(EXTSEC, 4) +CXLx_CAPABILITY_HEADER(SNOOP, 5) =20 /* * Capability structures contain the actual registers that the CXL compone= nt diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index 473895948b3d..91770f103a85 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -284,32 +284,6 @@ void cxl_component_register_init_common(uint32_t *reg_= state, { int caps =3D 0; =20 - /* - * In CXL 2.0 the capabilities required for each CXL component are such - * that, with the ordering chosen here, a single number can be used to - * define which capabilities should be provided. - */ - switch (type) { - case CXL2_DOWNSTREAM_PORT: - case CXL2_DEVICE: - /* RAS, Link */ - caps =3D 2; - break; - case CXL2_UPSTREAM_PORT: - case CXL2_TYPE3_DEVICE: - case CXL2_LOGICAL_DEVICE: - /* + HDM */ - caps =3D 3; - break; - case CXL2_ROOT_PORT: - case CXL2_RC: - /* + Extended Security, + Snoop */ - caps =3D 5; - break; - default: - abort(); - } - memset(reg_state, 0, CXL2_COMPONENT_CM_REGION_SIZE); =20 /* CXL Capability Header Register */ @@ -317,11 +291,12 @@ void cxl_component_register_init_common(uint32_t *reg= _state, ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, VERSION, CXL_CAPABILITY_VERSION); ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, = 1); - ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ARRAY_SIZE, caps); =20 #define init_cap_reg(reg, id, version) = \ do { = \ - int which =3D R_CXL_##reg##_CAPABILITY_HEADER; = \ + int which =3D CXL_##reg##_CAP_HDR_IDX; = \ + if (CXL_##reg##_CAP_HDR_IDX > caps) = \ + caps =3D CXL_##reg##_CAP_HDR_IDX; = \ reg_state[which] =3D FIELD_DP32(reg_state[which], = \ CXL_##reg##_CAPABILITY_HEADER, ID, i= d); \ reg_state[which] =3D = \ @@ -332,37 +307,35 @@ void cxl_component_register_init_common(uint32_t *reg= _state, CXL_##reg##_REGISTERS_OFFSET); = \ } while (0) =20 + /* CXL r3.2 8.2.4 Table 8-22 */ switch (type) { - case CXL2_DEVICE: - case CXL2_TYPE3_DEVICE: - case CXL2_LOGICAL_DEVICE: case CXL2_ROOT_PORT: + case CXL2_RC: + /* + Extended Security, + Snoop */ + init_cap_reg(EXTSEC, 6, 1); + init_cap_reg(SNOOP, 8, 1); + /* fallthrough */ case CXL2_UPSTREAM_PORT: + case CXL2_TYPE3_DEVICE: + case CXL2_LOGICAL_DEVICE: + /* + HDM */ + init_cap_reg(HDM, 5, 1); + hdm_init_common(reg_state, write_msk, type); + /* fallthrough */ case CXL2_DOWNSTREAM_PORT: - init_cap_reg(RAS, 2, CXL_RAS_CAPABILITY_VERSION); - ras_init_common(reg_state, write_msk); + case CXL2_DEVICE: + /* RAS, Link */ + if (type !=3D CXL2_RC) { + init_cap_reg(RAS, 2, 2); + ras_init_common(reg_state, write_msk); + } + init_cap_reg(LINK, 4, 2); break; default: - break; - } - - init_cap_reg(LINK, 4, CXL_LINK_CAPABILITY_VERSION); - - if (caps < 3) { - return; - } - - if (type !=3D CXL2_ROOT_PORT) { - init_cap_reg(HDM, 5, CXL_HDM_CAPABILITY_VERSION); - hdm_init_common(reg_state, write_msk, type); - } - if (caps < 5) { - return; + abort(); } =20 - init_cap_reg(EXTSEC, 6, CXL_EXTSEC_CAP_VERSION); - init_cap_reg(SNOOP, 8, CXL_SNOOP_CAP_VERSION); - + ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ARRAY_SIZE, caps); #undef init_cap_reg } =20 --=20 2.48.1 From nobody Mon Feb 9 04:45:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1767970013; cv=none; d=zohomail.com; s=zohoarc; b=SFV81dhSMVPcljZoGcUn07XQjR+TYYu8asgUhMgcfK24hYSfZE8WvR1vWdxJItz/vlYuPbmM0+SK97+RZVOGIPdyQ/UTBv4PEs/VPseDW1e2pGsjNaQwiKuqZyy+95rDFeU9b8WK2xwhk+i4YAF8bqZTJnsvmuLwGvRiIafaX+w= ARC-Message-Signature: i=1; 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Fri, 9 Jan 2026 14:46:45 +0000 To: Michael Tsirkin , , Davidlohr Bueso CC: , , Ravi Shankar , Marcel Apfelbaum , Markus Armbruster , Michael Roth Subject: [PATCH qemu v5 3/7] tests/bios-tables-test: Excluded CEDT.cxl for BI restriction relaxation. Date: Fri, 9 Jan 2026 14:45:07 +0000 Message-ID: <20260109144511.557781-4-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20260109144511.557781-1-Jonathan.Cameron@huawei.com> References: <20260109144511.557781-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.19.247] X-ClientProxiedBy: lhrpeml100010.china.huawei.com (7.191.174.197) To dubpeml100005.china.huawei.com (7.214.146.113) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1767970014329158500 Content-Type: text/plain; charset="utf-8" The next patch will relax restrictions on the fixed memory window to allow use with back invalidate capable devices. Signed-off-by: Jonathan Cameron --- v5: New patch as test data update was previously missing. --- tests/qtest/bios-tables-test-allowed-diff.h | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8bf4..b4646b5b3147 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,2 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/x86/q35/CEDT.cxl", --=20 2.48.1 From nobody Mon Feb 9 04:45:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1767970089; cv=none; d=zohomail.com; s=zohoarc; b=YpfGkDUzDIdL7eJMOXFWmES1Sp2eAmiPUYwKt1EnawRXP4RwxGOGsB+8h6pF4qN0dLHHib9ENclR4+rUfgxjOe8TTrbRH5GjZCBb4A+im/2H2mtLEEfxXQ6ILpejJYv9O2NS8M3kwOykjGwWWSdesSZuCdFQsizPz4rS9yo7mUI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767970089; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Fuykz2hNdDfejkkRPLEJuXQzMfxfWsY1owMajmCZB38=; b=B3xCQfcqdHeKNC3i68mtpbC07NXVfRAuKhI450mbzzXUZsKtuYP+Mo4CwirsuPL7XXSTdVr/f7ub2fQ4EgMeFswLW82ztKzB7Ihs0jXLTD5mq1zpf41bEvwFoZn5G69mlkAvLTsxpGCIhOPOSTmO+0MRoswqoczyBrXYvtrYIJ4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767970089338797.3593655461524; Fri, 9 Jan 2026 06:48:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1veDm3-0006Oz-Mu; Fri, 09 Jan 2026 09:47:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1veDlo-0006A0-5U for qemu-devel@nongnu.org; Fri, 09 Jan 2026 09:47:26 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1veDlm-00018H-OZ for qemu-devel@nongnu.org; Fri, 09 Jan 2026 09:47:19 -0500 Received: from mail.maildlp.com (unknown [172.18.224.107]) by frasgout.his.huawei.com (SkyGuard) with ESMTPS id 4dnl3f6R5XzJ46ck; Fri, 9 Jan 2026 22:47:10 +0800 (CST) Received: from dubpeml100005.china.huawei.com (unknown [7.214.146.113]) by mail.maildlp.com (Postfix) with ESMTPS id 824C140584; Fri, 9 Jan 2026 22:47:17 +0800 (CST) Received: from SecurePC-101-06.huawei.com (10.122.19.247) by dubpeml100005.china.huawei.com (7.214.146.113) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.36; Fri, 9 Jan 2026 14:47:16 +0000 To: Michael Tsirkin , , Davidlohr Bueso CC: , , Ravi Shankar , Marcel Apfelbaum , Markus Armbruster , Michael Roth Subject: [PATCH qemu v5 4/7] hw/cxl: Update CXL Fixed Memory Window ACPI description to include Back Invalidate support. Date: Fri, 9 Jan 2026 14:45:08 +0000 Message-ID: <20260109144511.557781-5-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20260109144511.557781-1-Jonathan.Cameron@huawei.com> References: <20260109144511.557781-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.19.247] X-ClientProxiedBy: lhrpeml100010.china.huawei.com (7.191.174.197) To dubpeml100005.china.huawei.com (7.214.146.113) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1767970090779158500 Content-Type: text/plain; charset="utf-8" Defaults for these windows has always been to enable anything QEMU supports. With the addition of back invalidate support it is necessary to specify that host windows support this. CXL emulation is currently only suitable for software stack verification. The relaxation of the restrictions on this window to include BI have no affect on the OS until BI capable devices are added and until now these have not existed. As such no backwards compatibility impacts are expected from this change. Signed-off-by: Jonathan Cameron Reviewed-by: Davidlohr Bueso --- v5: Equivalent of the default change in the window restrictions patch. That patch isn't ready for upstream just yet, so for now just change the value for everyone. --- hw/acpi/cxl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/acpi/cxl.c b/hw/acpi/cxl.c index 75edb2c0a652..f92f7fa3d558 100644 --- a/hw/acpi/cxl.c +++ b/hw/acpi/cxl.c @@ -172,7 +172,7 @@ static void cedt_build_cfmws(CXLFixedWindow *fw, Aml *c= edt) build_append_int_noprefix(table_data, fw->enc_int_gran, 4); =20 /* Window Restrictions */ - build_append_int_noprefix(table_data, 0x0f, 2); + build_append_int_noprefix(table_data, 0x2f, 2); =20 /* QTG ID */ build_append_int_noprefix(table_data, 0, 2); --=20 2.48.1 From nobody Mon Feb 9 04:45:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1767970085; cv=none; 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Fri, 9 Jan 2026 14:47:47 +0000 To: Michael Tsirkin , , Davidlohr Bueso CC: , , Ravi Shankar , Marcel Apfelbaum , Markus Armbruster , Michael Roth Subject: [PATCH qemu v5 5/7] tests/acpi/cxl: Update CEDT.cxl to allow BI in CFWMS Date: Fri, 9 Jan 2026 14:45:09 +0000 Message-ID: <20260109144511.557781-6-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20260109144511.557781-1-Jonathan.Cameron@huawei.com> References: <20260109144511.557781-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.19.247] X-ClientProxiedBy: lhrpeml100010.china.huawei.com (7.191.174.197) To dubpeml100005.china.huawei.com (7.214.146.113) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1767970086757158500 Content-Type: text/plain; charset="utf-8" With the addition of back invalidate support in the CXL emulation relax the restriction on the CXL Fixed Memory Window Structures so all advertised ranges continue to support being used with all features that QEMU emulates. [064h 0100 001h] Subtable Type : 01 [CXL Fixed Memory Window = Structure] [065h 0101 001h] Reserved : 00 [066h 0102 002h] Length : 0028 [068h 0104 004h] Reserved : 00000000 [06Ch 0108 008h] Window base address : 0000000110000000 [074h 0116 008h] Window size : 0000000100000000 [07Ch 0124 001h] Interleave Members : 00 [07Dh 0125 001h] Interleave Arithmetic : 00 [07Eh 0126 002h] Reserved : 0000 [080h 0128 004h] Granularity : 00000005 [084h 0132 002h] Restrictions : 002F # Changed from 000F [086h 0134 002h] QtgId : 0000 [088h 0136 004h] First Target : 0000000C Signed-off-by: Jonathan Cameron --- v5: New patch --- tests/qtest/bios-tables-test-allowed-diff.h | 1 - tests/data/acpi/x86/q35/CEDT.cxl | Bin 184 -> 184 bytes 2 files changed, 1 deletion(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index b4646b5b3147..dfb8523c8bf4 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,2 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/x86/q35/CEDT.cxl", diff --git a/tests/data/acpi/x86/q35/CEDT.cxl b/tests/data/acpi/x86/q35/CED= T.cxl index ff8203af070241bd23dd0eb8a51460692bb7d229..c35f3882eee67aa5613af427234= d1ccd196aa249 100644 GIT binary patch delta 36 ncmdnNxPy_)+0`Xv2Ll5G (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767970118638880.8728922706155; Fri, 9 Jan 2026 06:48:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1veDms-0007H0-53; Fri, 09 Jan 2026 09:48:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1veDmp-0007EG-Jz for qemu-devel@nongnu.org; Fri, 09 Jan 2026 09:48:24 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1veDmm-0001F2-Uk for qemu-devel@nongnu.org; Fri, 09 Jan 2026 09:48:23 -0500 Received: from mail.maildlp.com (unknown [172.18.224.83]) by frasgout.his.huawei.com (SkyGuard) with ESMTPS id 4dnl4n0CZDzHnH6L; Fri, 9 Jan 2026 22:48:09 +0800 (CST) Received: from dubpeml100005.china.huawei.com (unknown [7.214.146.113]) by mail.maildlp.com (Postfix) with ESMTPS id 47D6C40572; Fri, 9 Jan 2026 22:48:19 +0800 (CST) Received: from SecurePC-101-06.huawei.com (10.122.19.247) by dubpeml100005.china.huawei.com (7.214.146.113) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.36; Fri, 9 Jan 2026 14:48:18 +0000 To: Michael Tsirkin , , Davidlohr Bueso CC: , , Ravi Shankar , Marcel Apfelbaum , Markus Armbruster , Michael Roth Subject: [PATCH qemu v5 6/7] hw/cxl: Support type3 HDM-DB Date: Fri, 9 Jan 2026 14:45:10 +0000 Message-ID: <20260109144511.557781-7-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20260109144511.557781-1-Jonathan.Cameron@huawei.com> References: <20260109144511.557781-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.19.247] X-ClientProxiedBy: lhrpeml100010.china.huawei.com (7.191.174.197) To dubpeml100005.china.huawei.com (7.214.146.113) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1767970119021158500 Content-Type: text/plain; charset="utf-8" From: Davidlohr Bueso Add basic plumbing for memory expander devices that support Back Invalidation. This introduces a 'hdm-db=3Don|off' parameter and exposes the relevant BI RT/Decoder component cachemem registers. Some noteworthy properties: - Devices require enabling Flit mode across the CXL topology. - Explicit BI-ID commit is required. - HDM decoder support both host and dev coherency models. Tested-by: Dongjoo Seo Signed-off-by: Davidlohr Bueso Signed-off-by: Jonathan Cameron --- docs/system/devices/cxl.rst | 23 +++++ include/hw/cxl/cxl_component.h | 54 ++++++++++- include/hw/cxl/cxl_device.h | 3 + hw/cxl/cxl-component-utils.c | 142 ++++++++++++++++++++++++++-- hw/mem/cxl_type3.c | 9 +- hw/pci-bridge/cxl_downstream.c | 2 +- hw/pci-bridge/cxl_root_port.c | 3 +- hw/pci-bridge/cxl_upstream.c | 2 +- hw/pci-bridge/pci_expander_bridge.c | 2 +- 9 files changed, 225 insertions(+), 15 deletions(-) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index ca15a0da1c1d..9d0771cdfd73 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -384,6 +384,29 @@ An example of 4 devices below a switch suitable for 1,= 2 or 4 way interleave:: -device cxl-type3,bus=3Dswport3,persistent-memdev=3Dcxl-mem3,lsa=3Dcxl-l= sa3,id=3Dcxl-pmem3,sn=3D0x4 \ -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G,cxl-fmw.0.interleave-= granularity=3D4k =20 +An example of 4 type3 devices with volatile memory below a switch. Two of = the devices +use HDM-DB for coherence, which requires operating in Flit mode:: + + qemu-system-x86_64 -M q35,cxl=3Don -m 4G,maxmem=3D8G,slots=3D8 -smp 4 \ + ... + -object memory-backend-ram,id=3Dcxl-mem0,share=3Don,size=3D256M \ + -object memory-backend-ram,id=3Dcxl-mem1,share=3Don,size=3D256M \ + -object memory-backend-ram,id=3Dcxl-mem2,share=3Don,size=3D256M \ + -object memory-backend-ram,id=3Dcxl-mem3,share=3Don,size=3D256M \ + -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id=3Dcxl.1 \ + -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Droot_port0,chassis=3D0,slot=3D0= \ + -device cxl-rp,port=3D1,bus=3Dcxl.1,id=3Droot_port1,chassis=3D0,slot=3D1= \ + -device cxl-upstream,bus=3Droot_port0,id=3Dus0,x-256b-flit=3Don \ + -device cxl-downstream,port=3D0,bus=3Dus0,id=3Dswport0,chassis=3D0,slot= =3D4 \ + -device cxl-type3,bus=3Dswport0,volatile-memdev=3Dcxl-mem0,id=3Dcxl-mem0= ,sn=3D0x1,x-256b-flit=3Don,hdm-db=3Don \ + -device cxl-downstream,port=3D1,bus=3Dus0,id=3Dswport1,chassis=3D0,slot= =3D5 \ + -device cxl-type3,bus=3Dswport1,volatile-memdev=3Dcxl-mem1,id=3Dcxl-mem1= ,sn=3D0x2,x-256b-flit=3Don,hdm-db=3Don \ + -device cxl-downstream,port=3D2,bus=3Dus0,id=3Dswport2,chassis=3D0,slot= =3D6 \ + -device cxl-type3,bus=3Dswport2,volatile-memdev=3Dcxl-mem2,id=3Dcxl-mem2= ,sn=3D0x3 \ + -device cxl-downstream,port=3D3,bus=3Dus0,id=3Dswport3,chassis=3D0,slot= =3D7 \ + -device cxl-type3,bus=3Dswport3,volatile-memdev=3Dcxl-mem3,id=3Dcxl-mem3= ,sn=3D0x4 \ + -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G,cxl-fmw.0.interleave-= granularity=3D4k + A simple arm/virt example featuring a single direct connected CXL Type 3 Volatile Memory device:: =20 diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h index 1f167d3ef79b..ffc82202206c 100644 --- a/include/hw/cxl/cxl_component.h +++ b/include/hw/cxl/cxl_component.h @@ -67,6 +67,8 @@ CXLx_CAPABILITY_HEADER(LINK, 2) CXLx_CAPABILITY_HEADER(HDM, 3) CXLx_CAPABILITY_HEADER(EXTSEC, 4) CXLx_CAPABILITY_HEADER(SNOOP, 5) +CXLx_CAPABILITY_HEADER(BI_RT, 6) +CXLx_CAPABILITY_HEADER(BI_DECODER, 7) =20 /* * Capability structures contain the actual registers that the CXL compone= nt @@ -211,10 +213,55 @@ HDM_DECODER_INIT(3); (CXL_IDE_REGISTERS_OFFSET + CXL_IDE_REGISTERS_SIZE) #define CXL_SNOOP_REGISTERS_SIZE 0x8 =20 -QEMU_BUILD_BUG_MSG((CXL_SNOOP_REGISTERS_OFFSET + - CXL_SNOOP_REGISTERS_SIZE) >=3D 0x1000, +#define CXL_BI_RT_CAP_VERSION 1 +#define CXL_BI_RT_REGISTERS_OFFSET \ + (CXL_SNOOP_REGISTERS_OFFSET + CXL_SNOOP_REGISTERS_SIZE) +#define CXL_BI_RT_REGISTERS_SIZE 0xC + +REG32(CXL_BI_RT_CAPABILITY, CXL_BI_RT_REGISTERS_OFFSET) + FIELD(CXL_BI_RT_CAPABILITY, EXPLICIT_COMMIT, 0, 1) +REG32(CXL_BI_RT_CTRL, CXL_BI_RT_REGISTERS_OFFSET + 0x4) + FIELD(CXL_BI_RT_CTRL, COMMIT, 0, 1) +REG32(CXL_BI_RT_STATUS, CXL_BI_RT_REGISTERS_OFFSET + 0x8) + FIELD(CXL_BI_RT_STATUS, COMMITTED, 0, 1) + FIELD(CXL_BI_RT_STATUS, ERR_NOT_COMMITTED, 1, 1) + FIELD(CXL_BI_RT_STATUS, COMMIT_TMO_SCALE, 8, 4) + FIELD(CXL_BI_RT_STATUS, COMMIT_TMO_BASE, 12, 4) + +/* CXL r3.2 8.2.4.27 - CXL BI Decoder Capability Structure */ +#define CXL_BI_DECODER_CAP_VERSION 1 +#define CXL_BI_DECODER_REGISTERS_OFFSET \ + (CXL_BI_RT_REGISTERS_OFFSET + CXL_BI_RT_REGISTERS_SIZE) +#define CXL_BI_DECODER_REGISTERS_SIZE 0xC + +REG32(CXL_BI_DECODER_CAPABILITY, CXL_BI_DECODER_REGISTERS_OFFSET) + FIELD(CXL_BI_DECODER_CAPABILITY, HDM_D, 0, 1) + FIELD(CXL_BI_DECODER_CAPABILITY, EXPLICIT_COMMIT, 1, 1) +REG32(CXL_BI_DECODER_CTRL, CXL_BI_DECODER_REGISTERS_OFFSET + 0x4) + FIELD(CXL_BI_DECODER_CTRL, BI_FW, 0, 1) + FIELD(CXL_BI_DECODER_CTRL, BI_ENABLE, 1, 1) + FIELD(CXL_BI_DECODER_CTRL, COMMIT, 2, 1) +REG32(CXL_BI_DECODER_STATUS, CXL_BI_DECODER_REGISTERS_OFFSET + 0x8) + FIELD(CXL_BI_DECODER_STATUS, COMMITTED, 0, 1) + FIELD(CXL_BI_DECODER_STATUS, ERR_NOT_COMMITTED, 1, 1) + FIELD(CXL_BI_DECODER_STATUS, COMMIT_TMO_SCALE, 8, 4) + FIELD(CXL_BI_DECODER_STATUS, COMMIT_TMO_BASE, 12, 4) + +QEMU_BUILD_BUG_MSG((CXL_BI_DECODER_REGISTERS_OFFSET + + CXL_BI_DECODER_REGISTERS_SIZE) >=3D 0x1000, "No space for registers"); =20 +/* track BI explicit commit handling for route table and decoder */ +enum { + CXL_BISTATE_RT =3D 0, + CXL_BISTATE_DECODER, + CXL_BISTATE_MAX +}; + +typedef struct bi_state { + uint64_t last_commit; /* last 0->1 transition */ +} BIState; + typedef struct component_registers { /* * Main memory region to be registered with QEMU core. @@ -259,6 +306,7 @@ typedef struct cxl_component { }; =20 CDATObject cdat; + BIState bi_state[CXL_BISTATE_MAX]; } CXLComponentState; =20 void cxl_component_register_block_init(Object *obj, @@ -266,7 +314,7 @@ void cxl_component_register_block_init(Object *obj, const char *type); void cxl_component_register_init_common(uint32_t *reg_state, uint32_t *write_msk, - enum reg_type type); + enum reg_type type, bool bi); =20 void cxl_component_create_dvsec(CXLComponentState *cxl_cstate, enum reg_type cxl_dev_type, uint16_t lengt= h, diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index d2440b0f0f6b..0cd6a81d67e1 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -625,6 +625,9 @@ struct CXLType3Dev { CXLMemECSReadAttrs ecs_attrs; CXLMemECSWriteAttrs ecs_wr_attrs; =20 + /* BI flows */ + bool hdmdb; + struct dynamic_capacity { HostMemoryBackend *host_dc; AddressSpace host_dc_as; diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index 91770f103a85..213099402262 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -71,10 +71,40 @@ static uint64_t cxl_cache_mem_read_reg(void *opaque, hw= addr offset, case 4: if (cregs->special_ops && cregs->special_ops->read) { return cregs->special_ops->read(cxl_cstate, offset, 4); - } else { - QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_registers) !=3D 4); - return cregs->cache_mem_registers[offset / 4]; } + + QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_registers) !=3D 4); + + if (offset =3D=3D A_CXL_BI_RT_STATUS || + offset =3D=3D A_CXL_BI_DECODER_STATUS) { + int type; + uint64_t started; + + type =3D (offset =3D=3D A_CXL_BI_RT_STATUS) ? + CXL_BISTATE_RT : CXL_BISTATE_DECODER; + started =3D cxl_cstate->bi_state[type].last_commit; + + if (started) { + uint32_t *cache_mem =3D cregs->cache_mem_registers; + uint32_t val =3D cache_mem[offset / 4]; + uint64_t now; + int set; + + now =3D qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); + /* arbitrary 100 ms to do the commit */ + set =3D !!(now >=3D started + 100); + + if (offset =3D=3D A_CXL_BI_RT_STATUS) { + val =3D FIELD_DP32(val, CXL_BI_RT_STATUS, COMMITTED, s= et); + } else { + val =3D FIELD_DP32(val, CXL_BI_DECODER_STATUS, COMMITT= ED, + set); + } + stl_le_p((uint8_t *)cache_mem + offset, val); + } + } + + return cregs->cache_mem_registers[offset / 4]; case 8: qemu_log_mask(LOG_UNIMP, "CXL 8 byte cache mem registers not implemented\n"); @@ -118,6 +148,47 @@ static void dumb_hdm_handler(CXLComponentState *cxl_cs= tate, hwaddr offset, stl_le_p((uint8_t *)cache_mem + offset, value); } =20 +static void bi_handler(CXLComponentState *cxl_cstate, hwaddr offset, + uint32_t value) +{ + ComponentRegisters *cregs =3D &cxl_cstate->crb; + uint32_t sts, *cache_mem =3D cregs->cache_mem_registers; + bool to_commit =3D false; + int type; + + switch (offset) { + case A_CXL_BI_RT_CTRL: + to_commit =3D FIELD_EX32(value, CXL_BI_RT_CTRL, COMMIT); + if (to_commit) { + sts =3D cxl_cache_mem_read_reg(cxl_cstate, + R_CXL_BI_RT_STATUS, 4); + sts =3D FIELD_DP32(sts, CXL_BI_RT_STATUS, COMMITTED, 0); + stl_le_p((uint8_t *)cache_mem + R_CXL_BI_RT_STATUS, sts); + type =3D CXL_BISTATE_RT; + } + break; + case A_CXL_BI_DECODER_CTRL: + to_commit =3D FIELD_EX32(value, CXL_BI_DECODER_CTRL, COMMIT); + if (to_commit) { + sts =3D cxl_cache_mem_read_reg(cxl_cstate, + R_CXL_BI_DECODER_STATUS, 4); + sts =3D FIELD_DP32(sts, CXL_BI_DECODER_STATUS, COMMITTED, 0); + stl_le_p((uint8_t *)cache_mem + R_CXL_BI_DECODER_STATUS, sts); + type =3D CXL_BISTATE_DECODER; + } + break; + default: + break; + } + + if (to_commit) { + cxl_cstate->bi_state[type].last_commit =3D + qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); + } + + stl_le_p((uint8_t *)cache_mem + offset, value); +} + static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t = value, unsigned size) { @@ -141,6 +212,9 @@ static void cxl_cache_mem_write_reg(void *opaque, hwadd= r offset, uint64_t value, if (offset >=3D A_CXL_HDM_DECODER_CAPABILITY && offset <=3D A_CXL_HDM_DECODER3_TARGET_LIST_HI) { dumb_hdm_handler(cxl_cstate, offset, value); + } else if (offset =3D=3D A_CXL_BI_RT_CTRL || + offset =3D=3D A_CXL_BI_DECODER_CTRL) { + bi_handler(cxl_cstate, offset, value); } else { cregs->cache_mem_registers[offset / 4] =3D value; } @@ -230,7 +304,7 @@ static void ras_init_common(uint32_t *reg_state, uint32= _t *write_msk) } =20 static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk, - enum reg_type type) + enum reg_type type, bool bi) { int decoder_count =3D CXL_HDM_DECODER_COUNT; int hdm_inc =3D R_CXL_HDM_DECODER1_BASE_LO - R_CXL_HDM_DECODER0_BASE_L= O; @@ -255,7 +329,9 @@ static void hdm_init_common(uint32_t *reg_state, uint32= _t *write_msk, UIO_DECODER_COUNT, 0); ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, MEMDATA_NXM_CA= P, 0); ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, - SUPPORTED_COHERENCY_MODEL, 0); /* Unknown */ + SUPPORTED_COHERENCY_MODEL, + /* host+dev or Unknown */ + type =3D=3D CXL2_TYPE3_DEVICE && bi ? 3 : 0); ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL, HDM_DECODER_ENABLE, 0); write_msk[R_CXL_HDM_DECODER_GLOBAL_CONTROL] =3D 0x3; @@ -278,9 +354,43 @@ static void hdm_init_common(uint32_t *reg_state, uint3= 2_t *write_msk, } } =20 +static void bi_rt_init_common(uint32_t *reg_state, uint32_t *write_msk) +{ + /* switch usp must commit the new BI-ID, timeout of 2secs */ + ARRAY_FIELD_DP32(reg_state, CXL_BI_RT_CAPABILITY, EXPLICIT_COMMIT, 1); + + ARRAY_FIELD_DP32(reg_state, CXL_BI_RT_CTRL, COMMIT, 0); + write_msk[R_CXL_BI_RT_CTRL] =3D 0x1; + + ARRAY_FIELD_DP32(reg_state, CXL_BI_RT_STATUS, COMMITTED, 0); + ARRAY_FIELD_DP32(reg_state, CXL_BI_RT_STATUS, ERR_NOT_COMMITTED, 0); + ARRAY_FIELD_DP32(reg_state, CXL_BI_RT_STATUS, COMMIT_TMO_SCALE, 0x6); + ARRAY_FIELD_DP32(reg_state, CXL_BI_RT_STATUS, COMMIT_TMO_BASE, 0x2); +} + +static void bi_decoder_init_common(uint32_t *reg_state, uint32_t *write_ms= k, + enum reg_type type) +{ + ARRAY_FIELD_DP32(reg_state, CXL_BI_DECODER_CAPABILITY, HDM_D, 0); + /* switch dsp must commit the new BI-ID, timeout of 2secs */ + ARRAY_FIELD_DP32(reg_state, CXL_BI_DECODER_CAPABILITY, EXPLICIT_COMMIT, + (type !=3D CXL2_ROOT_PORT && type !=3D CXL2_TYPE3_DEV= ICE)); + + ARRAY_FIELD_DP32(reg_state, CXL_BI_DECODER_CTRL, BI_FW, 0); + ARRAY_FIELD_DP32(reg_state, CXL_BI_DECODER_CTRL, BI_ENABLE, 0); + ARRAY_FIELD_DP32(reg_state, CXL_BI_DECODER_CTRL, COMMIT, 0); + write_msk[R_CXL_BI_DECODER_CTRL] =3D 0x7; + + ARRAY_FIELD_DP32(reg_state, CXL_BI_DECODER_STATUS, COMMITTED, 0); + ARRAY_FIELD_DP32(reg_state, CXL_BI_DECODER_STATUS, ERR_NOT_COMMITTED, = 0); + ARRAY_FIELD_DP32(reg_state, CXL_BI_DECODER_STATUS, COMMIT_TMO_SCALE, 0= x6); + ARRAY_FIELD_DP32(reg_state, CXL_BI_DECODER_STATUS, COMMIT_TMO_BASE, 0x= 2); +} + void cxl_component_register_init_common(uint32_t *reg_state, uint32_t *write_msk, - enum reg_type type) + enum reg_type type, + bool bi) { int caps =3D 0; =20 @@ -320,7 +430,7 @@ void cxl_component_register_init_common(uint32_t *reg_s= tate, case CXL2_LOGICAL_DEVICE: /* + HDM */ init_cap_reg(HDM, 5, 1); - hdm_init_common(reg_state, write_msk, type); + hdm_init_common(reg_state, write_msk, type, bi); /* fallthrough */ case CXL2_DOWNSTREAM_PORT: case CXL2_DEVICE: @@ -335,6 +445,24 @@ void cxl_component_register_init_common(uint32_t *reg_= state, abort(); } =20 + /* back invalidate */ + if (bi) { + switch (type) { + case CXL2_UPSTREAM_PORT: + init_cap_reg(BI_RT, 11, CXL_BI_RT_CAP_VERSION); + bi_rt_init_common(reg_state, write_msk); + break; + case CXL2_ROOT_PORT: + case CXL2_DOWNSTREAM_PORT: + case CXL2_TYPE3_DEVICE: + init_cap_reg(BI_DECODER, 12, CXL_BI_DECODER_CAP_VERSION); + bi_decoder_init_common(reg_state, write_msk, type); + break; + default: + break; + } + } + ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ARRAY_SIZE, caps); #undef init_cap_reg } diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index f6907fb0c3aa..35394fabb89f 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -748,6 +748,11 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error = **errp) return false; } =20 + if (!ct3d->flitmode && ct3d->hdmdb) { + error_setg(errp, "hdm-db requires operating in 256b flit"); + return false; + } + if (ct3d->hostvmem) { MemoryRegion *vmr; char *v_name; @@ -1247,7 +1252,8 @@ static void ct3d_reset(DeviceState *dev) =20 pcie_cap_fill_link_ep_usp(PCI_DEVICE(dev), ct3d->width, ct3d->speed, ct3d->flitmode); - cxl_component_register_init_common(reg_state, write_msk, CXL2_TYPE3_DE= VICE); + cxl_component_register_init_common(reg_state, write_msk, + CXL2_TYPE3_DEVICE, ct3d->hdmdb); cxl_device_register_init_t3(ct3d, CXL_T3_MSIX_MBOX); =20 /* @@ -1286,6 +1292,7 @@ static const Property ct3_props[] =3D { DEFINE_PROP_PCIE_LINK_WIDTH("x-width", CXLType3Dev, width, PCIE_LINK_WIDTH_16), DEFINE_PROP_BOOL("x-256b-flit", CXLType3Dev, flitmode, false), + DEFINE_PROP_BOOL("hdm-db", CXLType3Dev, hdmdb, false), }; =20 static uint64_t get_lsa_size(CXLType3Dev *ct3d) diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index 64086d8ec2f2..320818a8f1ce 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -39,7 +39,7 @@ static void latch_registers(CXLDownstreamPort *dsp) uint32_t *write_msk =3D dsp->cxl_cstate.crb.cache_mem_regs_write_mask; =20 cxl_component_register_init_common(reg_state, write_msk, - CXL2_DOWNSTREAM_PORT); + CXL2_DOWNSTREAM_PORT, true); } =20 /* TODO: Look at sharing this code across all CXL port types */ diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 5641048084a4..e2093ac39ee6 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -101,7 +101,8 @@ static void latch_registers(CXLRootPort *crp) uint32_t *reg_state =3D crp->cxl_cstate.crb.cache_mem_registers; uint32_t *write_msk =3D crp->cxl_cstate.crb.cache_mem_regs_write_mask; =20 - cxl_component_register_init_common(reg_state, write_msk, CXL2_ROOT_POR= T); + cxl_component_register_init_common(reg_state, write_msk, CXL2_ROOT_POR= T, + true); } =20 static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index c352d11dc7b7..fb8d19539c9f 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -90,7 +90,7 @@ static void latch_registers(CXLUpstreamPort *usp) uint32_t *write_msk =3D usp->cxl_cstate.crb.cache_mem_regs_write_mask; =20 cxl_component_register_init_common(reg_state, write_msk, - CXL2_UPSTREAM_PORT); + CXL2_UPSTREAM_PORT, usp->flitmode); ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, = 8); } =20 diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 08d40aa2eae9..25dfee6a9b2d 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -301,7 +301,7 @@ static void pxb_cxl_dev_reset(DeviceState *dev) uint32_t *write_msk =3D cxl_cstate->crb.cache_mem_regs_write_mask; int dsp_count =3D 0; =20 - cxl_component_register_init_common(reg_state, write_msk, CXL2_RC); + cxl_component_register_init_common(reg_state, write_msk, CXL2_RC, fals= e); /* * The CXL specification allows for host bridges with no HDM decoders * if they only have a single root port. --=20 2.48.1 From nobody Mon Feb 9 04:45:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" From: Davidlohr Bueso ... this is unused, unlike its write counterpart. Suggested-by: Jonathan.Cameron@huawei.com Tested-by: Dongjoo Seo Signed-off-by: Davidlohr Bueso Signed-off-by: Jonathan Cameron --- hw/cxl/cxl-component-utils.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index 213099402262..d36162e91b4c 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -69,10 +69,6 @@ static uint64_t cxl_cache_mem_read_reg(void *opaque, hwa= ddr offset, =20 switch (size) { case 4: - if (cregs->special_ops && cregs->special_ops->read) { - return cregs->special_ops->read(cxl_cstate, offset, 4); - } - QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_registers) !=3D 4); =20 if (offset =3D=3D A_CXL_BI_RT_STATUS || --=20 2.48.1