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Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic Acked-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-ID: <20260108134128.2218102-5-djordje.todorovic@htecgroup.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 5 ++++ target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/xmips.decode | 11 ++++++++ target/riscv/cpu.c | 3 +++ target/riscv/translate.c | 3 +++ target/riscv/insn_trans/trans_xmips.c.inc | 33 +++++++++++++++++++++++ target/riscv/meson.build | 1 + 7 files changed, 57 insertions(+) create mode 100644 target/riscv/xmips.decode create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index aa28dc8d7e..2db471ad17 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -36,6 +36,11 @@ static inline bool always_true_p(const RISCVCPUConfig *c= fg __attribute__((__unus return true; } =20 +static inline bool has_xmips_p(const RISCVCPUConfig *cfg) +{ + return cfg->ext_xmipscmov; +} + static inline bool has_xthead_p(const RISCVCPUConfig *cfg) { return cfg->ext_xtheadba || cfg->ext_xtheadbb || diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index f4ff4f3f96..0b461bb05b 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -150,6 +150,7 @@ BOOL_FIELD(ext_xtheadmemidx) BOOL_FIELD(ext_xtheadmempair) BOOL_FIELD(ext_xtheadsync) BOOL_FIELD(ext_XVentanaCondOps) +BOOL_FIELD(ext_xmipscmov) =20 BOOL_FIELD(mmu) BOOL_FIELD(pmp) diff --git a/target/riscv/xmips.decode b/target/riscv/xmips.decode new file mode 100644 index 0000000000..fadcb78470 --- /dev/null +++ b/target/riscv/xmips.decode @@ -0,0 +1,11 @@ +# +# RISC-V translation routines for the MIPS extension +# +# Copyright (c) 2025 MIPS +# +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Reference: MIPS P8700 instructions +# (https://mips.com/products/hardware/p8700/) + +ccmov rs3:5 11 rs2:5 rs1:5 011 rd:5 0001011 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e17b3e0785..d0a6a88a4e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -252,6 +252,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(svrsw60t59b, PRIV_VERSION_1_13_0, ext_svrsw60t59b), ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte), ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc), + ISA_EXT_DATA_ENTRY(xmipscmov, PRIV_VERSION_1_12_0, ext_xmipscmov), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), @@ -1363,6 +1364,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = =3D { MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false), MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false), MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false), + MULTI_EXT_CFG_BOOL("xmipscmov", ext_xmipscmov, false), =20 { }, }; @@ -3315,6 +3317,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.pmp =3D true, .cfg.ext_zba =3D true, .cfg.ext_zbb =3D true, + .cfg.ext_xmipscmov =3D true, .cfg.marchid =3D 0x8000000000000201, .cfg.mvendorid =3D MIPS_VENDOR_ID, #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0d61420b46..f687c75fe4 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1211,8 +1211,10 @@ static uint32_t opcode_at(DisasContextBase *dcbase, = target_ulong pc) #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_rvbf16.c.inc" #include "decode-xthead.c.inc" +#include "decode-xmips.c.inc" #include "insn_trans/trans_xthead.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" +#include "insn_trans/trans_xmips.c.inc" =20 /* Include the auto-generated decoder for 16 bit insn */ #include "decode-insn16.c.inc" @@ -1229,6 +1231,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) =20 const RISCVDecoder decoder_table[] =3D { { always_true_p, decode_insn32 }, + { has_xmips_p, decode_xmips}, { has_xthead_p, decode_xthead}, { has_XVentanaCondOps_p, decode_XVentanaCodeOps}, }; diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_= trans/trans_xmips.c.inc new file mode 100644 index 0000000000..3202fd9cc0 --- /dev/null +++ b/target/riscv/insn_trans/trans_xmips.c.inc @@ -0,0 +1,33 @@ +/* + * RISC-V translation routines for the MIPS extensions (xmips*). + * + * Copyright (c) 2025 MIPS + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Reference: MIPS P8700 instructions + * (https://mips.com/products/hardware/p8700/) + */ + +#define REQUIRE_XMIPSCMOV(ctx) do { \ + if (!ctx->cfg_ptr->ext_xmipscmov) { \ + return false; \ + } \ +} while (0) + +/* Conditional move by MIPS. */ +static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a) +{ + REQUIRE_XMIPSCMOV(ctx); + + TCGv zero, source1, source2, source3; + zero =3D tcg_constant_tl(0); + source1 =3D get_gpr(ctx, a->rs1, EXT_NONE); + source2 =3D get_gpr(ctx, a->rs2, EXT_NONE); + source3 =3D get_gpr(ctx, a->rs3, EXT_NONE); + + tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[a->rd], + source2, zero, source1, source3); + + return true; +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 25d59ef9f9..3842c7c1a8 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -4,6 +4,7 @@ gen =3D [ decodetree.process('insn32.decode', extra_args: '--static-decode=3Ddecod= e_insn32'), decodetree.process('xthead.decode', extra_args: '--static-decode=3Ddecod= e_xthead'), decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decod= e=3Ddecode_XVentanaCodeOps'), + decodetree.process('xmips.decode', extra_args: '--static-decode=3Ddecode= _xmips'), ] =20 riscv_ss =3D ss.source_set() --=20 2.52.0