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Signed-off-by: Alistair Francis Reviewed-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20251103033713.904455-9-alistair.francis@wdc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 40 +++++++++------------------------------- 1 file changed, 9 insertions(+), 31 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4ef9e9c377..05c7ec8352 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1235,14 +1235,12 @@ static RISCVException write_mhpmeventh(CPURISCVStat= e *env, int csrno, return RISCV_EXCP_NONE; } =20 -static target_ulong riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *en= v, - int counter_idx, - bool upper_half) +static uint64_t riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *env, + int counter_idx) { int inst =3D riscv_pmu_ctr_monitor_instructions(env, counter_idx); uint64_t *counter_arr_virt =3D env->pmu_fixed_ctrs[inst].counter_virt; uint64_t *counter_arr =3D env->pmu_fixed_ctrs[inst].counter; - target_ulong result =3D 0; uint64_t curr_val =3D 0; uint64_t cfg_val =3D 0; =20 @@ -1262,7 +1260,7 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters_= val(CPURISCVState *env, curr_val =3D cpu_get_host_ticks(); } =20 - goto done; + return curr_val; } =20 /* Update counter before reading. */ @@ -1288,14 +1286,7 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters= _val(CPURISCVState *env, curr_val +=3D counter_arr_virt[PRV_U]; } =20 -done: - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - result =3D upper_half ? curr_val >> 32 : curr_val; - } else { - result =3D curr_val; - } - - return result; + return curr_val; } =20 static RISCVException riscv_pmu_write_ctr(CPURISCVState *env, target_ulong= val, @@ -1312,7 +1303,7 @@ static RISCVException riscv_pmu_write_ctr(CPURISCVSta= te *env, target_ulong val, if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { - ctr =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx, false); + ctr =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx); counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, 0, deposit_size, ctr); if (ctr_idx > 2) { @@ -1339,7 +1330,7 @@ static RISCVException riscv_pmu_write_ctrh(CPURISCVSt= ate *env, target_ulong val, if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { - ctrh =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx, true); + ctrh =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx); counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, 32, 32, ctrh); if (ctr_idx > 2) { @@ -1399,7 +1390,7 @@ RISCVException riscv_pmu_read_ctr(CPURISCVState *env,= target_ulong *val, */ if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { - *val =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx, upper_= half) - + *val =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx) - ctr_prev + ctr_val; } else { *val =3D ctr_val; @@ -3006,7 +2997,6 @@ static RISCVException write_mcountinhibit(CPURISCVSta= te *env, int csrno, uint32_t present_ctrs =3D cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTER= EN_IR; target_ulong updated_ctrs =3D (env->mcountinhibit ^ val) & present_ctr= s; uint64_t mhpmctr_val, prev_count, curr_count; - uint64_t ctrh; =20 /* WARL register - disable unavailable counters; TM bit is always 0 */ env->mcountinhibit =3D val & present_ctrs; @@ -3022,28 +3012,16 @@ static RISCVException write_mcountinhibit(CPURISCVS= tate *env, int csrno, counter =3D &env->pmu_ctrs[cidx]; =20 if (!get_field(env->mcountinhibit, BIT(cidx))) { - counter->mhpmcounter_prev =3D - riscv_pmu_ctr_get_fixed_counters_val(env, cidx, false); - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - ctrh =3D riscv_pmu_ctr_get_fixed_counters_val(env, cidx, t= rue); - counter->mhpmcounter_prev =3D deposit64(counter->mhpmcount= er_prev, - 32, 32, ctrh); - } + counter->mhpmcounter_prev =3D riscv_pmu_ctr_get_fixed_counters= _val(env, cidx); =20 if (cidx > 2) { riscv_pmu_setup_timer(env, counter->mhpmcounter_val, cidx); } } else { - curr_count =3D riscv_pmu_ctr_get_fixed_counters_val(env, cidx,= false); + curr_count =3D riscv_pmu_ctr_get_fixed_counters_val(env, cidx); =20 mhpmctr_val =3D counter->mhpmcounter_val; prev_count =3D counter->mhpmcounter_prev; - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - uint64_t tmp =3D - riscv_pmu_ctr_get_fixed_counters_val(env, cidx, true); - - curr_count =3D curr_count | (tmp << 32); - } =20 /* Adjust the counter for later reads. */ mhpmctr_val =3D curr_count - prev_count + mhpmctr_val; --=20 2.52.0