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No real advantage is gained by keeping them separate, and combining them allows for slight simplification. Signed-off-by: Anton Johansson Reviewed-by: Alistair Francis Reviewed-by: Pierrick Bouvier Message-ID: <20251027181831.27016-7-anjo@rev.ng> Signed-off-by: Alistair Francis Message-ID: <20251103033713.904455-6-alistair.francis@wdc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 +-- target/riscv/csr.c | 28 +++++++++++++++++----------- 2 files changed, 18 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f9d2ebfb5d..2942fc1eda 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -420,8 +420,7 @@ struct CPUArchState { uint32_t mcountinhibit; =20 /* PMU cycle & instret privilege mode filtering */ - target_ulong mcyclecfg; - target_ulong mcyclecfgh; + uint64_t mcyclecfg; target_ulong minstretcfg; target_ulong minstretcfgh; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0af85c4309..e9e30384b4 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1061,7 +1061,8 @@ static RISCVException read_hpmcounterh(CPURISCVState = *env, int csrno, static RISCVException read_mcyclecfg(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->mcyclecfg; + bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32; + *val =3D extract64(env->mcyclecfg, 0, rv32 ? 32 : 64); return RISCV_EXCP_NONE; } =20 @@ -1071,7 +1072,7 @@ static RISCVException write_mcyclecfg(CPURISCVState *= env, int csrno, uint64_t inh_avail_mask; =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - env->mcyclecfg =3D val; + env->mcyclecfg =3D deposit64(env->mcyclecfg, 0, 32, val); } else { /* Set xINH fields if priv mode supported */ inh_avail_mask =3D ~MHPMEVENT_FILTER_MASK | MCYCLECFG_BIT_MINH; @@ -1090,7 +1091,7 @@ static RISCVException write_mcyclecfg(CPURISCVState *= env, int csrno, static RISCVException read_mcyclecfgh(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->mcyclecfgh; + *val =3D extract64(env->mcyclecfg, 32, 32); return RISCV_EXCP_NONE; } =20 @@ -1108,7 +1109,7 @@ static RISCVException write_mcyclecfgh(CPURISCVState = *env, int csrno, inh_avail_mask |=3D (riscv_has_ext(env, RVH) && riscv_has_ext(env, RVS)) ? MCYCLECFGH_BIT_VSINH : 0; =20 - env->mcyclecfgh =3D val & inh_avail_mask; + env->mcyclecfg =3D deposit64(env->mcyclecfg, 32, 32, val & inh_avail_m= ask); return RISCV_EXCP_NONE; } =20 @@ -1244,8 +1245,7 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters_= val(CPURISCVState *env, uint64_t cfg_val =3D 0; =20 if (counter_idx =3D=3D 0) { - cfg_val =3D upper_half ? ((uint64_t)env->mcyclecfgh << 32) : - env->mcyclecfg; + cfg_val =3D env->mcyclecfg; } else if (counter_idx =3D=3D 2) { cfg_val =3D upper_half ? ((uint64_t)env->minstretcfgh << 32) : env->minstretcfg; @@ -1525,8 +1525,12 @@ static int rmw_cd_mhpmeventh(CPURISCVState *env, int= evt_index, } =20 static int rmw_cd_ctr_cfg(CPURISCVState *env, int cfg_index, target_ulong = *val, - target_ulong new_val, target_ulong wr_mask) + target_ulong new_val, uint64_t wr_mask) { + /* + * wr_mask is 64-bit so upper 32 bits of mcyclecfg and minstretcfg + * are retained. + */ switch (cfg_index) { case 0: /* CYCLECFG */ if (wr_mask) { @@ -1552,8 +1556,9 @@ static int rmw_cd_ctr_cfg(CPURISCVState *env, int cfg= _index, target_ulong *val, } =20 static int rmw_cd_ctr_cfgh(CPURISCVState *env, int cfg_index, target_ulong= *val, - target_ulong new_val, target_ulong wr_mask) + target_ulong new_val, target_ulong wr_mask) { + uint64_t cfgh; =20 if (riscv_cpu_mxl(env) !=3D MXL_RV32) { return RISCV_EXCP_ILLEGAL_INST; @@ -1561,12 +1566,13 @@ static int rmw_cd_ctr_cfgh(CPURISCVState *env, int = cfg_index, target_ulong *val, =20 switch (cfg_index) { case 0: /* CYCLECFGH */ + cfgh =3D extract64(env->mcyclecfg, 32, 32); if (wr_mask) { wr_mask &=3D ~MCYCLECFGH_BIT_MINH; - env->mcyclecfgh =3D (new_val & wr_mask) | - (env->mcyclecfgh & ~wr_mask); + cfgh =3D (new_val & wr_mask) | (cfgh & ~wr_mask); + env->mcyclecfg =3D deposit64(env->mcyclecfg, 32, 32, cfgh); } else { - *val =3D env->mcyclecfgh; + *val =3D cfgh; } break; case 2: /* INSTRETCFGH */ --=20 2.52.0