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Signed-off-by: Thomas Huth Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Nutty Liu Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20251027112803.54564-1-thuth@redhat.com> Signed-off-by: Alistair Francis --- tests/functional/riscv64/test_sifive_u.py | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/functional/riscv64/test_sifive_u.py b/tests/functional/r= iscv64/test_sifive_u.py index 358ff0d1f6..847f709da1 100755 --- a/tests/functional/riscv64/test_sifive_u.py +++ b/tests/functional/riscv64/test_sifive_u.py @@ -13,7 +13,6 @@ import os =20 from qemu_test import Asset, LinuxKernelTest -from qemu_test import skipIfMissingCommands =20 =20 class SifiveU(LinuxKernelTest): --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767941760; cv=none; d=zohomail.com; s=zohoarc; b=CiQoWl/VtcuspoLm9uJGTBs0rykisXGqjB29AwHF5aaOfbupiv1pjodfF8NSKcsxniCMcVT0oL3DlwOfrgPBZtw0RsXLJQ2tVjttOhT1qQ5dU7qvSmf2VAwpYMRbB8kxzg9hAHdd91vZoLHjcnaZNmi7hBcddMJx0GRJtpVapyU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767941760; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=azluCpwuy12fnH7pKEXgjFpDbSYy56nGenJ1NmQ5bGY=; b=nChp7BtYsqRvv7HkgYZeOBec9Q6RXptcFf8QmzmIbXBVs6p9zyDG2UDPuoWqD9tIuIjTZ/laNwJRRCWXqJ6fWK0K1rzuLfuiIS8Cd/KI+uz3/BZncLKUvBTf83Vn9ONYBubbGOF4cOQW2TYfuDfbVUpimFEpAD72JvQICQ6QIBk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767941760832181.81773285307247; Thu, 8 Jan 2026 22:56:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ve6PE-0003ZS-UW; Fri, 09 Jan 2026 01:55:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ve6P2-0003TX-3m for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:55:20 -0500 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ve6P0-0002nq-7A for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:55:19 -0500 Received: by mail-pg1-x536.google.com with SMTP id 41be03b00d2f7-bc274b8b15bso2586077a12.1 for ; Thu, 08 Jan 2026 22:55:17 -0800 (PST) Received: from toolbx.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. 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Thu, 08 Jan 2026 22:55:16 -0800 (PST) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 02/34] hw/core/loader: Fixup whitespace for get_image_size() Date: Fri, 9 Jan 2026 16:54:27 +1000 Message-ID: <20260109065459.19987-3-alistair.francis@wdc.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20260109065459.19987-1-alistair.francis@wdc.com> References: <20260109065459.19987-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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int64_t size; + fd =3D qemu_open(filename, O_RDONLY | O_BINARY, errp); - if (fd < 0) + + if (fd < 0) { return -1; + } + size =3D lseek(fd, 0, SEEK_END); + if (size < 0) { error_setg_errno(errp, errno, "lseek failure: %s", filename); return -1; } + close(fd); return size; } --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767941880; cv=none; d=zohomail.com; s=zohoarc; b=QoFVUdoGMPwQyBOBZHg9TXNphSoIRU7QVEpNZiXKIDIoSYE8LhrbuwH4nVwhmbSnWZl/S25K+SP4RVRhYqwWWZaRmbzMGROmrGxRFm2QypX+ZK0cxwQR2dn3CTmnOgCDcCG+6vpVm3388nZJdzSVXCCzW9s+FpLebVaHRXOsCts= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767941880; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 08 Jan 2026 22:55:19 -0800 (PST) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Vishal Chourasia Subject: [PULL 03/34] hw/core/loader: Free the image file descriptor on error Date: Fri, 9 Jan 2026 16:54:28 +1000 Message-ID: <20260109065459.19987-4-alistair.francis@wdc.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20260109065459.19987-1-alistair.francis@wdc.com> References: <20260109065459.19987-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1767941881125158500 From: Alistair Francis Coverity: CID 1642764 Fixes: f62226f7dc4 ("hw/core/loader: improve error handling in image loadin= g functions") Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Vishal Chourasia Message-ID: <20251030015306.2279148-2-alistair.francis@wdc.com> Signed-off-by: Alistair Francis --- hw/core/loader.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/core/loader.c b/hw/core/loader.c index b7638ccd72..3d2c1ae286 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -86,6 +86,7 @@ int64_t get_image_size(const char *filename, Error **errp) =20 if (size < 0) { error_setg_errno(errp, errno, "lseek failure: %s", filename); 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Coverity: CID 1642762 Fixes: f62226f7dc44 ("hw/core/loader: improve error handling in image loadi= ng functions") Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20251030015306.2279148-3-alistair.francis@wdc.com> Signed-off-by: Alistair Francis --- hw/core/loader.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/core/loader.c b/hw/core/loader.c index 3d2c1ae286..2fad7292e5 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -153,8 +153,12 @@ ssize_t load_image_targphys_as(const char *filename, } =20 if (size > max_sz) { + char *size_str =3D size_to_str(max_sz); + error_setg(errp, "%s exceeds maximum image size (%s)", - filename, size_to_str(max_sz)); + filename, size_str); + + g_free(size_str); return -1; } =20 --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767941789; cv=none; d=zohomail.com; s=zohoarc; b=XAMuIgQ88JFbnwO7nIeB/Bea50hrFCartl5aXOG5NwAs4f18hN5inOT6sJJUtoMN5w9vjnN9fbbOO9BlKJ6RlOgfffWL7kLwBSV/pKXAminUr6+dugW+wmq32oH4Ji/fD19TAt/1doZYsXFheSFW1NmhfLRcHRrZlLJPstmQJoY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767941789; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=sEEhUQKWzw7fzFc87JZFv1y0Ud0JmfLrIoan4P4nv+Y=; b=JNeVNTBBO+StmwyVo5uwuEhZgKeuhPlnAKB+LjuQ41TftXxgL2giJZe13VRF8wtMCpTxiNPVe1DVvU/1Y1n17IBpRVmSgAETp1FDEHI0zsFDPdtmCbglthRzdRb58JCVcvkX17e12ehhUo1Q3xgyDFwnZYVlgDovCtX+4MCEpek= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176794178977224.528092180117937; Thu, 8 Jan 2026 22:56:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ve6Pk-00045h-Mx; Fri, 09 Jan 2026 01:56:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ve6PB-0003ZT-2m for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:55:31 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ve6P9-0002ox-HM for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:55:28 -0500 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-7f89d0b37f0so1285950b3a.0 for ; Thu, 08 Jan 2026 22:55:27 -0800 (PST) Received: from toolbx.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. 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Add a helper to avoid code repetition. While we're at it fix the identation of the 'flags & CPU_DUMP_VPU' block. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250623172119.997166-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 54 +++++++++++++++++++--------------------------- 1 file changed, 22 insertions(+), 32 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8f26d8b8b0..c22c418625 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -516,6 +516,21 @@ char *riscv_cpu_get_name(RISCVCPU *cpu) return cpu_model_from_type(typename); } =20 +static void riscv_dump_csr(CPURISCVState *env, int csrno, FILE *f) +{ + target_ulong val =3D 0; + RISCVException res =3D riscv_csrrw_debug(env, csrno, &val, 0, 0); + + /* + * Rely on the smode, hmode, etc, predicates within csr.c + * to do the filtering of the registers that are present. + */ + if (res =3D=3D RISCV_EXCP_NONE) { + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", + csr_ops[csrno].name, val); + } +} + static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) { RISCVCPU *cpu =3D RISCV_CPU(cs); @@ -566,18 +581,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f= , int flags) }; =20 for (i =3D 0; i < ARRAY_SIZE(dump_csrs); ++i) { - int csrno =3D dump_csrs[i]; - target_ulong val =3D 0; - RISCVException res =3D riscv_csrrw_debug(env, csrno, &val, 0, = 0); - - /* - * Rely on the smode, hmode, etc, predicates within csr.c - * to do the filtering of the registers that are present. - */ - if (res =3D=3D RISCV_EXCP_NONE) { - qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", - csr_ops[csrno].name, val); - } + riscv_dump_csr(env, dump_csrs[i], f); } } #endif @@ -590,12 +594,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f= , int flags) } } if (flags & CPU_DUMP_FPU) { - target_ulong val =3D 0; - RISCVException res =3D riscv_csrrw_debug(env, CSR_FCSR, &val, 0, 0= ); - if (res =3D=3D RISCV_EXCP_NONE) { - qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", - csr_ops[CSR_FCSR].name, val); - } + riscv_dump_csr(env, CSR_FCSR, f); + for (i =3D 0; i < 32; i++) { qemu_fprintf(f, " %-8s %016" PRIx64, riscv_fpr_regnames[i], env->fpr[i]); @@ -613,22 +613,12 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *= f, int flags) CSR_VL, CSR_VTYPE, CSR_VLENB, - }; - for (i =3D 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) { - int csrno =3D dump_rvv_csrs[i]; - target_ulong val =3D 0; - RISCVException res =3D riscv_csrrw_debug(env, csrno, &val, 0, = 0); + }; + uint16_t vlenb =3D cpu->cfg.vlenb; =20 - /* - * Rely on the smode, hmode, etc, predicates within csr.c - * to do the filtering of the registers that are present. - */ - if (res =3D=3D RISCV_EXCP_NONE) { - qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", - csr_ops[csrno].name, val); - } + for (i =3D 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) { + riscv_dump_csr(env, dump_rvv_csrs[i], f); } - uint16_t vlenb =3D cpu->cfg.vlenb; =20 for (i =3D 0; i < 32; i++) { qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]); --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250623172119.997166-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c22c418625..063374be62 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -594,6 +594,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) } } if (flags & CPU_DUMP_FPU) { + riscv_dump_csr(env, CSR_FFLAGS, f); + riscv_dump_csr(env, CSR_FRM, f); riscv_dump_csr(env, CSR_FCSR, f); =20 for (i =3D 0; i < 32; i++) { --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767941815; cv=none; d=zohomail.com; s=zohoarc; b=dh2nG63WtUlvYrrq6c75+4o2PDdtfUYRPybRpgu1aQP+aRa605kHBP4Td2Pg5ZifuhwZL9c6tTxxZvrqUFUdtTSThmteMpTGKFWWZcg9GmgFyPCfX8/vUGgcCTShFs2tx5D3/X1m0PUTgp/iA/BpAVzu7WDFDcm5el7LrxV9294= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767941815; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xqVtcZ7GhetiIs9h/UKNMMBlkDbc7PuwUw9npuWelOU=; b=aXRZEv1BBzUTTQ564+g23IjxSjk4WXdoizrfjSZxmzs8tDGEMU/spXvOtwb0XZl1xOxja0HPRIs4zxUw83by39Hkf8dWYhH+dFAiNwpJHfXPNsEDFRl0uE4Y8Mivn16g5BKUjiruYexmq1EXjHTWjlzrSDCb+3rOog/5Vw1y2GM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767941815815483.1813085059763; Thu, 8 Jan 2026 22:56:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ve6Q1-0004T4-Nm; Fri, 09 Jan 2026 01:56:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ve6PH-0003dt-DR for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:55:37 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ve6PF-0002pX-PJ for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:55:35 -0500 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-2a102494058so12255395ad.0 for ; Thu, 08 Jan 2026 22:55:32 -0800 (PST) Received: from toolbx.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. 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There's no particular reason to not print all of them. We're ignoring the note about CSR_SSTATUS being ommited because it can be read via CSR_MSTATUS. There's a huge list of CSRs that would fall in this category and it would be an extra burden to manage them, not mentioning having to document "we're not listing X because it's the same value as Y" to users. Remove 'dump_csrs' and use the existing 'csr_ops' array to print all available CSRs. Create two helpers in csr.c to identify FPU and VPU CSRs and skip them - they'll be printed in the FPU/VPU blocks later. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250623172119.997166-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ target/riscv/cpu.c | 55 ++++++++++++++++------------------------------ target/riscv/csr.c | 18 +++++++++++++++ 3 files changed, 39 insertions(+), 36 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 90b3e95105..b3c0be5779 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -969,6 +969,8 @@ bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); =20 /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; +bool riscv_csr_is_fpu(int csrno); +bool riscv_csr_is_vpu(int csrno); =20 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 063374be62..60abdf3324 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -545,44 +545,27 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *= f, int flags) #endif qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); #ifndef CONFIG_USER_ONLY - { - static const int dump_csrs[] =3D { - CSR_MHARTID, - CSR_MSTATUS, - CSR_MSTATUSH, - /* - * CSR_SSTATUS is intentionally omitted here as its value - * can be figured out by looking at CSR_MSTATUS - */ - CSR_HSTATUS, - CSR_VSSTATUS, - CSR_MIP, - CSR_MIE, - CSR_MIDELEG, - CSR_HIDELEG, - CSR_MEDELEG, - CSR_HEDELEG, - CSR_MTVEC, - CSR_STVEC, - CSR_VSTVEC, - CSR_MEPC, - CSR_SEPC, - CSR_VSEPC, - CSR_MCAUSE, - CSR_SCAUSE, - CSR_VSCAUSE, - CSR_MTVAL, - CSR_STVAL, - CSR_HTVAL, - CSR_MTVAL2, - CSR_MSCRATCH, - CSR_SSCRATCH, - CSR_SATP, - }; + for (i =3D 0; i < ARRAY_SIZE(csr_ops); i++) { + int csrno =3D i; =20 - for (i =3D 0; i < ARRAY_SIZE(dump_csrs); ++i) { - riscv_dump_csr(env, dump_csrs[i], f); + /* + * Early skip when possible since we're going + * through a lot of NULL entries. + */ + if (csr_ops[csrno].predicate =3D=3D NULL) { + continue; } + + /* + * FPU and VPU CSRs will be printed in the + * CPU_DUMP_FPU/CPU_DUMP_VPU blocks later. + */ + if (riscv_csr_is_fpu(csrno) || + riscv_csr_is_vpu(csrno)) { + continue; + } + + riscv_dump_csr(env, csrno, f); } #endif =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5c91658c3d..a69b9a11ab 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -5802,6 +5802,24 @@ static RISCVException write_jvt(CPURISCVState *env, = int csrno, return RISCV_EXCP_NONE; } =20 +bool riscv_csr_is_fpu(int csrno) +{ + if (!csr_ops[csrno].predicate) { + return false; + } + + return csr_ops[csrno].predicate =3D=3D fs; +} + +bool riscv_csr_is_vpu(int csrno) +{ + if (!csr_ops[csrno].predicate) { + return false; + } + + return csr_ops[csrno].predicate =3D=3D vs; +} + /* * Control and Status Register function table * riscv_csr_operations::predicate() must be provided for an implemented C= SR --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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While we're at it, fix the formatting of the AIA bullet list. Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-ID: <20251028084622.1177574-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- docs/specs/riscv-aia.rst | 43 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 39 insertions(+), 4 deletions(-) diff --git a/docs/specs/riscv-aia.rst b/docs/specs/riscv-aia.rst index 8097e2f897..f3c6ab7fcb 100644 --- a/docs/specs/riscv-aia.rst +++ b/docs/specs/riscv-aia.rst @@ -8,10 +8,8 @@ RISC-V machine for TCG and KVM accelerators. =20 The support consists of two main modes: =20 -- "aia=3Daplic": adds one or more APLIC (Advanced Platform Level Interrupt= Controller) - devices -- "aia=3Daplic-imsic": adds one or more APLIC device and an IMSIC (Incomin= g MSI - Controller) device for each CPU +- *aia=3Daplic*: adds one or more APLIC (Advanced Platform Level Interrupt= Controller) devices +- *aia=3Daplic-imsic*: adds one or more APLIC device and an IMSIC (Incomin= g MSI Controller) device for each CPU =20 From an user standpoint, these modes will behave the same regardless of th= e accelerator used. From a developer standpoint the accelerator settings will change wh= at it being @@ -81,3 +79,40 @@ we will emulate in userspace: - n/a - emul - in-kernel + + +KVM accel option 'riscv-aia' +---------------------------- + +The KVM accelerator property 'riscv-aia' interacts with the "aia=3Daplic-i= msic" +to determine how the host KVM module will provide the in-kernel IMSIC s-mo= de +controller. The 'kernel-irqchip' setting has no impact in 'riscv-aia' giv= en +that any available 'kernel-irqchip' setting will always have an in-kernel +IMSIC s-mode. 'riscv-aia' has no impact in APLIC m-mode/s-mode and +IMSIC m-mode settings. + + +.. list-table:: How 'riscv-aia' changes in-kernel IMSIC s-mode provisioning + :widths: 25 25 25 25 + :header-rows: 1 + + * - Accel + - KVM riscv-aia + - AIA type + - IMSIC s-mode + * - kvm + - none + - aplic-imsic + - in-kernel, default to 'auto' + * - kvm + - auto + - aplic-imsic + - in-kernel, hwaccel if available, emul otherwise + * - kvm + - hwaccel + - aplic-imsic + - in-kernel, use IMSIC controller from guest hardware + * - kvm + - emul + - aplic-imsic + - in-kernel, IMSIC is emulated by KVM --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767941934; cv=none; d=zohomail.com; s=zohoarc; b=JB881Vw/OLWFDQsp8CvfwrQjvDWz+fGEIP7+a/wRFAYDmVNspJiFVmwg2lYdG4g0pM/x16CxT/rEmcIDYMYS4ND3cmUqKE4qIt0TZE8psvvzcdiUlzJHgUo8HjJ4MeJYlcIbsLakVjEkqDOG4MiXhX4JEEqeHEnThwNzbsxBlTc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767941934; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WBr/y8Mt2gjaIjzK6CaTi1BSaiLEfEtcTIr7bkjOqJE=; b=Up3ju9zFetTeFGna9JE80zjHahU/SfvnWnbmecBjEdpyHAe+PRdeqyjxnifxy0z769E9BOycxm4MHWfqt1p8QbI91wREOO0cxbUb0E/q/Cuiyik+SKrOR3LQSZufZJrKnuLP6DlN05lLS+M2Od7P7wFiAX8ya0uT961HnoRRZbI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767941934544559.5187258521077; Thu, 8 Jan 2026 22:58:54 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ve6Q8-0004x0-Vb; Fri, 09 Jan 2026 01:56:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ve6PO-0003mt-7X for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:55:48 -0500 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ve6PL-0002q7-O9 for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:55:40 -0500 Received: by mail-pg1-x534.google.com with SMTP id 41be03b00d2f7-c05d66dbab2so2545324a12.0 for ; Thu, 08 Jan 2026 22:55:39 -0800 (PST) Received: from toolbx.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. 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Signed-off-by: Akihiko Odaki Reviewed-by: Daniel Henrique Barboza Reviewed-by: Nutty Liu Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20251027-iommu-v1-1-0fc52a02a273@rsg.ci.i.u-tokyo.ac.jp> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index baaadadda1..01730109c7 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -1364,7 +1364,7 @@ static AddressSpace *riscv_iommu_space(RISCVIOMMUStat= e *s, uint32_t devid) /* IOVA address space, untranslated addresses */ memory_region_init_iommu(&as->iova_mr, sizeof(as->iova_mr), TYPE_RISCV_IOMMU_MEMORY_REGION, - OBJECT(as), "riscv_iommu", UINT64_MAX); + OBJECT(s), "riscv_iommu", UINT64_MAX); address_space_init(&as->iova_as, MEMORY_REGION(&as->iova_mr), name= ); =20 QLIST_INSERT_HEAD(&s->spaces, as, list); --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767942595; cv=none; d=zohomail.com; s=zohoarc; b=bM6248EhZ4/mo03tlF96cNZsiFUpumEHtd40h3t0jkqpS7kD5OHMy4F1uTXNW0UFV6E/17MeIEsuGWMoIrE3F3oMGn20Zvs/x0ik+0n8gGOV4gYuQEwZ0KseP2SfspSe6FAQOGsuBmUcej4DQAnzojUOnWfwQZdSFfIv5R4u2tQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767942595; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=C+XdEsEhM8+wyXLt72BIhQhNu5prCrMhg5aHsM0s/2w=; b=cC5lqPvyeZp1YIlvoj0oU5qrF5YlNVtbbHdf2PbZHRMjDGw8yFByTrRHcfDtnsaPA+UMt7VOPpZuVPk22Gmwq5KoXLgRd+gZYou5sIo4ynRwcKFknfaQulfzud/QsxIcBYiu8d+QSFr+7VZNbHnXMyJhIfO5UP4Ahb2NVkmyTek= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767942595233196.93623735714255; Thu, 8 Jan 2026 23:09:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ve6Q4-0004mA-T7; Fri, 09 Jan 2026 01:56:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ve6PU-0003pJ-F6 for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:55:50 -0500 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ve6PO-0002qT-UQ for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:55:45 -0500 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-7d26a7e5639so2703130b3a.1 for ; Thu, 08 Jan 2026 22:55:42 -0800 (PST) Received: from toolbx.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. 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Note, senvcfg is defined to be SXLEN bits wide, but is widened to 64 bits to match henvcfg and menvcfg. Next, [m|h]edeleg are changed to 64 bits as defined privileged specification, and hvictl is fixed to 32 bits which holds all relevant values, see HVICTL_VALID_MASK. The remaining fields touched in the commit are widened from [H|S|M]XLEN to 64-bit. Note, the cpu/hyper, cpu/envcfg, cpu/jvt, and cpu VMSTATE versions are bumped, breaking migration from older versions. References to the privileged/unprivileged RISCV specification refer to version 20250508. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Alistair Francis Message-ID: <20251027181831.27016-2-anjo@rev.ng> Signed-off-by: Alistair Francis Message-ID: <20251103033713.904455-2-alistair.francis@wdc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 78 +++++++++++++++++++-------------------- target/riscv/machine.c | 84 +++++++++++++++++++++--------------------- 2 files changed, 81 insertions(+), 81 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b3c0be5779..bc6e093ca2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -255,7 +255,7 @@ struct CPUArchState { /* 128-bit helpers upper part return value */ target_ulong retxh; =20 - target_ulong jvt; + uint64_t jvt; =20 /* elp state for zicfilp extension */ bool elp; @@ -272,7 +272,7 @@ struct CPUArchState { target_ulong priv; /* CSRs for execution environment configuration */ uint64_t menvcfg; - target_ulong senvcfg; + uint64_t senvcfg; =20 #ifndef CONFIG_USER_ONLY /* This contains QEMU specific information about the virt state. */ @@ -314,18 +314,18 @@ struct CPUArchState { */ uint64_t vsie; =20 - target_ulong satp; /* since: priv-1.10.0 */ - target_ulong stval; - target_ulong medeleg; + uint64_t satp; /* since: priv-1.10.0 */ + uint64_t stval; + uint64_t medeleg; =20 - target_ulong stvec; - target_ulong sepc; - target_ulong scause; + uint64_t stvec; + uint64_t sepc; + uint64_t scause; =20 - target_ulong mtvec; - target_ulong mepc; - target_ulong mcause; - target_ulong mtval; /* since: priv-1.10.0 */ + uint64_t mtvec; + uint64_t mepc; + uint64_t mcause; + uint64_t mtval; /* since: priv-1.10.0 */ =20 uint64_t mctrctl; uint32_t sctrdepth; @@ -347,13 +347,13 @@ struct CPUArchState { uint64_t mvip; =20 /* Hypervisor CSRs */ - target_ulong hstatus; - target_ulong hedeleg; + uint64_t hstatus; + uint64_t hedeleg; uint64_t hideleg; uint32_t hcounteren; - target_ulong htval; - target_ulong htinst; - target_ulong hgatp; + uint64_t htval; + uint64_t htinst; + uint64_t hgatp; target_ulong hgeie; target_ulong hgeip; uint64_t htimedelta; @@ -367,7 +367,7 @@ struct CPUArchState { uint64_t hvip; =20 /* Hypervisor controlled virtual interrupt priorities */ - target_ulong hvictl; + uint32_t hvictl; uint8_t hviprio[64]; =20 /* Upper 64-bits of 128-bit CSRs */ @@ -380,26 +380,26 @@ struct CPUArchState { * For RV64 this is a 64-bit vsstatus. */ uint64_t vsstatus; - target_ulong vstvec; - target_ulong vsscratch; - target_ulong vsepc; - target_ulong vscause; - target_ulong vstval; - target_ulong vsatp; + uint64_t vstvec; + uint64_t vsscratch; + uint64_t vsepc; + uint64_t vscause; + uint64_t vstval; + uint64_t vsatp; =20 /* AIA VS-mode CSRs */ target_ulong vsiselect; =20 - target_ulong mtval2; - target_ulong mtinst; + uint64_t mtval2; + uint64_t mtinst; =20 /* HS Backup CSRs */ - target_ulong stvec_hs; - target_ulong sscratch_hs; - target_ulong sepc_hs; - target_ulong scause_hs; - target_ulong stval_hs; - target_ulong satp_hs; + uint64_t stvec_hs; + uint64_t sscratch_hs; + uint64_t sepc_hs; + uint64_t scause_hs; + uint64_t stval_hs; + uint64_t satp_hs; uint64_t mstatus_hs; =20 /* @@ -436,8 +436,8 @@ struct CPUArchState { =20 PMUFixedCtrState pmu_fixed_ctrs[2]; =20 - target_ulong sscratch; - target_ulong mscratch; + uint64_t sscratch; + uint64_t mscratch; =20 /* Sstc CSRs */ uint64_t stimecmp; @@ -507,11 +507,11 @@ struct CPUArchState { #endif /* CONFIG_KVM */ =20 /* RNMI */ - target_ulong mnscratch; - target_ulong mnepc; - target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */ - target_ulong mnstatus; - target_ulong rnmip; + uint64_t mnscratch; + uint64_t mnepc; + uint64_t mncause; /* mncause without bit XLEN-1 set to 1 */ + uint64_t mnstatus; + uint64_t rnmip; uint64_t rnmi_irqvec; uint64_t rnmi_excpvec; }; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 18d790af0d..f6ca017211 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -80,17 +80,17 @@ static bool hyper_needed(void *opaque) =20 static const VMStateDescription vmstate_hyper =3D { .name =3D "cpu/hyper", - .version_id =3D 4, - .minimum_version_id =3D 4, + .version_id =3D 5, + .minimum_version_id =3D 5, .needed =3D hyper_needed, .fields =3D (const VMStateField[]) { - VMSTATE_UINTTL(env.hstatus, RISCVCPU), - VMSTATE_UINTTL(env.hedeleg, RISCVCPU), + VMSTATE_UINT64(env.hstatus, RISCVCPU), + VMSTATE_UINT64(env.hedeleg, RISCVCPU), VMSTATE_UINT64(env.hideleg, RISCVCPU), VMSTATE_UINT32(env.hcounteren, RISCVCPU), - VMSTATE_UINTTL(env.htval, RISCVCPU), - VMSTATE_UINTTL(env.htinst, RISCVCPU), - VMSTATE_UINTTL(env.hgatp, RISCVCPU), + VMSTATE_UINT64(env.htval, RISCVCPU), + VMSTATE_UINT64(env.htinst, RISCVCPU), + VMSTATE_UINT64(env.hgatp, RISCVCPU), VMSTATE_UINTTL(env.hgeie, RISCVCPU), VMSTATE_UINTTL(env.hgeip, RISCVCPU), VMSTATE_UINT64(env.hvien, RISCVCPU), @@ -98,28 +98,28 @@ static const VMStateDescription vmstate_hyper =3D { VMSTATE_UINT64(env.htimedelta, RISCVCPU), VMSTATE_UINT64(env.vstimecmp, RISCVCPU), =20 - VMSTATE_UINTTL(env.hvictl, RISCVCPU), + VMSTATE_UINT32(env.hvictl, RISCVCPU), VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64), =20 VMSTATE_UINT64(env.vsstatus, RISCVCPU), - VMSTATE_UINTTL(env.vstvec, RISCVCPU), - VMSTATE_UINTTL(env.vsscratch, RISCVCPU), - VMSTATE_UINTTL(env.vsepc, RISCVCPU), - VMSTATE_UINTTL(env.vscause, RISCVCPU), - VMSTATE_UINTTL(env.vstval, RISCVCPU), - VMSTATE_UINTTL(env.vsatp, RISCVCPU), + VMSTATE_UINT64(env.vstvec, RISCVCPU), + VMSTATE_UINT64(env.vsscratch, RISCVCPU), + VMSTATE_UINT64(env.vsepc, RISCVCPU), + VMSTATE_UINT64(env.vscause, RISCVCPU), + VMSTATE_UINT64(env.vstval, RISCVCPU), + VMSTATE_UINT64(env.vsatp, RISCVCPU), VMSTATE_UINTTL(env.vsiselect, RISCVCPU), VMSTATE_UINT64(env.vsie, RISCVCPU), =20 - VMSTATE_UINTTL(env.mtval2, RISCVCPU), - VMSTATE_UINTTL(env.mtinst, RISCVCPU), + VMSTATE_UINT64(env.mtval2, RISCVCPU), + VMSTATE_UINT64(env.mtinst, RISCVCPU), =20 - VMSTATE_UINTTL(env.stvec_hs, RISCVCPU), - VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU), - VMSTATE_UINTTL(env.sepc_hs, RISCVCPU), - VMSTATE_UINTTL(env.scause_hs, RISCVCPU), - VMSTATE_UINTTL(env.stval_hs, RISCVCPU), - VMSTATE_UINTTL(env.satp_hs, RISCVCPU), + VMSTATE_UINT64(env.stvec_hs, RISCVCPU), + VMSTATE_UINT64(env.sscratch_hs, RISCVCPU), + VMSTATE_UINT64(env.sepc_hs, RISCVCPU), + VMSTATE_UINT64(env.scause_hs, RISCVCPU), + VMSTATE_UINT64(env.stval_hs, RISCVCPU), + VMSTATE_UINT64(env.satp_hs, RISCVCPU), VMSTATE_UINT64(env.mstatus_hs, RISCVCPU), =20 VMSTATE_END_OF_LIST() @@ -291,12 +291,12 @@ static bool envcfg_needed(void *opaque) =20 static const VMStateDescription vmstate_envcfg =3D { .name =3D "cpu/envcfg", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .needed =3D envcfg_needed, .fields =3D (const VMStateField[]) { VMSTATE_UINT64(env.menvcfg, RISCVCPU), - VMSTATE_UINTTL(env.senvcfg, RISCVCPU), + VMSTATE_UINT64(env.senvcfg, RISCVCPU), VMSTATE_UINT64(env.henvcfg, RISCVCPU), VMSTATE_END_OF_LIST() } @@ -356,11 +356,11 @@ static bool jvt_needed(void *opaque) =20 static const VMStateDescription vmstate_jvt =3D { .name =3D "cpu/jvt", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .needed =3D jvt_needed, .fields =3D (const VMStateField[]) { - VMSTATE_UINTTL(env.jvt, RISCVCPU), + VMSTATE_UINT64(env.jvt, RISCVCPU), VMSTATE_END_OF_LIST() } }; @@ -427,8 +427,8 @@ static const VMStateDescription vmstate_sstc =3D { =20 const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", - .version_id =3D 10, - .minimum_version_id =3D 10, + .version_id =3D 11, + .minimum_version_id =3D 11, .post_load =3D riscv_cpu_post_load, .fields =3D (const VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), @@ -459,16 +459,16 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT64(env.mvip, RISCVCPU), VMSTATE_UINT64(env.sie, RISCVCPU), VMSTATE_UINT64(env.mideleg, RISCVCPU), - VMSTATE_UINTTL(env.satp, RISCVCPU), - VMSTATE_UINTTL(env.stval, RISCVCPU), - VMSTATE_UINTTL(env.medeleg, RISCVCPU), - VMSTATE_UINTTL(env.stvec, RISCVCPU), - VMSTATE_UINTTL(env.sepc, RISCVCPU), - VMSTATE_UINTTL(env.scause, RISCVCPU), - VMSTATE_UINTTL(env.mtvec, RISCVCPU), - VMSTATE_UINTTL(env.mepc, RISCVCPU), - VMSTATE_UINTTL(env.mcause, RISCVCPU), - VMSTATE_UINTTL(env.mtval, RISCVCPU), + VMSTATE_UINT64(env.satp, RISCVCPU), + VMSTATE_UINT64(env.stval, RISCVCPU), + VMSTATE_UINT64(env.medeleg, RISCVCPU), + VMSTATE_UINT64(env.stvec, RISCVCPU), + VMSTATE_UINT64(env.sepc, RISCVCPU), + VMSTATE_UINT64(env.scause, RISCVCPU), + VMSTATE_UINT64(env.mtvec, RISCVCPU), + VMSTATE_UINT64(env.mepc, RISCVCPU), + VMSTATE_UINT64(env.mcause, RISCVCPU), + VMSTATE_UINT64(env.mtval, RISCVCPU), VMSTATE_UINTTL(env.miselect, RISCVCPU), VMSTATE_UINTTL(env.siselect, RISCVCPU), VMSTATE_UINT32(env.scounteren, RISCVCPU), @@ -479,8 +479,8 @@ const VMStateDescription vmstate_riscv_cpu =3D { vmstate_pmu_ctr_state, PMUCTRState), VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENT= S), VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVEN= TS), - VMSTATE_UINTTL(env.sscratch, RISCVCPU), - VMSTATE_UINTTL(env.mscratch, RISCVCPU), + VMSTATE_UINT64(env.sscratch, RISCVCPU), + VMSTATE_UINT64(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.stimecmp, RISCVCPU), =20 VMSTATE_END_OF_LIST() --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Alistair Francis Message-ID: <20251027181831.27016-3-anjo@rev.ng> Signed-off-by: Alistair Francis Message-ID: <20251103033713.904455-3-alistair.francis@wdc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/cpu_helper.c | 2 +- target/riscv/machine.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bc6e093ca2..7b2c11af6b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -280,7 +280,7 @@ struct CPUArchState { target_ulong geilen; uint64_t resetvec; =20 - target_ulong mhartid; + uint64_t mhartid; /* * For RV32 this is 32-bit mstatus and 32-bit mstatush. * For RV64 this is a 64-bit mstatus. diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c4fb68b5de..dd6c861a90 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -2280,7 +2280,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_get_trap_name(cause, async)); =20 qemu_log_mask(CPU_LOG_INT, - "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_l= x", " + "%s: hart:%"PRIu64", async:%d, cause:"TARGET_FMT_lx", " "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=3D%= s\n", __func__, env->mhartid, async, cause, env->pc, tval, riscv_cpu_get_trap_name(cause, async)); diff --git a/target/riscv/machine.c b/target/riscv/machine.c index f6ca017211..ab0bc32e1f 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -450,7 +450,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.priv, RISCVCPU), VMSTATE_BOOL(env.virt_enabled, RISCVCPU), VMSTATE_UINT64(env.resetvec, RISCVCPU), - VMSTATE_UINTTL(env.mhartid, RISCVCPU), + VMSTATE_UINT64(env.mhartid, RISCVCPU), VMSTATE_UINT64(env.mstatus, RISCVCPU), VMSTATE_UINT64(env.mip, RISCVCPU), VMSTATE_UINT64(env.miclaim, RISCVCPU), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index bb03f8dc0c..cdc05f60e9 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -489,7 +489,7 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVC= PU *cpu) continue; } #ifndef CONFIG_USER_ONLY - warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx + warn_report("disabling %s extension for hart 0x%" PRIx64 " because privilege spec version does not match", edata->name, env->mhartid); #else --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767942077; cv=none; d=zohomail.com; s=zohoarc; b=E8/xeBtcC56f19N2jmZ5tKAZltwUHUGO20z8V+qmiG8WkVibp8CMlZiA7w1ZV7hmB7cGtcWYxtFOGY3onzzRY5a1KeYquhzkmRPYErH1UfZnazBlxbqPyiaMV0VBq0BG+bxwDt+wmvuYHwZErZ6XE8P30EXI6gg3KfxLJvOlkYs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767942077; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ERlf7UDAtb2XiXyt3aq1BL+KIr1toImgIxxx/WHIU0Q=; b=kJtcU4RLgWksfSyEabTwetosjPVioykEYjN/rhFk2XfadifTZxmcirwBs+6dIFP0D5K9btaGVwQYGGKCp6GiiNRNDle/bjKBisCf2pDZLY7KwXUERnXHKgxKVWqiS3JhLSbWKUezvcKVCrbeO5F3uEfsWc79OesFP/wkSzlVyYI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767942077444916.6336008273536; Thu, 8 Jan 2026 23:01:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ve6RV-0006m3-BP; Fri, 09 Jan 2026 01:57:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ve6PY-0003rk-Qc for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:55:54 -0500 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ve6PV-0002rB-F7 for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:55:51 -0500 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-7f89d0b37f0so1286094b3a.0 for ; Thu, 08 Jan 2026 22:55:49 -0800 (PST) Received: from toolbx.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. 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Signed-off-by: Anton Johansson Reviewed-by: Alistair Francis Reviewed-by: Pierrick Bouvier Message-ID: <20251027181831.27016-5-anjo@rev.ng> Signed-off-by: Alistair Francis Message-ID: <20251103033713.904455-4-alistair.francis@wdc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a69b9a11ab..a34b14c4f0 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1544,7 +1544,7 @@ static int rmw_cd_ctr_cfg(CPURISCVState *env, int cfg= _index, target_ulong *val, wr_mask &=3D ~MCYCLECFG_BIT_MINH; env->mcyclecfg =3D (new_val & wr_mask) | (env->mcyclecfg & ~wr= _mask); } else { - *val =3D env->mcyclecfg &=3D ~MHPMEVENTH_BIT_MINH; + *val =3D env->mcyclecfg &=3D ~MHPMEVENT_BIT_MINH; } break; case 2: /* INSTRETCFG */ @@ -1553,7 +1553,7 @@ static int rmw_cd_ctr_cfg(CPURISCVState *env, int cfg= _index, target_ulong *val, env->minstretcfg =3D (new_val & wr_mask) | (env->minstretcfg & ~wr_mask); } else { - *val =3D env->minstretcfg &=3D ~MHPMEVENTH_BIT_MINH; + *val =3D env->minstretcfg &=3D ~MHPMEVENT_BIT_MINH; } break; default: --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767942469; cv=none; d=zohomail.com; s=zohoarc; b=l++0S3roERAeEKMdkzKO0UZrjl5BSVTzMKIDc23pvtyGfW9/yeYv/noRZ88o/AiIne7r+rV2FaX4r+v0PScEUjtIcTV/zL7zR67Rn6Iy0HO2SKpo/sMxDwPK2cjRFKzvUMxBOmRm4hoT7Xj8gF/t9E0uO4+Cj8lMHAqVI/v5qQc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767942469; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TpxscUU6O5KKCW112jPr+EpUKLJfRQM0Sf58xqCyaWo=; b=H740/mhjKAAP/Nekpuwt8odkoLhOyHOlkzc6X4KRBz1N22LBuCuvAzV9ZIr0j3hCRnHKAVLJHvdeWq6gCueHXG0/bmlCXloZmmbEfYIyBswDSIKhsWj/7mr9dCkU/B3/2IWYGFCnKZ35RLjww+B/DqC4Ox3gBGvEz2KrKKiMOBg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767942469437151.76963159812556; Thu, 8 Jan 2026 23:07:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ve6Q4-0004j2-Gm; Fri, 09 Jan 2026 01:56:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ve6Pb-0003uN-0G for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:55:55 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ve6PY-0002rS-Qj for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:55:54 -0500 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-7aa9be9f03aso2326337b3a.2 for ; Thu, 08 Jan 2026 22:55:52 -0800 (PST) Received: from toolbx.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. 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Combine the two arrays of target_ulong mhpmeventh[] and mhpmevent[] to a single array of uint64_t. This also allows for some minor code simplification where branches handling either mhpmeventh[] or mhpmevent[] could be combined. Signed-off-by: Anton Johansson Reviewed-by: Alistair Francis Reviewed-by: Pierrick Bouvier Message-ID: <20251027181831.27016-6-anjo@rev.ng> Signed-off-by: Alistair Francis Message-ID: <20251103033713.904455-5-alistair.francis@wdc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 10 +++---- target/riscv/csr.c | 67 +++++++++++++++--------------------------- target/riscv/machine.c | 3 +- target/riscv/pmu.c | 53 ++++++++------------------------- 4 files changed, 42 insertions(+), 91 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7b2c11af6b..f9d2ebfb5d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -428,11 +428,11 @@ struct CPUArchState { /* PMU counter state */ PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; =20 - /* PMU event selector configured values. First three are unused */ - target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; - - /* PMU event selector configured values for RV32 */ - target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; + /* + * PMU event selector configured values. First three are unused. + * For RV32 top 32 bits are accessed via the mhpmeventh CSR. + */ + uint64_t mhpmevent_val[RV_MAX_MHPMEVENTS]; =20 PMUFixedCtrState pmu_fixed_ctrs[2]; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a34b14c4f0..0af85c4309 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1167,8 +1167,9 @@ static RISCVException read_mhpmevent(CPURISCVState *e= nv, int csrno, target_ulong *val) { int evt_index =3D csrno - CSR_MCOUNTINHIBIT; + bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32; =20 - *val =3D env->mhpmevent_val[evt_index]; + *val =3D extract64(env->mhpmevent_val[evt_index], 0, rv32 ? 32 : 64); =20 return RISCV_EXCP_NONE; } @@ -1177,13 +1178,11 @@ static RISCVException write_mhpmevent(CPURISCVState= *env, int csrno, target_ulong val, uintptr_t ra) { int evt_index =3D csrno - CSR_MCOUNTINHIBIT; - uint64_t mhpmevt_val =3D val; + uint64_t mhpmevt_val; uint64_t inh_avail_mask; =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - env->mhpmevent_val[evt_index] =3D val; - mhpmevt_val =3D mhpmevt_val | - ((uint64_t)env->mhpmeventh_val[evt_index] << 32); + mhpmevt_val =3D deposit64(env->mhpmevent_val[evt_index], 0, 32, va= l); } else { inh_avail_mask =3D ~MHPMEVENT_FILTER_MASK | MHPMEVENT_BIT_MINH; inh_avail_mask |=3D riscv_has_ext(env, RVU) ? MHPMEVENT_BIT_UINH := 0; @@ -1193,9 +1192,9 @@ static RISCVException write_mhpmevent(CPURISCVState *= env, int csrno, inh_avail_mask |=3D (riscv_has_ext(env, RVH) && riscv_has_ext(env, RVS)) ? MHPMEVENT_BIT_VSINH = : 0; mhpmevt_val =3D val & inh_avail_mask; - env->mhpmevent_val[evt_index] =3D mhpmevt_val; } =20 + env->mhpmevent_val[evt_index] =3D mhpmevt_val; riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); =20 return RISCV_EXCP_NONE; @@ -1206,7 +1205,7 @@ static RISCVException read_mhpmeventh(CPURISCVState *= env, int csrno, { int evt_index =3D csrno - CSR_MHPMEVENT3H + 3; =20 - *val =3D env->mhpmeventh_val[evt_index]; + *val =3D extract64(env->mhpmevent_val[evt_index], 32, 32); =20 return RISCV_EXCP_NONE; } @@ -1215,8 +1214,6 @@ static RISCVException write_mhpmeventh(CPURISCVState = *env, int csrno, target_ulong val, uintptr_t ra) { int evt_index =3D csrno - CSR_MHPMEVENT3H + 3; - uint64_t mhpmevth_val; - uint64_t mhpmevt_val =3D env->mhpmevent_val[evt_index]; target_ulong inh_avail_mask =3D (target_ulong)(~MHPMEVENTH_FILTER_MASK= | MHPMEVENTH_BIT_MINH); =20 @@ -1227,11 +1224,10 @@ static RISCVException write_mhpmeventh(CPURISCVStat= e *env, int csrno, inh_avail_mask |=3D (riscv_has_ext(env, RVH) && riscv_has_ext(env, RVS)) ? MHPMEVENTH_BIT_VSINH : 0; =20 - mhpmevth_val =3D val & inh_avail_mask; - mhpmevt_val =3D mhpmevt_val | (mhpmevth_val << 32); - env->mhpmeventh_val[evt_index] =3D mhpmevth_val; + env->mhpmevent_val[evt_index] =3D deposit64(env->mhpmevent_val[evt_ind= ex], + 32, 32, val & inh_avail_mask= ); =20 - riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); + riscv_pmu_update_event_map(env, env->mhpmevent_val[evt_index], evt_ind= ex); =20 return RISCV_EXCP_NONE; } @@ -1254,9 +1250,7 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters_= val(CPURISCVState *env, cfg_val =3D upper_half ? ((uint64_t)env->minstretcfgh << 32) : env->minstretcfg; } else { - cfg_val =3D upper_half ? - ((uint64_t)env->mhpmeventh_val[counter_idx] << 32) : - env->mhpmevent_val[counter_idx]; + cfg_val =3D env->mhpmevent_val[counter_idx]; cfg_val &=3D MHPMEVENT_FILTER_MASK; } =20 @@ -1475,27 +1469,23 @@ static int rmw_cd_mhpmcounterh(CPURISCVState *env, = int ctr_idx, =20 static int rmw_cd_mhpmevent(CPURISCVState *env, int evt_index, target_ulong *val, target_ulong new_val, - target_ulong wr_mask) + uint64_t wr_mask) { - uint64_t mhpmevt_val =3D new_val; + uint64_t mhpmevt_val =3D env->mhpmevent_val[evt_index]; =20 if (wr_mask !=3D 0 && wr_mask !=3D -1) { return -EINVAL; } =20 if (!wr_mask && val) { - *val =3D env->mhpmevent_val[evt_index]; + *val =3D mhpmevt_val; if (riscv_cpu_cfg(env)->ext_sscofpmf) { *val &=3D ~MHPMEVENT_BIT_MINH; } } else if (wr_mask) { wr_mask &=3D ~MHPMEVENT_BIT_MINH; - mhpmevt_val =3D (new_val & wr_mask) | - (env->mhpmevent_val[evt_index] & ~wr_mask); - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - mhpmevt_val =3D mhpmevt_val | - ((uint64_t)env->mhpmeventh_val[evt_index] << 32); - } + /* wr_mask is 64-bit so upper 32 bits of mhpmevt_val are retained = */ + mhpmevt_val =3D (new_val & wr_mask) | (mhpmevt_val & ~wr_mask); env->mhpmevent_val[evt_index] =3D mhpmevt_val; riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); } else { @@ -1509,24 +1499,23 @@ static int rmw_cd_mhpmeventh(CPURISCVState *env, in= t evt_index, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { - uint64_t mhpmevth_val; uint64_t mhpmevt_val =3D env->mhpmevent_val[evt_index]; + uint32_t mhpmevth_val =3D extract64(mhpmevt_val, 32, 32); =20 if (wr_mask !=3D 0 && wr_mask !=3D -1) { return -EINVAL; } =20 if (!wr_mask && val) { - *val =3D env->mhpmeventh_val[evt_index]; + *val =3D mhpmevth_val; if (riscv_cpu_cfg(env)->ext_sscofpmf) { *val &=3D ~MHPMEVENTH_BIT_MINH; } } else if (wr_mask) { wr_mask &=3D ~MHPMEVENTH_BIT_MINH; - env->mhpmeventh_val[evt_index] =3D - (new_val & wr_mask) | (env->mhpmeventh_val[evt_index] & ~wr_ma= sk); - mhpmevth_val =3D env->mhpmeventh_val[evt_index]; - mhpmevt_val =3D mhpmevt_val | (mhpmevth_val << 32); + mhpmevth_val =3D (new_val & wr_mask) | (mhpmevth_val & ~wr_mask); + mhpmevt_val =3D deposit64(mhpmevt_val, 32, 32, mhpmevth_val); + env->mhpmevent_val[evt_index] =3D mhpmevt_val; riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); } else { return -EINVAL; @@ -1602,8 +1591,6 @@ static RISCVException read_scountovf(CPURISCVState *e= nv, int csrno, int mhpmevt_start =3D CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT; int i; *val =3D 0; - target_ulong *mhpm_evt_val; - uint64_t of_bit_mask; =20 /* Virtualize scountovf for counter delegation */ if (riscv_cpu_cfg(env)->ext_sscofpmf && @@ -1613,19 +1600,11 @@ static RISCVException read_scountovf(CPURISCVState = *env, int csrno, return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } =20 - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - mhpm_evt_val =3D env->mhpmeventh_val; - of_bit_mask =3D MHPMEVENTH_BIT_OF; - } else { - mhpm_evt_val =3D env->mhpmevent_val; - of_bit_mask =3D MHPMEVENT_BIT_OF; - } - for (i =3D mhpmevt_start; i < RV_MAX_MHPMEVENTS; i++) { if ((get_field(env->mcounteren, BIT(i))) && - (mhpm_evt_val[i] & of_bit_mask)) { - *val |=3D BIT(i); - } + (env->mhpmevent_val[i] & MHPMEVENT_BIT_OF)) { + *val |=3D BIT(i); + } } =20 return RISCV_EXCP_NONE; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ab0bc32e1f..6146124229 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -477,8 +477,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT32(env.mcountinhibit, RISCVCPU), VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, = 0, vmstate_pmu_ctr_state, PMUCTRState), - VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENT= S), - VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVEN= TS), + VMSTATE_UINT64_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENT= S), VMSTATE_UINT64(env.sscratch, RISCVCPU), VMSTATE_UINT64(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.stimecmp, RISCVCPU), diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index a68809eef3..273822e921 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -110,15 +110,15 @@ static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uin= t32_t ctr_idx) =20 /* Privilege mode filtering */ if ((env->priv =3D=3D PRV_M && - (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_MINH)) || + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) || (env->priv =3D=3D PRV_S && virt_on && - (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VSINH)) || + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VSINH)) || (env->priv =3D=3D PRV_U && virt_on && - (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VUINH)) || + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VUINH)) || (env->priv =3D=3D PRV_S && !virt_on && - (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_SINH)) || + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) || (env->priv =3D=3D PRV_U && !virt_on && - (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_UINH))) { + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) { return 0; } =20 @@ -128,8 +128,8 @@ static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint3= 2_t ctr_idx) counter->mhpmcounter_val =3D 0; counter->mhpmcounterh_val =3D 0; /* Generate interrupt only if OF bit is clear */ - if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) { - env->mhpmeventh_val[ctr_idx] |=3D MHPMEVENTH_BIT_OF; + if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) { + env->mhpmevent_val[ctr_idx] |=3D MHPMEVENT_BIT_OF; riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); } } else { @@ -420,41 +420,14 @@ int riscv_pmu_update_event_map(CPURISCVState *env, ui= nt64_t value, return 0; } =20 -static bool pmu_hpmevent_is_of_set(CPURISCVState *env, uint32_t ctr_idx) -{ - target_ulong mhpmevent_val; - uint64_t of_bit_mask; - - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - mhpmevent_val =3D env->mhpmeventh_val[ctr_idx]; - of_bit_mask =3D MHPMEVENTH_BIT_OF; - } else { - mhpmevent_val =3D env->mhpmevent_val[ctr_idx]; - of_bit_mask =3D MHPMEVENT_BIT_OF; - } - - return get_field(mhpmevent_val, of_bit_mask); -} - static bool pmu_hpmevent_set_of_if_clear(CPURISCVState *env, uint32_t ctr_= idx) { - target_ulong *mhpmevent_val; - uint64_t of_bit_mask; - - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - mhpmevent_val =3D &env->mhpmeventh_val[ctr_idx]; - of_bit_mask =3D MHPMEVENTH_BIT_OF; - } else { - mhpmevent_val =3D &env->mhpmevent_val[ctr_idx]; - of_bit_mask =3D MHPMEVENT_BIT_OF; - } - - if (!get_field(*mhpmevent_val, of_bit_mask)) { - *mhpmevent_val |=3D of_bit_mask; + if (!get_field(env->mhpmevent_val[ctr_idx], MHPMEVENT_BIT_OF)) { + env->mhpmevent_val[ctr_idx] |=3D MHPMEVENT_BIT_OF; return true; + } else { + return false; } - - return false; } =20 static void pmu_timer_trigger_irq(RISCVCPU *cpu, @@ -479,7 +452,7 @@ static void pmu_timer_trigger_irq(RISCVCPU *cpu, } =20 /* Generate interrupt only if OF bit is clear */ - if (pmu_hpmevent_is_of_set(env, ctr_idx)) { + if (get_field(env->mhpmevent_val[ctr_idx], MHPMEVENT_BIT_OF)) { return; } =20 @@ -538,7 +511,7 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t = value, uint32_t ctr_idx) =20 /* No need to setup a timer if LCOFI is disabled when OF is set */ if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscofpmf || - pmu_hpmevent_is_of_set(env, ctr_idx)) { + get_field(env->mhpmevent_val[ctr_idx], MHPMEVENT_BIT_OF)) { return -1; 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No real advantage is gained by keeping them separate, and combining them allows for slight simplification. Signed-off-by: Anton Johansson Reviewed-by: Alistair Francis Reviewed-by: Pierrick Bouvier Message-ID: <20251027181831.27016-7-anjo@rev.ng> Signed-off-by: Alistair Francis Message-ID: <20251103033713.904455-6-alistair.francis@wdc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 +-- target/riscv/csr.c | 28 +++++++++++++++++----------- 2 files changed, 18 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f9d2ebfb5d..2942fc1eda 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -420,8 +420,7 @@ struct CPUArchState { uint32_t mcountinhibit; =20 /* PMU cycle & instret privilege mode filtering */ - target_ulong mcyclecfg; - target_ulong mcyclecfgh; + uint64_t mcyclecfg; target_ulong minstretcfg; target_ulong minstretcfgh; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0af85c4309..e9e30384b4 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1061,7 +1061,8 @@ static RISCVException read_hpmcounterh(CPURISCVState = *env, int csrno, static RISCVException read_mcyclecfg(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->mcyclecfg; + bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32; + *val =3D extract64(env->mcyclecfg, 0, rv32 ? 32 : 64); return RISCV_EXCP_NONE; } =20 @@ -1071,7 +1072,7 @@ static RISCVException write_mcyclecfg(CPURISCVState *= env, int csrno, uint64_t inh_avail_mask; =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - env->mcyclecfg =3D val; + env->mcyclecfg =3D deposit64(env->mcyclecfg, 0, 32, val); } else { /* Set xINH fields if priv mode supported */ inh_avail_mask =3D ~MHPMEVENT_FILTER_MASK | MCYCLECFG_BIT_MINH; @@ -1090,7 +1091,7 @@ static RISCVException write_mcyclecfg(CPURISCVState *= env, int csrno, static RISCVException read_mcyclecfgh(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->mcyclecfgh; + *val =3D extract64(env->mcyclecfg, 32, 32); return RISCV_EXCP_NONE; } =20 @@ -1108,7 +1109,7 @@ static RISCVException write_mcyclecfgh(CPURISCVState = *env, int csrno, inh_avail_mask |=3D (riscv_has_ext(env, RVH) && riscv_has_ext(env, RVS)) ? MCYCLECFGH_BIT_VSINH : 0; =20 - env->mcyclecfgh =3D val & inh_avail_mask; + env->mcyclecfg =3D deposit64(env->mcyclecfg, 32, 32, val & inh_avail_m= ask); return RISCV_EXCP_NONE; } =20 @@ -1244,8 +1245,7 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters_= val(CPURISCVState *env, uint64_t cfg_val =3D 0; =20 if (counter_idx =3D=3D 0) { - cfg_val =3D upper_half ? ((uint64_t)env->mcyclecfgh << 32) : - env->mcyclecfg; + cfg_val =3D env->mcyclecfg; } else if (counter_idx =3D=3D 2) { cfg_val =3D upper_half ? ((uint64_t)env->minstretcfgh << 32) : env->minstretcfg; @@ -1525,8 +1525,12 @@ static int rmw_cd_mhpmeventh(CPURISCVState *env, int= evt_index, } =20 static int rmw_cd_ctr_cfg(CPURISCVState *env, int cfg_index, target_ulong = *val, - target_ulong new_val, target_ulong wr_mask) + target_ulong new_val, uint64_t wr_mask) { + /* + * wr_mask is 64-bit so upper 32 bits of mcyclecfg and minstretcfg + * are retained. + */ switch (cfg_index) { case 0: /* CYCLECFG */ if (wr_mask) { @@ -1552,8 +1556,9 @@ static int rmw_cd_ctr_cfg(CPURISCVState *env, int cfg= _index, target_ulong *val, } =20 static int rmw_cd_ctr_cfgh(CPURISCVState *env, int cfg_index, target_ulong= *val, - target_ulong new_val, target_ulong wr_mask) + target_ulong new_val, target_ulong wr_mask) { + uint64_t cfgh; =20 if (riscv_cpu_mxl(env) !=3D MXL_RV32) { return RISCV_EXCP_ILLEGAL_INST; @@ -1561,12 +1566,13 @@ static int rmw_cd_ctr_cfgh(CPURISCVState *env, int = cfg_index, target_ulong *val, =20 switch (cfg_index) { case 0: /* CYCLECFGH */ + cfgh =3D extract64(env->mcyclecfg, 32, 32); if (wr_mask) { wr_mask &=3D ~MCYCLECFGH_BIT_MINH; - env->mcyclecfgh =3D (new_val & wr_mask) | - (env->mcyclecfgh & ~wr_mask); + cfgh =3D (new_val & wr_mask) | (cfgh & ~wr_mask); + env->mcyclecfg =3D deposit64(env->mcyclecfg, 32, 32, cfgh); } else { - *val =3D env->mcyclecfgh; + *val =3D cfgh; } break; case 2: /* INSTRETCFGH */ --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767942665; cv=none; d=zohomail.com; s=zohoarc; b=aU+VUd3AaXPgs9UM81vsbeuFuVbhsvldGPcBCcgjWldi2TIv0oCUwuKlhpjgiBBn0Zcrz5w7Lf24uLQ7ZPu5odV3zxKX2n/w8eStaNpwzT5RvXInRUzsMSTTtlPezkr05B8l/xtSUzVkb2Lv+zqlY+1PpXpPQFmbNilCGUPRHeU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767942665; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=NkrFTEiLemIfD4lfrK8zSoqhMztc5LwCsgR75zu82b4=; b=FLWVdlrocDCIgVpdMfOTnILbmSLLzHqpZBUhhXP3o9prRIwsLsRf9Fql/nl4Ncr8cR+W2kTUKQoIU9i+U5DrpZSVtS65nfP7AP4rlrHjNrpieZohzjSHXuQKO9mgZ0EbJAtsIS/OIWG4KOoKYjzVuhkNzlLuiK4Lm+keIrIyvxI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767942665399456.811307196361; Thu, 8 Jan 2026 23:11:05 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ve6QQ-0005AE-Mm; Fri, 09 Jan 2026 01:56:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ve6Ph-00044j-V8 for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:56:02 -0500 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ve6Pg-0002rw-4D for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:56:01 -0500 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-81dbc0a99d2so381826b3a.1 for ; Thu, 08 Jan 2026 22:55:59 -0800 (PST) Received: from toolbx.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. 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No real advantage is gained by keeping them separate, and combining them allows for slight simplification. Signed-off-by: Anton Johansson Reviewed-by: Alistair Francis Reviewed-by: Pierrick Bouvier Message-ID: <20251027181831.27016-8-anjo@rev.ng> Signed-off-by: Alistair Francis Message-ID: <20251103033713.904455-7-alistair.francis@wdc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 +-- target/riscv/csr.c | 18 ++++++++++-------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2942fc1eda..b94c444678 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -421,8 +421,7 @@ struct CPUArchState { =20 /* PMU cycle & instret privilege mode filtering */ uint64_t mcyclecfg; - target_ulong minstretcfg; - target_ulong minstretcfgh; + uint64_t minstretcfg; =20 /* PMU counter state */ PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e9e30384b4..894ae4d7bf 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1116,7 +1116,8 @@ static RISCVException write_mcyclecfgh(CPURISCVState = *env, int csrno, static RISCVException read_minstretcfg(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->minstretcfg; + bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32; + *val =3D extract64(env->minstretcfg, 0, rv32 ? 32 : 64); return RISCV_EXCP_NONE; } =20 @@ -1143,7 +1144,7 @@ static RISCVException write_minstretcfg(CPURISCVState= *env, int csrno, static RISCVException read_minstretcfgh(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->minstretcfgh; + *val =3D extract64(env->minstretcfg, 32, 32); return RISCV_EXCP_NONE; } =20 @@ -1160,7 +1161,8 @@ static RISCVException write_minstretcfgh(CPURISCVStat= e *env, int csrno, inh_avail_mask |=3D (riscv_has_ext(env, RVH) && riscv_has_ext(env, RVS)) ? MINSTRETCFGH_BIT_VSINH := 0; =20 - env->minstretcfgh =3D val & inh_avail_mask; + env->minstretcfg =3D deposit64(env->minstretcfg, 32, 32, + val & inh_avail_mask); return RISCV_EXCP_NONE; } =20 @@ -1247,8 +1249,7 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters_= val(CPURISCVState *env, if (counter_idx =3D=3D 0) { cfg_val =3D env->mcyclecfg; } else if (counter_idx =3D=3D 2) { - cfg_val =3D upper_half ? ((uint64_t)env->minstretcfgh << 32) : - env->minstretcfg; + cfg_val =3D env->minstretcfg; } else { cfg_val =3D env->mhpmevent_val[counter_idx]; cfg_val &=3D MHPMEVENT_FILTER_MASK; @@ -1576,12 +1577,13 @@ static int rmw_cd_ctr_cfgh(CPURISCVState *env, int = cfg_index, target_ulong *val, } break; case 2: /* INSTRETCFGH */ + cfgh =3D extract64(env->minstretcfg, 32, 32); if (wr_mask) { wr_mask &=3D ~MINSTRETCFGH_BIT_MINH; - env->minstretcfgh =3D (new_val & wr_mask) | - (env->minstretcfgh & ~wr_mask); + cfgh =3D (new_val & wr_mask) | (cfgh & ~wr_mask); + env->minstretcfg =3D deposit64(env->minstretcfg, 32, 32, cfgh); } else { - *val =3D env->minstretcfgh; + *val =3D cfgh; } break; default: --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767941922; cv=none; d=zohomail.com; s=zohoarc; b=XoVor5nWTOOIFMBD3+fuhqrEV7itqbxq7C/SbZTVmLya5woQV1cZhxveYh82CPGcgj3yhl+6bACEYnm9CH96LxObKg2zYH52FBs3vYm4QfPag0HcWaXoeW4Sx8LWdkaQpcFXB9DnopszHmXWhhsEEUawp2410AhZ3yXDapAyHyE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767941922; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JhSM44iRXsRS2SVISWdkH78+0dD+mTHwJ1Ir7bvefYU=; b=GDgf/ILV5/7ECKzecOhRXztEl7YfYAA8XdI9SOlkGGSjRyNzJnH+Szq7VVC/psPS1bCvm9rJdiuVoLOvlmdwRISCWNQAwKPje6PQn0xzhb3ki+NOX/fuEvZQImeeiRiBWwBTo23zKq/Ng6GIv/pdQe+z5TynAMAfNWU5YhAmZUI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767941922874809.634997767929; Thu, 8 Jan 2026 22:58:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ve6QW-0005GI-Ck; Fri, 09 Jan 2026 01:56:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ve6Pk-00047d-LD for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:56:07 -0500 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ve6Pi-0002s6-Gc for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:56:04 -0500 Received: by mail-pg1-x52b.google.com with SMTP id 41be03b00d2f7-c4464dfeae8so2638581a12.3 for ; Thu, 08 Jan 2026 22:56:02 -0800 (PST) Received: from toolbx.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. 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No real advantage is gained by keeping them separate, and combining allows for slight simplification. Note, the cpu/pmu VMSTATE version is bumped breaking migration from older versions. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Alistair Francis Message-ID: <20251027181831.27016-9-anjo@rev.ng> Signed-off-by: Alistair Francis Message-ID: <20251103033713.904455-8-alistair.francis@wdc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 10 ++-- target/riscv/csr.c | 76 ++++++++++++++-------------- target/riscv/machine.c | 10 ++-- target/riscv/pmu.c | 111 +++++++++++------------------------------ 4 files changed, 73 insertions(+), 134 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b94c444678..0939e6f08c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -196,13 +196,9 @@ FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - = 11) =20 typedef struct PMUCTRState { /* Current value of a counter */ - target_ulong mhpmcounter_val; - /* Current value of a counter in RV32 */ - target_ulong mhpmcounterh_val; - /* Snapshot values of counter */ - target_ulong mhpmcounter_prev; - /* Snapshort value of a counter in RV32 */ - target_ulong mhpmcounterh_prev; + uint64_t mhpmcounter_val; + /* Snapshot value of a counter */ + uint64_t mhpmcounter_prev; /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigge= r */ target_ulong irq_overflow_left; } PMUCTRState; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 894ae4d7bf..4ef9e9c377 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1302,24 +1302,27 @@ static RISCVException riscv_pmu_write_ctr(CPURISCVS= tate *env, target_ulong val, uint32_t ctr_idx) { PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; - uint64_t mhpmctr_val =3D val; + bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32; + int deposit_size =3D rv32 ? 32 : 64; + uint64_t ctr; + + counter->mhpmcounter_val =3D deposit64(counter->mhpmcounter_val, + 0, deposit_size, val); =20 - counter->mhpmcounter_val =3D val; if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { - counter->mhpmcounter_prev =3D riscv_pmu_ctr_get_fixed_counters_val= (env, - ctr_idx, f= alse); + ctr =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx, false); + counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, + 0, deposit_size, ctr); if (ctr_idx > 2) { - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - mhpmctr_val =3D mhpmctr_val | - ((uint64_t)counter->mhpmcounterh_val << 32); - } - riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); + riscv_pmu_setup_timer(env, counter->mhpmcounter_val, ctr_idx); } } else { /* Other counters can keep incrementing from the given value */ - counter->mhpmcounter_prev =3D val; + counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, + 0, deposit_size, val); + } =20 return RISCV_EXCP_NONE; @@ -1329,21 +1332,22 @@ static RISCVException riscv_pmu_write_ctrh(CPURISCV= State *env, target_ulong val, uint32_t ctr_idx) { PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; - uint64_t mhpmctr_val =3D counter->mhpmcounter_val; - uint64_t mhpmctrh_val =3D val; + uint64_t ctrh; =20 - counter->mhpmcounterh_val =3D val; - mhpmctr_val =3D mhpmctr_val | (mhpmctrh_val << 32); + counter->mhpmcounter_val =3D deposit64(counter->mhpmcounter_val, + 32, 32, val); if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { - counter->mhpmcounterh_prev =3D riscv_pmu_ctr_get_fixed_counters_va= l(env, - ctr_idx, = true); + ctrh =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx, true); + counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, + 32, 32, ctrh); if (ctr_idx > 2) { - riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); + riscv_pmu_setup_timer(env, counter->mhpmcounter_val, ctr_idx); } } else { - counter->mhpmcounterh_prev =3D val; + counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, + 32, 32, val); } =20 return RISCV_EXCP_NONE; @@ -1366,13 +1370,19 @@ static RISCVException write_mhpmcounterh(CPURISCVSt= ate *env, int csrno, } =20 RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, - bool upper_half, uint32_t ctr_idx) + bool upper_half, uint32_t ctr_idx) { PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; - target_ulong ctr_prev =3D upper_half ? counter->mhpmcounterh_prev : - counter->mhpmcounter_prev; - target_ulong ctr_val =3D upper_half ? counter->mhpmcounterh_val : - counter->mhpmcounter_val; + bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32; + int start =3D upper_half ? 32 : 0; + int length =3D rv32 ? 32 : 64; + uint64_t ctr_prev, ctr_val; + + /* Ensure upper_half is only set for XLEN =3D=3D 32 */ + g_assert(rv32 || !upper_half); + + ctr_prev =3D extract64(counter->mhpmcounter_prev, start, length); + ctr_val =3D extract64(counter->mhpmcounter_val, start, length); =20 if (get_field(env->mcountinhibit, BIT(ctr_idx))) { /* @@ -2996,6 +3006,7 @@ static RISCVException write_mcountinhibit(CPURISCVSta= te *env, int csrno, uint32_t present_ctrs =3D cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTER= EN_IR; target_ulong updated_ctrs =3D (env->mcountinhibit ^ val) & present_ctr= s; uint64_t mhpmctr_val, prev_count, curr_count; + uint64_t ctrh; =20 /* WARL register - disable unavailable counters; TM bit is always 0 */ env->mcountinhibit =3D val & present_ctrs; @@ -3014,17 +3025,13 @@ static RISCVException write_mcountinhibit(CPURISCVS= tate *env, int csrno, counter->mhpmcounter_prev =3D riscv_pmu_ctr_get_fixed_counters_val(env, cidx, false); if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - counter->mhpmcounterh_prev =3D - riscv_pmu_ctr_get_fixed_counters_val(env, cidx, true); + ctrh =3D riscv_pmu_ctr_get_fixed_counters_val(env, cidx, t= rue); + counter->mhpmcounter_prev =3D deposit64(counter->mhpmcount= er_prev, + 32, 32, ctrh); } =20 if (cidx > 2) { - mhpmctr_val =3D counter->mhpmcounter_val; - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - mhpmctr_val =3D mhpmctr_val | - ((uint64_t)counter->mhpmcounterh_val << 32); - } - riscv_pmu_setup_timer(env, mhpmctr_val, cidx); + riscv_pmu_setup_timer(env, counter->mhpmcounter_val, cidx); } } else { curr_count =3D riscv_pmu_ctr_get_fixed_counters_val(env, cidx,= false); @@ -3036,18 +3043,11 @@ static RISCVException write_mcountinhibit(CPURISCVS= tate *env, int csrno, riscv_pmu_ctr_get_fixed_counters_val(env, cidx, true); =20 curr_count =3D curr_count | (tmp << 32); - mhpmctr_val =3D mhpmctr_val | - ((uint64_t)counter->mhpmcounterh_val << 32); - prev_count =3D prev_count | - ((uint64_t)counter->mhpmcounterh_prev << 32); } =20 /* Adjust the counter for later reads. */ mhpmctr_val =3D curr_count - prev_count + mhpmctr_val; counter->mhpmcounter_val =3D mhpmctr_val; - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - counter->mhpmcounterh_val =3D mhpmctr_val >> 32; - } } } =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 6146124229..09c032a879 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -335,14 +335,12 @@ static bool pmu_needed(void *opaque) =20 static const VMStateDescription vmstate_pmu_ctr_state =3D { .name =3D "cpu/pmu", - .version_id =3D 2, - .minimum_version_id =3D 2, + .version_id =3D 3, + .minimum_version_id =3D 3, .needed =3D pmu_needed, .fields =3D (const VMStateField[]) { - VMSTATE_UINTTL(mhpmcounter_val, PMUCTRState), - VMSTATE_UINTTL(mhpmcounterh_val, PMUCTRState), - VMSTATE_UINTTL(mhpmcounter_prev, PMUCTRState), - VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState), + VMSTATE_UINT64(mhpmcounter_val, PMUCTRState), + VMSTATE_UINT64(mhpmcounter_prev, PMUCTRState), VMSTATE_END_OF_LIST() } }; diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 273822e921..708f2ec7aa 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -101,82 +101,6 @@ static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, u= int32_t ctr_idx) } } =20 -static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx) -{ - CPURISCVState *env =3D &cpu->env; - target_ulong max_val =3D UINT32_MAX; - PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; - bool virt_on =3D env->virt_enabled; - - /* Privilege mode filtering */ - if ((env->priv =3D=3D PRV_M && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) || - (env->priv =3D=3D PRV_S && virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VSINH)) || - (env->priv =3D=3D PRV_U && virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VUINH)) || - (env->priv =3D=3D PRV_S && !virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) || - (env->priv =3D=3D PRV_U && !virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) { - return 0; - } - - /* Handle the overflow scenario */ - if (counter->mhpmcounter_val =3D=3D max_val) { - if (counter->mhpmcounterh_val =3D=3D max_val) { - counter->mhpmcounter_val =3D 0; - counter->mhpmcounterh_val =3D 0; - /* Generate interrupt only if OF bit is clear */ - if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) { - env->mhpmevent_val[ctr_idx] |=3D MHPMEVENT_BIT_OF; - riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); - } - } else { - counter->mhpmcounterh_val++; - } - } else { - counter->mhpmcounter_val++; - } - - return 0; -} - -static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx) -{ - CPURISCVState *env =3D &cpu->env; - PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; - uint64_t max_val =3D UINT64_MAX; - bool virt_on =3D env->virt_enabled; - - /* Privilege mode filtering */ - if ((env->priv =3D=3D PRV_M && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) || - (env->priv =3D=3D PRV_S && virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VSINH)) || - (env->priv =3D=3D PRV_U && virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VUINH)) || - (env->priv =3D=3D PRV_S && !virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) || - (env->priv =3D=3D PRV_U && !virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) { - return 0; - } - - /* Handle the overflow scenario */ - if (counter->mhpmcounter_val =3D=3D max_val) { - counter->mhpmcounter_val =3D 0; - /* Generate interrupt only if OF bit is clear */ - if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) { - env->mhpmevent_val[ctr_idx] |=3D MHPMEVENT_BIT_OF; - riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); - } - } else { - counter->mhpmcounter_val++; - } - return 0; -} - /* * Information needed to update counters: * new_priv, new_virt: To correctly save starting snapshot for the newly @@ -275,8 +199,10 @@ void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, t= arget_ulong newpriv, int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) { uint32_t ctr_idx; - int ret; CPURISCVState *env =3D &cpu->env; + uint64_t max_val =3D UINT64_MAX; + bool virt_on =3D env->virt_enabled; + PMUCTRState *counter; gpointer value; =20 if (!cpu->cfg.pmu_mask) { @@ -293,13 +219,34 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_= event_idx event_idx) return -1; } =20 - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - ret =3D riscv_pmu_incr_ctr_rv32(cpu, ctr_idx); + /* Privilege mode filtering */ + if ((env->priv =3D=3D PRV_M && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) || + (env->priv =3D=3D PRV_S && virt_on && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VSINH)) || + (env->priv =3D=3D PRV_U && virt_on && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VUINH)) || + (env->priv =3D=3D PRV_S && !virt_on && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) || + (env->priv =3D=3D PRV_U && !virt_on && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) { + return 0; + } + + /* Handle the overflow scenario */ + counter =3D &env->pmu_ctrs[ctr_idx]; + if (counter->mhpmcounter_val =3D=3D max_val) { + counter->mhpmcounter_val =3D 0; + /* Generate interrupt only if OF bit is clear */ + if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) { + env->mhpmevent_val[ctr_idx] |=3D MHPMEVENT_BIT_OF; + riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); + } } else { - ret =3D riscv_pmu_incr_ctr_rv64(cpu, ctr_idx); + counter->mhpmcounter_val++; } =20 - return ret; + return 0; } =20 bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, @@ -470,8 +417,6 @@ static void pmu_timer_trigger_irq(RISCVCPU *cpu, if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { riscv_pmu_read_ctr(env, (target_ulong *)&curr_ctrh_val, true, ctr_= idx); curr_ctr_val =3D curr_ctr_val | (curr_ctrh_val << 32); - ctr_val =3D ctr_val | - ((uint64_t)counter->mhpmcounterh_val << 32); } =20 /* --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767942102; cv=none; d=zohomail.com; s=zohoarc; b=E/6Sdws+ewpOxOVZK4Kw6NxOXijayaT7ou8M1SIsp5ZS9xHI6MylDP0/utcZxkDdp+aJBTdUZu3RpOoHuvuJ2Oqsbp1IcZWr8ZlkBgZWezt1Sf4TigmCmgxOduwJOALM5IREeKEOnRKK0sH05lp2Q0qLyWebuNqoGqL+IoGGShI= ARC-Message-Signature: i=1; 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Signed-off-by: Alistair Francis Reviewed-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20251103033713.904455-9-alistair.francis@wdc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 40 +++++++++------------------------------- 1 file changed, 9 insertions(+), 31 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4ef9e9c377..05c7ec8352 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1235,14 +1235,12 @@ static RISCVException write_mhpmeventh(CPURISCVStat= e *env, int csrno, return RISCV_EXCP_NONE; } =20 -static target_ulong riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *en= v, - int counter_idx, - bool upper_half) +static uint64_t riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *env, + int counter_idx) { int inst =3D riscv_pmu_ctr_monitor_instructions(env, counter_idx); uint64_t *counter_arr_virt =3D env->pmu_fixed_ctrs[inst].counter_virt; uint64_t *counter_arr =3D env->pmu_fixed_ctrs[inst].counter; - target_ulong result =3D 0; uint64_t curr_val =3D 0; uint64_t cfg_val =3D 0; =20 @@ -1262,7 +1260,7 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters_= val(CPURISCVState *env, curr_val =3D cpu_get_host_ticks(); } =20 - goto done; + return curr_val; } =20 /* Update counter before reading. */ @@ -1288,14 +1286,7 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters= _val(CPURISCVState *env, curr_val +=3D counter_arr_virt[PRV_U]; } =20 -done: - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - result =3D upper_half ? curr_val >> 32 : curr_val; - } else { - result =3D curr_val; - } - - return result; + return curr_val; } =20 static RISCVException riscv_pmu_write_ctr(CPURISCVState *env, target_ulong= val, @@ -1312,7 +1303,7 @@ static RISCVException riscv_pmu_write_ctr(CPURISCVSta= te *env, target_ulong val, if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { - ctr =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx, false); + ctr =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx); counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, 0, deposit_size, ctr); if (ctr_idx > 2) { @@ -1339,7 +1330,7 @@ static RISCVException riscv_pmu_write_ctrh(CPURISCVSt= ate *env, target_ulong val, if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { - ctrh =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx, true); + ctrh =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx); counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, 32, 32, ctrh); if (ctr_idx > 2) { @@ -1399,7 +1390,7 @@ RISCVException riscv_pmu_read_ctr(CPURISCVState *env,= target_ulong *val, */ if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { - *val =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx, upper_= half) - + *val =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx) - ctr_prev + ctr_val; } else { *val =3D ctr_val; @@ -3006,7 +2997,6 @@ static RISCVException write_mcountinhibit(CPURISCVSta= te *env, int csrno, uint32_t present_ctrs =3D cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTER= EN_IR; target_ulong updated_ctrs =3D (env->mcountinhibit ^ val) & present_ctr= s; uint64_t mhpmctr_val, prev_count, curr_count; - uint64_t ctrh; =20 /* WARL register - disable unavailable counters; TM bit is always 0 */ env->mcountinhibit =3D val & present_ctrs; @@ -3022,28 +3012,16 @@ static RISCVException write_mcountinhibit(CPURISCVS= tate *env, int csrno, counter =3D &env->pmu_ctrs[cidx]; =20 if (!get_field(env->mcountinhibit, BIT(cidx))) { - counter->mhpmcounter_prev =3D - riscv_pmu_ctr_get_fixed_counters_val(env, cidx, false); - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - ctrh =3D riscv_pmu_ctr_get_fixed_counters_val(env, cidx, t= rue); - counter->mhpmcounter_prev =3D deposit64(counter->mhpmcount= er_prev, - 32, 32, ctrh); - } + counter->mhpmcounter_prev =3D riscv_pmu_ctr_get_fixed_counters= _val(env, cidx); =20 if (cidx > 2) { riscv_pmu_setup_timer(env, counter->mhpmcounter_val, cidx); } } else { - curr_count =3D riscv_pmu_ctr_get_fixed_counters_val(env, cidx,= false); + curr_count =3D riscv_pmu_ctr_get_fixed_counters_val(env, cidx); =20 mhpmctr_val =3D counter->mhpmcounter_val; prev_count =3D counter->mhpmcounter_prev; - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - uint64_t tmp =3D - riscv_pmu_ctr_get_fixed_counters_val(env, cidx, true); - - curr_count =3D curr_count | (tmp << 32); - } =20 /* Adjust the counter for later reads. */ mhpmctr_val =3D curr_count - prev_count + mhpmctr_val; --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767941929; cv=none; d=zohomail.com; s=zohoarc; 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A source is inactive if it is delegated to a child domain or its source mode is INACTIVE. The previous implementation only checked SM =3D=3D INACTIVE. This patch adds full compliance: - Return zero on read if D =3D=3D 1 or SM =3D=3D INACTIVE - Ignore writes in both cases Fixes: b6f1244678 ("intc/riscv_aplic: Fix target register read when source = is inactive") Signed-off-by: Nikita Novikov Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <20251029-n-novikov-aplic_aia_ro-v1-1-39fec74c918a@syntacore.co= m> Signed-off-by: Alistair Francis --- hw/intc/riscv_aplic.c | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 92ff0ecaa7..cf6c4148a3 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -193,6 +193,26 @@ void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *a= plic, hwaddr addr) #endif } =20 +/* + * APLIC target[i] must be read-only zero if the source i is inactive + * in this domain (delegated or SM =3D=3D INACTIVE) + */ +static inline bool riscv_aplic_source_active(RISCVAPLICState *aplic, + uint32_t irq) +{ + uint32_t sc, sm; + + if ((irq =3D=3D 0) || (aplic->num_irqs <=3D irq)) { + return false; + } + sc =3D aplic->sourcecfg[irq]; + if (sc & APLIC_SOURCECFG_D) { + return false; + } + sm =3D sc & APLIC_SOURCECFG_SM_MASK; + return sm !=3D APLIC_SOURCECFG_SM_INACTIVE; +} + static bool riscv_aplic_irq_rectified_val(RISCVAPLICState *aplic, uint32_t irq) { @@ -635,7 +655,7 @@ static void riscv_aplic_request(void *opaque, int irq, = int level) =20 static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size) { - uint32_t irq, word, idc, sm; + uint32_t irq, word, idc; RISCVAPLICState *aplic =3D opaque; =20 /* Reads must be 4 byte words */ @@ -703,8 +723,7 @@ static uint64_t riscv_aplic_read(void *opaque, hwaddr a= ddr, unsigned size) } else if ((APLIC_TARGET_BASE <=3D addr) && (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) { irq =3D ((addr - APLIC_TARGET_BASE) >> 2) + 1; - sm =3D aplic->sourcecfg[irq] & APLIC_SOURCECFG_SM_MASK; - if (sm =3D=3D APLIC_SOURCECFG_SM_INACTIVE) { + if (!riscv_aplic_source_active(aplic, irq)) { return 0; } return aplic->target[irq]; @@ -841,6 +860,9 @@ static void riscv_aplic_write(void *opaque, hwaddr addr= , uint64_t value, } else if ((APLIC_TARGET_BASE <=3D addr) && (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) { irq =3D ((addr - APLIC_TARGET_BASE) >> 2) + 1; + if (!riscv_aplic_source_active(aplic, irq)) { + return; + } if (aplic->msimode) { aplic->target[irq] =3D value; } else { --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767942148; cv=none; d=zohomail.com; s=zohoarc; b=VQAdMWzqdjjfAHY6AVyoObwtqqqoVqRdutt9UZU3eSlCVlL4lWEWnbpfRXc5PE/iTPBhLnPzn79x4wvbixnPLdZ70t8l24Y5ZJKKBZGU9OVh6VrUkwmd8pPr34nHaROkf/e7O068oUXNZqueDp28jSbMeIBCvYrYIFRmfb14sEI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767942148; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/I2ae6W/g5Y8Bus0uQM50dGXtk4AiQeiFr067MHCGJI=; b=NiVmf8WaH/UAqmFDTL8IOjylJ6ppe9cvozFkM/v101ncp/1pNASG3OpR4jKYKo5HN0MWPedE+leZSaqSQl72Ode+LqtUZpKMxGlnmKigcRmFH1ND3NPodhQ6fgtqNjx/IRUC5xVwWqgf0e2XGBuvlMCGhJxYP/s7qJm1MwY1dsw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767942148874568.1251970017256; Thu, 8 Jan 2026 23:02:28 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ve6RG-0005tt-0Z; Fri, 09 Jan 2026 01:57:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ve6Py-0004HZ-Aa for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:56:18 -0500 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ve6Pw-0002st-AC for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:56:18 -0500 Received: by mail-pg1-x529.google.com with SMTP id 41be03b00d2f7-c026e074373so2039520a12.1 for ; Thu, 08 Jan 2026 22:56:12 -0800 (PST) Received: from toolbx.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. 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Signed-off-by: Nikita Novikov Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <20251029-n-novikov-aplic_aia_ro-v1-2-39fec74c918a@syntacore.co= m> Signed-off-by: Alistair Francis --- hw/intc/riscv_aplic.c | 44 +++++++------------------------------------ 1 file changed, 7 insertions(+), 37 deletions(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index cf6c4148a3..8f70043111 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -216,22 +216,13 @@ static inline bool riscv_aplic_source_active(RISCVAPL= ICState *aplic, static bool riscv_aplic_irq_rectified_val(RISCVAPLICState *aplic, uint32_t irq) { - uint32_t sourcecfg, sm, raw_input, irq_inverted; + uint32_t sm, raw_input, irq_inverted; =20 - if (!irq || aplic->num_irqs <=3D irq) { - return false; - } - - sourcecfg =3D aplic->sourcecfg[irq]; - if (sourcecfg & APLIC_SOURCECFG_D) { - return false; - } - - sm =3D sourcecfg & APLIC_SOURCECFG_SM_MASK; - if (sm =3D=3D APLIC_SOURCECFG_SM_INACTIVE) { + if (!riscv_aplic_source_active(aplic, irq)) { return false; } =20 + sm =3D aplic->sourcecfg[irq] & APLIC_SOURCECFG_SM_MASK; raw_input =3D (aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0; irq_inverted =3D (sm =3D=3D APLIC_SOURCECFG_SM_LEVEL_LOW || sm =3D=3D APLIC_SOURCECFG_SM_EDGE_FALL) ? 1 : 0; @@ -284,22 +275,13 @@ static void riscv_aplic_set_pending_raw(RISCVAPLICSta= te *aplic, static void riscv_aplic_set_pending(RISCVAPLICState *aplic, uint32_t irq, bool pending) { - uint32_t sourcecfg, sm; + uint32_t sm; =20 - if ((irq <=3D 0) || (aplic->num_irqs <=3D irq)) { - return; - } - - sourcecfg =3D aplic->sourcecfg[irq]; - if (sourcecfg & APLIC_SOURCECFG_D) { - return; - } - - sm =3D sourcecfg & APLIC_SOURCECFG_SM_MASK; - if (sm =3D=3D APLIC_SOURCECFG_SM_INACTIVE) { + if (!riscv_aplic_source_active(aplic, irq)) { return; } =20 + sm =3D aplic->sourcecfg[irq] & APLIC_SOURCECFG_SM_MASK; if ((sm =3D=3D APLIC_SOURCECFG_SM_LEVEL_HIGH) || (sm =3D=3D APLIC_SOURCECFG_SM_LEVEL_LOW)) { if (!aplic->msimode) { @@ -370,19 +352,7 @@ static void riscv_aplic_set_enabled_raw(RISCVAPLICStat= e *aplic, static void riscv_aplic_set_enabled(RISCVAPLICState *aplic, uint32_t irq, bool enabled) { - uint32_t sourcecfg, sm; - - if ((irq <=3D 0) || (aplic->num_irqs <=3D irq)) { - return; - } - - sourcecfg =3D aplic->sourcecfg[irq]; - if (sourcecfg & APLIC_SOURCECFG_D) { - return; - } - - sm =3D sourcecfg & APLIC_SOURCECFG_SM_MASK; - if (sm =3D=3D APLIC_SOURCECFG_SM_INACTIVE) { + if (!riscv_aplic_source_active(aplic, irq)) { return; } =20 --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767942153; cv=none; d=zohomail.com; s=zohoarc; b=BGCa+7QXcpVil8FQFdsei+I1YE6a1VV5m8jZyWokuEG461ZH+WVvhI71crFxtyJGEoiMqZDucEPP3rz9MlCfpzYREl7m23/pwjEr/Ie0m5OVve00LS9zuEnaV4Lii2alif1z8uAQY89zzkmmI+XrJkZ5uImrVnxqz/N4zLmd5uc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767942153; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fsAe4IlyePu7Wh/22qQPwxy3w2E4OsZSEQYaosoGNL0=; b=XyeGpPUcJ/Qrx13GVX070dszU/FVkr42uE6P1u6qqt6ugFEzF+cBedhuOOlGlx7pOQ2wOV+4DBjwP9kJhsRz/kRf9srOyaqRphqskMrAklMgPAA5AXtJ03X8778X0f+mulf/KTZn0vBXc2mSyfpL93XBWk1YNYDWP6jnLvJiUsU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767942153536725.4062274531082; Thu, 8 Jan 2026 23:02:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ve6Qu-0005SV-OM; Fri, 09 Jan 2026 01:57:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ve6Py-0004Ha-D9 for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:56:19 -0500 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ve6Pw-0002sy-Tv for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:56:18 -0500 Received: by mail-pg1-x530.google.com with SMTP id 41be03b00d2f7-c47ee987401so1202066a12.1 for ; Thu, 08 Jan 2026 22:56:15 -0800 (PST) Received: from toolbx.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c4cc02ecfaasm9953644a12.14.2026.01.08.22.56.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 22:56:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1767941774; x=1768546574; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fsAe4IlyePu7Wh/22qQPwxy3w2E4OsZSEQYaosoGNL0=; b=U/NcmQW+Dyo3kTPXqcFgvI+q4topLnKP6JXrofo9WnRlM6L1Shb2mcIK01gqf4GQ2A asHB0JJTzcJFcYJxkJRKU8JWD/yY8CoacyMGEon5vbIgRPr6kJiZeJHLeLU1mwOpliow aco+EE2jCtXzwQyenONVrM9dAQEG0sqQztAplcd6+avdAoy0/BWkZgt/IBB+LFLJvoJ1 gkNtmv2ia0SOOWl+aDeyHkfTTS1Pt/osAnG/Wee5dHlfOcv1ZJb1L5auSxyG9NWdpWeJ os/0MPpDSOjbYYofgWo9sV98r2wd+tRKTUEbubfD3ENrGyclFGPG3b/N89cGKPMJAMmd 6TPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767941774; x=1768546574; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=fsAe4IlyePu7Wh/22qQPwxy3w2E4OsZSEQYaosoGNL0=; b=bEBa+IT0UBe5O43iSJNJ/+jvWrEVANI70zr9RQsCiElCXDrr2bzzT1VxuhKd5j3u3w 8sUDiUwxq8F5nY9BpaJMYHEryI6j2hoLg8vzu4ABI0oGeZLULgEIwH79I4Aof8v7vo2J gP8yycgVlghfxC6Jw15rjPDcSXMi7UWXwCmUDGiMBwG29XTtgThSNoxPN8vl/cdMUwDF mGhN8o7tUUR85JK/vy02ApUtdONmkaPyLIDWl7c6Cm2R8K+IK8e2ZkC/jT7ZcbDMIc6D UV5UTGpfLYd7QqEZGLouCiFfppApiSZyYZneATjApUlOFleeO8fWfQUyxHQ9QhILRL3X p3fw== X-Gm-Message-State: AOJu0YwO7jF/Ssl0EIRLM9T1eKLoOOLfL8+r41MhkSDPmshhFh5G7pZC Rf5FKVx+Djq6NsZoF+MR3bPfZ/PshsRPa+gEjslae0fWZUPetlImLf7hWZKxFw== X-Gm-Gg: AY/fxX7XrPtuHfAkqQsLXRJPuk9/8nbdQtVsBpmEsF8DgXcKdlyYR4AtvHgPWNMAwoY jG8j12IJnrMm5SGbEj5PMMo69DFJRxqkX9gUSg0dCY9mS7WmSd+jfyRjQ0fhGpfscAiGwo1td3Y l7cUUy2jCI+opgnnpCxZG67In6nj3eCU6g/OX9VEjkIIhD0frPoVtkOfcH2w+0/p9agCKUeUkip J/2/KLp5o/mAh3wwBz6Xnlrox5Hh4HQXuhZf0pD4Rx7FgSfMJvIHRMqA95jR7QPkiofCaOXYhXE 9nTsU6E3Yii8c3C5Tg0S7ZGAsn8q+00ubMDoSQeJ/Q4tKGuMhEpXtgFVwdiAJ2lrXqKSvW/8pjL TzG+bg8dLFJL+4+IZtPNXyYtoggsdKpuMKXm4s0olZapkOPMHVfrrHTu0jRrFzktnszge6JNUud 8w9PJkueSz61znbLq4J8QYfHQt9w0Byo/ZeSnyhWEc+XhQKzElSFXvnVI0fiuPqCT2sVStXil+U thGywTS2pfml2cDCu0= X-Google-Smtp-Source: AGHT+IHxcBB0/dJSPa8fGxOIAWv5iOuWAttEquhsLcfaKwSW8/l5U+0BoQG8LxtdoyBWPBoHbQsbyw== X-Received: by 2002:a05:6a20:1591:b0:368:9449:8364 with SMTP id adf61e73a8af0-3898e9e72a5mr9238466637.9.1767941774122; Thu, 08 Jan 2026 22:56:14 -0800 (PST) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Frank Chang , Alistair Francis , Daniel Henrique Barboza , Jim Shu Subject: [PULL 20/34] hw/riscv: riscv-iommu: Don't look up DDT cache in Off and Bare modes Date: Fri, 9 Jan 2026 16:54:45 +1000 Message-ID: <20260109065459.19987-21-alistair.francis@wdc.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20260109065459.19987-1-alistair.francis@wdc.com> References: <20260109065459.19987-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=alistair23@gmail.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1767942154419158500 Content-Type: text/plain; charset="utf-8" From: Frank Chang According to the RISC-V IOMMU specification: * When ddtp.iommu_mode is set to Off, there is no DDT look-up, and an "All inbound transactions disallowed" fault (cause =3D 256) is reported for any inbound transaction. * When ddtp.iommu_mode is set to Bare, there is no DDT look-up, and the translated address is the same as the IOVA, unless the transaction type is disallowed (cause =3D 260). In the current implementation, the DDT cache is incorrectly looked up even when ddtp.iommu_mode is set to Off or Bare. This may result in unintended cache hits. Therefore, the DDT cache must not be looked up when ddtp.iommu_mode is set to Off or Bare. For other modes, software is required to issue cache invalidation commands before any inbound transactions. Signed-off-by: Frank Chang Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Jim Shu Message-ID: <20251028085032.2053569-1-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 01730109c7..b46b337375 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -1292,13 +1292,18 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMM= UState *s, .devid =3D devid, .process_id =3D process_id, }; + unsigned mode =3D get_field(s->ddtp, RISCV_IOMMU_DDTP_MODE); =20 ctx_cache =3D g_hash_table_ref(s->ctx_cache); - ctx =3D g_hash_table_lookup(ctx_cache, &key); =20 - if (ctx && (ctx->tc & RISCV_IOMMU_DC_TC_V)) { - *ref =3D ctx_cache; - return ctx; + if (mode !=3D RISCV_IOMMU_DDTP_MODE_OFF && + mode !=3D RISCV_IOMMU_DDTP_MODE_BARE) { + ctx =3D g_hash_table_lookup(ctx_cache, &key); + + if (ctx && (ctx->tc & RISCV_IOMMU_DC_TC_V)) { + *ref =3D ctx_cache; + return ctx; + } } =20 ctx =3D g_new0(RISCVIOMMUContext, 1); --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767942146; cv=none; d=zohomail.com; s=zohoarc; b=fYJkgqFIvoBZpSJymF8e3UIi/3SnQ5gSyFdzimoxM+WE2FExI3OzurJIDXssnvbTf0RKsu84yff9qd6XlpSYMuonWb9pyz34PBLwKCKny6yAFDyhPu5GWPIzJ2fh1/ZQvsBnArZB7LzuGnwM2fWhi1tJBOAhyOvTMSqGowgPu8A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767942146; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=POiDnI8BIOUkZ2LDLAStq+imox0YEbmN0To2N6UkRIc=; b=ftC9Ofr3ZNMPecCXxN23fSAiUodD9eahjYVWemyEBAvzI/+PdF8BxfIr25VD2fawPRfgITNYYHQoBjNFZUSooO48U2dB1/xi1dBWM8Rlwccbw77A3aORazI6bAbUfOnbPtb6slarJYe6OaI1MZWMe+z8jjmFUx1t0BMpK1vQsgg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767942145997879.2885215537931; Thu, 8 Jan 2026 23:02:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ve6RE-0005kn-21; Fri, 09 Jan 2026 01:57:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ve6Q2-0004bZ-Sa for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:56:23 -0500 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ve6Pz-0002tH-Tw for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:56:22 -0500 Received: by mail-pg1-x52d.google.com with SMTP id 41be03b00d2f7-bc274b8b15bso2586491a12.1 for ; Thu, 08 Jan 2026 22:56:19 -0800 (PST) Received: from toolbx.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. 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In-Reply-To: <20260109065459.19987-1-alistair.francis@wdc.com> References: <20260109065459.19987-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1767942146507158500 Content-Type: text/plain; charset="utf-8" From: lxx <1733205434@qq.com> This patch adds support for the Zilsd and Zclsd extension, which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v1= .0 Signed-off-by: LIU Xu Co-developed-by: SUN Dongya Co-developed-by: ZHAO Fujin Reviewed-by: Alistair Francis Message-ID: <176154834968.21563.217396575391240410-1@git.sr.ht> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg_fields.h.inc | 2 + target/riscv/insn16.decode | 8 ++ target/riscv/insn32.decode | 12 ++- target/riscv/cpu.c | 4 + target/riscv/tcg/tcg-cpu.c | 33 +++++++ target/riscv/translate.c | 1 + target/riscv/insn_trans/trans_zilsd.c.inc | 105 ++++++++++++++++++++++ 7 files changed, 163 insertions(+), 2 deletions(-) create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index a154ecdc79..0a12ccd6cd 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -19,6 +19,7 @@ BOOL_FIELD(ext_zce) BOOL_FIELD(ext_zcf) BOOL_FIELD(ext_zcmp) BOOL_FIELD(ext_zcmt) +BOOL_FIELD(ext_zclsd) BOOL_FIELD(ext_zk) BOOL_FIELD(ext_zkn) BOOL_FIELD(ext_zknd) @@ -41,6 +42,7 @@ BOOL_FIELD(ext_zicond) BOOL_FIELD(ext_zihintntl) BOOL_FIELD(ext_zihintpause) BOOL_FIELD(ext_zihpm) +BOOL_FIELD(ext_zilsd) BOOL_FIELD(ext_zimop) BOOL_FIELD(ext_zcmop) BOOL_FIELD(ext_ztso) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index bf893d1c2e..c34020e4dc 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -130,10 +130,14 @@ sw 110 ... ... .. ... 00 @cs_w { ld 011 ... ... .. ... 00 @cl_d c_flw 011 ... ... .. ... 00 @cl_w + # *** Zclsd Extension *** + zclsd_ld 011 ... ... .. ... 00 @cl_d } { sd 111 ... ... .. ... 00 @cs_d c_fsw 111 ... ... .. ... 00 @cs_w + # *** Zclsd Extension *** + zclsd_sd 111 ... ... .. ... 00 @cs_d } =20 # *** RV32/64C Standard Extension (Quadrant 1) *** @@ -212,10 +216,14 @@ sw 110 . ..... ..... 10 @c_swsp c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=3D0 ld 011 . ..... ..... 10 @c_ldsp c_flw 011 . ..... ..... 10 @c_lwsp + # *** Zclsd Extension *** + zclsd_ldsp 011 . ..... ..... 10 @c_ldsp } { sd 111 . ..... ..... 10 @c_sdsp c_fsw 111 . ..... ..... 10 @c_swsp + # *** Zclsd Extension *** + zclsd_sd 111 . ..... ..... 10 @c_sdsp } =20 # *** RV64 and RV32 Zcb Extension *** diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index cd23b1f3a9..b341832e41 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -182,8 +182,16 @@ csrrci ............ ..... 111 ..... 1110011 @csr =20 # *** RV64I Base Instruction Set (in addition to RV32I) *** lwu ............ ..... 110 ..... 0000011 @i -ld ............ ..... 011 ..... 0000011 @i -sd ....... ..... ..... 011 ..... 0100011 @s +{ + ld ............ ..... 011 ..... 0000011 @i + # *** Zilsd instructions *** + zilsd_ld ............ ..... 011 ..... 0000011 @i +} +{ + sd ....... ..... ..... 011 ..... 0100011 @s + # *** Zilsd instructions *** + zilsd_sd ....... ..... ..... 011 ..... 0100011 @s +} addiw ............ ..... 000 ..... 0011011 @i slliw 0000000 ..... ..... 001 ..... 0011011 @sh5 srliw 0000000 ..... ..... 101 ..... 0011011 @sh5 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 60abdf3324..d48ff50232 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -121,6 +121,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl), ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm), + ISA_EXT_DATA_ENTRY(zilsd, PRIV_VERSION_1_12_0, ext_zilsd), ISA_EXT_DATA_ENTRY(zimop, PRIV_VERSION_1_13_0, ext_zimop), ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_12), @@ -144,6 +145,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zcmop, PRIV_VERSION_1_13_0, ext_zcmop), ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp), ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt), + ISA_EXT_DATA_ENTRY(zclsd, PRIV_VERSION_1_12_0, ext_zclsd), ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba), ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb), ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc), @@ -1267,6 +1269,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { =20 MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true), MULTI_EXT_CFG_BOOL("zihpm", ext_zihpm, true), + MULTI_EXT_CFG_BOOL("zilsd", ext_zilsd, false), =20 MULTI_EXT_CFG_BOOL("zba", ext_zba, true), MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true), @@ -1306,6 +1309,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("zcmp", ext_zcmp, false), MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false), MULTI_EXT_CFG_BOOL("zicond", ext_zicond, false), + MULTI_EXT_CFG_BOOL("zclsd", ext_zclsd, false), =20 /* Vector cryptography extensions */ MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index cdc05f60e9..988b2d905f 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -834,6 +834,19 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) cpu->pmu_avail_ctrs =3D 0; } =20 + if (cpu->cfg.ext_zclsd) { + if (riscv_has_ext(env, RVC) && riscv_has_ext(env, RVF)) { + error_setg(errp, + "Zclsd cannot be supported together with C and F exten= sion"); + return; + } + if (cpu->cfg.ext_zcf) { + error_setg(errp, + "Zclsd cannot be supported together with Zcf extension= "); + return; + } + } + if (cpu->cfg.ext_zicfilp && !cpu->cfg.ext_zicsr) { error_setg(errp, "zicfilp extension requires zicsr extension"); return; @@ -1097,6 +1110,20 @@ static void cpu_enable_zc_implied_rules(RISCVCPU *cp= u) } } =20 +static void cpu_enable_zilsd_implied_rules(RISCVCPU *cpu) +{ + CPURISCVState *env =3D &cpu->env; + + if (cpu->cfg.ext_zilsd && riscv_has_ext(env, RVC)) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zclsd), true); + } + + if (cpu->cfg.ext_zclsd) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zilsd), true); + } +} + static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu) { RISCVCPUImpliedExtsRule *rule; @@ -1105,6 +1132,9 @@ static void riscv_cpu_enable_implied_rules(RISCVCPU *= cpu) /* Enable the implied extensions for Zc. */ cpu_enable_zc_implied_rules(cpu); =20 + /* Enable the implied extensions for Zilsd. */ + cpu_enable_zilsd_implied_rules(cpu); + /* Enable the implied MISAs. */ for (i =3D 0; (rule =3D riscv_misa_ext_implied_rules[i]); i++) { if (riscv_has_ext(&cpu->env, rule->ext)) { @@ -1608,6 +1638,9 @@ static void riscv_init_max_cpu_extensions(Object *obj) isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); =20 + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zilsd), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zclsd), false); + if (env->misa_mxl !=3D MXL_RV32) { isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); } else { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e1f4dc5ffd..280ce48a1e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1216,6 +1216,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) /* Include the auto-generated decoder for 16 bit insn */ #include "decode-insn16.c.inc" #include "insn_trans/trans_rvzce.c.inc" +#include "insn_trans/trans_zilsd.c.inc" #include "insn_trans/trans_rvzcmop.c.inc" #include "insn_trans/trans_rvzicfiss.c.inc" =20 diff --git a/target/riscv/insn_trans/trans_zilsd.c.inc b/target/riscv/insn_= trans/trans_zilsd.c.inc new file mode 100644 index 0000000000..369c33004b --- /dev/null +++ b/target/riscv/insn_trans/trans_zilsd.c.inc @@ -0,0 +1,105 @@ +/* + * RISC-V translation routines for the Zilsd & Zclsd Extension. + * + * Copyright (c) 2025 Nucleisys, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * The documentation of the ISA extensions can be found here: + * https://github.com/riscv/riscv-zilsd/releases/tag/v1.0 + */ + +#define REQUIRE_ZILSD(ctx) do { \ + if (!ctx->cfg_ptr->ext_zilsd) \ + return false; \ +} while (0) + +#define REQUIRE_ZCLSD(ctx) do { \ + if (!ctx->cfg_ptr->ext_zclsd) \ + return false; \ +} while (0) + +static bool gen_load_i64(DisasContext *ctx, arg_ld *a) +{ + if ((a->rd) % 2) { + return false; + } + + TCGv dest_low =3D dest_gpr(ctx, a->rd); + TCGv dest_high =3D dest_gpr(ctx, a->rd + 1); + TCGv addr =3D get_address(ctx, a->rs1, a->imm); + TCGv_i64 tmp =3D tcg_temp_new_i64(); + + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_TESQ); + + if (a->rd =3D=3D 0) { + return true; + } + + tcg_gen_extr_i64_tl(dest_low, dest_high, tmp); + + gen_set_gpr(ctx, a->rd, dest_low); + gen_set_gpr(ctx, a->rd + 1, dest_high); + + return true; +} + +static bool trans_zilsd_ld(DisasContext *ctx, arg_zilsd_ld *a) +{ + REQUIRE_32BIT(ctx); + REQUIRE_ZILSD(ctx); + return gen_load_i64(ctx, a); +} + +static bool trans_zclsd_ld(DisasContext *ctx, arg_zclsd_ld *a) +{ + REQUIRE_32BIT(ctx); + REQUIRE_ZCLSD(ctx); + return gen_load_i64(ctx, a); +} + +static bool trans_zclsd_ldsp(DisasContext *ctx, arg_zclsd_ldsp *a) +{ + REQUIRE_32BIT(ctx); + REQUIRE_ZCLSD(ctx); + + if (a->rd =3D=3D 0) { + return false; + } + return gen_load_i64(ctx, a); +} + +static bool gen_store_i64(DisasContext *ctx, arg_sd *a) +{ + if ((a->rs2) % 2) { + return false; + } + + TCGv data_low =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGv data_high =3D get_gpr(ctx, a->rs2 + 1, EXT_NONE); + TCGv addr =3D get_address(ctx, a->rs1, a->imm); + TCGv_i64 tmp =3D tcg_temp_new_i64(); + + if (a->rs2 =3D=3D 0) { + tmp =3D tcg_constant_i64(0); + } else { + tcg_gen_concat_tl_i64(tmp, data_low, data_high); + } + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_TESQ); + + return true; +} + +static bool trans_zilsd_sd(DisasContext *ctx, arg_zilsd_sd *a) +{ + REQUIRE_32BIT(ctx); + REQUIRE_ZILSD(ctx); + return gen_store_i64(ctx, a); +} + +static bool trans_zclsd_sd(DisasContext *ctx, arg_zclsd_sd *a) +{ + REQUIRE_32BIT(ctx); + REQUIRE_ZCLSD(ctx); + return gen_store_i64(ctx, a); +} --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as 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The specification is listed as in Ratified state [2]. [1]: https://github.com/riscv/riscv-zalasr/tree/v0.9 [2]: https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154882/All+RIS= C-V+Specifications+Under+Active+Development Reviewed-by: Alistair Francis Signed-off-by: Roan Richmond Message-ID: <20251112162923.311714-1-roan.richmond@codethink.co.uk> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/insn32.decode | 10 ++ target/riscv/cpu.c | 2 + target/riscv/translate.c | 1 + target/riscv/insn_trans/trans_rvzalasr.c.inc | 113 +++++++++++++++++++ 5 files changed, 127 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzalasr.c.inc diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index 0a12ccd6cd..f4ff4f3f96 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -67,6 +67,7 @@ BOOL_FIELD(ext_zaamo) BOOL_FIELD(ext_zacas) BOOL_FIELD(ext_zama16b) BOOL_FIELD(ext_zabha) +BOOL_FIELD(ext_zalasr) BOOL_FIELD(ext_zalrsc) BOOL_FIELD(ext_zawrs) BOOL_FIELD(ext_zfa) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b341832e41..6e35c4b1e6 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -1074,3 +1074,13 @@ amominu_h 11000 . . ..... ..... 001 ..... 0101111 @= atom_st amomaxu_h 11100 . . ..... ..... 001 ..... 0101111 @atom_st amocas_b 00101 . . ..... ..... 000 ..... 0101111 @atom_st amocas_h 00101 . . ..... ..... 001 ..... 0101111 @atom_st + +# *** Zalasr Standard Extension *** +lb_aqrl 00110 . . ..... ..... 000 ..... 0101111 @atom_st +lh_aqrl 00110 . . ..... ..... 001 ..... 0101111 @atom_st +lw_aqrl 00110 . . ..... ..... 010 ..... 0101111 @atom_st +ld_aqrl 00110 . . ..... ..... 011 ..... 0101111 @atom_st +sb_aqrl 00111 . . ..... ..... 000 ..... 0101111 @atom_st +sh_aqrl 00111 . . ..... ..... 001 ..... 0101111 @atom_st +sw_aqrl 00111 . . ..... ..... 010 ..... 0101111 @atom_st +sd_aqrl 00111 . . ..... ..... 011 ..... 0101111 @atom_st diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d48ff50232..f22b504772 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -128,6 +128,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo), ISA_EXT_DATA_ENTRY(zabha, PRIV_VERSION_1_13_0, ext_zabha), ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas), + ISA_EXT_DATA_ENTRY(zalasr, PRIV_VERSION_1_12_0, ext_zalasr), ISA_EXT_DATA_ENTRY(zalrsc, PRIV_VERSION_1_12_0, ext_zalrsc), ISA_EXT_DATA_ENTRY(zama16b, PRIV_VERSION_1_13_0, ext_zama16b), ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), @@ -1230,6 +1231,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("zama16b", ext_zama16b, false), MULTI_EXT_CFG_BOOL("zabha", ext_zabha, false), MULTI_EXT_CFG_BOOL("zaamo", ext_zaamo, false), + MULTI_EXT_CFG_BOOL("zalasr", ext_zalasr, false), MULTI_EXT_CFG_BOOL("zalrsc", ext_zalrsc, false), MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true), MULTI_EXT_CFG_BOOL("zfa", ext_zfa, true), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 280ce48a1e..0d61420b46 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1199,6 +1199,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) #include "insn_trans/trans_rvzicond.c.inc" #include "insn_trans/trans_rvzacas.c.inc" #include "insn_trans/trans_rvzabha.c.inc" +#include "insn_trans/trans_rvzalasr.c.inc" #include "insn_trans/trans_rvzawrs.c.inc" #include "insn_trans/trans_rvzicbo.c.inc" #include "insn_trans/trans_rvzimop.c.inc" diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/in= sn_trans/trans_rvzalasr.c.inc new file mode 100644 index 0000000000..bf86805cef --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc @@ -0,0 +1,113 @@ +/* + * RISC-V translation routines for the ZALASR (Load-Aquire and Store-Relea= se) + * Extension. + * + * Copyright (c) 2025 Roan Richmond, roan.richmond@codethink.co.uk + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * The documentation of the ISA extension can be found here: + * https://github.com/riscv/riscv-zalasr/tree/v0.9 + */ + +#define REQUIRE_ZALASR(ctx) do { \ + if (!ctx->cfg_ptr->ext_zalasr) { \ + return false; \ + } \ +} while (0) + +static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memo= p) +{ + decode_save_opc(ctx, 0); + + TCGv addr =3D get_address(ctx, a->rs1, 0); + TCGv dest =3D get_gpr(ctx, a->rd, EXT_NONE); + TCGBar bar =3D (a->rl) ? TCG_BAR_STRL : 0; + + /* Check that AQ is set, as this is mandatory */ + if (!a->aq) { + return false; + } + + memop |=3D (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0; + + tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop); + gen_set_gpr(ctx, a->rd, dest); + + /* Add a memory barrier implied by AQ (mandatory) and RL (optional) */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ | bar); + + return true; +} + +static bool trans_lb_aqrl(DisasContext *ctx, arg_lb_aqrl *a) +{ + REQUIRE_ZALASR(ctx); + return gen_load_acquire(ctx, a, (MO_ALIGN | MO_SB)); +} + +static bool trans_lh_aqrl(DisasContext *ctx, arg_lh_aqrl *a) +{ + REQUIRE_ZALASR(ctx); + return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TESW)); +} + +static bool trans_lw_aqrl(DisasContext *ctx, arg_lw_aqrl *a) +{ + REQUIRE_ZALASR(ctx); + return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TESL)); +} + +static bool trans_ld_aqrl(DisasContext *ctx, arg_ld_aqrl *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_ZALASR(ctx); + return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TEUQ)); +} + +static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp mem= op) +{ + decode_save_opc(ctx, 0); + + TCGv addr =3D get_address(ctx, a->rs1, 0); + TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGBar bar =3D (a->aq) ? TCG_BAR_LDAQ : 0; + + /* Check that RL is set, as this is mandatory */ + if (!a->rl) { + return false; + } + + memop |=3D (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0; + + /* Add a memory barrier implied by RL (mandatory) and AQ (optional) */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL | bar); + + tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); + return true; +} + +static bool trans_sb_aqrl(DisasContext *ctx, arg_sb_aqrl *a) +{ + REQUIRE_ZALASR(ctx); + return gen_store_release(ctx, a, (MO_ALIGN | MO_SB)); +} + +static bool trans_sh_aqrl(DisasContext *ctx, arg_sh_aqrl *a) +{ + REQUIRE_ZALASR(ctx); + return gen_store_release(ctx, a, (MO_ALIGN | MO_TESW)); +} + +static bool trans_sw_aqrl(DisasContext *ctx, arg_sw_aqrl *a) +{ + REQUIRE_ZALASR(ctx); + return gen_store_release(ctx, a, (MO_ALIGN | MO_TESL)); +} + +static bool trans_sd_aqrl(DisasContext *ctx, arg_sd_aqrl *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_ZALASR(ctx); + return gen_store_release(ctx, a, (MO_ALIGN | MO_TEUQ)); +} --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767942254; cv=none; d=zohomail.com; s=zohoarc; b=FsCe3pfvZzmNHGwNwO4wRYLQhVMhdAWhCvzghcyY296CpbvsQVZUNVl2uO40DGa67w7FOfxY3R1il3UYfpBqtlyMFLl3IfMd2UpEWggu2CVJqPvZgiU8pGpJR00yZiLsCzBJS/438c4kamgaQOQLNy5058WJmNTJ4yXut0AfyyE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767942254; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZA2w/oxYr+Q1uGgUesLYCh7glRA4PbkOh40jya8E0ng=; b=j5lsVMQ8N8LeL81ooX0vTUu6I3nQVyLiNmACRSXlAI0uG4WPwA5lyn38RfYoJnXRb5uZYbNVWMn7ZLanZIF5aHkbZuhQ/9Kq0SZHk1EIXS2ZpOhC8IObkpsrJwm+UmoKQFYctmuzEFsaAfz8ITXaiSw9OqERc/6Aygdx6XwS1DM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767942254615544.4479412636463; Thu, 8 Jan 2026 23:04:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ve6RR-0006dq-Uy; Fri, 09 Jan 2026 01:57:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ve6Q7-0004wt-Ua for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:56:28 -0500 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ve6Q6-0002tl-Fa for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:56:27 -0500 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-c0ec27cad8cso1779808a12.1 for ; Thu, 08 Jan 2026 22:56:26 -0800 (PST) Received: from toolbx.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. 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Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20260108134128.2218102-2-djordje.todorovic@htecgroup.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 4 ++++ target/riscv/cpu.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0939e6f08c..08a6e491f3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -668,6 +668,10 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *e= nv, target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); =20 +#ifndef CONFIG_USER_ONLY +void cpu_set_exception_base(int vp_index, target_ulong address); +#endif + FIELD(TB_FLAGS, MEM_IDX, 0, 3) FIELD(TB_FLAGS, FS, 3, 2) /* Vector flags */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f22b504772..c2222228d5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -73,6 +73,22 @@ bool riscv_cpu_option_set(const char *optname) return g_hash_table_contains(general_user_opts, optname); } =20 +#ifndef CONFIG_USER_ONLY +/* This is used in runtime only. */ +void cpu_set_exception_base(int vp_index, target_ulong address) +{ + RISCVCPU *cpu; + CPUState *cs =3D qemu_get_cpu(vp_index); + if (cs =3D=3D NULL) { + qemu_log_mask(LOG_GUEST_ERROR, + "cpu_set_exception_base: invalid vp_index: %u", + vp_index); + } + cpu =3D RISCV_CPU(cs); + cpu->env.resetvec =3D address; +} +#endif + static void riscv_cpu_cfg_merge(RISCVCPUConfig *dest, const RISCVCPUConfig= *src) { #define BOOL_FIELD(x) dest->x |=3D src->x; --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767942077; cv=none; d=zohomail.com; s=zohoarc; b=Zxz41OE2jj2+auZ1sKxsKlw0J77El24lk15k5Hvuk1Cbyd0ALDDBiQer8XB0mKPCAJKC07IpcoryKIQDTqlihjiRXssqDBXV3a4Ls7dpPQ9mj4K1zEPae87tSCEuJ8QzakzaDrysBI+XM0OIcI/raBP7RnHKpq8xY+pXkm5iofU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767942077; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HjFpuKrI65dY4xPj+2D6qx22ukyO0mIgkNS35Pgtsp8=; b=SES0GtcdIBZZYWtH2jRMmCxKIGQfDJWIT0SQ3+U7FR/CMfGYTPSUh/NGB+QUCacgLO+jJqybABPcQ7lyiNMgj5380/YD9l77clJntxtXyzGRLIavF1csy5rbftARxP6UJ++rVJo3rYc3li00rf/3LUS2XCm/AY01CAOLI7mIyU8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767942077316750.579692674577; Thu, 8 Jan 2026 23:01:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ve6RI-00067R-P4; Fri, 09 Jan 2026 01:57:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ve6QC-00055Q-0F for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:56:33 -0500 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ve6QA-0002u5-BL for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:56:31 -0500 Received: by mail-pg1-x532.google.com with SMTP id 41be03b00d2f7-c5513f598c0so347035a12.0 for ; Thu, 08 Jan 2026 22:56:29 -0800 (PST) Received: from toolbx.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. 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Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20260108134128.2218102-3-djordje.todorovic@htecgroup.com> Signed-off-by: Alistair Francis --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu_vendorid.h | 1 + target/riscv/cpu.c | 16 ++++++++++++++++ 3 files changed, 18 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 75f4e43408..30dcdcfaae 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -56,6 +56,7 @@ #define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon") #define TYPE_RISCV_CPU_XIANGSHAN_NANHU RISCV_CPU_TYPE_NAME("xiangshan-nan= hu") #define TYPE_RISCV_CPU_XIANGSHAN_KMH RISCV_CPU_TYPE_NAME("xiangshan-kun= minghu") +#define TYPE_RISCV_CPU_MIPS_P8700 RISCV_CPU_TYPE_NAME("mips-p8700") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") =20 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h index 96b6b9c2cb..f1ffc66542 100644 --- a/target/riscv/cpu_vendorid.h +++ b/target/riscv/cpu_vendorid.h @@ -2,6 +2,7 @@ #define TARGET_RISCV_CPU_VENDORID_H =20 #define THEAD_VENDOR_ID 0x5b7 +#define MIPS_VENDOR_ID 0x127 =20 #define VEYRON_V1_MARCHID 0x8000000000010000 #define VEYRON_V1_MIMPID 0x111 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c2222228d5..3562cbec32 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3303,6 +3303,22 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.max_satp_mode =3D VM_1_10_SV48, ), =20 + /* https://mips.com/products/hardware/p8700/ */ + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MIPS_P8700, TYPE_RISCV_VENDOR_CPU, + .misa_mxl_max =3D MXL_RV64, + .misa_ext =3D RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU, + .priv_spec =3D PRIV_VERSION_1_12_0, + .cfg.max_satp_mode =3D VM_1_10_SV48, + .cfg.ext_zifencei =3D true, + .cfg.ext_zicsr =3D true, + .cfg.mmu =3D true, + .cfg.pmp =3D true, + .cfg.ext_zba =3D true, + .cfg.ext_zbb =3D true, + .cfg.marchid =3D 0x8000000000000201, + .cfg.mvendorid =3D MIPS_VENDOR_ID, + ), + #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU, .cfg.max_satp_mode =3D VM_1_10_SV57, --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767942146; cv=none; d=zohomail.com; s=zohoarc; b=KUC7cAREdqc9CHakVfzxhpzjpxTLb1KuebqdiRcn1Mzo+oTQxcE2Jj7IRHeYM6LAQVNhLZQHlnqC1Hmba0ick+ogd7d1vIglRkjGLNe41epqWfn87hQJfLz2Z5HtLsJfJsRckYVmu7ISs00qcRhDXVFRY8BH8wtgsIz8R5QojsE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767942146; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Aeod3ku1ZvciysL5QBT9RVp5GEzJeCAgzafr1FJ8KfY=; b=VsvgKZAngIoDrYm9XJFocvtp5xF9qZM9D9JiPjxEkf/GSifzcLm6ouPn4nfGsPSY0YaYjUsRWrpfBP574a2DvcxZIctA20QxkLCj3JC0kV342a1dD0j20hWrXrcOMWB8t/HX1snp73fmxaA10oA8pbBMj/bYsiS2XQ+0FIRXqMI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767942146171474.22344800922053; Thu, 8 Jan 2026 23:02:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ve6RI-00067k-Op; Fri, 09 Jan 2026 01:57:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ve6QF-00056a-Rk for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:56:38 -0500 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ve6QD-0002uK-W2 for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:56:35 -0500 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-bcfd82f55ebso1262236a12.1 for ; Thu, 08 Jan 2026 22:56:33 -0800 (PST) Received: from toolbx.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. 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Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20260108134128.2218102-4-djordje.todorovic@htecgroup.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 + target/riscv/cpu.c | 3 + target/riscv/mips_csr.c | 217 +++++++++++++++++++++++++++++++++++++++ target/riscv/meson.build | 1 + 4 files changed, 224 insertions(+) create mode 100644 target/riscv/mips_csr.c diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 08a6e491f3..35d1f6362c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -985,5 +985,8 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32= _bit); /* In th_csr.c */ extern const RISCVCSR th_csr_list[]; =20 +/* Implemented in mips_csr.c */ +extern const RISCVCSR mips_csr_list[]; + const char *priv_spec_to_str(int priv_version); #endif /* RISCV_CPU_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3562cbec32..e17b3e0785 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3317,6 +3317,9 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.ext_zbb =3D true, .cfg.marchid =3D 0x8000000000000201, .cfg.mvendorid =3D MIPS_VENDOR_ID, +#ifndef CONFIG_USER_ONLY + .custom_csrs =3D mips_csr_list, +#endif ), =20 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) diff --git a/target/riscv/mips_csr.c b/target/riscv/mips_csr.c new file mode 100644 index 0000000000..822e25e346 --- /dev/null +++ b/target/riscv/mips_csr.c @@ -0,0 +1,217 @@ +/* + * MIPS-specific CSRs. + * + * Copyright (c) 2025 MIPS + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "cpu_vendorid.h" + +/* Static MIPS CSR state storage */ +static struct { + uint64_t tvec; + uint64_t config[12]; + uint64_t pmacfg[16]; +} mips_csr_state; + +/* MIPS CSR */ +#define CSR_MIPSTVEC 0x7c0 +#define CSR_MIPSCONFIG0 0x7d0 +#define CSR_MIPSCONFIG1 0x7d1 +#define CSR_MIPSCONFIG2 0x7d2 +#define CSR_MIPSCONFIG3 0x7d3 +#define CSR_MIPSCONFIG4 0x7d4 +#define CSR_MIPSCONFIG5 0x7d5 +#define CSR_MIPSCONFIG6 0x7d6 +#define CSR_MIPSCONFIG7 0x7d7 +#define CSR_MIPSCONFIG8 0x7d8 +#define CSR_MIPSCONFIG9 0x7d9 +#define CSR_MIPSCONFIG10 0x7da +#define CSR_MIPSCONFIG11 0x7db +#define CSR_MIPSPMACFG0 0x7e0 +#define CSR_MIPSPMACFG1 0x7e1 +#define CSR_MIPSPMACFG2 0x7e2 +#define CSR_MIPSPMACFG3 0x7e3 +#define CSR_MIPSPMACFG4 0x7e4 +#define CSR_MIPSPMACFG5 0x7e5 +#define CSR_MIPSPMACFG6 0x7e6 +#define CSR_MIPSPMACFG7 0x7e7 +#define CSR_MIPSPMACFG8 0x7e8 +#define CSR_MIPSPMACFG9 0x7e9 +#define CSR_MIPSPMACFG10 0x7ea +#define CSR_MIPSPMACFG11 0x7eb +#define CSR_MIPSPMACFG12 0x7ec +#define CSR_MIPSPMACFG13 0x7ed +#define CSR_MIPSPMACFG14 0x7ee +#define CSR_MIPSPMACFG15 0x7ef + +static RISCVException any(CPURISCVState *env, int csrno) +{ + return RISCV_EXCP_NONE; +} + +static RISCVException read_mipstvec(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D mips_csr_state.tvec; + return RISCV_EXCP_NONE; +} + +static RISCVException write_mipstvec(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + mips_csr_state.tvec =3D val; + return RISCV_EXCP_NONE; +} + +static RISCVException read_mipsconfig(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D mips_csr_state.config[csrno - CSR_MIPSCONFIG0]; + return RISCV_EXCP_NONE; +} + +static RISCVException write_mipsconfig(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + mips_csr_state.config[csrno - CSR_MIPSCONFIG0] =3D val; + return RISCV_EXCP_NONE; +} + +static RISCVException read_mipspmacfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D mips_csr_state.pmacfg[csrno - CSR_MIPSPMACFG0]; + return RISCV_EXCP_NONE; +} + +static RISCVException write_mipspmacfg(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + mips_csr_state.pmacfg[csrno - CSR_MIPSPMACFG0] =3D val; + return RISCV_EXCP_NONE; +} + +const RISCVCSR mips_csr_list[] =3D { + { + .csrno =3D CSR_MIPSTVEC, + .csr_ops =3D { "mipstvec", any, read_mipstvec, write_mipstvec } + }, + { + .csrno =3D CSR_MIPSCONFIG0, + .csr_ops =3D { "mipsconfig0", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG1, + .csr_ops =3D { "mipsconfig1", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG2, + .csr_ops =3D { "mipsconfig2", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG3, + .csr_ops =3D { "mipsconfig3", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG4, + .csr_ops =3D { "mipsconfig4", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG5, + .csr_ops =3D { "mipsconfig5", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG6, + .csr_ops =3D { "mipsconfig6", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG7, + .csr_ops =3D { "mipsconfig7", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG8, + .csr_ops =3D { "mipsconfig8", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG9, + .csr_ops =3D { "mipsconfig9", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG10, + .csr_ops =3D { "mipsconfig10", any, read_mipsconfig, write_mipscon= fig } + }, + { + .csrno =3D CSR_MIPSCONFIG11, + .csr_ops =3D { "mipsconfig11", any, read_mipsconfig, write_mipscon= fig } + }, + { + .csrno =3D CSR_MIPSPMACFG0, + .csr_ops =3D { "mipspmacfg0", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG1, + .csr_ops =3D { "mipspmacfg1", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG2, + .csr_ops =3D { "mipspmacfg2", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG3, + .csr_ops =3D { "mipspmacfg3", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG4, + .csr_ops =3D { "mipspmacfg4", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG5, + .csr_ops =3D { "mipspmacfg5", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG6, + .csr_ops =3D { "mipspmacfg6", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG7, + .csr_ops =3D { "mipspmacfg7", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG8, + .csr_ops =3D { "mipspmacfg8", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG9, + .csr_ops =3D { "mipspmacfg9", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG10, + .csr_ops =3D { "mipspmacfg10", any, read_mipspmacfg, write_mipspma= cfg } + }, + { + .csrno =3D CSR_MIPSPMACFG11, + .csr_ops =3D { "mipspmacfg11", any, read_mipspmacfg, write_mipspma= cfg } + }, + { + .csrno =3D CSR_MIPSPMACFG12, + .csr_ops =3D { "mipspmacfg12", any, read_mipspmacfg, write_mipspma= cfg } + }, + { + .csrno =3D CSR_MIPSPMACFG13, + .csr_ops =3D { "mipspmacfg13", any, read_mipspmacfg, write_mipspma= cfg } + }, + { + .csrno =3D CSR_MIPSPMACFG14, + .csr_ops =3D { "mipspmacfg14", any, read_mipspmacfg, write_mipspma= cfg } + }, + { + .csrno =3D CSR_MIPSPMACFG15, + .csr_ops =3D { "mipspmacfg15", any, read_mipspmacfg, write_mipspma= cfg } + }, + { }, +}; diff --git a/target/riscv/meson.build b/target/riscv/meson.build index fdefe88ccd..25d59ef9f9 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -36,6 +36,7 @@ riscv_system_ss.add(files( 'debug.c', 'monitor.c', 'machine.c', + 'mips_csr.c', 'pmu.c', 'th_csr.c', 'time_helper.c', --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767942180; cv=none; d=zohomail.com; s=zohoarc; b=ZmXR3Y83YuuJD61x/4K9z9YbCYMo9KPsbr/g7zsNM2Ly2uYAFPrL4SmloiDfWpmBqn6MjhIClOcCLclrMXFu9Fgt55iUsK6zjgo5yeHjuwLci+ekVKeTYL+1nqDgCJDLtTP4G17J8+7ebdEFQkVajPap4UCouz1P7RDICc3yDkw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767942180; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic Acked-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-ID: <20260108134128.2218102-5-djordje.todorovic@htecgroup.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 5 ++++ target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/xmips.decode | 11 ++++++++ target/riscv/cpu.c | 3 +++ target/riscv/translate.c | 3 +++ target/riscv/insn_trans/trans_xmips.c.inc | 33 +++++++++++++++++++++++ target/riscv/meson.build | 1 + 7 files changed, 57 insertions(+) create mode 100644 target/riscv/xmips.decode create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index aa28dc8d7e..2db471ad17 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -36,6 +36,11 @@ static inline bool always_true_p(const RISCVCPUConfig *c= fg __attribute__((__unus return true; } =20 +static inline bool has_xmips_p(const RISCVCPUConfig *cfg) +{ + return cfg->ext_xmipscmov; +} + static inline bool has_xthead_p(const RISCVCPUConfig *cfg) { return cfg->ext_xtheadba || cfg->ext_xtheadbb || diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index f4ff4f3f96..0b461bb05b 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -150,6 +150,7 @@ BOOL_FIELD(ext_xtheadmemidx) BOOL_FIELD(ext_xtheadmempair) BOOL_FIELD(ext_xtheadsync) BOOL_FIELD(ext_XVentanaCondOps) +BOOL_FIELD(ext_xmipscmov) =20 BOOL_FIELD(mmu) BOOL_FIELD(pmp) diff --git a/target/riscv/xmips.decode b/target/riscv/xmips.decode new file mode 100644 index 0000000000..fadcb78470 --- /dev/null +++ b/target/riscv/xmips.decode @@ -0,0 +1,11 @@ +# +# RISC-V translation routines for the MIPS extension +# +# Copyright (c) 2025 MIPS +# +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Reference: MIPS P8700 instructions +# (https://mips.com/products/hardware/p8700/) + +ccmov rs3:5 11 rs2:5 rs1:5 011 rd:5 0001011 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e17b3e0785..d0a6a88a4e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -252,6 +252,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(svrsw60t59b, PRIV_VERSION_1_13_0, ext_svrsw60t59b), ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte), ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc), + ISA_EXT_DATA_ENTRY(xmipscmov, PRIV_VERSION_1_12_0, ext_xmipscmov), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), @@ -1363,6 +1364,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = =3D { MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false), MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false), MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false), + MULTI_EXT_CFG_BOOL("xmipscmov", ext_xmipscmov, false), =20 { }, }; @@ -3315,6 +3317,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.pmp =3D true, .cfg.ext_zba =3D true, .cfg.ext_zbb =3D true, + .cfg.ext_xmipscmov =3D true, .cfg.marchid =3D 0x8000000000000201, .cfg.mvendorid =3D MIPS_VENDOR_ID, #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0d61420b46..f687c75fe4 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1211,8 +1211,10 @@ static uint32_t opcode_at(DisasContextBase *dcbase, = target_ulong pc) #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_rvbf16.c.inc" #include "decode-xthead.c.inc" +#include "decode-xmips.c.inc" #include "insn_trans/trans_xthead.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" +#include "insn_trans/trans_xmips.c.inc" =20 /* Include the auto-generated decoder for 16 bit insn */ #include "decode-insn16.c.inc" @@ -1229,6 +1231,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) =20 const RISCVDecoder decoder_table[] =3D { { always_true_p, decode_insn32 }, + { has_xmips_p, decode_xmips}, { has_xthead_p, decode_xthead}, { has_XVentanaCondOps_p, decode_XVentanaCodeOps}, }; diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_= trans/trans_xmips.c.inc new file mode 100644 index 0000000000..3202fd9cc0 --- /dev/null +++ b/target/riscv/insn_trans/trans_xmips.c.inc @@ -0,0 +1,33 @@ +/* + * RISC-V translation routines for the MIPS extensions (xmips*). + * + * Copyright (c) 2025 MIPS + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Reference: MIPS P8700 instructions + * (https://mips.com/products/hardware/p8700/) + */ + +#define REQUIRE_XMIPSCMOV(ctx) do { \ + if (!ctx->cfg_ptr->ext_xmipscmov) { \ + return false; \ + } \ +} while (0) + +/* Conditional move by MIPS. */ +static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a) +{ + REQUIRE_XMIPSCMOV(ctx); + + TCGv zero, source1, source2, source3; + zero =3D tcg_constant_tl(0); + source1 =3D get_gpr(ctx, a->rs1, EXT_NONE); + source2 =3D get_gpr(ctx, a->rs2, EXT_NONE); + source3 =3D get_gpr(ctx, a->rs3, EXT_NONE); + + tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[a->rd], + source2, zero, source1, source3); + + return true; +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 25d59ef9f9..3842c7c1a8 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -4,6 +4,7 @@ gen =3D [ decodetree.process('insn32.decode', extra_args: '--static-decode=3Ddecod= e_insn32'), decodetree.process('xthead.decode', extra_args: '--static-decode=3Ddecod= e_xthead'), decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decod= e=3Ddecode_XVentanaCodeOps'), + decodetree.process('xmips.decode', extra_args: '--static-decode=3Ddecode= _xmips'), ] =20 riscv_ss =3D ss.source_set() --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767942082; cv=none; d=zohomail.com; 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Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-ID: <20260108134128.2218102-6-djordje.todorovic@htecgroup.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 2 +- target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/xmips.decode | 1 + target/riscv/cpu.c | 3 +++ target/riscv/insn_trans/trans_xmips.c.inc | 15 +++++++++++++++ 5 files changed, 21 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 2db471ad17..e4d5039c49 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -38,7 +38,7 @@ static inline bool always_true_p(const RISCVCPUConfig *cf= g __attribute__((__unus =20 static inline bool has_xmips_p(const RISCVCPUConfig *cfg) { - return cfg->ext_xmipscmov; + return cfg->ext_xmipscbop || cfg->ext_xmipscmov; } =20 static inline bool has_xthead_p(const RISCVCPUConfig *cfg) diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index 0b461bb05b..af92a7e615 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -150,6 +150,7 @@ BOOL_FIELD(ext_xtheadmemidx) BOOL_FIELD(ext_xtheadmempair) BOOL_FIELD(ext_xtheadsync) BOOL_FIELD(ext_XVentanaCondOps) +BOOL_FIELD(ext_xmipscbop) BOOL_FIELD(ext_xmipscmov) =20 BOOL_FIELD(mmu) diff --git a/target/riscv/xmips.decode b/target/riscv/xmips.decode index fadcb78470..4215813b32 100644 --- a/target/riscv/xmips.decode +++ b/target/riscv/xmips.decode @@ -9,3 +9,4 @@ # (https://mips.com/products/hardware/p8700/) =20 ccmov rs3:5 11 rs2:5 rs1:5 011 rd:5 0001011 +pref 000 imm_9:9 rs1:5 000 imm_hint:5 0001011 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d0a6a88a4e..9a27097189 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -252,6 +252,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(svrsw60t59b, PRIV_VERSION_1_13_0, ext_svrsw60t59b), ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte), ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc), + ISA_EXT_DATA_ENTRY(xmipscbop, PRIV_VERSION_1_12_0, ext_xmipscbop), ISA_EXT_DATA_ENTRY(xmipscmov, PRIV_VERSION_1_12_0, ext_xmipscmov), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), @@ -1364,6 +1365,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = =3D { MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false), MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false), MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false), + MULTI_EXT_CFG_BOOL("xmipscbop", ext_xmipscbop, false), MULTI_EXT_CFG_BOOL("xmipscmov", ext_xmipscmov, false), =20 { }, @@ -3317,6 +3319,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.pmp =3D true, .cfg.ext_zba =3D true, .cfg.ext_zbb =3D true, + .cfg.ext_xmipscbop =3D true, .cfg.ext_xmipscmov =3D true, .cfg.marchid =3D 0x8000000000000201, .cfg.mvendorid =3D MIPS_VENDOR_ID, diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_= trans/trans_xmips.c.inc index 3202fd9cc0..bfe9046153 100644 --- a/target/riscv/insn_trans/trans_xmips.c.inc +++ b/target/riscv/insn_trans/trans_xmips.c.inc @@ -9,6 +9,12 @@ * (https://mips.com/products/hardware/p8700/) */ =20 +#define REQUIRE_XMIPSCBOP(ctx) do { \ + if (!ctx->cfg_ptr->ext_xmipscbop) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XMIPSCMOV(ctx) do { \ if (!ctx->cfg_ptr->ext_xmipscmov) { \ return false; \ @@ -31,3 +37,12 @@ static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a) =20 return true; } + +/* Move data from memory into cache. */ +static bool trans_pref(DisasContext *ctx, arg_pref *a) +{ + REQUIRE_XMIPSCBOP(ctx); + + /* Nop */ + return true; +} --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767942493; cv=none; d=zohomail.com; s=zohoarc; b=jPUAnelsvjH+L47AqlZqfbX+kKsMgmOsw72PAkHhiSmLhnFsRZoxMuKcFkMSbS6f8I/oO18MaWGXFeAGZ6be3JaARkw3AHuORSkRdrijrch33LuMRUtqUfCiwlFkVE0opsIwHQvpKkGjsRiUW/s0gWsfLN8vHbR9LC6LSZ3+pI0= ARC-Message-Signature: i=1; a=rsa-sha256; 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Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic Acked-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-ID: <20260108134128.2218102-7-djordje.todorovic@htecgroup.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 2 +- target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/xmips.decode | 23 ++++++ target/riscv/cpu.c | 3 + target/riscv/insn_trans/trans_xmips.c.inc | 88 +++++++++++++++++++++++ 5 files changed, 116 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index e4d5039c49..cd1cba797c 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -38,7 +38,7 @@ static inline bool always_true_p(const RISCVCPUConfig *cf= g __attribute__((__unus =20 static inline bool has_xmips_p(const RISCVCPUConfig *cfg) { - return cfg->ext_xmipscbop || cfg->ext_xmipscmov; + return cfg->ext_xmipscbop || cfg->ext_xmipscmov || cfg->ext_xmipslsp; } =20 static inline bool has_xthead_p(const RISCVCPUConfig *cfg) diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index af92a7e615..70ec650abf 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -152,6 +152,7 @@ BOOL_FIELD(ext_xtheadsync) BOOL_FIELD(ext_XVentanaCondOps) BOOL_FIELD(ext_xmipscbop) BOOL_FIELD(ext_xmipscmov) +BOOL_FIELD(ext_xmipslsp) =20 BOOL_FIELD(mmu) BOOL_FIELD(pmp) diff --git a/target/riscv/xmips.decode b/target/riscv/xmips.decode index 4215813b32..3174f17aa4 100644 --- a/target/riscv/xmips.decode +++ b/target/riscv/xmips.decode @@ -8,5 +8,28 @@ # Reference: MIPS P8700 instructions # (https://mips.com/products/hardware/p8700/) =20 +# Fields +%rs3 27:5 +%rs2 20:5 +%rs1 15:5 +%rd 7:5 +%imm_9 20:9 +%imm_hint 7:5 +%imm_v 25:2 9:3 !function=3Dex_shift_2 +%imm_w 25:2 10:2 !function=3Dex_shift_3 +%imm_x 22:5 !function=3Dex_shift_2 +%imm_y 23:4 !function=3Dex_shift_3 + +# Formats +@r4_immv ..... .. ..... ..... ... ... .. ....... %rs2 %rs3 %imm_v %rs1 +@r4_immw ..... .. ..... ..... ... .. ... ....... %rs2 %rs3 %imm_w %rs1 +@r4_immx ..... ..... .. ..... ... ..... ....... %rs3 %imm_x %rs1 %rd +@r4_immy ..... .... ... ..... ... ..... ....... %rs3 %imm_y %rs1 %rd + +# *** RV64 MIPS Extension *** ccmov rs3:5 11 rs2:5 rs1:5 011 rd:5 0001011 pref 000 imm_9:9 rs1:5 000 imm_hint:5 0001011 +ldp ..... .... 000 ..... 100 ..... 0001011 @r4_immy +lwp ..... ..... 01 ..... 100 ..... 0001011 @r4_immx +sdp ..... .. ..... ..... 101 .. 0000001011 @r4_immw +swp ..... .. ..... ..... 101 ... 010001011 @r4_immv diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9a27097189..ffd98e8eed 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -254,6 +254,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc), ISA_EXT_DATA_ENTRY(xmipscbop, PRIV_VERSION_1_12_0, ext_xmipscbop), ISA_EXT_DATA_ENTRY(xmipscmov, PRIV_VERSION_1_12_0, ext_xmipscmov), + ISA_EXT_DATA_ENTRY(xmipslsp, PRIV_VERSION_1_12_0, ext_xmipslsp), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), @@ -1367,6 +1368,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = =3D { MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false), MULTI_EXT_CFG_BOOL("xmipscbop", ext_xmipscbop, false), MULTI_EXT_CFG_BOOL("xmipscmov", ext_xmipscmov, false), + MULTI_EXT_CFG_BOOL("xmipslsp", ext_xmipslsp, false), =20 { }, }; @@ -3319,6 +3321,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.pmp =3D true, .cfg.ext_zba =3D true, .cfg.ext_zbb =3D true, + .cfg.ext_xmipslsp =3D true, .cfg.ext_xmipscbop =3D true, .cfg.ext_xmipscmov =3D true, .cfg.marchid =3D 0x8000000000000201, diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_= trans/trans_xmips.c.inc index bfe9046153..9a72f3392f 100644 --- a/target/riscv/insn_trans/trans_xmips.c.inc +++ b/target/riscv/insn_trans/trans_xmips.c.inc @@ -21,6 +21,12 @@ } \ } while (0) =20 +#define REQUIRE_XMIPSLSP(ctx) do { \ + if (!ctx->cfg_ptr->ext_xmipslsp) { \ + return false; \ + } \ +} while (0) + /* Conditional move by MIPS. */ static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a) { @@ -38,6 +44,88 @@ static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a) return true; } =20 +/* Load Doubleword Pair. */ +static bool trans_ldp(DisasContext *ctx, arg_ldp *a) +{ + REQUIRE_XMIPSLSP(ctx); + REQUIRE_64_OR_128BIT(ctx); + + TCGv src =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv dest0 =3D dest_gpr(ctx, a->rd); + TCGv dest1 =3D dest_gpr(ctx, a->rs3); + TCGv addr =3D tcg_temp_new(); + + tcg_gen_addi_tl(addr, src, a->imm_y); + tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESQ); + gen_set_gpr(ctx, a->rd, dest0); + + tcg_gen_addi_tl(addr, addr, 8); + tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESQ); + gen_set_gpr(ctx, a->rs3, dest1); + + return true; +} + +/* Load Word Pair. */ +static bool trans_lwp(DisasContext *ctx, arg_lwp *a) +{ + REQUIRE_XMIPSLSP(ctx); + + TCGv src =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv dest0 =3D dest_gpr(ctx, a->rd); + TCGv dest1 =3D dest_gpr(ctx, a->rs3); + TCGv addr =3D tcg_temp_new(); + + tcg_gen_addi_tl(addr, src, a->imm_x); + tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESL); + gen_set_gpr(ctx, a->rd, dest0); + + tcg_gen_addi_tl(addr, addr, 4); + tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESL); + gen_set_gpr(ctx, a->rs3, dest1); + + return true; +} + +/* Store Doubleword Pair. */ +static bool trans_sdp(DisasContext *ctx, arg_sdp *a) +{ + REQUIRE_XMIPSLSP(ctx); + REQUIRE_64_OR_128BIT(ctx); + + TCGv src =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv data0 =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGv data1 =3D get_gpr(ctx, a->rs3, EXT_NONE); + TCGv addr =3D tcg_temp_new(); + + tcg_gen_addi_tl(addr, src, a->imm_w); + tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TEUQ); + + tcg_gen_addi_tl(addr, addr, 8); + tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TEUQ); + + return true; +} + +/* Store Word Pair. */ +static bool trans_swp(DisasContext *ctx, arg_swp *a) +{ + REQUIRE_XMIPSLSP(ctx); + + TCGv src =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv data0 =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGv data1 =3D get_gpr(ctx, a->rs3, EXT_NONE); + TCGv addr =3D tcg_temp_new(); + + tcg_gen_addi_tl(addr, src, a->imm_v); + tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TESL); + + tcg_gen_addi_tl(addr, addr, 4); + tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TESL); + + return true; +} + /* Move data from memory into cache. */ static bool trans_pref(DisasContext *ctx, arg_pref *a) { --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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It is based on the existing MIPS CMGCR implementation but adapted for RISC-V systems. The CMGCR device provides global system control for multi-core configurations in RISC-V systems. This is needed for the MIPS BOSTON AIA board. Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic Reviewed-by: Daniel Henrique Barboza Message-ID: <20260108134128.2218102-8-djordje.todorovic@htecgroup.com> Signed-off-by: Alistair Francis --- include/hw/misc/riscv_cmgcr.h | 48 +++++++ hw/misc/riscv_cmgcr.c | 243 ++++++++++++++++++++++++++++++++++ hw/misc/Kconfig | 9 ++ hw/misc/meson.build | 2 + 4 files changed, 302 insertions(+) create mode 100644 include/hw/misc/riscv_cmgcr.h create mode 100644 hw/misc/riscv_cmgcr.c diff --git a/include/hw/misc/riscv_cmgcr.h b/include/hw/misc/riscv_cmgcr.h new file mode 100644 index 0000000000..1878d98fc6 --- /dev/null +++ b/include/hw/misc/riscv_cmgcr.h @@ -0,0 +1,48 @@ +/* + * Coherent Manager Global Control Register + * + * Copyright (C) 2015 Imagination Technologies + * + * Copyright (C) 2025 MIPS + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + */ + +#ifndef RISCV_CMGCR_H +#define RISCV_CMGCR_H + +#include "hw/core/sysbus.h" +#include "qom/object.h" + +#define TYPE_RISCV_GCR "riscv-gcr" +OBJECT_DECLARE_SIMPLE_TYPE(RISCVGCRState, RISCV_GCR) + +#define GCR_BASE_ADDR 0x1fb80000ULL +#define GCR_MAX_VPS 256 + +typedef struct RISCVGCRVPState RISCVGCRVPState; +struct RISCVGCRVPState { + uint64_t reset_base; +}; + +typedef struct RISCVGCRState RISCVGCRState; +struct RISCVGCRState { + SysBusDevice parent_obj; + + int32_t gcr_rev; + uint32_t cluster_id; + uint32_t num_vps; + uint32_t num_hart; + uint32_t num_core; + hwaddr gcr_base; + MemoryRegion iomem; + MemoryRegion *cpc_mr; + + uint64_t cpc_base; + + /* VP Local/Other Registers */ + RISCVGCRVPState *vps; +}; + +#endif /* RISCV_CMGCR_H */ diff --git a/hw/misc/riscv_cmgcr.c b/hw/misc/riscv_cmgcr.c new file mode 100644 index 0000000000..b0294e7663 --- /dev/null +++ b/hw/misc/riscv_cmgcr.c @@ -0,0 +1,243 @@ +/* + * Coherent Manager Global Control Register + * + * Copyright (C) 2015 Imagination Technologies + * + * Copyright (C) 2025 MIPS + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Reference: MIPS P8700 documentation + * (https://mips.com/products/hardware/p8700/) + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qapi/error.h" +#include "hw/core/sysbus.h" +#include "migration/vmstate.h" +#include "hw/misc/riscv_cmgcr.h" +#include "hw/core/qdev-properties.h" + +#include "cpu.h" + +#define CM_RESET_VEC 0x1FC00000 +#define GCR_ADDRSPACE_SZ 0x8000 + +/* Offsets to register blocks */ +#define RISCV_GCB_OFS 0x0000 /* Global Control Block */ +#define RISCV_CLCB_OFS 0x2000 /* Core Control Block */ +#define RISCV_CORE_REG_STRIDE 0x100 /* Stride between core-specific regist= ers */ + +/* Global Control Block Register Map */ +#define GCR_CONFIG_OFS 0x0000 +#define GCR_BASE_OFS 0x0008 +#define GCR_REV_OFS 0x0030 +#define GCR_CPC_STATUS_OFS 0x00F0 +#define GCR_L2_CONFIG_OFS 0x0130 + +/* GCR_L2_CONFIG register fields */ +#define GCR_L2_CONFIG_BYPASS_SHF 20 +#define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF) + +/* GCR_BASE register fields */ +#define GCR_BASE_GCRBASE_MSK 0xffffffff8000ULL + +/* GCR_CPC_BASE register fields */ +#define GCR_CPC_BASE_CPCEN_MSK 1 +#define GCR_CPC_BASE_CPCBASE_MSK 0xFFFFFFFF8000ULL +#define GCR_CPC_BASE_MSK (GCR_CPC_BASE_CPCEN_MSK | GCR_CPC_BASE_CPCBASE_MS= K) + +/* GCR_CL_RESETBASE_OFS register fields */ +#define GCR_CL_RESET_BASE_RESETBASE_MSK 0xFFFFFFFFFFFFF000U +#define GCR_CL_RESET_BASE_MSK GCR_CL_RESET_BASE_RESETBASE_MSK + +static inline bool is_cpc_connected(RISCVGCRState *s) +{ + return s->cpc_mr !=3D NULL; +} + +static inline void update_cpc_base(RISCVGCRState *gcr, uint64_t val) +{ + if (is_cpc_connected(gcr)) { + gcr->cpc_base =3D val & GCR_CPC_BASE_MSK; + memory_region_transaction_begin(); + memory_region_set_address(gcr->cpc_mr, + gcr->cpc_base & GCR_CPC_BASE_CPCBASE_MSK= ); + memory_region_set_enabled(gcr->cpc_mr, + gcr->cpc_base & GCR_CPC_BASE_CPCEN_MSK); + memory_region_transaction_commit(); + } +} + +static inline void update_gcr_base(RISCVGCRState *gcr, uint64_t val) +{ + gcr->gcr_base =3D val & GCR_BASE_GCRBASE_MSK; + memory_region_set_address(&gcr->iomem, gcr->gcr_base); + + /* + * For boston-aia, cpc_base is set to gcr_base + 0x8001 to enable + * cpc automatically. + */ + update_cpc_base(gcr, val + 0x8001); +} + +/* Read GCR registers */ +static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size) +{ + RISCVGCRState *gcr =3D (RISCVGCRState *) opaque; + + switch (addr) { + /* Global Control Block Register */ + case GCR_CONFIG_OFS: + /* Set PCORES to 0 */ + return 0; + case GCR_BASE_OFS: + return gcr->gcr_base; + case GCR_REV_OFS: + return gcr->gcr_rev; + case GCR_CPC_STATUS_OFS: + return is_cpc_connected(gcr); + case GCR_L2_CONFIG_OFS: + /* L2 BYPASS */ + return GCR_L2_CONFIG_BYPASS_MSK; + default: + qemu_log_mask(LOG_UNIMP, "Read %d bytes at GCR offset 0x%" HWADDR_= PRIx + "\n", size, addr); + } + return 0; +} + +static inline target_ulong get_exception_base(RISCVGCRVPState *vps) +{ + return vps->reset_base & GCR_CL_RESET_BASE_RESETBASE_MSK; +} + +/* Write GCR registers */ +static void gcr_write(void *opaque, hwaddr addr, uint64_t data, unsigned s= ize) +{ + RISCVGCRState *gcr =3D (RISCVGCRState *)opaque; + RISCVGCRVPState *current_vps; + int cpu_index, c, h; + + for (c =3D 0; c < gcr->num_core; c++) { + for (h =3D 0; h < gcr->num_hart; h++) { + if (addr =3D=3D RISCV_CLCB_OFS + c * RISCV_CORE_REG_STRIDE + h= * 8) { + cpu_index =3D c * gcr->num_hart + h; + current_vps =3D &gcr->vps[cpu_index]; + current_vps->reset_base =3D data & GCR_CL_RESET_BASE_MSK; + cpu_set_exception_base(cpu_index + gcr->cluster_id * + gcr->num_core * gcr->num_hart, + get_exception_base(current_vps)); + return; + } + } + } + + switch (addr) { + case GCR_BASE_OFS: + update_gcr_base(gcr, data); + break; + default: + qemu_log_mask(LOG_UNIMP, "Write %d bytes at GCR offset 0x%" HWADDR= _PRIx + " 0x%" PRIx64 "\n", size, addr, data); + break; + } +} + +static const MemoryRegionOps gcr_ops =3D { + .read =3D gcr_read, + .write =3D gcr_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .max_access_size =3D 8, + }, +}; + +static void riscv_gcr_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + RISCVGCRState *s =3D RISCV_GCR(obj); + + memory_region_init_io(&s->iomem, OBJECT(s), &gcr_ops, s, + "riscv-gcr", GCR_ADDRSPACE_SZ); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void riscv_gcr_reset(DeviceState *dev) +{ + RISCVGCRState *s =3D RISCV_GCR(dev); + int i; + + /* Update cpc_base to gcr_base + 0x8001 to enable cpc automatically. */ + update_cpc_base(s, s->gcr_base + 0x8001); + + for (i =3D 0; i < s->num_vps; i++) { + s->vps[i].reset_base =3D CM_RESET_VEC & GCR_CL_RESET_BASE_MSK; + cpu_set_exception_base(i, get_exception_base(&s->vps[i])); + } +} + +static const VMStateDescription vmstate_riscv_gcr =3D { + .name =3D "riscv-gcr", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(cpc_base, RISCVGCRState), + VMSTATE_END_OF_LIST() + }, +}; + +static const Property riscv_gcr_properties[] =3D { + DEFINE_PROP_UINT32("cluster-id", RISCVGCRState, cluster_id, 0), + DEFINE_PROP_UINT32("num-vp", RISCVGCRState, num_vps, 1), + DEFINE_PROP_UINT32("num-hart", RISCVGCRState, num_hart, 1), + DEFINE_PROP_UINT32("num-core", RISCVGCRState, num_core, 1), + DEFINE_PROP_INT32("gcr-rev", RISCVGCRState, gcr_rev, 0xa00), + DEFINE_PROP_UINT64("gcr-base", RISCVGCRState, gcr_base, GCR_BASE_ADDR), + DEFINE_PROP_LINK("cpc", RISCVGCRState, cpc_mr, TYPE_MEMORY_REGION, + MemoryRegion *), +}; + +static void riscv_gcr_realize(DeviceState *dev, Error **errp) +{ + RISCVGCRState *s =3D RISCV_GCR(dev); + + /* Validate num_vps */ + if (s->num_vps =3D=3D 0) { + error_setg(errp, "num-vp must be at least 1"); + return; + } + if (s->num_vps > GCR_MAX_VPS) { + error_setg(errp, "num-vp cannot exceed %d", GCR_MAX_VPS); + return; + } + + /* Create local set of registers for each VP */ + s->vps =3D g_new(RISCVGCRVPState, s->num_vps); +} + +static void riscv_gcr_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + device_class_set_props(dc, riscv_gcr_properties); + dc->vmsd =3D &vmstate_riscv_gcr; + device_class_set_legacy_reset(dc, riscv_gcr_reset); + dc->realize =3D riscv_gcr_realize; +} + +static const TypeInfo riscv_gcr_info =3D { + .name =3D TYPE_RISCV_GCR, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RISCVGCRState), + .instance_init =3D riscv_gcr_init, + .class_init =3D riscv_gcr_class_init, +}; + +static void riscv_gcr_register_types(void) +{ + type_register_static(&riscv_gcr_info); +} + +type_init(riscv_gcr_register_types) diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index fccd735c24..404500979c 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -121,6 +121,15 @@ config MIPS_ITU bool depends on TCG =20 +config RISCV_MIPS_CMGCR + bool + +config MIPS_BOSTON_AIA + bool + default y + depends on RISCV64 + select RISCV_MIPS_CMGCR + config MPS2_FPGAIO bool select LED diff --git a/hw/misc/meson.build b/hw/misc/meson.build index b1d8d8e5d2..489f0f3319 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -157,6 +157,8 @@ specific_ss.add(when: 'CONFIG_MAC_VIA', if_true: files(= 'mac_via.c')) specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_cmgcr.c', 'm= ips_cpc.c')) specific_ss.add(when: 'CONFIG_MIPS_ITU', if_true: files('mips_itu.c')) =20 +specific_ss.add(when: 'CONFIG_RISCV_MIPS_CMGCR', if_true: files('riscv_cmg= cr.c')) + system_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c')) =20 # HPPA devices --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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It is based on the existing MIPS CPC implementations but adapted for RISC-V systems. The CPC device manages power control for CPU clusters in RISC-V systems. This is needed for the MIPS BOSTON AIA board. Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic Reviewed-by: Daniel Henrique Barboza Message-ID: <20260108134128.2218102-9-djordje.todorovic@htecgroup.com> Signed-off-by: Alistair Francis --- include/hw/misc/riscv_cpc.h | 64 +++++++++ hw/misc/riscv_cpc.c | 265 ++++++++++++++++++++++++++++++++++++ hw/misc/Kconfig | 4 + hw/misc/meson.build | 1 + 4 files changed, 334 insertions(+) create mode 100644 include/hw/misc/riscv_cpc.h create mode 100644 hw/misc/riscv_cpc.c diff --git a/include/hw/misc/riscv_cpc.h b/include/hw/misc/riscv_cpc.h new file mode 100644 index 0000000000..43343ed9e6 --- /dev/null +++ b/include/hw/misc/riscv_cpc.h @@ -0,0 +1,64 @@ +/* + * Cluster Power Controller emulation + * + * Copyright (c) 2016 Imagination Technologies + * + * Copyright (c) 2025 MIPS + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + */ + +#ifndef RISCV_CPC_H +#define RISCV_CPC_H + +#include "hw/core/sysbus.h" +#include "qom/object.h" + +#define CPC_ADDRSPACE_SZ 0x6000 + +/* CPC global register offsets relative to base address */ +#define CPC_MTIME_REG_OFS 0x50 + +#define CPC_CM_STAT_CONF_OFS 0x1008 + +/* CPC blocks offsets relative to base address */ +#define CPC_CL_BASE_OFS 0x2000 +#define CPC_CORE_REG_STRIDE 0x100 /* Stride between core-specific register= s */ + +/* CPC register offsets relative to block offsets */ +#define CPC_STAT_CONF_OFS 0x08 +#define CPC_VP_STOP_OFS 0x20 +#define CPC_VP_RUN_OFS 0x28 +#define CPC_VP_RUNNING_OFS 0x30 + +#define SEQ_STATE_BIT 19 +#define SEQ_STATE_U5 0x6 +#define SEQ_STATE_U6 0x7 +#define CPC_Cx_STAT_CONF_SEQ_STATE_U5 (SEQ_STATE_U5 << SEQ_STATE_BIT) +#define CPC_Cx_STAT_CONF_SEQ_STATE_U6 (SEQ_STATE_U6 << SEQ_STATE_BIT) + +#define TYPE_RISCV_CPC "xmips-cpc" +OBJECT_DECLARE_SIMPLE_TYPE(RISCVCPCState, RISCV_CPC) + +typedef struct RISCVCPCState { + SysBusDevice parent_obj; + + uint32_t cluster_id; + uint32_t num_vp; + uint32_t num_hart; + uint32_t num_core; + /* VPs running from restart mask */ + uint64_t vps_start_running_mask; + + MemoryRegion mr; + /* Indicates which VPs are in the run state mask */ + uint64_t vps_running_mask; + + /* Array of CPUs managed by this CPC */ + CPUState **cpus; +} RISCVCPCState; + +#define CPC_MAX_VPS 64 /* Maximum number of VPs supported */ + +#endif /* RISCV_CPC_H */ diff --git a/hw/misc/riscv_cpc.c b/hw/misc/riscv_cpc.c new file mode 100644 index 0000000000..231a419062 --- /dev/null +++ b/hw/misc/riscv_cpc.c @@ -0,0 +1,265 @@ +/* + * Cluster Power Controller emulation + * + * Copyright (c) 2016 Imagination Technologies + * + * Copyright (c) 2025 MIPS + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Reference: MIPS P8700 documentation + * (https://mips.com/products/hardware/p8700/) + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "cpu.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/timer.h" +#include "qemu/bitops.h" +#include "hw/core/sysbus.h" +#include "migration/vmstate.h" + +#include "hw/misc/riscv_cpc.h" +#include "hw/core/qdev-properties.h" +#include "hw/intc/riscv_aclint.h" +#include "hw/core/resettable.h" + +static inline uint64_t cpc_vp_run_mask(RISCVCPCState *cpc) +{ + return MAKE_64BIT_MASK(0, cpc->num_vp); +} + +static void riscv_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data) +{ + RISCVCPCState *cpc =3D (RISCVCPCState *) data.host_ptr; + int i; + + cpu_reset(cs); + cs->halted =3D 0; + + /* Find this CPU's index in the CPC's CPU array */ + for (i =3D 0; i < cpc->num_vp; i++) { + if (cpc->cpus[i] =3D=3D cs) { + cpc->vps_running_mask |=3D BIT_ULL(i); + break; + } + } +} + +static void cpc_run_vp(RISCVCPCState *cpc, uint64_t vps_run_mask) +{ + int vp; + + for (vp =3D 0; vp < cpc->num_vp; vp++) { + CPUState *cs =3D cpc->cpus[vp]; + + if (!extract64(vps_run_mask, vp, 1)) { + continue; + } + + if (extract64(cpc->vps_running_mask, vp, 1)) { + continue; + } + + /* + * To avoid racing with a CPU we are just kicking off. + * We do the final bit of preparation for the work in + * the target CPUs context. + */ + async_safe_run_on_cpu(cs, riscv_cpu_reset_async_work, + RUN_ON_CPU_HOST_PTR(cpc)); + } +} + +static void cpc_stop_vp(RISCVCPCState *cpc, uint64_t vps_stop_mask) +{ + int vp; + + for (vp =3D 0; vp < cpc->num_vp; vp++) { + CPUState *cs =3D cpc->cpus[vp]; + + if (!extract64(vps_stop_mask, vp, 1)) { + continue; + } + + if (!extract64(cpc->vps_running_mask, vp, 1)) { + continue; + } + + cpu_interrupt(cs, CPU_INTERRUPT_HALT); + cpc->vps_running_mask &=3D ~BIT_ULL(vp); + } +} + +static void cpc_write(void *opaque, hwaddr offset, uint64_t data, + unsigned size) +{ + RISCVCPCState *s =3D opaque; + int cpu_index, c; + + for (c =3D 0; c < s->num_core; c++) { + cpu_index =3D c * s->num_hart + + s->cluster_id * s->num_core * s->num_hart; + if (offset =3D=3D + CPC_CL_BASE_OFS + CPC_VP_RUN_OFS + c * CPC_CORE_REG_STRIDE) { + cpc_run_vp(s, (data << cpu_index) & cpc_vp_run_mask(s)); + return; + } + if (offset =3D=3D + CPC_CL_BASE_OFS + CPC_VP_STOP_OFS + c * CPC_CORE_REG_STRIDE) { + cpc_stop_vp(s, (data << cpu_index) & cpc_vp_run_mask(s)); + return; + } + } + + switch (offset) { + default: + qemu_log_mask(LOG_UNIMP, + "%s: Bad offset 0x%x\n", __func__, (int)offset); + break; + } + + return; +} + +static uint64_t cpc_read(void *opaque, hwaddr offset, unsigned size) +{ + RISCVCPCState *s =3D opaque; + int c; + + for (c =3D 0; c < s->num_core; c++) { + if (offset =3D=3D + CPC_CL_BASE_OFS + CPC_STAT_CONF_OFS + c * CPC_CORE_REG_STRIDE)= { + /* Return the state as U6. */ + return CPC_Cx_STAT_CONF_SEQ_STATE_U6; + } + } + + switch (offset) { + case CPC_CM_STAT_CONF_OFS: + return CPC_Cx_STAT_CONF_SEQ_STATE_U5; + case CPC_MTIME_REG_OFS: + return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, + NANOSECONDS_PER_SECOND); + return 0; + default: + qemu_log_mask(LOG_UNIMP, + "%s: Bad offset 0x%x\n", __func__, (int)offset); + return 0; + } +} + +static const MemoryRegionOps cpc_ops =3D { + .read =3D cpc_read, + .write =3D cpc_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 8, + }, +}; + +static void riscv_cpc_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + RISCVCPCState *s =3D RISCV_CPC(obj); + int i; + + memory_region_init_io(&s->mr, OBJECT(s), &cpc_ops, s, "xmips-cpc", + CPC_ADDRSPACE_SZ); + sysbus_init_mmio(sbd, &s->mr); + + /* Allocate CPU array */ + s->cpus =3D g_new0(CPUState *, CPC_MAX_VPS); + + /* Create link properties for each possible CPU slot */ + for (i =3D 0; i < CPC_MAX_VPS; i++) { + char *propname =3D g_strdup_printf("cpu[%d]", i); + object_property_add_link(obj, propname, TYPE_CPU, + (Object **)&s->cpus[i], + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + g_free(propname); + } +} + +static void riscv_cpc_realize(DeviceState *dev, Error **errp) +{ + RISCVCPCState *s =3D RISCV_CPC(dev); + int i; + + if (s->vps_start_running_mask & ~cpc_vp_run_mask(s)) { + error_setg(errp, + "incorrect vps-start-running-mask 0x%" PRIx64 + " for num_vp =3D %d", + s->vps_start_running_mask, s->num_vp); + return; + } + + /* Verify that required CPUs have been linked */ + for (i =3D 0; i < s->num_vp; i++) { + if (!s->cpus[i]) { + error_setg(errp, "CPU %d has not been linked", i); + return; + } + } +} + +static void riscv_cpc_reset_hold(Object *obj, ResetType type) +{ + RISCVCPCState *s =3D RISCV_CPC(obj); + + /* Reflect the fact that all VPs are halted on reset */ + s->vps_running_mask =3D 0; + + /* Put selected VPs into run state */ + cpc_run_vp(s, s->vps_start_running_mask); +} + +static const VMStateDescription vmstate_riscv_cpc =3D { + .name =3D "xmips-cpc", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(vps_running_mask, RISCVCPCState), + VMSTATE_END_OF_LIST() + }, +}; + +static const Property riscv_cpc_properties[] =3D { + DEFINE_PROP_UINT32("cluster-id", RISCVCPCState, cluster_id, 0x0), + DEFINE_PROP_UINT32("num-vp", RISCVCPCState, num_vp, 0x1), + DEFINE_PROP_UINT32("num-hart", RISCVCPCState, num_hart, 0x1), + DEFINE_PROP_UINT32("num-core", RISCVCPCState, num_core, 0x1), + DEFINE_PROP_UINT64("vps-start-running-mask", RISCVCPCState, + vps_start_running_mask, 0x1), +}; + +static void riscv_cpc_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + dc->realize =3D riscv_cpc_realize; + rc->phases.hold =3D riscv_cpc_reset_hold; + dc->vmsd =3D &vmstate_riscv_cpc; + device_class_set_props(dc, riscv_cpc_properties); + dc->user_creatable =3D false; +} + +static const TypeInfo riscv_cpc_info =3D { + .name =3D TYPE_RISCV_CPC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RISCVCPCState), + .instance_init =3D riscv_cpc_init, + .class_init =3D riscv_cpc_class_init, +}; + +static void riscv_cpc_register_types(void) +{ + type_register_static(&riscv_cpc_info); +} + +type_init(riscv_cpc_register_types) diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 404500979c..38be72b141 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -124,11 +124,15 @@ config MIPS_ITU config RISCV_MIPS_CMGCR bool =20 +config RISCV_MIPS_CPC + bool + config MIPS_BOSTON_AIA bool default y depends on RISCV64 select RISCV_MIPS_CMGCR + select RISCV_MIPS_CPC =20 config MPS2_FPGAIO bool diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 489f0f3319..32b878e035 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -158,6 +158,7 @@ specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files= ('mips_cmgcr.c', 'mips_cp specific_ss.add(when: 'CONFIG_MIPS_ITU', if_true: files('mips_itu.c')) =20 specific_ss.add(when: 'CONFIG_RISCV_MIPS_CMGCR', if_true: files('riscv_cmg= cr.c')) +specific_ss.add(when: 'CONFIG_RISCV_MIPS_CPC', if_true: files('riscv_cpc.c= ')) =20 system_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c')) =20 --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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This enables SMP support for RISC-V boards that require cache-coherent multiprocessor systems. Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic Acked-by: Daniel Henrique Barboza Message-ID: <20260108134128.2218102-10-djordje.todorovic@htecgroup.com> Signed-off-by: Alistair Francis --- include/hw/riscv/cps.h | 66 ++++++++++++++ hw/riscv/cps.c | 196 +++++++++++++++++++++++++++++++++++++++++ hw/misc/Kconfig | 4 + hw/riscv/meson.build | 2 + 4 files changed, 268 insertions(+) create mode 100644 include/hw/riscv/cps.h create mode 100644 hw/riscv/cps.c diff --git a/include/hw/riscv/cps.h b/include/hw/riscv/cps.h new file mode 100644 index 0000000000..f33fd7ac86 --- /dev/null +++ b/include/hw/riscv/cps.h @@ -0,0 +1,66 @@ +/* + * Coherent Processing System emulation. + * + * Copyright (c) 2016 Imagination Technologies + * + * Copyright (c) 2025 MIPS + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + */ + +#ifndef RISCV_CPS_H +#define RISCV_CPS_H + +#include "hw/core/sysbus.h" +#include "hw/misc/riscv_cmgcr.h" +#include "hw/misc/riscv_cpc.h" +#include "target/riscv/cpu.h" +#include "qom/object.h" + +#define TYPE_RISCV_CPS "riscv-cps" +OBJECT_DECLARE_SIMPLE_TYPE(RISCVCPSState, RISCV_CPS) + +/* The model supports up to 64 harts. */ +#define MAX_HARTS 64 + +/* The global CM base for the boston-aia model. */ +#define GLOBAL_CM_BASE 0x16100000 +/* The CM block is 512 KiB. */ +#define CM_SIZE (1 << 19) + +/* + * The mhartid bits has cluster at bit 16, core at bit 4, and hart at + * bit 0. + */ + +#define MHARTID_CLUSTER_SHIFT 16 +#define MHARTID_CORE_SHIFT 4 +#define MHARTID_HART_SHIFT 0 + +#define APLIC_NUM_SOURCES 0x35 /* Arbitray maximum number of interrupts. */ +#define APLIC_NUM_PRIO_BITS 3 +#define AIA_PLIC_M_OFFSET 0x40000 +#define AIA_PLIC_M_SIZE 0x8000 +#define AIA_PLIC_S_OFFSET 0x60000 +#define AIA_PLIC_S_SIZE 0x8000 +#define AIA_CLINT_OFFSET 0x50000 + +typedef struct RISCVCPSState { + SysBusDevice parent_obj; + + uint32_t num_vp; + uint32_t num_hart; + uint32_t num_core; + uint64_t gcr_base; + char *cpu_type; + + MemoryRegion container; + RISCVGCRState gcr; + RISCVCPCState cpc; + + DeviceState *aplic; + CPUState **cpus; +} RISCVCPSState; + +#endif diff --git a/hw/riscv/cps.c b/hw/riscv/cps.c new file mode 100644 index 0000000000..86172be5b3 --- /dev/null +++ b/hw/riscv/cps.c @@ -0,0 +1,196 @@ +/* + * Coherent Processing System emulation. + * + * Copyright (c) 2016 Imagination Technologies + * + * Copyright (c) 2025 MIPS + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/module.h" +#include "hw/riscv/cps.h" +#include "hw/core/qdev-properties.h" +#include "system/reset.h" +#include "hw/intc/riscv_aclint.h" +#include "hw/intc/riscv_aplic.h" +#include "hw/intc/riscv_imsic.h" +#include "hw/pci/msi.h" + +static void riscv_cps_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + RISCVCPSState *s =3D RISCV_CPS(obj); + + /* + * Cover entire address space as there do not seem to be any + * constraints for the base address of CPC . + */ + memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MA= X); + sysbus_init_mmio(sbd, &s->container); +} + +static void main_cpu_reset(void *opaque) +{ + CPUState *cs =3D opaque; + + cpu_reset(cs); +} + +static void riscv_cps_realize(DeviceState *dev, Error **errp) +{ + RISCVCPSState *s =3D RISCV_CPS(dev); + RISCVCPU *cpu; + int i; + + /* Validate num_vp */ + if (s->num_vp =3D=3D 0) { + error_setg(errp, "num-vp must be at least 1"); + return; + } + if (s->num_vp > MAX_HARTS) { + error_setg(errp, "num-vp cannot exceed %d", MAX_HARTS); + return; + } + + /* Allocate CPU array */ + s->cpus =3D g_new0(CPUState *, s->num_vp); + + /* Set up cpu_index and mhartid for avaiable CPUs. */ + int harts_in_cluster =3D s->num_hart * s->num_core; + int num_of_clusters =3D s->num_vp / harts_in_cluster; + for (i =3D 0; i < s->num_vp; i++) { + cpu =3D RISCV_CPU(object_new(s->cpu_type)); + + /* All VPs are halted on reset. Leave powering up to CPC. */ + object_property_set_bool(OBJECT(cpu), "start-powered-off", true, + &error_abort); + + if (!qdev_realize_and_unref(DEVICE(cpu), NULL, errp)) { + return; + } + + /* Store CPU in array */ + s->cpus[i] =3D CPU(cpu); + + /* Set up mhartid */ + int cluster_id =3D i / harts_in_cluster; + int hart_id =3D (i % harts_in_cluster) % s->num_hart; + int core_id =3D (i % harts_in_cluster) / s->num_hart; + int mhartid =3D (cluster_id << MHARTID_CLUSTER_SHIFT) + + (core_id << MHARTID_CORE_SHIFT) + + (hart_id << MHARTID_HART_SHIFT); + cpu->env.mhartid =3D mhartid; + qemu_register_reset(main_cpu_reset, s->cpus[i]); + } + + /* Cluster Power Controller */ + object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_RISCV_CPC); + object_property_set_uint(OBJECT(&s->cpc), "cluster-id", 0, + &error_abort); + object_property_set_uint(OBJECT(&s->cpc), "num-vp", s->num_vp, + &error_abort); + object_property_set_uint(OBJECT(&s->cpc), "num-hart", s->num_hart, + &error_abort); + object_property_set_uint(OBJECT(&s->cpc), "num-core", s->num_core, + &error_abort); + + /* Pass CPUs to CPC using link properties */ + for (i =3D 0; i < s->num_vp; i++) { + char *propname =3D g_strdup_printf("cpu[%d]", i); + object_property_set_link(OBJECT(&s->cpc), propname, + OBJECT(s->cpus[i]), &error_abort); + g_free(propname); + } + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpc), errp)) { + return; + } + + memory_region_add_subregion(&s->container, 0, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc)= , 0)); + + /* Global Configuration Registers */ + object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_RISCV_GCR); + object_property_set_uint(OBJECT(&s->gcr), "cluster-id", 0, + &error_abort); + object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp, + &error_abort); + object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0xa00, + &error_abort); + object_property_set_int(OBJECT(&s->gcr), "gcr-base", s->gcr_base, + &error_abort); + object_property_set_link(OBJECT(&s->gcr), "cpc", OBJECT(&s->cpc.mr), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { + return; + } + + memory_region_add_subregion(&s->container, s->gcr_base, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr)= , 0)); + + for (i =3D 0; i < num_of_clusters; i++) { + uint64_t cm_base =3D GLOBAL_CM_BASE + (CM_SIZE * i); + uint32_t hartid_base =3D i << MHARTID_CLUSTER_SHIFT; + s->aplic =3D riscv_aplic_create(cm_base + AIA_PLIC_M_OFFSET, + AIA_PLIC_M_SIZE, + hartid_base, /* hartid_base */ + MAX_HARTS, /* num_harts */ + APLIC_NUM_SOURCES, + APLIC_NUM_PRIO_BITS, + false, true, NULL); + riscv_aplic_create(cm_base + AIA_PLIC_S_OFFSET, + AIA_PLIC_S_SIZE, + hartid_base, /* hartid_base */ + MAX_HARTS, /* num_harts */ + APLIC_NUM_SOURCES, + APLIC_NUM_PRIO_BITS, + false, false, s->aplic); + /* PLIC changes msi_nonbroken to ture. We revert the change. */ + msi_nonbroken =3D false; + riscv_aclint_swi_create(cm_base + AIA_CLINT_OFFSET, + hartid_base, MAX_HARTS, false); + riscv_aclint_mtimer_create(cm_base + AIA_CLINT_OFFSET + + RISCV_ACLINT_SWI_SIZE, + RISCV_ACLINT_DEFAULT_MTIMER_SIZE, + hartid_base, + MAX_HARTS, + RISCV_ACLINT_DEFAULT_MTIMECMP, + RISCV_ACLINT_DEFAULT_MTIME, + RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, fal= se); + } +} + +static const Property riscv_cps_properties[] =3D { + DEFINE_PROP_UINT32("num-vp", RISCVCPSState, num_vp, 1), + DEFINE_PROP_UINT32("num-hart", RISCVCPSState, num_hart, 1), + DEFINE_PROP_UINT32("num-core", RISCVCPSState, num_core, 1), + DEFINE_PROP_UINT64("gcr-base", RISCVCPSState, gcr_base, GCR_BASE_ADDR), + DEFINE_PROP_STRING("cpu-type", RISCVCPSState, cpu_type), +}; + +static void riscv_cps_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D riscv_cps_realize; + device_class_set_props(dc, riscv_cps_properties); +} + +static const TypeInfo riscv_cps_info =3D { + .name =3D TYPE_RISCV_CPS, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RISCVCPSState), + .instance_init =3D riscv_cps_init, + .class_init =3D riscv_cps_class_init, +}; + +static void riscv_cps_register_types(void) +{ + type_register_static(&riscv_cps_info); +} + +type_init(riscv_cps_register_types) diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 38be72b141..4a22d68233 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -127,12 +127,16 @@ config RISCV_MIPS_CMGCR config RISCV_MIPS_CPC bool =20 +config RISCV_MIPS_CPS + bool + config MIPS_BOSTON_AIA bool default y depends on RISCV64 select RISCV_MIPS_CMGCR select RISCV_MIPS_CPC + select RISCV_MIPS_CPS =20 config MPS2_FPGAIO bool diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 2a8d5b136c..9023b80087 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -15,4 +15,6 @@ riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files( riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-gen= eric.c')) riscv_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true: files('xiangshan= _kmh.c')) =20 +riscv_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true: files('cps.c')) + hw_arch +=3D {'riscv': riscv_ss} --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767941873; cv=none; d=zohomail.com; s=zohoarc; b=Tp/M7wzJIhhKDxeUVgcy1LwlEsbJ8TeWJNgI/BLxFIsIoO0OmOWQD54mqOnF39xSFoLyNyMf57WSNsgUCnG5HPLLct8uJy9wck7Wwrz84GrkUrzPZ2kL++SPHaeULTv350d1S/KAva8gHQFaCYkhnPIsslAeEP9BFSgOFusHLSM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767941873; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mjPsO1iN8zblKX1agU+MryhlTz3TLPeuoLfrtv2SguQ=; b=TDicR67wNQ3KvOJipUlrKzhOkgpKBV0IIwpqtZv74tolw4p54udmGX+Hojh0VI5EX0m8zD0ujhYOkSXqMVz29jVIlCyEA5xF+ouT7rePoOrm16XI8HiCZXM7bocy8hQxUyPJRySIjBD0Mp/xTt4E+7HMxkIB/Cm/HXxGbQF+DPw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176794187357518.906986790640076; Thu, 8 Jan 2026 22:57:53 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ve6RE-0005mg-M7; Fri, 09 Jan 2026 01:57:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ve6Qh-0005Qp-DW for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:57:05 -0500 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ve6Qe-0002xV-Li for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:57:03 -0500 Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-bd1ce1b35e7so2511034a12.0 for ; Thu, 08 Jan 2026 22:57:00 -0800 (PST) Received: from toolbx.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. 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The model can create boot code, if there is no -bios parameter. We can specify -smp x, cores=3Dy,thread=3Dz. Ex: Use 4 cores and 2 threads with each core to have 8 smp cpus as follows. qemu-system-riscv64 -cpu mips-p8700 \ -m 2G -M boston-aia \ -smp 8,cores=3D4,threads=3D2 -kernel fw_payload.bin \ -drive file=3Drootfs.ext2,format=3Draw -serial stdio Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic Acked-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-ID: <20260108134128.2218102-11-djordje.todorovic@htecgroup.com> Signed-off-by: Alistair Francis --- docs/system/riscv/mips.rst | 20 + docs/system/target-riscv.rst | 1 + configs/devices/riscv64-softmmu/default.mak | 1 + hw/riscv/boston-aia.c | 471 ++++++++++++++++++++ hw/riscv/Kconfig | 6 + hw/riscv/meson.build | 1 + 6 files changed, 500 insertions(+) create mode 100644 docs/system/riscv/mips.rst create mode 100644 hw/riscv/boston-aia.c diff --git a/docs/system/riscv/mips.rst b/docs/system/riscv/mips.rst new file mode 100644 index 0000000000..97096421e1 --- /dev/null +++ b/docs/system/riscv/mips.rst @@ -0,0 +1,20 @@ +Boards for RISC-V Processors by MIPS +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +RISC-V processors developed by MIPS support Boston-aia board model. The bo= ard +model supports up to 64 harts with MIPS CPS, MIPS GCR, MIPS CPC, AIA plic, +and AIA clint devices. The model can create boot code, if there is no +```-bios``` parameter. Also, we can specify ```-smp x,cores=3Dy,thread=3Dz= ```. + +Running Linux kernel +-------------------- + +For example, to use 4 cores and 2 threads with each core to have 8 smp cpu= s, +that runs on the ```mips-p8700``` CPU, run qemu as follows: + +.. code-block:: bash + + qemu-system-riscv64 -cpu mips-p8700 \ + -m 2G -M boston-aia \ + -smp 8,cores=3D4,threads=3D2 -kernel fw_payload.bin \ + -drive file=3Drootfs.ext2,format=3Draw -serial stdio diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst index 89b2cb732c..3ad5d1ddaf 100644 --- a/docs/system/target-riscv.rst +++ b/docs/system/target-riscv.rst @@ -68,6 +68,7 @@ undocumented; you can get a complete list by running =20 riscv/microblaze-v-generic riscv/microchip-icicle-kit + riscv/mips riscv/shakti-c riscv/sifive_u riscv/virt diff --git a/configs/devices/riscv64-softmmu/default.mak b/configs/devices/= riscv64-softmmu/default.mak index e485bbd1a3..a8e4d0ab33 100644 --- a/configs/devices/riscv64-softmmu/default.mak +++ b/configs/devices/riscv64-softmmu/default.mak @@ -12,3 +12,4 @@ # CONFIG_MICROCHIP_PFSOC=3Dn # CONFIG_SHAKTI_C=3Dn # CONFIG_XIANGSHAN_KUNMINGHU=3Dn +# CONFIG_MIPS_BOSTON_AIA=3Dn diff --git a/hw/riscv/boston-aia.c b/hw/riscv/boston-aia.c new file mode 100644 index 0000000000..1d9fa868c8 --- /dev/null +++ b/hw/riscv/boston-aia.c @@ -0,0 +1,471 @@ +/* + * MIPS Boston-aia development board emulation. + * + * Copyright (c) 2016 Imagination Technologies + * + * Copyright (c) 2025 MIPS + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" + +#include "hw/core/boards.h" +#include "hw/char/serial-mm.h" +#include "hw/ide/pci.h" +#include "hw/ide/ahci-pci.h" +#include "hw/core/loader.h" +#include "hw/riscv/cps.h" +#include "hw/pci-host/xilinx-pcie.h" +#include "hw/core/qdev-properties.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "chardev/char.h" +#include "system/address-spaces.h" +#include "system/device_tree.h" +#include "system/system.h" +#include "system/qtest.h" +#include "system/runstate.h" + +#include +#include "qom/object.h" + +#define TYPE_MIPS_BOSTON_AIA "mips-boston-aia" +typedef struct BostonState BostonState; +DECLARE_INSTANCE_CHECKER(BostonState, BOSTON, + TYPE_MIPS_BOSTON_AIA) + +enum { + BOSTON_PCIE2, + BOSTON_PCIE2_MMIO, + BOSTON_PLATREG, + BOSTON_UART, + BOSTON_LCD, + BOSTON_FLASH, + BOSTON_HIGHDDR, +}; + +static const MemMapEntry boston_memmap[] =3D { + [BOSTON_PCIE2] =3D { 0x14000000, 0x2000000 }, + [BOSTON_PCIE2_MMIO] =3D { 0x16000000, 0x100000 }, + [BOSTON_PLATREG] =3D { 0x17ffd000, 0x1000 }, + [BOSTON_UART] =3D { 0x17ffe000, 0x20 }, + [BOSTON_LCD] =3D { 0x17fff000, 0x8 }, + [BOSTON_FLASH] =3D { 0x18000000, 0x8000000 }, + [BOSTON_HIGHDDR] =3D { 0x80000000, 0x0 }, +}; + +/* Interrupt numbers for APLIC. */ +#define UART_INT 4 +#define PCIE2_INT 7 + +struct BostonState { + SysBusDevice parent_obj; + + MachineState *mach; + RISCVCPSState cps; + SerialMM *uart; + + CharFrontend lcd_display; + char lcd_content[8]; + bool lcd_inited; +}; + +enum boston_plat_reg { + PLAT_FPGA_BUILD =3D 0x00, + PLAT_CORE_CL =3D 0x04, + PLAT_WRAPPER_CL =3D 0x08, + PLAT_SYSCLK_STATUS =3D 0x0c, + PLAT_SOFTRST_CTL =3D 0x10, +#define PLAT_SOFTRST_CTL_SYSRESET (1 << 4) + PLAT_DDR3_STATUS =3D 0x14, +#define PLAT_DDR3_STATUS_LOCKED (1 << 0) +#define PLAT_DDR3_STATUS_CALIBRATED (1 << 2) +#define PLAT_DDR3_INTERFACE_RESET (1 << 3) + PLAT_PCIE_STATUS =3D 0x18, +#define PLAT_PCIE_STATUS_PCIE0_LOCKED (1 << 0) +#define PLAT_PCIE_STATUS_PCIE1_LOCKED (1 << 8) +#define PLAT_PCIE_STATUS_PCIE2_LOCKED (1 << 16) + PLAT_FLASH_CTL =3D 0x1c, + PLAT_SPARE0 =3D 0x20, + PLAT_SPARE1 =3D 0x24, + PLAT_SPARE2 =3D 0x28, + PLAT_SPARE3 =3D 0x2c, + PLAT_MMCM_DIV =3D 0x30, +#define PLAT_MMCM_DIV_CLK0DIV_SHIFT 0 +#define PLAT_MMCM_DIV_INPUT_SHIFT 8 +#define PLAT_MMCM_DIV_MUL_SHIFT 16 +#define PLAT_MMCM_DIV_CLK1DIV_SHIFT 24 + PLAT_BUILD_CFG =3D 0x34, +#define PLAT_BUILD_CFG_IOCU_EN (1 << 0) +#define PLAT_BUILD_CFG_PCIE0_EN (1 << 1) +#define PLAT_BUILD_CFG_PCIE1_EN (1 << 2) +#define PLAT_BUILD_CFG_PCIE2_EN (1 << 3) + PLAT_DDR_CFG =3D 0x38, +#define PLAT_DDR_CFG_SIZE (0xf << 0) +#define PLAT_DDR_CFG_MHZ (0xfff << 4) + PLAT_NOC_PCIE0_ADDR =3D 0x3c, + PLAT_NOC_PCIE1_ADDR =3D 0x40, + PLAT_NOC_PCIE2_ADDR =3D 0x44, + PLAT_SYS_CTL =3D 0x48, +}; + +static void boston_lcd_event(void *opaque, QEMUChrEvent event) +{ + BostonState *s =3D opaque; + if (event =3D=3D CHR_EVENT_OPENED && !s->lcd_inited) { + qemu_chr_fe_printf(&s->lcd_display, " "); + s->lcd_inited =3D true; + } +} + +static uint64_t boston_lcd_read(void *opaque, hwaddr addr, + unsigned size) +{ + BostonState *s =3D opaque; + uint64_t val =3D 0; + + switch (size) { + case 8: + val |=3D (uint64_t)s->lcd_content[(addr + 7) & 0x7] << 56; + val |=3D (uint64_t)s->lcd_content[(addr + 6) & 0x7] << 48; + val |=3D (uint64_t)s->lcd_content[(addr + 5) & 0x7] << 40; + val |=3D (uint64_t)s->lcd_content[(addr + 4) & 0x7] << 32; + /* fall through */ + case 4: + val |=3D (uint64_t)s->lcd_content[(addr + 3) & 0x7] << 24; + val |=3D (uint64_t)s->lcd_content[(addr + 2) & 0x7] << 16; + /* fall through */ + case 2: + val |=3D (uint64_t)s->lcd_content[(addr + 1) & 0x7] << 8; + /* fall through */ + case 1: + val |=3D (uint64_t)s->lcd_content[(addr + 0) & 0x7]; + break; + } + + return val; +} + +static void boston_lcd_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + BostonState *s =3D opaque; + + switch (size) { + case 8: + s->lcd_content[(addr + 7) & 0x7] =3D val >> 56; + s->lcd_content[(addr + 6) & 0x7] =3D val >> 48; + s->lcd_content[(addr + 5) & 0x7] =3D val >> 40; + s->lcd_content[(addr + 4) & 0x7] =3D val >> 32; + /* fall through */ + case 4: + s->lcd_content[(addr + 3) & 0x7] =3D val >> 24; + s->lcd_content[(addr + 2) & 0x7] =3D val >> 16; + /* fall through */ + case 2: + s->lcd_content[(addr + 1) & 0x7] =3D val >> 8; + /* fall through */ + case 1: + s->lcd_content[(addr + 0) & 0x7] =3D val; + break; + } + + qemu_chr_fe_printf(&s->lcd_display, + "\r%-8.8s", s->lcd_content); +} + +static const MemoryRegionOps boston_lcd_ops =3D { + .read =3D boston_lcd_read, + .write =3D boston_lcd_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static uint64_t boston_platreg_read(void *opaque, hwaddr addr, + unsigned size) +{ + BostonState *s =3D opaque; + uint32_t gic_freq, val; + + switch (addr & 0xffff) { + case PLAT_FPGA_BUILD: + case PLAT_CORE_CL: + case PLAT_WRAPPER_CL: + return 0; + case PLAT_DDR3_STATUS: + return PLAT_DDR3_STATUS_LOCKED | PLAT_DDR3_STATUS_CALIBRATED + | PLAT_DDR3_INTERFACE_RESET; + case PLAT_MMCM_DIV: + gic_freq =3D 25000000 / 1000000; + val =3D gic_freq << PLAT_MMCM_DIV_INPUT_SHIFT; + val |=3D 1 << PLAT_MMCM_DIV_MUL_SHIFT; + val |=3D 1 << PLAT_MMCM_DIV_CLK0DIV_SHIFT; + val |=3D 1 << PLAT_MMCM_DIV_CLK1DIV_SHIFT; + return val; + case PLAT_BUILD_CFG: + val =3D PLAT_BUILD_CFG_PCIE0_EN; + val |=3D PLAT_BUILD_CFG_PCIE1_EN; + val |=3D PLAT_BUILD_CFG_PCIE2_EN; + return val; + case PLAT_DDR_CFG: + val =3D s->mach->ram_size / GiB; + assert(!(val & ~PLAT_DDR_CFG_SIZE)); + val |=3D PLAT_DDR_CFG_MHZ; + return val; + default: + qemu_log_mask(LOG_UNIMP, "Read platform register 0x%" HWADDR_PRIx = "\n", + addr & 0xffff); + return 0; + } +} + +static void boston_platreg_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + if (size !=3D 4) { + qemu_log_mask(LOG_UNIMP, "%uB platform register write\n", size); + return; + } + + switch (addr & 0xffff) { + case PLAT_FPGA_BUILD: + case PLAT_CORE_CL: + case PLAT_WRAPPER_CL: + case PLAT_DDR3_STATUS: + case PLAT_PCIE_STATUS: + case PLAT_MMCM_DIV: + case PLAT_BUILD_CFG: + case PLAT_DDR_CFG: + /* read only */ + break; + case PLAT_SOFTRST_CTL: + if (val & PLAT_SOFTRST_CTL_SYSRESET) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + } + break; + default: + qemu_log_mask(LOG_UNIMP, "Write platform register 0x%" HWADDR_PRIx + " =3D 0x%" PRIx64 "\n", addr & 0xffff, val); + break; + } +} + +static const MemoryRegionOps boston_platreg_ops =3D { + .read =3D boston_platreg_read, + .write =3D boston_platreg_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static const TypeInfo boston_device =3D { + .name =3D TYPE_MIPS_BOSTON_AIA, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(BostonState), +}; + +static void boston_register_types(void) +{ + type_register_static(&boston_device); +} +type_init(boston_register_types) + +#define NUM_INSNS 6 +static void gen_firmware(uint32_t *p) +{ + int i; + uint32_t reset_vec[NUM_INSNS] =3D { + /* CM relocate */ + 0x1fb802b7, /* li t0,0x1fb80000 */ + 0x16100337, /* li t1,0x16100000 */ + 0x0062b423, /* sd t1,8(t0) */ + /* Jump to 0x80000000 */ + 0x00100293, /* li t0,1 */ + 0x01f29293, /* slli t0,t0,1f */ + 0x00028067 /* jr t0 */ + }; + + for (i =3D 0; i < NUM_INSNS; i++) { + *p++ =3D reset_vec[i]; + } +} + +static inline XilinxPCIEHost * +xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr, + hwaddr cfg_base, uint64_t cfg_size, + hwaddr mmio_base, uint64_t mmio_size, + qemu_irq irq) +{ + DeviceState *dev; + MemoryRegion *cfg, *mmio; + + dev =3D qdev_new(TYPE_XILINX_PCIE_HOST); + + qdev_prop_set_uint32(dev, "bus_nr", bus_nr); + qdev_prop_set_uint64(dev, "cfg_base", cfg_base); + qdev_prop_set_uint64(dev, "cfg_size", cfg_size); + qdev_prop_set_uint64(dev, "mmio_base", mmio_base); + qdev_prop_set_uint64(dev, "mmio_size", mmio_size); + + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + cfg =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0); + + mmio =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); + memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0); + + qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq); + + return XILINX_PCIE_HOST(dev); +} + +static void boston_mach_init(MachineState *machine) +{ + DeviceState *dev; + BostonState *s; + MemoryRegion *flash, *ddr_low_alias, *lcd, *platreg; + MemoryRegion *sys_mem =3D get_system_memory(); + XilinxPCIEHost *pcie2; + PCIDevice *pdev; + AHCIPCIState *ich9; + DriveInfo *hd[6]; + Chardev *chr; + int fw_size; + + if ((machine->ram_size % GiB) || + (machine->ram_size > (4 * GiB))) { + error_report("Memory size must be 1GB, 2GB, 3GB, or 4GB"); + exit(1); + } + + if (machine->smp.cpus / machine->smp.cores / machine->smp.threads > 1)= { + error_report( + "Invalid -smp x,cores=3Dy,threads=3Dz. The max number of clust= ers " + "supported is 1"); + exit(1); + } + + dev =3D qdev_new(TYPE_MIPS_BOSTON_AIA); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + s =3D BOSTON(dev); + s->mach =3D machine; + + object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_RISCV_CP= S); + object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, + &error_fatal); + object_property_set_uint(OBJECT(&s->cps), "num-vp", machine->smp.cpus, + &error_fatal); + object_property_set_uint(OBJECT(&s->cps), "num-hart", machine->smp.thr= eads, + &error_fatal); + object_property_set_uint(OBJECT(&s->cps), "num-core", machine->smp.cor= es, + &error_fatal); + object_property_set_uint(OBJECT(&s->cps), "gcr-base", GCR_BASE_ADDR, + &error_fatal); + sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); + + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); + + flash =3D g_new(MemoryRegion, 1); + memory_region_init_rom(flash, NULL, "boston.flash", + boston_memmap[BOSTON_FLASH].size, &error_fatal); + memory_region_add_subregion_overlap(sys_mem, + boston_memmap[BOSTON_FLASH].base, + flash, 0); + + memory_region_add_subregion_overlap(sys_mem, + boston_memmap[BOSTON_HIGHDDR].base, + machine->ram, 0); + + ddr_low_alias =3D g_new(MemoryRegion, 1); + memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr", + machine->ram, 0, + MIN(machine->ram_size, (256 * MiB))); + memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0); + + pcie2 =3D xilinx_pcie_init(sys_mem, 2, + boston_memmap[BOSTON_PCIE2].base, + boston_memmap[BOSTON_PCIE2].size, + boston_memmap[BOSTON_PCIE2_MMIO].base, + boston_memmap[BOSTON_PCIE2_MMIO].size, + qdev_get_gpio_in(s->cps.aplic, PCIE2_INT)); + + platreg =3D g_new(MemoryRegion, 1); + memory_region_init_io(platreg, NULL, &boston_platreg_ops, s, + "boston-platregs", + boston_memmap[BOSTON_PLATREG].size); + memory_region_add_subregion_overlap(sys_mem, + boston_memmap[BOSTON_PLATREG].base, platreg, 0); + + s->uart =3D serial_mm_init(sys_mem, boston_memmap[BOSTON_UART].base, 2, + qdev_get_gpio_in(s->cps.aplic, UART_INT), 100= 00000, + serial_hd(0), DEVICE_LITTLE_ENDIAN); + + lcd =3D g_new(MemoryRegion, 1); + memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8= ); + memory_region_add_subregion_overlap(sys_mem, + boston_memmap[BOSTON_LCD].base, lc= d, 0); + + chr =3D qemu_chr_new("lcd", "vc:320x240", NULL); + qemu_chr_fe_init(&s->lcd_display, chr, NULL); + qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL, + boston_lcd_event, NULL, s, NULL, true); + + pdev =3D pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->se= c_bus, + PCI_DEVFN(0, 0), TYPE_ICH9_AHCI= ); + ich9 =3D ICH9_AHCI(pdev); + g_assert(ARRAY_SIZE(hd) =3D=3D ich9->ahci.ports); + ide_drive_get(hd, ich9->ahci.ports); + ahci_ide_create_devs(&ich9->ahci, hd); + + if (machine->firmware) { + fw_size =3D load_image_targphys(machine->firmware, + 0x1fc00000, 4 * MiB, NULL); + if (fw_size =3D=3D -1) { + error_report("unable to load firmware image '%s'", + machine->firmware); + exit(1); + } + if (machine->kernel_filename) { + fw_size =3D load_image_targphys(machine->kernel_filename, + 0x80000000, 64 * MiB, NULL); + if (fw_size =3D=3D -1) { + error_report("unable to load kernel image '%s'", + machine->kernel_filename); + exit(1); + } + } + } else if (machine->kernel_filename) { + fw_size =3D load_image_targphys(machine->kernel_filename, + 0x80000000, 64 * MiB, NULL); + if (fw_size =3D=3D -1) { + error_report("unable to load kernel image '%s'", + machine->kernel_filename); + exit(1); + } + + gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000); + } else if (!qtest_enabled()) { + error_report("Please provide either a -kernel or -bios argument"); + exit(1); + } +} + +static void boston_mach_class_init(MachineClass *mc) +{ + mc->desc =3D "MIPS Boston-aia"; + mc->init =3D boston_mach_init; + mc->block_default_type =3D IF_IDE; + mc->default_ram_size =3D 2 * GiB; + mc->default_ram_id =3D "boston.ddr"; + mc->max_cpus =3D MAX_HARTS; + mc->default_cpu_type =3D TYPE_RISCV_CPU_MIPS_P8700; +} + +DEFINE_MACHINE("boston-aia", boston_mach_class_init) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index fc9c35bd98..0222c93f87 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -128,3 +128,9 @@ config XIANGSHAN_KUNMINGHU select RISCV_APLIC select RISCV_IMSIC select SERIAL_MM + +config MIPS_BOSTON_AIA + bool + default y + select PCI_EXPRESS + select PCI_EXPRESS_XILINX diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 9023b80087..533472e22a 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -16,5 +16,6 @@ riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files(= 'microblaze-v-generic.c riscv_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true: files('xiangshan= _kmh.c')) =20 riscv_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true: files('cps.c')) +riscv_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: files('boston-aia.c'= )) =20 hw_arch +=3D {'riscv': riscv_ss} --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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There is no PCH GbE device emulation, so use an `e1000e` instead. We place it in **slot 0, function 1** in order not to conflict with the existing AHCI device in slot 0 func 0. Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic Reviewed-by: Daniel Henrique Barboza Message-ID: <20260108134128.2218102-12-djordje.todorovic@htecgroup.com> Signed-off-by: Alistair Francis --- hw/riscv/boston-aia.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/riscv/boston-aia.c b/hw/riscv/boston-aia.c index 1d9fa868c8..b90da096ea 100644 --- a/hw/riscv/boston-aia.c +++ b/hw/riscv/boston-aia.c @@ -424,6 +424,11 @@ static void boston_mach_init(MachineState *machine) ide_drive_get(hd, ich9->ahci.ports); ahci_ide_create_devs(&ich9->ahci, hd); =20 + /* Create e1000e using slot 0 func 1 */ + pci_init_nic_in_slot(&PCI_BRIDGE(&pcie2->root)->sec_bus, "e1000e", NUL= L, + "00.1"); + pci_init_nic_devices(&PCI_BRIDGE(&pcie2->root)->sec_bus, "e1000e"); + if (machine->firmware) { fw_size =3D load_image_targphys(machine->firmware, 0x1fc00000, 4 * MiB, NULL); --=20 2.52.0 From nobody Mon Feb 9 16:27:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1767942001; cv=none; d=zohomail.com; s=zohoarc; b=XIExz7QJSQkWjnwWHoZN1/u791mPOYUX/2IcxtAFGqX192DrcT7IXU5y9ckbxsfgF+muEvtYoV6kCSLP/xl/ZjrHa1PLs9BdeUIOauR0ceviGDmVUAsKxbMmdr7uDpcy5HNYYmNjehEqqxM2R+4XUFRX0fHvCGFcCHfCtafrBow= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767942001; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+j/qPjdKZed+xiVY9WDXNNYe7vPb+h/Yx+dAPCmE0lo=; b=hkMJXBVsph8iQZMnaWlNFEuJQCheIzqWLMdDIQqrBFFBkgPXtRP7nxMcvJ7hkUXrmxSZ37bjEFGXE78wawY2zESLCK2WIixriqQ1/U1Qn4NlBtiRVEFPN2c6ydjvIqt5kEiHH0AShRUZ09R8qBj3/mP0jE9vc8XjQlgSVl5IDhw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176794200174410.800250950180725; Thu, 8 Jan 2026 23:00:01 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ve6RP-0006Vo-Ji; Fri, 09 Jan 2026 01:57:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ve6Qn-0005Tx-Uh for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:57:13 -0500 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ve6Ql-0002yo-Vx for qemu-devel@nongnu.org; Fri, 09 Jan 2026 01:57:09 -0500 Received: by mail-pg1-x535.google.com with SMTP id 41be03b00d2f7-bc274b8b15bso2586964a12.1 for ; Thu, 08 Jan 2026 22:57:07 -0800 (PST) Received: from toolbx.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. 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The P8700 RISC-V based CPU by MIPS supports it at the moment. Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic Acked-by: Alistair Francis Reviewed-by: Thomas Huth Message-ID: <20260108134128.2218102-13-djordje.todorovic@htecgroup.com> Signed-off-by: Alistair Francis --- tests/functional/riscv64/meson.build | 2 + tests/functional/riscv64/test_boston.py | 123 ++++++++++++++++++++++++ 2 files changed, 125 insertions(+) create mode 100755 tests/functional/riscv64/test_boston.py diff --git a/tests/functional/riscv64/meson.build b/tests/functional/riscv6= 4/meson.build index c1704d9275..b996c89d7d 100644 --- a/tests/functional/riscv64/meson.build +++ b/tests/functional/riscv64/meson.build @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later =20 test_riscv64_timeouts =3D { + 'boston' : 120, 'tuxrun' : 120, } =20 @@ -10,6 +11,7 @@ tests_riscv64_system_quick =3D [ ] =20 tests_riscv64_system_thorough =3D [ + 'boston', 'sifive_u', 'tuxrun', ] diff --git a/tests/functional/riscv64/test_boston.py b/tests/functional/ris= cv64/test_boston.py new file mode 100755 index 0000000000..385de6a61d --- /dev/null +++ b/tests/functional/riscv64/test_boston.py @@ -0,0 +1,123 @@ +#!/usr/bin/env python3 +# +# Boston board test for RISC-V P8700 processor by MIPS +# +# Copyright (c) 2025 MIPS +# +# SPDX-License-Identifier: GPL-2.0-or-later +# + +from qemu_test import QemuSystemTest, Asset +from qemu_test import wait_for_console_pattern + + +class RiscvBostonTest(QemuSystemTest): + """ + Test the boston-aia board with P8700 processor + """ + + ASSET_FW_PAYLOAD =3D Asset( + 'https://github.com/MIPS/linux-test-downloads/raw/main/p8700/fw_pa= yload.bin', + 'd6f4ae14d0c178c1d0bb38ddf64557536ca8602a588b220729a8aa17caa383aa') + + ASSET_ROOTFS =3D Asset( + 'https://github.com/MIPS/linux-test-downloads/raw/main/p8700/rootf= s.ext2', + 'f937e21b588f0d1d17d10a063053979686897bbbbc5e9617a5582f7c1f48e565') + + def _boot_linux_test(self, smp_count): + """Common setup and boot test for Linux on Boston board + + Args: + smp_count: Number of CPUs to use for SMP + """ + self.set_machine('boston-aia') + fw_payload_path =3D self.ASSET_FW_PAYLOAD.fetch() + rootfs_path =3D self.ASSET_ROOTFS.fetch() + + self.vm.add_args('-cpu', 'mips-p8700') + self.vm.add_args('-m', '2G') + self.vm.add_args('-smp', str(smp_count)) + self.vm.add_args('-kernel', fw_payload_path) + self.vm.add_args('-drive', f'file=3D{rootfs_path},format=3Draw,sna= pshot=3Don') + + self.vm.set_console() + self.vm.launch() + + # Wait for OpenSBI + wait_for_console_pattern(self, 'OpenSBI') + + # Wait for Linux kernel boot + wait_for_console_pattern(self, 'Linux version') + wait_for_console_pattern(self, 'Machine model: MIPS P8700') + + # Test e1000e network card functionality + wait_for_console_pattern(self, 'e1000e') + wait_for_console_pattern(self, 'Network Connection') + + # Wait for boot to complete - system reaches login prompt + wait_for_console_pattern(self, 'Run /sbin/init as init process') + + def test_boston_boot_linux_min_cpus(self): + """ + Test Linux kernel boot with minimum CPU count (2) + """ + self._boot_linux_test(smp_count=3D2) + + def test_boston_boot_linux_7_cpus(self): + """ + Test Linux kernel boot with 7 CPUs + + 7 CPUs is a special configuration that tests odd CPU count + handling and ensures proper core distribution across clusters. + """ + self._boot_linux_test(smp_count=3D7) + + def test_boston_boot_linux_35_cpus(self): + """ + Test Linux kernel boot with 35 CPUs + + 35 CPUs is a special configuration that tests a non-power-of-2 + CPU count above 32, validating proper handling of larger + asymmetric SMP configurations. + """ + self._boot_linux_test(smp_count=3D35) + + def test_boston_boot_linux_max_cpus(self): + """ + Test Linux kernel boot with maximum supported CPU count (64) + """ + self._boot_linux_test(smp_count=3D64) + + def test_boston_invalid_cpu_count(self): + """ + Test that 65 CPUs is rejected as invalid (negative test case) + """ + from subprocess import run, PIPE + + fw_payload_path =3D self.ASSET_FW_PAYLOAD.fetch() + rootfs_path =3D self.ASSET_ROOTFS.fetch() + + cmd =3D [ + self.qemu_bin, + '-M', 'boston-aia', + '-cpu', 'mips-p8700', + '-m', '2G', + '-smp', '65', + '-kernel', fw_payload_path, + '-drive', f'file=3D{rootfs_path},format=3Draw,snapshot=3Don', + '-nographic' + ] + + # Run QEMU and expect it to fail immediately. + result =3D run(cmd, capture_output=3DTrue, text=3DTrue, timeout=3D= 5) + + # Check that QEMU exited with error code 1 + self.assertEqual(result.returncode, 1, + "QEMU should exit with code 1 for invalid SMP cou= nt") + + # Check error message + self.assertIn('Invalid SMP CPUs 65', result.stderr, + "Error message should indicate invalid SMP CPU count= ") + +if __name__ =3D=3D '__main__': + QemuSystemTest.main() --=20 2.52.0