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And the VTYPE.altfmt field is used to select the OFP8 format. * altfmt =3D 0: OFP8.e4m3 to BF16 * altfmt =3D 1: OFP8.e5m2 to BF16 Signed-off-by: Max Chou --- target/riscv/helper.h | 12 +++ target/riscv/insn_trans/trans_rvbf16.c.inc | 16 +++- target/riscv/vector_helper.c | 93 ++++++++++++++++++++++ 3 files changed, 117 insertions(+), 4 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index eb0a488ba8..356c24d9fb 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1247,6 +1247,18 @@ DEF_HELPER_5(vfwcvtbf16_f_f_v, void, ptr, ptr, ptr, = env, i32) DEF_HELPER_6(vfwmaccbf16_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwmaccbf16_vf, void, ptr, ptr, i64, ptr, env, i32) =20 +/* OFP8 functions */ +DEF_HELPER_5(vfwcvtbf16_f_f_v_ofp8e4m3, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvtbf16_f_f_v_ofp8e5m2, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvtbf16_f_f_w_ofp8e4m3, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvtbf16_f_f_w_ofp8e5m2, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvtbf16_sat_f_f_w_ofp8e4m3, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvtbf16_sat_f_f_w_ofp8e5m2, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_f_q_ofp8e4m3, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_f_q_ofp8e5m2, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_sat_f_f_q_ofp8e4m3, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_sat_f_f_q_ofp8e5m2, void, ptr, ptr, ptr, env, i32) + /* Vector crypto functions */ DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn= _trans/trans_rvbf16.c.inc index 6cfda03d2e..9aafd4d2ef 100644 --- a/target/riscv/insn_trans/trans_rvbf16.c.inc +++ b/target/riscv/insn_trans/trans_rvbf16.c.inc @@ -92,11 +92,20 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, a= rg_vfncvtbf16_f_f_w *a) static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v= *a) { REQUIRE_FPU; - REQUIRE_ZVFBFMIN(ctx); =20 - if (opfv_widen_check(ctx, a) && (ctx->sew =3D=3D MO_16)) { + if (opfv_widen_check(ctx, a) && + ((ctx->sew =3D=3D MO_16 && ctx->cfg_ptr->ext_zvfbfmin) || + (ctx->sew =3D=3D MO_8 && ctx->cfg_ptr->ext_zvfofp8min))) { + gen_helper_gvec_3_ptr *fn; uint32_t data =3D 0; =20 + if (ctx->sew =3D=3D MO_16) { + fn =3D gen_helper_vfwcvtbf16_f_f_v; + } else { + fn =3D ctx->altfmt ? gen_helper_vfwcvtbf16_f_f_v_ofp8e5m2 : + gen_helper_vfwcvtbf16_f_f_v_ofp8e4m3; + } + gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -106,8 +115,7 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, a= rg_vfwcvtbf16_f_f_v *a) tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), vreg_ofs(ctx, a->rs2), tcg_env, ctx->cfg_ptr->vlenb, - ctx->cfg_ptr->vlenb, data, - gen_helper_vfwcvtbf16_f_f_v); + ctx->cfg_ptr->vlenb, data, fn); finalize_rvv_inst(ctx); return true; } diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index ee5a1e595b..759ebb3251 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -5024,6 +5024,99 @@ GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4) RVVCALL(OPFVV1, vfncvtbf16_f_f_w, NOP_UU_H, H2, H4, float32_to_bfloat16) GEN_VEXT_V_ENV(vfncvtbf16_f_f_w, 2) =20 +/* + * Vector OFP8 conversion operations for Zvfofp8min + * + * Note: The OCP FP8 conversion functions use flags in float_status to con= trol + * the same_canonical_nan and only_quiet_nan behavior. RISC-V should set + * ocp_fp8_same_canonical_nan and ocp_fp8e5m2_no_signal_nan flags during C= PU + * initialization to get the correct Zvfofp8min behavior. + */ + +/* Wrapper functions for RVVCALL macro compatibility */ +static uint8_t vfncvt_bf16_to_e4m3(uint16_t a, float_status *s) +{ + return bfloat16_to_float8_e4m3(a, false, s); +} + +static uint8_t vfncvt_bf16_to_e5m2(uint16_t a, float_status *s) +{ + return bfloat16_to_float8_e5m2(a, false, s); +} + +static uint8_t vfncvt_bf16_to_e4m3_sat(uint16_t a, float_status *s) +{ + return bfloat16_to_float8_e4m3(a, true, s); +} + +static uint8_t vfncvt_bf16_to_e5m2_sat(uint16_t a, float_status *s) +{ + return bfloat16_to_float8_e5m2(a, true, s); +} + +static uint8_t vfncvt_f32_to_e4m3(uint32_t a, float_status *s) +{ + return float32_to_float8_e4m3(a, false, s); +} + +static uint8_t vfncvt_f32_to_e5m2(uint32_t a, float_status *s) +{ + return float32_to_float8_e5m2(a, false, s); +} + +static uint8_t vfncvt_f32_to_e4m3_sat(uint32_t a, float_status *s) +{ + return float32_to_float8_e4m3(a, true, s); +} + +static uint8_t vfncvt_f32_to_e5m2_sat(uint32_t a, float_status *s) +{ + return float32_to_float8_e5m2(a, true, s); +} + +/* vfwcvtbf16.f.f.w vd, vs2, vm # Convert OFP8 to BF16. */ +RVVCALL(OPFVV1, vfwcvtbf16_f_f_v_ofp8e4m3, WOP_UU_B, H2, H1, + float8_e4m3_to_bfloat16) +RVVCALL(OPFVV1, vfwcvtbf16_f_f_v_ofp8e5m2, WOP_UU_B, H2, H1, + float8_e5m2_to_bfloat16) +GEN_VEXT_V_ENV(vfwcvtbf16_f_f_v_ofp8e4m3, 2) +GEN_VEXT_V_ENV(vfwcvtbf16_f_f_v_ofp8e5m2, 2) + +/* vfncvtbf16.f.f.w vd, vs2, vm # Convert BF16 to OFP8 without saturation.= */ +RVVCALL(OPFVV1, vfncvtbf16_f_f_w_ofp8e4m3, NOP_UU_B, H1, H2, + vfncvt_bf16_to_e4m3) +RVVCALL(OPFVV1, vfncvtbf16_f_f_w_ofp8e5m2, NOP_UU_B, H1, H2, + vfncvt_bf16_to_e5m2) +GEN_VEXT_V_ENV(vfncvtbf16_f_f_w_ofp8e4m3, 1) +GEN_VEXT_V_ENV(vfncvtbf16_f_f_w_ofp8e5m2, 1) + +/* vfncvtbf16.sat.f.f.w vd, vs2, vm # Convert BF16 to OFP8 with saturation= . */ +RVVCALL(OPFVV1, vfncvtbf16_sat_f_f_w_ofp8e4m3, NOP_UU_B, H1, H2, + vfncvt_bf16_to_e4m3_sat) +RVVCALL(OPFVV1, vfncvtbf16_sat_f_f_w_ofp8e5m2, NOP_UU_B, H1, H2, + vfncvt_bf16_to_e5m2_sat) +GEN_VEXT_V_ENV(vfncvtbf16_sat_f_f_w_ofp8e4m3, 1) +GEN_VEXT_V_ENV(vfncvtbf16_sat_f_f_w_ofp8e5m2, 1) + +/* Quad-width narrowing type for FP32 to OFP8 */ +#define QOP_UU_B uint8_t, uint32_t, uint32_t + +/* vfncvt.f.f.q vd, vs2, vm # Convert FP32 to OFP8. */ +RVVCALL(OPFVV1, vfncvt_f_f_q_ofp8e4m3, QOP_UU_B, H1, H4, + vfncvt_f32_to_e4m3) +RVVCALL(OPFVV1, vfncvt_f_f_q_ofp8e5m2, QOP_UU_B, H1, H4, + vfncvt_f32_to_e5m2) +GEN_VEXT_V_ENV(vfncvt_f_f_q_ofp8e4m3, 1) +GEN_VEXT_V_ENV(vfncvt_f_f_q_ofp8e5m2, 1) + +/* vfncvt.sat.f.f.q vd, vs2, vm # Convert FP32 to OFP8 with saturation. */ +RVVCALL(OPFVV1, vfncvt_sat_f_f_q_ofp8e4m3, QOP_UU_B, H1, H4, + vfncvt_f32_to_e4m3_sat) +RVVCALL(OPFVV1, vfncvt_sat_f_f_q_ofp8e5m2, QOP_UU_B, H1, H4, + vfncvt_f32_to_e5m2_sat) +GEN_VEXT_V_ENV(vfncvt_sat_f_f_q_ofp8e4m3, 1) +GEN_VEXT_V_ENV(vfncvt_sat_f_f_q_ofp8e5m2, 1) + /* * Vector Reduction Operations */ --=20 2.43.7