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Thu, 08 Jan 2026 07:16:59 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Aurelien Jarno , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Max Chou , Alistair Francis Subject: [PATCH 01/18] target/riscv: rvv: Fix NOP_UU_B vs2 width Date: Thu, 8 Jan 2026 23:16:32 +0800 Message-ID: <20260108151650.16329-2-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260108151650.16329-1-max.chou@sifive.com> References: <20260108151650.16329-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=max.chou@sifive.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1767885637171158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Max Chou --- target/riscv/vector_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 5aea553814..ec0ea4c143 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4972,7 +4972,7 @@ GEN_VEXT_V_ENV(vfwcvtbf16_f_f_v, 4) =20 /* Narrowing Floating-Point/Integer Type-Convert Instructions */ /* (TD, T2, TX2) */ -#define NOP_UU_B uint8_t, uint16_t, uint32_t +#define NOP_UU_B uint8_t, uint16_t, uint16_t #define NOP_UU_H uint16_t, uint32_t, uint32_t #define NOP_UU_W uint32_t, uint64_t, uint64_t /* vfncvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */ --=20 2.43.7 From nobody Mon Feb 9 03:17:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Max Chou --- fpu/softfloat-specialize.c.inc | 57 ++++++++++++++++++++++++++- include/fpu/softfloat-helpers.h | 20 ++++++++++ include/fpu/softfloat-types.h | 23 +++++++++++ include/fpu/softfloat.h | 70 +++++++++++++++++++++++++++++++++ 4 files changed, 169 insertions(+), 1 deletion(-) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index ba4fa08b7b..3a3bcd22ae 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -226,6 +226,30 @@ floatx80 floatx80_default_inf(bool zSign, float_status= *status) return packFloatx80(zSign, 0x7fff, z ? 0 : (1ULL << 63)); } =20 +/*------------------------------------------------------------------------= ---- +| Returns 1 if the OCP(Open Compute Platform) FP8 value `a' is a quiet NaN; +| otherwise returns 0. +*-------------------------------------------------------------------------= ---*/ + +bool float8_e4m3_is_quiet_nan(float8_e4m3 a_, float_status *status) +{ + return float8_e4m3_is_any_nan(a_); +} + +bool float8_e5m2_is_quiet_nan(float8_e5m2 a_, float_status *status) +{ + if (no_signaling_nans(status) || status->ocp_fp8e5m2_no_signal_nan) { + return float8_e5m2_is_any_nan(a_); + } else { + uint8_t a =3D float8_e5m2_val(a_); + if (snan_bit_is_one(status)) { + return (((a >> 1) & 0x3F) =3D=3D 0x3E) && (a & 0x1); + } else { + return ((a >> 1) & 0x3F) =3D=3D 0x3F; + } + } +} + /*------------------------------------------------------------------------= ---- | Returns 1 if the half-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -240,7 +264,6 @@ bool float16_is_quiet_nan(float16 a_, float_status *sta= tus) if (snan_bit_is_one(status)) { return (((a >> 9) & 0x3F) =3D=3D 0x3E) && (a & 0x1FF); } else { - return ((a >> 9) & 0x3F) =3D=3D 0x3F; } } @@ -265,6 +288,38 @@ bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *= status) } } =20 +/*------------------------------------------------------------------------= ---- +| Returns 1 if the OCP(Open Compute Platform) FP8 value `a' is a signaling= NaN; +| otherwise returns 0. +*-------------------------------------------------------------------------= ---*/ + +bool float8_e4m3_is_signaling_nan(float8_e4m3 a_, float_status *status) +{ + if (no_signaling_nans(status)) { + return false; + } else { + if (snan_bit_is_one(status)) { + return float8_e4m3_is_any_nan(a_); + } else { + return false; + } + } +} + +bool float8_e5m2_is_signaling_nan(float8_e5m2 a_, float_status *status) +{ + if (no_signaling_nans(status)) { + return false; + } else { + uint8_t a =3D float8_e5m2_val(a_); + if (snan_bit_is_one(status)) { + return ((a >> 1) & 0x3F) =3D=3D 0x3F; + } else { + return (((a >> 1) & 0x3F) =3D=3D 0x3E && (a & 0x1)); + } + } +} + /*------------------------------------------------------------------------= ---- | Returns 1 if the half-precision floating-point value `a' is a signaling | NaN; otherwise returns 0. diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helper= s.h index 90862f5cd2..4e278a3ee3 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -136,6 +136,26 @@ static inline void set_no_signaling_nans(bool val, flo= at_status *status) status->no_signaling_nans =3D val; } =20 +static inline void set_ocp_fp8e5m2_no_signal_nan(bool val, float_status *s= tatus) +{ + status->ocp_fp8e5m2_no_signal_nan =3D val; +} + +static inline bool get_ocp_fp8e5m2_no_signal_nan(const float_status *statu= s) +{ + return status->ocp_fp8e5m2_no_signal_nan; +} + +static inline void set_ocp_fp8_same_canonical_nan(bool val, float_status *= status) +{ + status->ocp_fp8_same_canonical_nan =3D val; +} + +static inline bool get_ocp_fp8_same_canonical_nan(const float_status *stat= us) +{ + return status->ocp_fp8_same_canonical_nan; +} + static inline bool get_float_detect_tininess(const float_status *status) { return status->tininess_before_rounding; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 8f82fdfc97..835dd33bf1 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -119,6 +119,18 @@ typedef struct { */ typedef uint16_t bfloat16; =20 +/* + * Software OCP(Open Compute Project) 8-bit floating point types + */ +typedef uint8_t float8_e4m3; +typedef uint8_t float8_e5m2; +#define float8_e4m3_val(x) (x) +#define float8_e5m2_val(x) (x) +#define make_float8_e4m3(x) (x) +#define make_float8_e5m2(x) (x) +#define const_float8_e4m3(x) (x) +#define const_float8_e5m2(x) (x) + /* * Software IEC/IEEE floating-point underflow tininess-detection mode. */ @@ -410,6 +422,17 @@ typedef struct float_status { */ bool snan_bit_is_one; bool no_signaling_nans; + /* + * When true, OCP FP8 E5M2 format does not generate signaling NaNs. + * RISC-V uses only quiet NaNs in its OCP FP8 implementation. + */ + bool ocp_fp8e5m2_no_signal_nan; + /* + * When true, OCP FP8 formats use the same canonical NaN representation + * (0x7F) for all NaN outputs. RISC-V specifies a single canonical NaN + * for both E4M3 and E5M2. + */ + bool ocp_fp8_same_canonical_nan; /* should overflowed results subtract re_bias to its exponent? */ bool rebias_overflow; /* should underflowed results add re_bias to its exponent? */ diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index c18ab2cb60..6f7259f9dd 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -189,6 +189,76 @@ float128 int128_to_float128(Int128, float_status *stat= us); float128 uint64_to_float128(uint64_t, float_status *status); float128 uint128_to_float128(Int128, float_status *status); =20 +/*------------------------------------------------------------------------= ---- +| Software OCP FP8 operations. +*-------------------------------------------------------------------------= ---*/ + +bool float8_e4m3_is_quiet_nan(float8_e4m3, float_status *status); +bool float8_e4m3_is_signaling_nan(float8_e4m3, float_status *status); +bool float8_e5m2_is_quiet_nan(float8_e5m2, float_status *status); +bool float8_e5m2_is_signaling_nan(float8_e5m2, float_status *status); + +static inline bool float8_e4m3_is_any_nan(float8_e4m3 a) +{ + return ((float8_e4m3_val(a) & ~0x80) =3D=3D 0x7f); +} + +static inline bool float8_e5m2_is_any_nan(float8_e5m2 a) +{ + return ((float8_e5m2_val(a) & ~0x80) > 0x7c); +} + +static inline bool float8_e4m3_is_neg(float8_e4m3 a) +{ + return float8_e4m3_val(a) >> 7; +} + +static inline bool float8_e5m2_is_neg(float8_e5m2 a) +{ + return float8_e5m2_val(a) >> 7; +} + +static inline bool float8_e4m3_is_infinity(float8_e4m3 a) +{ + return false; +} + +static inline bool float8_e5m2_is_infinity(float8_e5m2 a) +{ + return (float8_e5m2_val(a) & 0x7f) =3D=3D 0x7c; +} + +static inline bool float8_e4m3_is_zero(float8_e4m3 a) +{ + return (float8_e4m3_val(a) & 0x7f) =3D=3D 0; +} + +static inline bool float8_e5m2_is_zero(float8_e5m2 a) +{ + return (float8_e5m2_val(a) & 0x7f) =3D=3D 0; +} + +static inline bool float8_e4m3_is_zero_or_denormal(float8_e4m3 a) +{ + return (float8_e4m3_val(a) & 0x78) =3D=3D 0; +} + +static inline bool float8_e5m2_is_zero_or_denormal(float8_e5m2 a) +{ + return (float8_e5m2_val(a) & 0x7c) =3D=3D 0; +} + +static inline bool float8_e4m3_is_normal(float8_e4m3 a) +{ + uint8_t em =3D float8_e4m3_val(a) & 0x7f; + return em >=3D 0x8 && em <=3D 0x7e; +} + +static inline bool float8_e5m2_is_normal(float8_e5m2 a) +{ + return (((float8_e5m2_val(a) >> 2) + 1) & 0x1f) >=3D 2; +} + /*------------------------------------------------------------------------= ---- | Software half-precision conversion routines. *-------------------------------------------------------------------------= ---*/ --=20 2.43.7 From nobody Mon Feb 9 03:17:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1767885583; cv=none; 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Signed-off-by: Max Chou --- fpu/softfloat-parts.c.inc | 77 +++++++++++- fpu/softfloat.c | 241 ++++++++++++++++++++++++++++++++++++++ include/fpu/softfloat.h | 11 ++ 3 files changed, 323 insertions(+), 6 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 5e0438fc0b..d9ec3ca8ae 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -227,7 +227,8 @@ static void partsN(canonicalize)(FloatPartsN *p, float_= status *status, p->exp =3D fmt->frac_shift - fmt->exp_bias - shift + !has_pseudo_denormals; } - } else if (likely(p->exp < fmt->exp_max) || fmt->arm_althp) { + } else if (likely(p->exp < fmt->exp_max) || fmt->arm_althp || + ocpfp_is_normal(p, fmt, false)) { p->cls =3D float_class_normal; p->exp -=3D fmt->exp_bias; frac_shl(p, fmt->frac_shift); @@ -236,8 +237,12 @@ static void partsN(canonicalize)(FloatPartsN *p, float= _status *status, p->cls =3D float_class_inf; } else { frac_shl(p, fmt->frac_shift); - p->cls =3D (parts_is_snan_frac(p->frac_hi, status) - ? float_class_snan : float_class_qnan); + if (parts_is_snan_frac(p->frac_hi, status) =3D=3D false || + (fmt->ocpfp && status->ocp_fp8e5m2_no_signal_nan)) { + p->cls =3D float_class_qnan; + } else { + p->cls =3D float_class_snan; + } } } =20 @@ -313,8 +318,40 @@ static void partsN(uncanon_normal)(FloatPartsN *p, flo= at_status *s, } p->frac_lo &=3D ~round_mask; } + p->exp =3D exp; =20 - if (fmt->arm_althp) { + if (fmt->ocpfp) { + if (ocpfp_is_normal(p, fmt, true) =3D=3D false) { + flags |=3D float_flag_overflow; + flags |=3D float_flag_inexact; + if (fmt->exp_size =3D=3D 4) { + if (fmt->ocpfp_sat || overflow_norm) { + /* S.1111.110 */ + exp =3D exp_max; + frac_clear(p); + frac_addi(p, p, 0b110); + frac_shl(p, frac_shift); + } else { + /* S.1111.111 NaN */ + p->cls =3D float_class_qnan; + p->sign =3D (s->ocp_fp8_same_canonical_nan ? 0 : p= ->sign); + exp =3D exp_max; + frac_allones(p); + } + } else if (fmt->exp_size =3D=3D 5) { + if (fmt->ocpfp_sat || overflow_norm) { + /* S.11110.11 */ + exp =3D exp_max - 1; + frac_allones(p); + } else { + /* S.11111.00 Inf */ + p->cls =3D float_class_inf; + exp =3D exp_max; + frac_clear(p); + } + } + } + } else if (fmt->arm_althp) { /* ARM Alt HP eschews Inf and NaN for a wider exponent. */ if (unlikely(exp > exp_max)) { /* Overflow. Return the maximum normal. */ @@ -435,8 +472,36 @@ static void partsN(uncanon)(FloatPartsN *p, float_stat= us *s, return; case float_class_inf: g_assert(!fmt->arm_althp); - p->exp =3D fmt->exp_max; - frac_clear(p); + if (fmt->ocpfp) { + if (fmt->ocpfp_sat) { + if (fmt->exp_size =3D=3D 4) { + /* S.1111.110 */ + p->exp =3D fmt->exp_max; + frac_clear(p); + frac_addi(p, p, 0x6); + } else { + /* S.11110.11 */ + p->exp =3D fmt->exp_max - 1; + frac_allones(p); + } + } else { + if (fmt->exp_size =3D=3D 4) { + /* S.1111.111 NaN */ + p->cls =3D float_class_qnan; + p->sign =3D (s->ocp_fp8_same_canonical_nan ? 0 : p= ->sign); + p->exp =3D fmt->exp_max; + frac_allones(p); + } else { + /* S.11111.00 Inf */ + p->cls =3D float_class_inf; + p->exp =3D fmt->exp_max; + frac_clear(p); + } + } + } else { + p->exp =3D fmt->exp_max; + frac_clear(p); + } return; case float_class_qnan: case float_class_snan: diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 8094358c2e..0c7f052ec0 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -544,6 +544,8 @@ typedef struct { int frac_shift; bool arm_althp; bool has_explicit_bit; + bool ocpfp; + bool ocpfp_sat; uint64_t round_mask; } FloatFmt; =20 @@ -560,6 +562,28 @@ typedef struct { .frac_shift =3D (-F - 1) & 63, \ .round_mask =3D (1ull << ((-F - 1) & 63)) - 1 =20 +static const FloatFmt float8_e4m3_params =3D { + FLOAT_PARAMS(4, 3), + .ocpfp =3D true +}; + +static const FloatFmt float8_e4m3_params_sat =3D { + FLOAT_PARAMS(4, 3), + .ocpfp =3D true, + .ocpfp_sat =3D true +}; + +static const FloatFmt float8_e5m2_params =3D { + FLOAT_PARAMS(5, 2), + .ocpfp =3D true +}; + +static const FloatFmt float8_e5m2_params_sat =3D { + FLOAT_PARAMS(5, 2), + .ocpfp =3D true, + .ocpfp_sat =3D true +}; + static const FloatFmt float16_params =3D { FLOAT_PARAMS(5, 10) }; @@ -614,6 +638,16 @@ static void unpack_raw64(FloatParts64 *r, const FloatF= mt *fmt, uint64_t raw) }; } =20 +static void QEMU_FLATTEN float8_e4m3_unpack_raw(FloatParts64 *p, float8_e4= m3 f) +{ + unpack_raw64(p, &float8_e4m3_params, f); +} + +static void QEMU_FLATTEN float8_e5m2_unpack_raw(FloatParts64 *p, float8_e5= m2 f) +{ + unpack_raw64(p, &float8_e5m2_params, f); +} + static void QEMU_FLATTEN float16_unpack_raw(FloatParts64 *p, float16 f) { unpack_raw64(p, &float16_params, f); @@ -671,6 +705,16 @@ static uint64_t pack_raw64(const FloatParts64 *p, cons= t FloatFmt *fmt) return ret; } =20 +static float8_e4m3 QEMU_FLATTEN float8_e4m3_pack_raw(const FloatParts64 *p) +{ + return make_float8_e4m3(pack_raw64(p, &float8_e4m3_params)); +} + +static float8_e5m2 QEMU_FLATTEN float8_e5m2_pack_raw(const FloatParts64 *p) +{ + return make_float8_e5m2(pack_raw64(p, &float8_e5m2_params)); +} + static float16 QEMU_FLATTEN float16_pack_raw(const FloatParts64 *p) { return make_float16(pack_raw64(p, &float16_params)); @@ -1604,6 +1648,91 @@ static void frac128_widen(FloatParts256 *r, FloatPar= ts128 *a) =20 #define frac_widen(A, B) FRAC_GENERIC_64_128(widen, B)(A, B) =20 +#define OCPFP_GENERIC_64_128(NAME, P) \ + _Generic((P), FloatParts64 *: ocpfp64_##NAME, \ + FloatParts128 *: ocpfp128_##NAME) + +static bool ocpfp64_is_normal(const FloatParts64 *a, const FloatFmt *fmt, + bool is_normalized) +{ + FloatParts64 input; + input.exp =3D a->exp; + input.frac =3D a->frac; + if (!is_normalized) { + frac64_shl(&input, fmt->frac_shift); + input.frac_hi |=3D DECOMPOSED_IMPLICIT_BIT; + } + + if (fmt->ocpfp) { + if (fmt->exp_size =3D=3D 4 && fmt->frac_size =3D=3D 3) { + /* + * The OCP E4M3 format uses only two bit patterns for NaN (a + * single mantissa-exponent bit pattern with the sign bit) in + * order to increase emax to 8 and thus to increase the dynamic + * range by one binade. + */ + FloatParts64 tmp; + frac64_clear(&tmp); + tmp.frac_lo =3D 0b110; + frac64_shl(&tmp, fmt->frac_shift); + tmp.frac_hi |=3D DECOMPOSED_IMPLICIT_BIT; + if (!(input.exp > fmt->exp_max || + (input.exp =3D=3D fmt->exp_max && + frac64_cmp(&input, &tmp) =3D=3D float_relation_greater)= )) { + return true; + } + } else if (fmt->exp_size =3D=3D 5 && fmt->frac_size =3D=3D 2) { + if (input.exp < fmt->exp_max) { + return true; + } + } + } + + return false; +} + +static bool ocpfp128_is_normal(const FloatParts128 *a, const FloatFmt *fmt, + bool is_normalized) +{ + FloatParts128 input; + input.exp =3D a->exp; + input.frac_hi =3D a->frac_hi; + input.frac_lo =3D a->frac_lo; + if (!is_normalized) { + frac128_shl(&input, fmt->frac_shift); + input.frac_hi |=3D DECOMPOSED_IMPLICIT_BIT; + } + + if (fmt->ocpfp) { + if (fmt->exp_size =3D=3D 4 && fmt->frac_size =3D=3D 3) { + /* + * The OCP E4M3 format uses only two bit patterns for NaN (a + * single mantissa-exponent bit pattern with the sign bit) in + * order to increase emax to 8 and thus to increase the dynamic + * range by one binade. + */ + FloatParts128 tmp; + frac128_clear(&tmp); + tmp.frac_lo =3D 0b110; + frac128_shl(&tmp, fmt->frac_shift); + tmp.frac_hi |=3D DECOMPOSED_IMPLICIT_BIT; + if (!(input.exp > fmt->exp_max || + (input.exp =3D=3D fmt->exp_max && + frac128_cmp(&input, &tmp) =3D=3D float_relation_greater= ))) { + return true; + } + } else if (fmt->exp_size =3D=3D 5 && fmt->frac_size =3D=3D 2) { + if (input.exp < fmt->exp_max) { + return true; + } + } + } + + return false; +} + +#define ocpfp_is_normal(A, F, N) OCPFP_GENERIC_64_128(is_normal, A)(A, F,= N) + /* * Reciprocal sqrt table. 1 bit of exponent, 6-bits of mantessa. * From https://git.musl-libc.org/cgit/musl/tree/src/math/sqrt_data.c @@ -1662,6 +1791,20 @@ static const uint16_t rsqrt_tab[128] =3D { * Pack/unpack routines with a specific FloatFmt. */ =20 +static void float8_e4m3_unpack_canonical(FloatParts64 *p, float8_e4m3 f, + float_status *s) +{ + float8_e4m3_unpack_raw(p, f); + parts_canonicalize(p, s, &float8_e4m3_params); +} + +static void float8_e5m2_unpack_canonical(FloatParts64 *p, float8_e5m2 f, + float_status *s) +{ + float8_e5m2_unpack_raw(p, f); + parts_canonicalize(p, s, &float8_e5m2_params); +} + static void float16a_unpack_canonical(FloatParts64 *p, float16 f, float_status *s, const FloatFmt *par= ams) { @@ -1682,6 +1825,22 @@ static void bfloat16_unpack_canonical(FloatParts64 *= p, bfloat16 f, parts_canonicalize(p, s, &bfloat16_params); } =20 +static float8_e4m3 float8_e4m3_round_pack_canonical(FloatParts64 *p, + float_status *status, + const FloatFmt *params) +{ + parts_uncanon(p, status, params); + return float8_e4m3_pack_raw(p); +} + +static float8_e5m2 float8_e5m2_round_pack_canonical(FloatParts64 *p, + float_status *status, + const FloatFmt *params) +{ + parts_uncanon(p, status, params); + return float8_e5m2_pack_raw(p); +} + static float16 float16a_round_pack_canonical(FloatParts64 *p, float_status *s, const FloatFmt *params) @@ -2759,6 +2918,23 @@ static void parts_float_to_ahp(FloatParts64 *a, floa= t_status *s) } } =20 +static void parts_float_to_ofp8(FloatParts64 *a, float_status *s, + const FloatFmt *fmt) +{ + if (is_nan(a->cls)) { + if (s->ocp_fp8_same_canonical_nan) { + if (a->cls =3D=3D float_class_snan) { + float_raise(float_flag_invalid | float_flag_invalid_snan, = s); + } + a->sign =3D 0; + a->exp =3D fmt->exp_max; + frac_allones(a); + } else { + parts_return_nan(a, s); + } + } +} + static void parts64_float_to_float(FloatParts64 *a, float_status *s) { if (is_nan(a->cls)) { @@ -2823,6 +2999,71 @@ static void parts_float_to_float_widen(FloatParts128= *a, FloatParts64 *b, } } =20 + +bfloat16 float8_e4m3_to_bfloat16(float8_e4m3 a, float_status *s) +{ + FloatParts64 p; + + float8_e4m3_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + + return bfloat16_round_pack_canonical(&p, s); +} + +bfloat16 float8_e5m2_to_bfloat16(float8_e5m2 a, float_status *s) +{ + FloatParts64 p; + + float8_e5m2_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + + return bfloat16_round_pack_canonical(&p, s); +} + +float8_e4m3 bfloat16_to_float8_e4m3(bfloat16 a, bool saturate, float_statu= s *s) +{ + const FloatFmt *fmt =3D saturate ? &float8_e4m3_params_sat + : &float8_e4m3_params; + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + parts_float_to_ofp8(&p, s, fmt); + return float8_e4m3_round_pack_canonical(&p, s, fmt); +} + +float8_e5m2 bfloat16_to_float8_e5m2(bfloat16 a, bool saturate, float_statu= s *s) +{ + const FloatFmt *fmt =3D saturate ? &float8_e5m2_params_sat + : &float8_e5m2_params; + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + parts_float_to_ofp8(&p, s, fmt); + return float8_e5m2_round_pack_canonical(&p, s, fmt); +} + +float8_e4m3 float32_to_float8_e4m3(float32 a, bool saturate, float_status = *s) +{ + const FloatFmt *fmt =3D saturate ? &float8_e4m3_params_sat + : &float8_e4m3_params; + FloatParts64 p; + + float32_unpack_canonical(&p, a, s); + parts_float_to_ofp8(&p, s, fmt); + return float8_e4m3_round_pack_canonical(&p, s, fmt); +} + +float8_e5m2 float32_to_float8_e5m2(float32 a, bool saturate, float_status = *s) +{ + const FloatFmt *fmt =3D saturate ? &float8_e5m2_params_sat + : &float8_e5m2_params; + FloatParts64 p; + + float32_unpack_canonical(&p, a, s); + parts_float_to_ofp8(&p, s, fmt); + return float8_e5m2_round_pack_canonical(&p, s, fmt); +} + float32 float16_to_float32(float16 a, bool ieee, float_status *s) { const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 6f7259f9dd..7ab585bfc8 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -189,6 +189,17 @@ float128 int128_to_float128(Int128, float_status *stat= us); float128 uint64_to_float128(uint64_t, float_status *status); float128 uint128_to_float128(Int128, float_status *status); =20 +/*------------------------------------------------------------------------= ---- +| Software OCP FP8 conversion routines. +*-------------------------------------------------------------------------= ---*/ + +bfloat16 float8_e4m3_to_bfloat16(float8_e4m3, float_status *status); +bfloat16 float8_e5m2_to_bfloat16(float8_e5m2, float_status *status); +float8_e4m3 bfloat16_to_float8_e4m3(bfloat16, bool saturate, float_status = *status); +float8_e5m2 bfloat16_to_float8_e5m2(bfloat16, bool saturate, float_status = *status); +float8_e4m3 float32_to_float8_e4m3(float32, bool saturate, float_status *s= tatus); +float8_e5m2 float32_to_float8_e5m2(float32, bool saturate, float_status *s= tatus); + /*------------------------------------------------------------------------= ---- | Software OCP FP8 operations. *-------------------------------------------------------------------------= ---*/ --=20 2.43.7 From nobody Mon Feb 9 03:17:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1767885617; cv=none; d=zohomail.com; s=zohoarc; b=QVEkgBqETe3aWGOjX6Ekwr0NYf1x/SwQhY2+0Oe/1gA0w8QCSUs7FCjVohFJIahMwzJmnjHL/hNUtqlVXeXXhtyoQkfKoRrucuTJZKLXOhBVRc4aF0NMoKATBYgS4Y6Gw23AOL0aACCxZculQVV5Cf9Wt9jJNYYA1uLog+nRACg= ARC-Message-Signature: i=1; a=rsa-sha256; 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Signed-off-by: Max Chou --- include/fpu/softfloat-types.h | 7 +++++- include/fpu/softfloat.h | 45 +++++++++++++++++++++++++++++++++-- 2 files changed, 49 insertions(+), 3 deletions(-) diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 835dd33bf1..82a54e9e6d 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -120,7 +120,7 @@ typedef struct { typedef uint16_t bfloat16; =20 /* - * Software OCP(Open Compute Project) 8-bit floating point types + * Software OCP(Open Compute Project) floating point types */ typedef uint8_t float8_e4m3; typedef uint8_t float8_e5m2; @@ -131,6 +131,11 @@ typedef uint8_t float8_e5m2; #define const_float8_e4m3(x) (x) #define const_float8_e5m2(x) (x) =20 +typedef uint8_t float4_e2m1; +#define float4_e2m1_val(x) (x & 0xf) +#define make_float4_e2m1(x) (x & 0xf) +#define const_float4_e2m1(x) (x & 0xf) + /* * Software IEC/IEEE floating-point underflow tininess-detection mode. */ diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 7ab585bfc8..13b882bc67 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -190,7 +190,7 @@ float128 uint64_to_float128(uint64_t, float_status *sta= tus); float128 uint128_to_float128(Int128, float_status *status); =20 /*------------------------------------------------------------------------= ---- -| Software OCP FP8 conversion routines. +| Software OCP FP conversion routines. *-------------------------------------------------------------------------= ---*/ =20 bfloat16 float8_e4m3_to_bfloat16(float8_e4m3, float_status *status); @@ -201,7 +201,7 @@ float8_e4m3 float32_to_float8_e4m3(float32, bool satura= te, float_status *status) float8_e5m2 float32_to_float8_e5m2(float32, bool saturate, float_status *s= tatus); =20 /*------------------------------------------------------------------------= ---- -| Software OCP FP8 operations. +| Software OCP FP operations. *-------------------------------------------------------------------------= ---*/ =20 bool float8_e4m3_is_quiet_nan(float8_e4m3, float_status *status); @@ -270,6 +270,47 @@ static inline bool float8_e5m2_is_normal(float8_e5m2 a) return (((float8_e5m2_val(a) >> 2) + 1) & 0x1f) >=3D 2; } =20 +static inline bool float4_e2m1_is_quiet_nan(float4_e2m1 a, float_status *s= tatus) +{ + return false; +} + +static inline bool float4_e2m1_is_signaling_nan(float4_e2m1 a, float_statu= s *status) +{ + return false; +} + +static inline bool float4_e2m1_is_any_nan(float4_e2m1 a) +{ + return false; +} + +static inline bool float4_e2m1_is_neg(float4_e2m1 a) +{ + return float4_e2m1_val(a) >> 3; +} + +static inline bool float4_e2m1_is_infinity(float4_e2m1 a) +{ + return false; +} + +static inline bool float4_e2m1_is_zero(float4_e2m1 a) +{ + return (float4_e2m1_val(a) & 0x7) =3D=3D 0; +} + +static inline bool float4_e2m1_is_zero_or_denormal(float4_e2m1 a) +{ + return (float4_e2m1_val(a) & 0x6) =3D=3D 0; +} + +static inline bool float4_e2m1_is_normal(float4_e2m1 a) +{ + uint8_t em =3D float4_e2m1_val(a) & 0x7; + return em >=3D 0x2 && em <=3D 0x7; +} + /*------------------------------------------------------------------------= ---- | Software half-precision conversion routines. *-------------------------------------------------------------------------= ---*/ --=20 2.43.7 From nobody Mon Feb 9 03:17:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Max Chou --- fpu/softfloat.c | 37 +++++++++++++++++++++++++++++++++++-- include/fpu/softfloat.h | 2 ++ 2 files changed, 37 insertions(+), 2 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 0c7f052ec0..30ba6d6c09 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -562,6 +562,11 @@ typedef struct { .frac_shift =3D (-F - 1) & 63, \ .round_mask =3D (1ull << ((-F - 1) & 63)) - 1 =20 +static const FloatFmt float4_e2m1_params =3D { + FLOAT_PARAMS(2, 1), + .ocpfp =3D true +}; + static const FloatFmt float8_e4m3_params =3D { FLOAT_PARAMS(4, 3), .ocpfp =3D true @@ -638,6 +643,11 @@ static void unpack_raw64(FloatParts64 *r, const FloatF= mt *fmt, uint64_t raw) }; } =20 +static void QEMU_FLATTEN float4_e2m1_unpack_raw(FloatParts64 *p, float4_e2= m1 f) +{ + unpack_raw64(p, &float4_e2m1_params, f); +} + static void QEMU_FLATTEN float8_e4m3_unpack_raw(FloatParts64 *p, float8_e4= m3 f) { unpack_raw64(p, &float8_e4m3_params, f); @@ -1664,7 +1674,11 @@ static bool ocpfp64_is_normal(const FloatParts64 *a,= const FloatFmt *fmt, } =20 if (fmt->ocpfp) { - if (fmt->exp_size =3D=3D 4 && fmt->frac_size =3D=3D 3) { + if (fmt->exp_size =3D=3D 2 && fmt->frac_size =3D=3D 1) { + if (input.exp <=3D fmt->exp_max) { + return true; + } + } else if (fmt->exp_size =3D=3D 4 && fmt->frac_size =3D=3D 3) { /* * The OCP E4M3 format uses only two bit patterns for NaN (a * single mantissa-exponent bit pattern with the sign bit) in @@ -1704,7 +1718,11 @@ static bool ocpfp128_is_normal(const FloatParts128 *= a, const FloatFmt *fmt, } =20 if (fmt->ocpfp) { - if (fmt->exp_size =3D=3D 4 && fmt->frac_size =3D=3D 3) { + if (fmt->exp_size =3D=3D 2 && fmt->frac_size =3D=3D 1) { + if (input.exp <=3D fmt->exp_max) { + return true; + } + } else if (fmt->exp_size =3D=3D 4 && fmt->frac_size =3D=3D 3) { /* * The OCP E4M3 format uses only two bit patterns for NaN (a * single mantissa-exponent bit pattern with the sign bit) in @@ -1791,6 +1809,13 @@ static const uint16_t rsqrt_tab[128] =3D { * Pack/unpack routines with a specific FloatFmt. */ =20 +static void float4_e2m1_unpack_canonical(FloatParts64 *p, float4_e2m1 f, + float_status *s) +{ + float4_e2m1_unpack_raw(p, f); + parts_canonicalize(p, s, &float4_e2m1_params); +} + static void float8_e4m3_unpack_canonical(FloatParts64 *p, float8_e4m3 f, float_status *s) { @@ -2999,6 +3024,14 @@ static void parts_float_to_float_widen(FloatParts128= *a, FloatParts64 *b, } } =20 +float8_e4m3 float4_e2m1_to_float8_e4m3(float4_e2m1 a, float_status *s) +{ + FloatParts64 p; + + float4_e2m1_unpack_canonical(&p, a, s); + parts_float_to_ofp8(&p, s, &float8_e4m3_params); + return float8_e4m3_round_pack_canonical(&p, s, &float8_e4m3_params); +} =20 bfloat16 float8_e4m3_to_bfloat16(float8_e4m3 a, float_status *s) { diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 13b882bc67..b199a029b0 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -200,6 +200,8 @@ float8_e5m2 bfloat16_to_float8_e5m2(bfloat16, bool satu= rate, float_status *statu float8_e4m3 float32_to_float8_e4m3(float32, bool saturate, float_status *s= tatus); float8_e5m2 float32_to_float8_e5m2(float32, bool saturate, float_status *s= tatus); =20 +float8_e4m3 float4_e2m1_to_float8_e4m3(float4_e2m1, float_status *status); + /*------------------------------------------------------------------------= ---- | Software OCP FP operations. *-------------------------------------------------------------------------= ---*/ --=20 2.43.7 From nobody Mon Feb 9 03:17:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Max Chou --- target/riscv/cpu.c | 8 ++++++++ target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/tcg/tcg-cpu.c | 5 +++++ target/riscv/vector_helper.c | 3 ++- 4 files changed, 16 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8eab992154..b4b10b52d8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -193,6 +193,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), + ISA_EXT_DATA_ENTRY(zvfofp8min, PRIV_VERSION_1_12_0, ext_zvfofp8min), ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb), ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), ISA_EXT_DATA_ENTRY(zvkn, PRIV_VERSION_1_12_0, ext_zvkn), @@ -778,6 +779,13 @@ static void riscv_cpu_reset_hold(Object *obj, ResetTyp= e type) set_default_nan_mode(1, &env->fp_status); /* Default NaN value: sign bit clear, frac msb set */ set_float_default_nan_pattern(0b01000000, &env->fp_status); + /* + * RISC-V Zvfofp8min extension requires: + * - Same canonical NaN (0x7F) for both E4M3 and E5M2 formats + * - E5M2 format does not generate signaling NaNs (all NaNs are quiet) + */ + set_ocp_fp8_same_canonical_nan(true, &env->fp_status); + set_ocp_fp8e5m2_no_signal_nan(true, &env->fp_status); env->vill =3D true; =20 #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index 3696f02ee0..59302894af 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -104,6 +104,7 @@ BOOL_FIELD(ext_zvfbfmin) BOOL_FIELD(ext_zvfbfwma) BOOL_FIELD(ext_zvfh) BOOL_FIELD(ext_zvfhmin) +BOOL_FIELD(ext_zvfofp8min) BOOL_FIELD(ext_smaia) BOOL_FIELD(ext_ssaia) BOOL_FIELD(ext_smctr) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 378b298886..ba89436f13 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -710,6 +710,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) return; } =20 + if (cpu->cfg.ext_zvfofp8min && !cpu->cfg.ext_zve32f) { + error_setg(errp, "Zvfofp8min extension depends on Zve32f extension= "); + return; + } + if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { error_setg(errp, "Zvfh extensions requires Zfhmin extension"); return; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index ec0ea4c143..ee5a1e595b 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -38,7 +38,8 @@ static target_ulong vtype_reserved(CPURISCVState *env, ta= rget_ulong vtype) int xlen =3D riscv_cpu_xlen(env); target_ulong reserved =3D 0; =20 - if (riscv_cpu_cfg(env)->ext_zvfbfa) { + if (riscv_cpu_cfg(env)->ext_zvfbfa || + riscv_cpu_cfg(env)->ext_zvfofp8min) { reserved =3D vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, xlen - 1 - R_VTYPE_RESERVED_SHI= FT); } else { --=20 2.43.7 From nobody Mon Feb 9 03:17:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Signed-off-by: Max Chou --- target/riscv/cpu.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b4b10b52d8..53b5aeb9b2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2513,6 +2513,15 @@ static RISCVCPUImpliedExtsRule ZVFHMIN_IMPLIED =3D { }, }; =20 +static RISCVCPUImpliedExtsRule ZVFOFP8MIN_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvfofp8min), + .implied_multi_exts =3D { + CPU_CFG_OFFSET(ext_zve32f), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + static RISCVCPUImpliedExtsRule ZVKN_IMPLIED =3D { .ext =3D CPU_CFG_OFFSET(ext_zvkn), .implied_multi_exts =3D { @@ -2650,7 +2659,8 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rule= s[] =3D { &ZKS_IMPLIED, &ZVBB_IMPLIED, &ZVE32F_IMPLIED, &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED, &ZVE64X_IMPLIED, &ZVFBFA_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED, - &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED, + &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVFOFP8MIN_IMPLIED, + &ZVKN_IMPLIED, &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED, &SUPM_IMPLIED, &SSPM_IMPLIED, &SMCTR_IMPLIED, &SSCTR_IMPLIED, --=20 2.43.7 From nobody Mon Feb 9 03:17:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1767885562; cv=none; d=zohomail.com; s=zohoarc; b=V+0hiC4fxVa0AcFNfCdm7vxx0/J4C4TwPScuZ0lJsAdI7rya5Dxf5B1lNUd3kVJ1Cv3N++bDsQNYbm8SzzPpcKdjjvGZiMl5Cal1AvY0OBo8wH92UfBn4EMu7qu/DuChvREDm8ug+gk6rGL4bjeZwZokOBNPKuGePKn7xF4JB1U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767885562; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=LU5IHKX/mvJC/jNBpl926F0veAMaprINCGZ2jgZDcOo=; b=g4p8EMBSZIeWeC8X745yWdNrdtJ9Lia1+pfMEeNrFqHUDXTqQFUjpDemKzS7f9ze7Mjtu6i0jf3FqX487urjtvwQtd56hQ4drt0VGrldYn1pj3cW+WuAXeGOUSf5niZPJxMh8cfs2XQjktgngKqZ91ad2wdXmiMuzy27HzS8OJU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767885562336254.09325875453203; Thu, 8 Jan 2026 07:19:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vdrlO-0000y5-R4; Thu, 08 Jan 2026 10:17:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vdrlN-0000wv-2v for qemu-devel@nongnu.org; Thu, 08 Jan 2026 10:17:25 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vdrlL-0003Uf-CC for qemu-devel@nongnu.org; Thu, 08 Jan 2026 10:17:24 -0500 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-81c5ff546f6so535127b3a.1 for ; Thu, 08 Jan 2026 07:17:23 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. 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And the VTYPE.altfmt field is used to select the OFP8 format. * altfmt =3D 0: OFP8.e4m3 to BF16 * altfmt =3D 1: OFP8.e5m2 to BF16 Signed-off-by: Max Chou --- target/riscv/helper.h | 12 +++ target/riscv/insn_trans/trans_rvbf16.c.inc | 16 +++- target/riscv/vector_helper.c | 93 ++++++++++++++++++++++ 3 files changed, 117 insertions(+), 4 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index eb0a488ba8..356c24d9fb 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1247,6 +1247,18 @@ DEF_HELPER_5(vfwcvtbf16_f_f_v, void, ptr, ptr, ptr, = env, i32) DEF_HELPER_6(vfwmaccbf16_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwmaccbf16_vf, void, ptr, ptr, i64, ptr, env, i32) =20 +/* OFP8 functions */ +DEF_HELPER_5(vfwcvtbf16_f_f_v_ofp8e4m3, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvtbf16_f_f_v_ofp8e5m2, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvtbf16_f_f_w_ofp8e4m3, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvtbf16_f_f_w_ofp8e5m2, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvtbf16_sat_f_f_w_ofp8e4m3, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvtbf16_sat_f_f_w_ofp8e5m2, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_f_q_ofp8e4m3, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_f_q_ofp8e5m2, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_sat_f_f_q_ofp8e4m3, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_sat_f_f_q_ofp8e5m2, void, ptr, ptr, ptr, env, i32) + /* Vector crypto functions */ DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn= _trans/trans_rvbf16.c.inc index 6cfda03d2e..9aafd4d2ef 100644 --- a/target/riscv/insn_trans/trans_rvbf16.c.inc +++ b/target/riscv/insn_trans/trans_rvbf16.c.inc @@ -92,11 +92,20 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, a= rg_vfncvtbf16_f_f_w *a) static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v= *a) { REQUIRE_FPU; - REQUIRE_ZVFBFMIN(ctx); =20 - if (opfv_widen_check(ctx, a) && (ctx->sew =3D=3D MO_16)) { + if (opfv_widen_check(ctx, a) && + ((ctx->sew =3D=3D MO_16 && ctx->cfg_ptr->ext_zvfbfmin) || + (ctx->sew =3D=3D MO_8 && ctx->cfg_ptr->ext_zvfofp8min))) { + gen_helper_gvec_3_ptr *fn; uint32_t data =3D 0; =20 + if (ctx->sew =3D=3D MO_16) { + fn =3D gen_helper_vfwcvtbf16_f_f_v; + } else { + fn =3D ctx->altfmt ? gen_helper_vfwcvtbf16_f_f_v_ofp8e5m2 : + gen_helper_vfwcvtbf16_f_f_v_ofp8e4m3; + } + gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -106,8 +115,7 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, a= rg_vfwcvtbf16_f_f_v *a) tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), vreg_ofs(ctx, a->rs2), tcg_env, ctx->cfg_ptr->vlenb, - ctx->cfg_ptr->vlenb, data, - gen_helper_vfwcvtbf16_f_f_v); + ctx->cfg_ptr->vlenb, data, fn); finalize_rvv_inst(ctx); return true; } diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index ee5a1e595b..759ebb3251 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -5024,6 +5024,99 @@ GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4) RVVCALL(OPFVV1, vfncvtbf16_f_f_w, NOP_UU_H, H2, H4, float32_to_bfloat16) GEN_VEXT_V_ENV(vfncvtbf16_f_f_w, 2) =20 +/* + * Vector OFP8 conversion operations for Zvfofp8min + * + * Note: The OCP FP8 conversion functions use flags in float_status to con= trol + * the same_canonical_nan and only_quiet_nan behavior. RISC-V should set + * ocp_fp8_same_canonical_nan and ocp_fp8e5m2_no_signal_nan flags during C= PU + * initialization to get the correct Zvfofp8min behavior. + */ + +/* Wrapper functions for RVVCALL macro compatibility */ +static uint8_t vfncvt_bf16_to_e4m3(uint16_t a, float_status *s) +{ + return bfloat16_to_float8_e4m3(a, false, s); +} + +static uint8_t vfncvt_bf16_to_e5m2(uint16_t a, float_status *s) +{ + return bfloat16_to_float8_e5m2(a, false, s); +} + +static uint8_t vfncvt_bf16_to_e4m3_sat(uint16_t a, float_status *s) +{ + return bfloat16_to_float8_e4m3(a, true, s); +} + +static uint8_t vfncvt_bf16_to_e5m2_sat(uint16_t a, float_status *s) +{ + return bfloat16_to_float8_e5m2(a, true, s); +} + +static uint8_t vfncvt_f32_to_e4m3(uint32_t a, float_status *s) +{ + return float32_to_float8_e4m3(a, false, s); +} + +static uint8_t vfncvt_f32_to_e5m2(uint32_t a, float_status *s) +{ + return float32_to_float8_e5m2(a, false, s); +} + +static uint8_t vfncvt_f32_to_e4m3_sat(uint32_t a, float_status *s) +{ + return float32_to_float8_e4m3(a, true, s); +} + +static uint8_t vfncvt_f32_to_e5m2_sat(uint32_t a, float_status *s) +{ + return float32_to_float8_e5m2(a, true, s); +} + +/* vfwcvtbf16.f.f.w vd, vs2, vm # Convert OFP8 to BF16. */ +RVVCALL(OPFVV1, vfwcvtbf16_f_f_v_ofp8e4m3, WOP_UU_B, H2, H1, + float8_e4m3_to_bfloat16) +RVVCALL(OPFVV1, vfwcvtbf16_f_f_v_ofp8e5m2, WOP_UU_B, H2, H1, + float8_e5m2_to_bfloat16) +GEN_VEXT_V_ENV(vfwcvtbf16_f_f_v_ofp8e4m3, 2) +GEN_VEXT_V_ENV(vfwcvtbf16_f_f_v_ofp8e5m2, 2) + +/* vfncvtbf16.f.f.w vd, vs2, vm # Convert BF16 to OFP8 without saturation.= */ +RVVCALL(OPFVV1, vfncvtbf16_f_f_w_ofp8e4m3, NOP_UU_B, H1, H2, + vfncvt_bf16_to_e4m3) +RVVCALL(OPFVV1, vfncvtbf16_f_f_w_ofp8e5m2, NOP_UU_B, H1, H2, + vfncvt_bf16_to_e5m2) +GEN_VEXT_V_ENV(vfncvtbf16_f_f_w_ofp8e4m3, 1) +GEN_VEXT_V_ENV(vfncvtbf16_f_f_w_ofp8e5m2, 1) + +/* vfncvtbf16.sat.f.f.w vd, vs2, vm # Convert BF16 to OFP8 with saturation= . */ +RVVCALL(OPFVV1, vfncvtbf16_sat_f_f_w_ofp8e4m3, NOP_UU_B, H1, H2, + vfncvt_bf16_to_e4m3_sat) +RVVCALL(OPFVV1, vfncvtbf16_sat_f_f_w_ofp8e5m2, NOP_UU_B, H1, H2, + vfncvt_bf16_to_e5m2_sat) +GEN_VEXT_V_ENV(vfncvtbf16_sat_f_f_w_ofp8e4m3, 1) +GEN_VEXT_V_ENV(vfncvtbf16_sat_f_f_w_ofp8e5m2, 1) + +/* Quad-width narrowing type for FP32 to OFP8 */ +#define QOP_UU_B uint8_t, uint32_t, uint32_t + +/* vfncvt.f.f.q vd, vs2, vm # Convert FP32 to OFP8. */ +RVVCALL(OPFVV1, vfncvt_f_f_q_ofp8e4m3, QOP_UU_B, H1, H4, + vfncvt_f32_to_e4m3) +RVVCALL(OPFVV1, vfncvt_f_f_q_ofp8e5m2, QOP_UU_B, H1, H4, + vfncvt_f32_to_e5m2) +GEN_VEXT_V_ENV(vfncvt_f_f_q_ofp8e4m3, 1) +GEN_VEXT_V_ENV(vfncvt_f_f_q_ofp8e5m2, 1) + +/* vfncvt.sat.f.f.q vd, vs2, vm # Convert FP32 to OFP8 with saturation. */ +RVVCALL(OPFVV1, vfncvt_sat_f_f_q_ofp8e4m3, QOP_UU_B, H1, H4, + vfncvt_f32_to_e4m3_sat) +RVVCALL(OPFVV1, vfncvt_sat_f_f_q_ofp8e5m2, QOP_UU_B, H1, H4, + vfncvt_f32_to_e5m2_sat) +GEN_VEXT_V_ENV(vfncvt_sat_f_f_q_ofp8e4m3, 1) +GEN_VEXT_V_ENV(vfncvt_sat_f_f_q_ofp8e5m2, 1) + /* * Vector Reduction Operations */ --=20 2.43.7 From nobody Mon Feb 9 03:17:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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And the VTYPE.altfmt field is used to select the OFP8 format. * altfmt =3D 0: BF16 to OFP8.e4m3 * altfmt =3D 1: BF16 to OFP8.e5m2 Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvbf16.c.inc | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn= _trans/trans_rvbf16.c.inc index 9aafd4d2ef..16f4403909 100644 --- a/target/riscv/insn_trans/trans_rvbf16.c.inc +++ b/target/riscv/insn_trans/trans_rvbf16.c.inc @@ -67,11 +67,20 @@ static bool trans_fcvt_s_bf16(DisasContext *ctx, arg_fc= vt_s_bf16 *a) static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w= *a) { REQUIRE_FPU; - REQUIRE_ZVFBFMIN(ctx); =20 - if (opfv_narrow_check(ctx, a) && (ctx->sew =3D=3D MO_16)) { + if (opfv_narrow_check(ctx, a) && + ((ctx->sew =3D=3D MO_16 && ctx->cfg_ptr->ext_zvfbfmin) || + (ctx->sew =3D=3D MO_8 && ctx->cfg_ptr->ext_zvfofp8min))) { + gen_helper_gvec_3_ptr *fn; uint32_t data =3D 0; =20 + if (ctx->sew =3D=3D MO_16) { + fn =3D gen_helper_vfncvtbf16_f_f_w; + } else { + fn =3D ctx->altfmt ? gen_helper_vfncvtbf16_f_f_w_ofp8e5m2 : + gen_helper_vfncvtbf16_f_f_w_ofp8e4m3; + } + gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -81,8 +90,7 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg= _vfncvtbf16_f_f_w *a) tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), vreg_ofs(ctx, a->rs2), tcg_env, ctx->cfg_ptr->vlenb, - ctx->cfg_ptr->vlenb, data, - gen_helper_vfncvtbf16_f_f_w); + ctx->cfg_ptr->vlenb, data, fn); finalize_rvv_inst(ctx); return true; } --=20 2.43.7 From nobody Mon Feb 9 03:17:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1767885572; cv=none; d=zohomail.com; s=zohoarc; b=GSvo4RivwHO+1yLrtrTUVhKgdiBfKN03CD05hEKMF+2WrcpMJA5U6EBIUlJsS/+TC3Kcmu43rPHokyW8gJN/F7vmYz/N97sjet/m2ILoZy8hF/5hn/sCuz95H4QKWFUPz7pzICEksKP+R5ibZc9uweifHB70c/2izNgS+5Jma8M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767885572; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=GRBuMviCQzKLoZJcd93haU3Tf4rhKSDwz1QTnIhNPyo=; b=EwXaJvBvAe3c2j5VdpkjLV+TI3iskwkXmNVFIBPjS6IGmBkTA8p+rs8ci/g0t0y18JRQD290UDVXD351w8lyhFyNEsloWvvbzqmuiSHkVwSkyX3+lLp70uXBgLF6BWB0vXDctf8d6MPgLnjIe6zmRV4bAlWwnmiMOVdoeZM+igE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767885572140678.1679531498955; Thu, 8 Jan 2026 07:19:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vdrm3-0001Ti-TK; Thu, 08 Jan 2026 10:18:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vdrlU-00013S-6O for qemu-devel@nongnu.org; Thu, 08 Jan 2026 10:17:41 -0500 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vdrlR-0003ZY-N9 for qemu-devel@nongnu.org; Thu, 08 Jan 2026 10:17:31 -0500 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-7b80fed1505so2340880b3a.3 for ; Thu, 08 Jan 2026 07:17:29 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. 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The VTYPE.altfmt field is used to select the format of the 8-bit floating-p= oint numbers. * altfmt =3D 0: BF16 to OFP8.e4m3 * altfmt =3D 1: BF16 to OFP8.e5m2 Signed-off-by: Max Chou --- target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvofp8.c.inc | 53 ++++++++++++++++++++++ target/riscv/translate.c | 1 + 3 files changed, 57 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvofp8.c.inc diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 6e35c4b1e6..49201c0c20 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -973,6 +973,9 @@ vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 101011= 1 @r2_vm vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 1010111 @r_vm vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm =20 +# *** Zvfofp8min Extension *** +vfncvtbf16_sat_f_f_w 010010 . ..... 11111 001 ..... 1010111 @r2_vm + # *** Zvbc vector crypto extension *** vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvofp8.c.inc b/target/riscv/insn= _trans/trans_rvofp8.c.inc new file mode 100644 index 0000000000..70a22616dc --- /dev/null +++ b/target/riscv/insn_trans/trans_rvofp8.c.inc @@ -0,0 +1,53 @@ +/* + * RISC-V translation routines for the OFP8 Standard Extensions. + * + * Copyright (C) 2025 SiFive, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#define REQUIRE_ZVFOFP8MIN(ctx) do { \ + if (!ctx->cfg_ptr->ext_zvfofp8min) { \ + return false; \ + } \ +} while (0) + + +static bool trans_vfncvtbf16_sat_f_f_w(DisasContext *ctx, arg_rmr *a) +{ + REQUIRE_FPU; + REQUIRE_ZVFOFP8MIN(ctx); + + if (opfv_narrow_check(ctx, a) && ctx->sew =3D=3D MO_8) { + gen_helper_gvec_3_ptr *fn; + uint32_t data =3D 0; + + fn =3D ctx->altfmt ? gen_helper_vfncvtbf16_sat_f_f_w_ofp8e5m2 : + gen_helper_vfncvtbf16_sat_f_f_w_ofp8e4m3; + + gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); + + data =3D FIELD_DP32(data, VDATA, VM, a->vm); + data =3D FIELD_DP32(data, VDATA, LMUL, ctx->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, ctx->vta); + data =3D FIELD_DP32(data, VDATA, VMA, ctx->vma); + tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), + vreg_ofs(ctx, a->rs2), tcg_env, + ctx->cfg_ptr->vlenb, + ctx->cfg_ptr->vlenb, data, fn); + finalize_rvv_inst(ctx); + return true; + } + return false; +} + diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a1c4b325e5..137022d7fb 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1219,6 +1219,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_rvbf16.c.inc" +#include "insn_trans/trans_rvofp8.c.inc" #include "decode-xthead.c.inc" #include "decode-xmips.c.inc" #include "insn_trans/trans_xthead.c.inc" --=20 2.43.7 From nobody Mon Feb 9 03:17:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1767885502; cv=none; d=zohomail.com; s=zohoarc; b=ns1+B/rzb9U4kzQBD/f9vP+iiwhg73gz0j7HrYLgHDrcXvxWHBoI0GgBmeIF7uINzxSmg0gDLgtmXWDJswH6GORLnjZFEf6ycqGgPT+sGme31ArJgSQv99XdDxppgZm5IFWmXJJtnVQrFL4cN2GgjylSSXgJsuf98h3d7XMLlnE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767885502; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=m0aTJbNlL9KZs7WjXY/+Go/wD74fcQhsCJqmty/0+W8=; b=UCHFZkNAHVe9+WQkEIedLr880afHicoJJPso+5vf+q8tZStaW3UHG/weCPJ7TNIgLjDHJqhkL8D7ja0wbrD7aWuKDd93dUOMnDfXHhDhZsAIsZ3mFBrL9DlX5SgW6LxEEnBSy5D5NWPHBaMP4waHtU+7egpm1HFB+LUlRQV4Uyg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767885502372230.44367388326646; Thu, 8 Jan 2026 07:18:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vdrm9-0001YJ-P3; Thu, 08 Jan 2026 10:18:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vdrlY-00015X-1j for qemu-devel@nongnu.org; Thu, 08 Jan 2026 10:17:41 -0500 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vdrlW-0003bR-8g for qemu-devel@nongnu.org; Thu, 08 Jan 2026 10:17:35 -0500 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-7baf61be569so2245916b3a.3 for ; Thu, 08 Jan 2026 07:17:32 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. 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The vfncvt.sat.f.fq instruction converts a vector of FP32 elements to a vector of OFP8 elements with satura= tion. The VTYPE.altfmt field is used to select the OFP8 format. * altfmt =3D 0: FP32 to OFP8.e4m3 * altfmt =3D 1: FP32 to OFP8.e5m2 Signed-off-by: Max Chou --- target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvofp8.c.inc | 62 ++++++++++++++++++++++ target/riscv/insn_trans/trans_rvv.c.inc | 39 ++++++++++++++ 3 files changed, 103 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 49201c0c20..f2b413c7d4 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -974,6 +974,8 @@ vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 101011= 1 @r_vm vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm =20 # *** Zvfofp8min Extension *** +vfncvt_f_f_q 010010 . ..... 11001 001 ..... 1010111 @r2_vm +vfncvt_sat_f_f_q 010010 . ..... 11011 001 ..... 1010111 @r2_vm vfncvtbf16_sat_f_f_w 010010 . ..... 11111 001 ..... 1010111 @r2_vm =20 # *** Zvbc vector crypto extension *** diff --git a/target/riscv/insn_trans/trans_rvofp8.c.inc b/target/riscv/insn= _trans/trans_rvofp8.c.inc index 70a22616dc..4b44417c47 100644 --- a/target/riscv/insn_trans/trans_rvofp8.c.inc +++ b/target/riscv/insn_trans/trans_rvofp8.c.inc @@ -22,6 +22,13 @@ } \ } while (0) =20 +static bool zvfofp8min_narrow_quad_check(DisasContext *s, arg_rmr *a) +{ + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_sq(s, a->rd, a->rs2, a->vm) && + (s->sew =3D=3D MO_8); +} =20 static bool trans_vfncvtbf16_sat_f_f_w(DisasContext *ctx, arg_rmr *a) { @@ -51,3 +58,58 @@ static bool trans_vfncvtbf16_sat_f_f_w(DisasContext *ctx= , arg_rmr *a) return false; } =20 +static bool trans_vfncvt_f_f_q(DisasContext *ctx, arg_rmr *a) +{ + REQUIRE_FPU; + REQUIRE_ZVFOFP8MIN(ctx); + + if (zvfofp8min_narrow_quad_check(ctx, a)) { + gen_helper_gvec_3_ptr *fn; + uint32_t data =3D 0; + + fn =3D ctx->altfmt ? gen_helper_vfncvt_f_f_q_ofp8e5m2 : + gen_helper_vfncvt_f_f_q_ofp8e4m3; + + gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); + + data =3D FIELD_DP32(data, VDATA, VM, a->vm); + data =3D FIELD_DP32(data, VDATA, LMUL, ctx->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, ctx->vta); + data =3D FIELD_DP32(data, VDATA, VMA, ctx->vma); + tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), + vreg_ofs(ctx, a->rs2), tcg_env, + ctx->cfg_ptr->vlenb, + ctx->cfg_ptr->vlenb, data, fn); + finalize_rvv_inst(ctx); + return true; + } + return false; +} + +static bool trans_vfncvt_sat_f_f_q(DisasContext *ctx, arg_rmr *a) +{ + REQUIRE_FPU; + REQUIRE_ZVFOFP8MIN(ctx); + + if (zvfofp8min_narrow_quad_check(ctx, a)) { + gen_helper_gvec_3_ptr *fn; + uint32_t data =3D 0; + + fn =3D ctx->altfmt ? gen_helper_vfncvt_sat_f_f_q_ofp8e5m2 : + gen_helper_vfncvt_sat_f_f_q_ofp8e4m3; + + gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); + + data =3D FIELD_DP32(data, VDATA, VM, a->vm); + data =3D FIELD_DP32(data, VDATA, LMUL, ctx->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, ctx->vta); + data =3D FIELD_DP32(data, VDATA, VMA, ctx->vma); + tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), + vreg_ofs(ctx, a->rs2), tcg_env, + ctx->cfg_ptr->vlenb, + ctx->cfg_ptr->vlenb, data, fn); + finalize_rvv_inst(ctx); + return true; + } + return false; +} diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index bcd45b0aa3..93c0761171 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -621,6 +621,45 @@ static bool vext_check_sds(DisasContext *s, int vd, in= t vs1, int vs2, int vm) require_align(vs1, s->lmul); } =20 +/* + * Common check function for vector narrowing instructions + * of single-width result (SEW) and quad-width source (4*SEW). + * + * Rules to be checked here: + * 1. The largest vector register group used by an instruction + * can not be greater than 8 vector registers=20 + * (Section 31.5.2) + * 2. Quad-width SEW cannot greater than ELEN. + * (Section 31.2) + * 3. Source vector register number is multiples of 4 * LMUL. + * (Section 31.3.4.2) + * 4. Destination vector register number is multiples of LMUL. + * (Section 31.3.4.2) + * 5. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 31.5.3) + * risc-v unprivileged spec + */ +static bool vext_quad_narrow_check_common(DisasContext *s, int vd, int vs2, + int vm) +{ + return (s->lmul <=3D 1) && + (s->sew < MO_32) && + ((s->sew + 2) <=3D (s->cfg_ptr->elen >> 4)) && + require_align(vs2, s->lmul + 2) && + require_align(vd, s->lmul) && + require_vm(vm, vd); +} + +static bool vext_check_sq(DisasContext *s, int vd, int vs, int vm) +{ + bool ret =3D vext_quad_narrow_check_common(s, vd, vs, vm); + if (vd !=3D vs) { + ret &=3D require_noover(vd, s->lmul, vs, s->lmul + 2); + } + return ret; +} + /* * Check function for vector reduction instructions. * --=20 2.43.7 From nobody Mon Feb 9 03:17:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1767885644; cv=none; d=zohomail.com; s=zohoarc; b=hxEBlLQ3dGwJFb91f7QApN6fWJu79yKqPC/iGS1Pdbsp810JGNgQ0Ad8ogluppjFRXuRjjwmFtDH/kSs6vYlDMgXaCg9t4enEpttkx4gpqUhRYy4SXvTmuffGsBT+/IknYkmS1YxjCIjCjGSISe4rOKGUfTFC/T0AJkGZTsm9W8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767885644; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=T6mlGA7uiLEOZV5HBdCHILUSjjtgFUZKMqLepK9svPQ=; b=GOkpAD6nLfL38TKDZ0jJKOt4GlrEcTo18hhtfYsZCWHr+6Q9Qd8slZLqcCAlvV7bjKTS+i21cHXKlR32TcsW9f/LzrzhT9qPxGccUm7MPFz4b9kgyoy2HjqsVzeOMy3Cexxnlvpf26sqqgsBgCvMVVM18tKUVbnEVDCIae7S3TY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767885644743831.0795324638387; Thu, 8 Jan 2026 07:20:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vdrlo-0001DZ-SB; Thu, 08 Jan 2026 10:17:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vdrlZ-00015b-2x for qemu-devel@nongnu.org; Thu, 08 Jan 2026 10:17:41 -0500 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vdrlX-0003dJ-Dt for qemu-devel@nongnu.org; Thu, 08 Jan 2026 10:17:36 -0500 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-7b80fed1505so2340932b3a.3 for ; Thu, 08 Jan 2026 07:17:35 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. 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Thu, 08 Jan 2026 07:17:33 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Aurelien Jarno , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Max Chou , Alistair Francis Subject: [PATCH 12/18] target/riscv: Expose Zvfofp8min properity Date: Thu, 8 Jan 2026 23:16:43 +0800 Message-ID: <20260108151650.16329-13-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260108151650.16329-1-max.chou@sifive.com> References: <20260108151650.16329-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=max.chou@sifive.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1767885645182158501 Content-Type: text/plain; charset="utf-8" Signed-off-by: Max Chou --- target/riscv/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 53b5aeb9b2..081891c97a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1387,6 +1387,9 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_e= xts[] =3D { MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false), MULTI_EXT_CFG_BOOL("x-zvfbfa", ext_zvfbfa, false), =20 + /* Zvfofp8min extension for OFP8 conversion */ + MULTI_EXT_CFG_BOOL("x-zvfofp8min", ext_zvfofp8min, false), + { }, }; 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Signed-off-by: Max Chou --- disas/riscv.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index 85cd2a9c2a..daffe9917f 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -984,6 +984,9 @@ typedef enum { rv_op_ssamoswap_d =3D 953, rv_op_c_sspush =3D 954, rv_op_c_sspopchk =3D 955, + rv_op_vfncvtbf16_sat_f_f_w =3D 956, + rv_op_vfncvt_f_f_q =3D 957, + rv_op_vfncvt_sat_f_f_q =3D 958, } rv_op; =20 /* register names */ @@ -2254,6 +2257,9 @@ const rv_opcode_data rvi_opcode_data[] =3D { rv_op_sspush, 0 }, { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL, rv_op_sspopchk, rv_op_sspopchk, 0 }, + { "vfncvtbf16.sat.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, = 0 }, + { "vfncvt.f.f.q", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, + { "vfncvt.sat.f.f.q", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, }; =20 /* CSR names */ @@ -3630,7 +3636,10 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) case 21: op =3D rv_op_vfncvt_rod_f_f_w; break; case 22: op =3D rv_op_vfncvt_rtz_xu_f_w; break; case 23: op =3D rv_op_vfncvt_rtz_x_f_w; break; + case 25: op =3D rv_op_vfncvt_f_f_q; break; + case 27: op =3D rv_op_vfncvt_sat_f_f_q; break; case 29: op =3D rv_op_vfncvtbf16_f_f_w; break; + case 31: op =3D rv_op_vfncvtbf16_sat_f_f_w; break; } break; case 19: --=20 2.43.7 From nobody Mon Feb 9 03:17:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1767885562; cv=none; d=zohomail.com; s=zohoarc; b=aeelkMjqAe5IgMIhcv4tPG3++T5UETE+md1ruAkCCizSr3rjy2an/dFnV58J6EyFKXEoEjy/EEsPb+YRGAkVaOTS7fOP9ZUM0fhwODyOo4yyxUma4G4O1ZAGCMI4V2JUfMC/spfRutUUBbOJkXiW6wqX01xhyWP2ETjjsVEp0WM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767885562; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HFri5ZA09xRzAtu6L+gPED6chTkzb719Dd9fZBMyM3c=; b=K/iWnjZzjB/k97ZLmmhWPaFdRqtg8Ju2OlWnYsdseDPrep3eiCZRypWlFq2tTGa4gI2leZAVeLGgp//FA7xgcmbHmj1sxtYCwxl90uAHhCEw/+fMLPBBBwAYJ3GztJTY9IebzbGRCQ7tKQeIsWQo76Rty4C/SIZMrnzzkGi7jCE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767885562730566.4157017949971; Thu, 8 Jan 2026 07:19:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vdrmY-00026y-Tj; Thu, 08 Jan 2026 10:18:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vdrlf-00018Z-OG for qemu-devel@nongnu.org; Thu, 08 Jan 2026 10:17:45 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vdrld-0003gE-Hc for qemu-devel@nongnu.org; Thu, 08 Jan 2026 10:17:43 -0500 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-7b8eff36e3bso3426641b3a.2 for ; Thu, 08 Jan 2026 07:17:41 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. 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Signed-off-by: Max Chou --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/tcg/tcg-cpu.c | 10 ++++++++++ 3 files changed, 12 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 081891c97a..9d4fc3ab6b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -193,6 +193,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), + ISA_EXT_DATA_ENTRY(zvfofp4min, PRIV_VERSION_1_12_0, ext_zvfofp4min), ISA_EXT_DATA_ENTRY(zvfofp8min, PRIV_VERSION_1_12_0, ext_zvfofp8min), ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb), ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index 59302894af..353a932c36 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -104,6 +104,7 @@ BOOL_FIELD(ext_zvfbfmin) BOOL_FIELD(ext_zvfbfwma) BOOL_FIELD(ext_zvfh) BOOL_FIELD(ext_zvfhmin) +BOOL_FIELD(ext_zvfofp4min) BOOL_FIELD(ext_zvfofp8min) BOOL_FIELD(ext_smaia) BOOL_FIELD(ext_ssaia) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ba89436f13..c095bc9efd 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -715,6 +715,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) return; } =20 + if (cpu->cfg.ext_zvfofp4min && !cpu->cfg.ext_zve32f) { + error_setg(errp, "Zvfofp4min extension depends on Zve32f extension= "); + return; + } + if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { error_setg(errp, "Zvfh extensions requires Zfhmin extension"); return; @@ -738,6 +743,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) } } =20 + if (cpu->cfg.ext_zvfofp4min && !cpu->cfg.ext_zve32f) { + error_setg(errp, "Zvfofp4min extension depends on Zve32f extension= "); + return; + } + if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfi= nx) { error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); return; --=20 2.43.7 From nobody Mon Feb 9 03:17:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1767885582; cv=none; d=zohomail.com; s=zohoarc; b=Qqy87OH3NfAaHoNdpIpOcGfcz+uTOJKdrZn4JSCnMPesQkEh+RSwJOQUV+t8NB92VAyChN7Oc7dIww6YjR/StiKfkIb0fqMyrV2DqS7IVvP9w+J/8UyH1UpnWDbtmRt476LKmCAm8vKHwsKarMO8sks/7Ocwc6F25Flvl8HtGFc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767885582; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=OstMPI/h+uk1U6Kh39t8Ott75csp0bQMtJ3rPEB+Wdo=; b=cLhqwwp4sf+n+qBbkpCmiwasFrRNzaJjovQKTSWpez90AnayhMppbRuMLZzEgw7LVdBKgxAgHGR/Fu6KGcXM0w6C41E0aD9IHPL2FGHlrpJYB07e7hgT95XgqC0lTthxQdRCxRb4/zpjutjCdHmaNnvukcEE/cJgG+CtghLbdAk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767885582726937.5084557732139; Thu, 8 Jan 2026 07:19:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vdrmU-0001ve-Vz; Thu, 08 Jan 2026 10:18:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vdrli-000197-2F for qemu-devel@nongnu.org; Thu, 08 Jan 2026 10:17:46 -0500 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vdrlg-0003ho-IW for qemu-devel@nongnu.org; Thu, 08 Jan 2026 10:17:45 -0500 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-7aae5f2633dso2402614b3a.3 for ; Thu, 08 Jan 2026 07:17:44 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. 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Signed-off-by: Max Chou --- target/riscv/cpu.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9d4fc3ab6b..ec1bf8034f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2526,6 +2526,15 @@ static RISCVCPUImpliedExtsRule ZVFOFP8MIN_IMPLIED = =3D { }, }; =20 +static RISCVCPUImpliedExtsRule ZVFOFP4MIN_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvfofp4min), + .implied_multi_exts =3D { + CPU_CFG_OFFSET(ext_zve32f), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + static RISCVCPUImpliedExtsRule ZVKN_IMPLIED =3D { .ext =3D CPU_CFG_OFFSET(ext_zvkn), .implied_multi_exts =3D { @@ -2663,7 +2672,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rule= s[] =3D { &ZKS_IMPLIED, &ZVBB_IMPLIED, &ZVE32F_IMPLIED, &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED, &ZVE64X_IMPLIED, &ZVFBFA_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED, - &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVFOFP8MIN_IMPLIED, + &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVFOFP4MIN_IMPLIED, &ZVFOFP8MIN_IMPL= IED, &ZVKN_IMPLIED, &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED, --=20 2.43.7 From nobody Mon Feb 9 03:17:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1767885658; cv=none; d=zohomail.com; s=zohoarc; b=lrUlk0sjTL8WtjC1JNmbt20vvCaiOpl40PblMnqyvImth9pThOTEyy4BCR8cQrCbdmBBsJEGsrhkjNY7tFEsNHTcdemtn5LTBEQnRgyzmmQ2OwI9zB1xvI/NkmzjIVV5gNL5VHrcQZALMyWwSF6I8dUt9F8DHLtfGDttgKBV/aI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767885658; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=W9qRPVM03Rx4n3geGklLvEZ9LglgGb2enjbhLFzxO7c=; b=FhOsqETZgHTtY7DdcvefZYGcy0CHZFKUbPbQlx5n0of97cRAKxggI/D1P80+zbGCMoZ5J4jYEPXuo2zXtykAGnyQzF2uixxKwsFNWeRNweEYKUvzjWA2cTHNTK1AsK1evim695bWaPbH9ogKxGRNj+HFhkr70BVW7sUxg4q3tzM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767885658730947.8226101977687; Thu, 8 Jan 2026 07:20:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vdrmV-00020z-My; Thu, 08 Jan 2026 10:18:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vdrln-0001Dz-21 for qemu-devel@nongnu.org; Thu, 08 Jan 2026 10:17:52 -0500 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vdrll-0003lS-5q for qemu-devel@nongnu.org; Thu, 08 Jan 2026 10:17:50 -0500 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-7f121c00dedso2883525b3a.0 for ; Thu, 08 Jan 2026 07:17:47 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. 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Signed-off-by: Max Chou --- target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvofp4.c.inc | 54 ++++++++++++++++++++++ target/riscv/translate.c | 1 + target/riscv/vector_helper.c | 33 +++++++++++++ 5 files changed, 94 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvofp4.c.inc diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 356c24d9fb..162303fb6c 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1259,6 +1259,9 @@ DEF_HELPER_5(vfncvt_f_f_q_ofp8e5m2, void, ptr, ptr, p= tr, env, i32) DEF_HELPER_5(vfncvt_sat_f_f_q_ofp8e4m3, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfncvt_sat_f_f_q_ofp8e5m2, void, ptr, ptr, ptr, env, i32) =20 +/* OFP4 function */ +DEF_HELPER_5(vfext_vf2, void, ptr, ptr, ptr, env, i32) + /* Vector crypto functions */ DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f2b413c7d4..c58223ebd8 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -754,6 +754,9 @@ vsext_vf2 010010 . ..... 00111 010 ..... 1010111 = @r2_vm vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm =20 +# Zvfofp4min Extension +vfext_vf2 010010 . ..... 10110 010 ..... 1010111 @r2_vm + vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11 vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10 vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvofp4.c.inc b/target/riscv/insn= _trans/trans_rvofp4.c.inc new file mode 100644 index 0000000000..4040a54ab6 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvofp4.c.inc @@ -0,0 +1,54 @@ +/* + * RISC-V translation routines for the OFP4 Standard Extensions. + * + * Copyright (C) 2025 SiFive, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +static bool vext_zvfofp4min_check(DisasContext *s, arg_rmr *a) +{ + return s->cfg_ptr->ext_zvfofp4min && + (s->sew =3D=3D MO_8) && + vext_check_altfmt(s, -1) && + (s->lmul >=3D -2) && + require_rvv(s) && + vext_check_isa_ill(s) && + (a->rd !=3D a->rs2) && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul - 1) && + require_vm(a->vm, a->rd) && + require_noover(a->rd, s->lmul, a->rs2, s->lmul - 1); +} + +static bool trans_vfext_vf2(DisasContext *s, arg_rmr *a) +{ + if (vext_zvfofp4min_check(s, a)) { + uint32_t data =3D 0; + + data =3D FIELD_DP32(data, VDATA, VM, a->vm); + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), + vreg_ofs(s, a->rs2), tcg_env, + s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data, + gen_helper_vfext_vf2); + tcg_gen_movi_tl(cpu_vstart, 0); + finalize_rvv_inst(s); + + return true; + } + return false; +} + diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 137022d7fb..bf403785b5 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1220,6 +1220,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_rvbf16.c.inc" #include "insn_trans/trans_rvofp8.c.inc" +#include "insn_trans/trans_rvofp4.c.inc" #include "decode-xthead.c.inc" #include "decode-xmips.c.inc" #include "insn_trans/trans_xthead.c.inc" diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 759ebb3251..86057f2bf4 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -5117,6 +5117,7 @@ RVVCALL(OPFVV1, vfncvt_sat_f_f_q_ofp8e5m2, QOP_UU_B, = H1, H4, GEN_VEXT_V_ENV(vfncvt_sat_f_f_q_ofp8e4m3, 1) GEN_VEXT_V_ENV(vfncvt_sat_f_f_q_ofp8e5m2, 1) =20 +/* Zvfofp4min: vfext.vf2 - OFP4 E2M1 to OFP8 E4M3 conversion */ /* * Vector Reduction Operations */ @@ -5916,3 +5917,35 @@ GEN_VEXT_INT_EXT(vsext_vf2_d, int64_t, int32_t, H8, = H4) GEN_VEXT_INT_EXT(vsext_vf4_w, int32_t, int8_t, H4, H1) GEN_VEXT_INT_EXT(vsext_vf4_d, int64_t, int16_t, H8, H2) GEN_VEXT_INT_EXT(vsext_vf8_d, int64_t, int8_t, H8, H1) + + +void HELPER(vfext_vf2)(void *vd, void *v0, void *vs2, CPURISCVState *env, + uint32_t desc) +{ + float_status fp_status =3D env->fp_status; + uint32_t vl =3D env->vl; + uint32_t vm =3D vext_vm(desc); + uint32_t esz =3D sizeof(uint8_t); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); + uint32_t i; + + VSTART_CHECK_EARLY_EXIT(env, vl); + + for (i =3D env->vstart; i < vl; ++i) { + if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); + continue; + } + + uint8_t input =3D *((uint8_t *)vs2 + H1((i % 2 ? i - 1 : i) / 2)); + input =3D (i % 2) ? ((input >> 4) & 0xf) : (input & 0xf); + *((uint8_t *)vd + H1(i)) =3D float4_e2m1_to_float8_e4m3(input, + &fp_status); + } + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); +} --=20 2.43.7 From nobody Mon Feb 9 03:17:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1767885659; cv=none; d=zohomail.com; s=zohoarc; b=ZsM1ieM1pGX62blTXXDWzCsH+2WczcEerlMevaDSRAtr+KecSkrkwwVPCKATJpiNBsLCUPBq90ZXh+u7Fz75H6MOqvlyMVNYVB3WfIdtv84vYRet8fDqN5qUnwjDJd8adHeYE96RPXOuBAmtSUyD6By0q+d3j+nmcrtJvCV4EPM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767885659; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nAQpf0m4HgwG3NyjurT915nb5JF68SP63rgAnrYfyaY=; b=M+sMfN1y52jaOYeu3Tn9kptqf4l5Pb7FIur07OQ5Wji7yYdTlt5J0Vo5He/jsLam5uYEUSeb79o2nYoyYQzOB+hKV2KyasTDIAcGH9VVtOVfQPXshJEQcJIqsJ+b9/x+A5lEJVsB3PipWVdKO7pcHks4NImd4HjZaNYV5UCIuZE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767885659238646.9244883790317; Thu, 8 Jan 2026 07:20:59 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vdrmp-0002Oh-0v; Thu, 08 Jan 2026 10:18:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vdrlp-0001GK-GO for qemu-devel@nongnu.org; Thu, 08 Jan 2026 10:17:56 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vdrlo-0003qj-5c for qemu-devel@nongnu.org; Thu, 08 Jan 2026 10:17:53 -0500 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-803474aaa8bso1139614b3a.0 for ; Thu, 08 Jan 2026 07:17:51 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. 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Thu, 08 Jan 2026 07:17:50 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Aurelien Jarno , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Max Chou , Alistair Francis Subject: [PATCH 17/18] target/riscv: Expose Zvfofp4min properity Date: Thu, 8 Jan 2026 23:16:48 +0800 Message-ID: <20260108151650.16329-18-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260108151650.16329-1-max.chou@sifive.com> References: <20260108151650.16329-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=max.chou@sifive.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1767885661180158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Max Chou --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ec1bf8034f..0345a4f037 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1390,6 +1390,8 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_e= xts[] =3D { =20 /* Zvfofp8min extension for OFP8 conversion */ MULTI_EXT_CFG_BOOL("x-zvfofp8min", ext_zvfofp8min, false), + /* Zvfofp4min extension for OFP4 conversion */ + MULTI_EXT_CFG_BOOL("x-zvfofp4min", ext_zvfofp4min, false), =20 { }, }; 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Signed-off-by: Max Chou --- disas/riscv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index daffe9917f..9abf86f2d7 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -987,6 +987,7 @@ typedef enum { rv_op_vfncvtbf16_sat_f_f_w =3D 956, rv_op_vfncvt_f_f_q =3D 957, rv_op_vfncvt_sat_f_f_q =3D 958, + rv_op_vfext_vf2 =3D 959, } rv_op; =20 /* register names */ @@ -2260,6 +2261,7 @@ const rv_opcode_data rvi_opcode_data[] =3D { { "vfncvtbf16.sat.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, = 0 }, { "vfncvt.f.f.q", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, { "vfncvt.sat.f.f.q", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, + { "vfext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, }; =20 /* CSR names */ @@ -3715,6 +3717,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa= isa) case 12: op =3D rv_op_vclz_v; break; case 13: op =3D rv_op_vctz_v; break; case 14: op =3D rv_op_vcpop_v; break; + case 22: op =3D rv_op_vfext_vf2; break; } break; case 20: --=20 2.43.7