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Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/tcg/tcg-opc.h | 1 - tcg/optimize.c | 18 --------- tcg/tcg-op-vec.c | 14 +------ tcg/tcg.c | 94 ------------------------------------------- 4 files changed, 2 insertions(+), 125 deletions(-) diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index fc1270f01e..28806057c5 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -130,7 +130,6 @@ DEF(qemu_st2, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_S= IDE_EFFECTS | TCG_OPF_INT DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) =20 DEF(dup_vec, 1, 1, 0, TCG_OPF_VECTOR) -DEF(dup2_vec, 1, 2, 0, TCG_OPF_VECTOR) =20 DEF(ld_vec, 1, 1, 1, TCG_OPF_VECTOR) DEF(st_vec, 0, 2, 1, TCG_OPF_VECTOR) diff --git a/tcg/optimize.c b/tcg/optimize.c index 995e26f0bb..adc5be3379 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1715,21 +1715,6 @@ static bool fold_dup(OptContext *ctx, TCGOp *op) return finish_folding(ctx, op); } =20 -static bool fold_dup2(OptContext *ctx, TCGOp *op) -{ - if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { - uint64_t t =3D deposit64(arg_const_val(op->args[1]), 32, 32, - arg_const_val(op->args[2])); - return tcg_opt_gen_movi(ctx, op, op->args[0], t); - } - - if (args_are_copies(op->args[1], op->args[2])) { - op->opc =3D INDEX_op_dup_vec; - TCGOP_VECE(op) =3D MO_32; - } - return finish_folding(ctx, op); -} - static bool fold_eqv(OptContext *ctx, TCGOp *op) { uint64_t z_mask, o_mask, s_mask; @@ -2886,9 +2871,6 @@ void tcg_optimize(TCGContext *s) case INDEX_op_dup_vec: done =3D fold_dup(&ctx, op); break; - case INDEX_op_dup2_vec: - done =3D fold_dup2(&ctx, op); - break; case INDEX_op_eqv: case INDEX_op_eqv_vec: done =3D fold_eqv(&ctx, op); diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 893d68e7d8..67e837174b 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -75,7 +75,6 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list, case INDEX_op_xor_vec: case INDEX_op_mov_vec: case INDEX_op_dup_vec: - case INDEX_op_dup2_vec: case INDEX_op_ld_vec: case INDEX_op_st_vec: case INDEX_op_bitsel_vec: @@ -228,20 +227,11 @@ void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint= 64_t a) void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a) { TCGArg ri =3D tcgv_vec_arg(r); + TCGArg ai =3D tcgv_i64_arg(a); TCGTemp *rt =3D arg_temp(ri); TCGType type =3D rt->base_type; =20 - if (TCG_TARGET_REG_BITS =3D=3D 64) { - TCGArg ai =3D tcgv_i64_arg(a); - vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); - } else if (vece =3D=3D MO_64) { - TCGArg al =3D tcgv_i32_arg(TCGV_LOW(a)); - TCGArg ah =3D tcgv_i32_arg(TCGV_HIGH(a)); - vec_gen_3(INDEX_op_dup2_vec, type, MO_64, ri, al, ah); - } else { - TCGArg ai =3D tcgv_i32_arg(TCGV_LOW(a)); - vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); - } + vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); } =20 void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec r, TCGv_i32 a) diff --git a/tcg/tcg.c b/tcg/tcg.c index b6a65fe224..2b3bcbe750 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2493,8 +2493,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, uns= igned flags) case INDEX_op_xor_vec: case INDEX_op_cmp_vec: return has_type; - case INDEX_op_dup2_vec: - return has_type && TCG_TARGET_REG_BITS =3D=3D 32; case INDEX_op_not_vec: return has_type && TCG_TARGET_HAS_not_vec; case INDEX_op_neg_vec: @@ -5888,93 +5886,6 @@ static void tcg_reg_alloc_op(TCGContext *s, const TC= GOp *op) } } =20 -static bool tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op) -{ - const TCGLifeData arg_life =3D op->life; - TCGTemp *ots, *itsl, *itsh; - TCGType vtype =3D TCGOP_TYPE(op); - - /* This opcode is only valid for 32-bit hosts, for 64-bit elements. */ - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); - tcg_debug_assert(TCGOP_VECE(op) =3D=3D MO_64); - - ots =3D arg_temp(op->args[0]); - itsl =3D arg_temp(op->args[1]); - itsh =3D arg_temp(op->args[2]); - - /* ENV should not be modified. */ - tcg_debug_assert(!temp_readonly(ots)); - - /* Allocate the output register now. */ - if (ots->val_type !=3D TEMP_VAL_REG) { - TCGRegSet allocated_regs =3D s->reserved_regs; - TCGRegSet dup_out_regs =3D opcode_args_ct(op)[0].regs; - TCGReg oreg; - - /* Make sure to not spill the input registers. */ - if (!IS_DEAD_ARG(1) && itsl->val_type =3D=3D TEMP_VAL_REG) { - tcg_regset_set_reg(allocated_regs, itsl->reg); - } - if (!IS_DEAD_ARG(2) && itsh->val_type =3D=3D TEMP_VAL_REG) { - tcg_regset_set_reg(allocated_regs, itsh->reg); - } - - oreg =3D tcg_reg_alloc(s, dup_out_regs, allocated_regs, - output_pref(op, 0), ots->indirect_base); - set_temp_val_reg(s, ots, oreg); - } - - /* Promote dup2 of immediates to dupi_vec. */ - if (itsl->val_type =3D=3D TEMP_VAL_CONST && itsh->val_type =3D=3D TEMP= _VAL_CONST) { - uint64_t val =3D deposit64(itsl->val, 32, 32, itsh->val); - MemOp vece =3D MO_64; - - if (val =3D=3D dup_const(MO_8, val)) { - vece =3D MO_8; - } else if (val =3D=3D dup_const(MO_16, val)) { - vece =3D MO_16; - } else if (val =3D=3D dup_const(MO_32, val)) { - vece =3D MO_32; - } - - tcg_out_dupi_vec(s, vtype, vece, ots->reg, val); - goto done; - } - - /* If the two inputs form one 64-bit value, try dupm_vec. */ - if (itsl->temp_subindex =3D=3D HOST_BIG_ENDIAN && - itsh->temp_subindex =3D=3D !HOST_BIG_ENDIAN && - itsl =3D=3D itsh + (HOST_BIG_ENDIAN ? 1 : -1)) { - TCGTemp *its =3D itsl - HOST_BIG_ENDIAN; - - temp_sync(s, its + 0, s->reserved_regs, 0, 0); - temp_sync(s, its + 1, s->reserved_regs, 0, 0); - - if (tcg_out_dupm_vec(s, vtype, MO_64, ots->reg, - its->mem_base->reg, its->mem_offset)) { - goto done; - } - } - - /* Fall back to generic expansion. */ - return false; - - done: - ots->mem_coherent =3D 0; - if (IS_DEAD_ARG(1)) { - temp_dead(s, itsl); - } - if (IS_DEAD_ARG(2)) { - temp_dead(s, itsh); - } - if (NEED_SYNC_ARG(0)) { - temp_sync(s, ots, s->reserved_regs, 0, IS_DEAD_ARG(0)); - } else if (IS_DEAD_ARG(0)) { - temp_dead(s, ots); - } - return true; -} - static void load_arg_reg(TCGContext *s, TCGReg reg, TCGTemp *ts, TCGRegSet allocated_regs) { @@ -6939,11 +6850,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb= , uint64_t pc_start) case INDEX_op_mb: tcg_out_mb(s, op->args[0]); break; - case INDEX_op_dup2_vec: - if (tcg_reg_alloc_dup2(s, op)) { - break; - } - /* fall through */ default: do_default: /* Sanity check that we've not introduced any unhandled opcode= s. */ --=20 2.43.0