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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/arm/tcg/gengvec.c | 32 ++++++------- target/arm/tcg/gengvec64.c | 4 +- target/arm/tcg/translate-sve.c | 26 +++++------ tcg/tcg-op-gvec.c | 62 ++++++++++++------------- target/i386/tcg/emit.c.inc | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 6 files changed, 64 insertions(+), 64 deletions(-) diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c index 01867f8ace..f97d63549c 100644 --- a/target/arm/tcg/gengvec.c +++ b/target/arm/tcg/gengvec.c @@ -165,7 +165,7 @@ void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint= 32_t rm_ofs, { .fni8 =3D gen_ssra64_i64, .fniv =3D gen_ssra_vec, .fno =3D gen_helper_gvec_ssra_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .load_dest =3D true, .vece =3D MO_64 }, @@ -241,7 +241,7 @@ void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint= 32_t rm_ofs, { .fni8 =3D gen_usra64_i64, .fniv =3D gen_usra_vec, .fno =3D gen_helper_gvec_usra_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .load_dest =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64, }, @@ -349,7 +349,7 @@ void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uin= t32_t rm_ofs, { .fni8 =3D gen_srshr64_i64, .fniv =3D gen_srshr_vec, .fno =3D gen_helper_gvec_srshr_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64 }, }; @@ -439,7 +439,7 @@ void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uin= t32_t rm_ofs, { .fni8 =3D gen_srsra64_i64, .fniv =3D gen_srsra_vec, .fno =3D gen_helper_gvec_srsra_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .load_dest =3D true, .vece =3D MO_64 }, @@ -543,7 +543,7 @@ void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uin= t32_t rm_ofs, { .fni8 =3D gen_urshr64_i64, .fniv =3D gen_urshr_vec, .fno =3D gen_helper_gvec_urshr_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64 }, }; @@ -652,7 +652,7 @@ void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uin= t32_t rm_ofs, { .fni8 =3D gen_ursra64_i64, .fniv =3D gen_ursra_vec, .fno =3D gen_helper_gvec_ursra_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .load_dest =3D true, .vece =3D MO_64 }, @@ -736,7 +736,7 @@ void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint3= 2_t rm_ofs, { .fni8 =3D gen_shr64_ins_i64, .fniv =3D gen_shr_ins_vec, .fno =3D gen_helper_gvec_sri_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .load_dest =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64 }, @@ -823,7 +823,7 @@ void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint3= 2_t rm_ofs, { .fni8 =3D gen_shl64_ins_i64, .fniv =3D gen_shl_ins_vec, .fno =3D gen_helper_gvec_sli_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .load_dest =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64 }, @@ -927,7 +927,7 @@ void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint3= 2_t rn_ofs, .vece =3D MO_32 }, { .fni8 =3D gen_mla64_i64, .fniv =3D gen_mla_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .load_dest =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64 }, @@ -959,7 +959,7 @@ void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint3= 2_t rn_ofs, .vece =3D MO_32 }, { .fni8 =3D gen_mls64_i64, .fniv =3D gen_mls_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .load_dest =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64 }, @@ -1002,7 +1002,7 @@ void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, u= int32_t rn_ofs, .vece =3D MO_32 }, { .fni8 =3D gen_cmtst_i64, .fniv =3D gen_cmtst_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64 }, }; @@ -1691,7 +1691,7 @@ void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, ui= nt32_t rn_ofs, { .fni8 =3D gen_sabd_i64, .fniv =3D gen_sabd_vec, .fno =3D gen_helper_gvec_sabd_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64 }, }; @@ -1748,7 +1748,7 @@ void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, ui= nt32_t rn_ofs, { .fni8 =3D gen_uabd_i64, .fniv =3D gen_uabd_vec, .fno =3D gen_helper_gvec_uabd_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .vece =3D MO_64 }, }; @@ -1803,7 +1803,7 @@ void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, ui= nt32_t rn_ofs, { .fni8 =3D gen_saba_i64, .fniv =3D gen_saba_vec, .fno =3D gen_helper_gvec_saba_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .load_dest =3D true, .vece =3D MO_64 }, @@ -1859,7 +1859,7 @@ void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, ui= nt32_t rn_ofs, { .fni8 =3D gen_uaba_i64, .fniv =3D gen_uaba_vec, .fno =3D gen_helper_gvec_uaba_d, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .opt_opc =3D vecop_list, .load_dest =3D true, .vece =3D MO_64 }, @@ -2429,7 +2429,7 @@ void gen_gvec_rev32(unsigned vece, uint32_t rd_ofs, u= int32_t rn_ofs, static const GVecGen2 g =3D { .fni8 =3D gen_bswap32_i64, .fni4 =3D tcg_gen_bswap32_i32, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_32 }; =20 diff --git a/target/arm/tcg/gengvec64.c b/target/arm/tcg/gengvec64.c index 2429cab1b8..c425d2b149 100644 --- a/target/arm/tcg/gengvec64.c +++ b/target/arm/tcg/gengvec64.c @@ -157,7 +157,7 @@ void gen_gvec_eor3(unsigned vece, uint32_t d, uint32_t = n, uint32_t m, .fniv =3D gen_eor3_vec, .fno =3D gen_helper_sve2_eor3, .vece =3D MO_64, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); } @@ -183,7 +183,7 @@ void gen_gvec_bcax(unsigned vece, uint32_t d, uint32_t = n, uint32_t m, .fniv =3D gen_bcax_vec, .fno =3D gen_helper_sve2_bcax, .vece =3D MO_64, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); } diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 07b827fa8e..64adb5c1ce 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -623,7 +623,7 @@ static void gen_bsl1n(unsigned vece, uint32_t d, uint32= _t n, uint32_t m, .fniv =3D gen_bsl1n_vec, .fno =3D gen_helper_sve2_bsl1n, .vece =3D MO_64, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); } @@ -661,7 +661,7 @@ static void gen_bsl2n(unsigned vece, uint32_t d, uint32= _t n, uint32_t m, .fniv =3D gen_bsl2n_vec, .fno =3D gen_helper_sve2_bsl2n, .vece =3D MO_64, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); } @@ -690,7 +690,7 @@ static void gen_nbsl(unsigned vece, uint32_t d, uint32_= t n, uint32_t m, .fniv =3D gen_nbsl_vec, .fno =3D gen_helper_sve2_nbsl, .vece =3D MO_64, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); } @@ -1367,7 +1367,7 @@ static bool trans_AND_pppp(DisasContext *s, arg_rprr_= s *a) .fni8 =3D gen_and_pg_i64, .fniv =3D gen_and_pg_vec, .fno =3D gen_helper_sve_and_pppp, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (!dc_isar_feature(aa64_sve, s)) { @@ -1405,7 +1405,7 @@ static bool trans_BIC_pppp(DisasContext *s, arg_rprr_= s *a) .fni8 =3D gen_bic_pg_i64, .fniv =3D gen_bic_pg_vec, .fno =3D gen_helper_sve_bic_pppp, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (!dc_isar_feature(aa64_sve, s)) { @@ -1436,7 +1436,7 @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_= s *a) .fni8 =3D gen_eor_pg_i64, .fniv =3D gen_eor_pg_vec, .fno =3D gen_helper_sve_eor_pppp, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (!dc_isar_feature(aa64_sve, s)) { @@ -1483,7 +1483,7 @@ static bool trans_ORR_pppp(DisasContext *s, arg_rprr_= s *a) .fni8 =3D gen_orr_pg_i64, .fniv =3D gen_orr_pg_vec, .fno =3D gen_helper_sve_orr_pppp, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (!dc_isar_feature(aa64_sve, s)) { @@ -1514,7 +1514,7 @@ static bool trans_ORN_pppp(DisasContext *s, arg_rprr_= s *a) .fni8 =3D gen_orn_pg_i64, .fniv =3D gen_orn_pg_vec, .fno =3D gen_helper_sve_orn_pppp, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (!dc_isar_feature(aa64_sve, s)) { @@ -1542,7 +1542,7 @@ static bool trans_NOR_pppp(DisasContext *s, arg_rprr_= s *a) .fni8 =3D gen_nor_pg_i64, .fniv =3D gen_nor_pg_vec, .fno =3D gen_helper_sve_nor_pppp, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (!dc_isar_feature(aa64_sve, s)) { @@ -1570,7 +1570,7 @@ static bool trans_NAND_pppp(DisasContext *s, arg_rprr= _s *a) .fni8 =3D gen_nand_pg_i64, .fniv =3D gen_nand_pg_vec, .fno =3D gen_helper_sve_nand_pppp, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (!dc_isar_feature(aa64_sve, s)) { @@ -3680,7 +3680,7 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_e= sz *a) .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_sve_subri_d, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64, .scalar_first =3D true } }; @@ -8024,7 +8024,7 @@ static void gen_sclamp(unsigned vece, uint32_t d, uin= t32_t n, uint32_t m, .fno =3D gen_helper_gvec_sclamp_d, .opt_opc =3D vecop, .vece =3D MO_64, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64 } + .prefer_i64 =3D true } }; tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]); } @@ -8075,7 +8075,7 @@ static void gen_uclamp(unsigned vece, uint32_t d, uin= t32_t n, uint32_t m, .fno =3D gen_helper_gvec_uclamp_d, .opt_opc =3D vecop, .vece =3D MO_64, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64 } + .prefer_i64 =3D true } }; tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]); } diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 9c33430638..2cfc7e9409 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -1754,7 +1754,7 @@ void tcg_gen_gvec_mov_var(unsigned vece, TCGv_ptr dba= se, uint32_t dofs, .fni8 =3D tcg_gen_mov_i64, .fniv =3D vec_mov2, .fno =3D gen_helper_gvec_mov, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (dofs =3D=3D aofs && dbase =3D=3D abase) { @@ -1917,7 +1917,7 @@ void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, u= int32_t aofs, .fni8 =3D tcg_gen_not_i64, .fniv =3D tcg_gen_not_vec, .fno =3D gen_helper_gvec_not, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g); } @@ -2030,7 +2030,7 @@ void tcg_gen_gvec_add_var(unsigned vece, TCGv_ptr dba= se, uint32_t dofs, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_add64, .opt_opc =3D vecop_list_add, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -2069,7 +2069,7 @@ void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, = uint32_t aofs, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_adds64, .opt_opc =3D vecop_list_add, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -2109,7 +2109,7 @@ void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, = uint32_t aofs, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_subs64, .opt_opc =3D vecop_list_sub, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -2221,7 +2221,7 @@ void tcg_gen_gvec_sub_var(unsigned vece, TCGv_ptr dba= se, uint32_t dofs, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_sub64, .opt_opc =3D vecop_list_sub, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -2260,7 +2260,7 @@ void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, u= int32_t aofs, .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_mul64, .opt_opc =3D vecop_list_mul, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -2289,7 +2289,7 @@ void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, = uint32_t aofs, .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_muls64, .opt_opc =3D vecop_list_mul, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -2618,7 +2618,7 @@ void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, u= int32_t aofs, .fniv =3D tcg_gen_neg_vec, .fno =3D gen_helper_gvec_neg64, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -2682,7 +2682,7 @@ void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, u= int32_t aofs, .fniv =3D tcg_gen_abs_vec, .fno =3D gen_helper_gvec_abs64, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -2697,7 +2697,7 @@ void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, u= int32_t aofs, .fni8 =3D tcg_gen_and_i64, .fniv =3D tcg_gen_and_vec, .fno =3D gen_helper_gvec_and, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (aofs =3D=3D bofs) { @@ -2714,7 +2714,7 @@ void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, ui= nt32_t aofs, .fni8 =3D tcg_gen_or_i64, .fniv =3D tcg_gen_or_vec, .fno =3D gen_helper_gvec_or, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (aofs =3D=3D bofs) { @@ -2731,7 +2731,7 @@ void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, u= int32_t aofs, .fni8 =3D tcg_gen_xor_i64, .fniv =3D tcg_gen_xor_vec, .fno =3D gen_helper_gvec_xor, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (aofs =3D=3D bofs) { @@ -2748,7 +2748,7 @@ void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, = uint32_t aofs, .fni8 =3D tcg_gen_andc_i64, .fniv =3D tcg_gen_andc_vec, .fno =3D gen_helper_gvec_andc, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (aofs =3D=3D bofs) { @@ -2765,7 +2765,7 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, u= int32_t aofs, .fni8 =3D tcg_gen_orc_i64, .fniv =3D tcg_gen_orc_vec, .fno =3D gen_helper_gvec_orc, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (aofs =3D=3D bofs) { @@ -2782,7 +2782,7 @@ void tcg_gen_gvec_nand(unsigned vece, uint32_t dofs, = uint32_t aofs, .fni8 =3D tcg_gen_nand_i64, .fniv =3D tcg_gen_nand_vec, .fno =3D gen_helper_gvec_nand, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (aofs =3D=3D bofs) { @@ -2799,7 +2799,7 @@ void tcg_gen_gvec_nor(unsigned vece, uint32_t dofs, u= int32_t aofs, .fni8 =3D tcg_gen_nor_i64, .fniv =3D tcg_gen_nor_vec, .fno =3D gen_helper_gvec_nor, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (aofs =3D=3D bofs) { @@ -2816,7 +2816,7 @@ void tcg_gen_gvec_eqv(unsigned vece, uint32_t dofs, u= int32_t aofs, .fni8 =3D tcg_gen_eqv_i64, .fniv =3D tcg_gen_eqv_vec, .fno =3D gen_helper_gvec_eqv, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, }; =20 if (aofs =3D=3D bofs) { @@ -2830,7 +2830,7 @@ static const GVecGen2s gop_ands =3D { .fni8 =3D tcg_gen_and_i64, .fniv =3D tcg_gen_and_vec, .fno =3D gen_helper_gvec_ands, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }; =20 @@ -2857,7 +2857,7 @@ void tcg_gen_gvec_andcs(unsigned vece, uint32_t dofs,= uint32_t aofs, .fni8 =3D tcg_gen_andc_i64, .fniv =3D tcg_gen_andc_vec, .fno =3D gen_helper_gvec_andcs, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }; =20 @@ -2871,7 +2871,7 @@ static const GVecGen2s gop_xors =3D { .fni8 =3D tcg_gen_xor_i64, .fniv =3D tcg_gen_xor_vec, .fno =3D gen_helper_gvec_xors, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }; =20 @@ -2895,7 +2895,7 @@ static const GVecGen2s gop_ors =3D { .fni8 =3D tcg_gen_or_i64, .fniv =3D tcg_gen_or_vec, .fno =3D gen_helper_gvec_ors, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }; =20 @@ -2967,7 +2967,7 @@ void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, = uint32_t aofs, .fniv =3D tcg_gen_shli_vec, .fno =3D gen_helper_gvec_shl64i, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -3032,7 +3032,7 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, = uint32_t aofs, .fniv =3D tcg_gen_shri_vec, .fno =3D gen_helper_gvec_shr64i, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -3125,7 +3125,7 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, = uint32_t aofs, .fniv =3D tcg_gen_sari_vec, .fno =3D gen_helper_gvec_sar64i, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -3184,7 +3184,7 @@ void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs,= uint32_t aofs, .fniv =3D tcg_gen_rotli_vec, .fno =3D gen_helper_gvec_rotl64i, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -3513,7 +3513,7 @@ void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, = uint32_t aofs, .fniv =3D tcg_gen_shlv_mod_vec, .fno =3D gen_helper_gvec_shl64v, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -3576,7 +3576,7 @@ void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, = uint32_t aofs, .fniv =3D tcg_gen_shrv_mod_vec, .fno =3D gen_helper_gvec_shr64v, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -3639,7 +3639,7 @@ void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, = uint32_t aofs, .fniv =3D tcg_gen_sarv_mod_vec, .fno =3D gen_helper_gvec_sar64v, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -3702,7 +3702,7 @@ void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs,= uint32_t aofs, .fniv =3D tcg_gen_rotlv_mod_vec, .fno =3D gen_helper_gvec_rotl64v, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 @@ -3761,7 +3761,7 @@ void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs,= uint32_t aofs, .fniv =3D tcg_gen_rotrv_mod_vec, .fno =3D gen_helper_gvec_rotr64v, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 0fde3d669d..535844dc09 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -3005,7 +3005,7 @@ static void gen_PMOVMSKB(DisasContext *s, X86DecodedI= nsn *decode) .fniv =3D gen_pmovmskb_vec, .opt_opc =3D vecop_list, .vece =3D MO_64, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64 + .prefer_i64 =3D true }; MemOp ot =3D decode->op[2].ot; int vec_len =3D vector_len(s, decode); diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 2a487179f6..caefd38216 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1489,7 +1489,7 @@ static void tcg_gen_gvec_rsubs(unsigned vece, uint32_= t dofs, uint32_t aofs, .fniv =3D gen_rsub_vec, .fno =3D gen_helper_vec_rsubs64, .opt_opc =3D vecop_list, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .prefer_i64 =3D true, .vece =3D MO_64 }, }; =20 --=20 2.43.0